Method for evaluating heat sensitive structures and heat sensitive structures of integrated circuit designs

Abstract

A method for evaluating a thermally sensitive structure. An electromigration (EM) verification method is disclosed that analyzes an integrated circuit design layout to identify thermally sensitive structures, self-heating effects, heat generating structures, and heat dissipation structures. The EM verification method includes adjusting an evaluation temperature of a thermally sensitive structure by calculating self-heating effects within the temperature sensitive structure and additional heating and / or cooling as a function of thermal coupling with surrounding heat generating structures and / or heat dissipation elements within a defined thermal coupling range. A method for evaluating a thermally sensitive structure of an integrated circuit design is also disclosed.

Description

Technical Field

[0001] The present disclosure relates to an evaluation method, and more particularly to an evaluation method for a heat-sensitive structure and a heat-sensitive structure of an integrated circuit design. Background Art

[0002] The current passing through the conductive line causes electromigration (EM), that is, the movement of metal atoms caused by the momentum transfer between the electrons passing through the conductive line and the metal atoms that make up the conductive line. Over time, EM leads to the formation of protrusions (accumulation of excess metal) and / or voids (depletion of the original metal) in the line, which in turn tends to cause short circuits (protrusions) or opens (voids).

[0003] The mean time to failure (MTTF) of a conductive line due to EM is estimated by taking into account a number of operating factors, including, for example, the size of the conductive line, the composition of the conductive line, the microstructure of the conductive line, the current density carried by the conductive line, the duty cycle of the current applied to the conductive line, and the operating temperature of the conductive line. EM evaluation, analysis, and verification methods applied to a particular integrated circuit design attempt to take into account at least some of these operating factors in order to provide a reasonable and prudent estimate of the lifetime of a semiconductor device fabricated using the integrated circuit design to avoid premature failure of the semiconductor device. Summary of the invention

[0004] Embodiments of the disclosure relate to a method for evaluating a thermally sensitive structure, comprising the following operations: identifying a thermally sensitive structure in an integrated circuit design layout, the thermally sensitive structure having a nominal temperature T nom ; Identify the first heating structure within the thermal coupling range of the thermosensitive structure; Calculate the operating temperature T of the first heating structure oph1 ; Calculated by and at operating temperature T oph1 The temperature of the thermosensitive structure induced by the thermal coupling of the first heat-generating structure increases by ΔT h1 ; and at the evaluation temperature T E =T nom +ΔT h1 The embodiment of the disclosure is related to a method for evaluating the thermally sensitive structure of an integrated circuit design, which comprises the following operations: identifying the thermally sensitive structure; calculating the nominal temperature T nom ; Identify the first heat dissipation structure within the first thermal coupling distance of the thermosensitive structure; calculate the operating temperature T of the heat dissipation structure opc1 ; Calculate the operating temperature T of the heat dissipation structure opc1 The temperature ΔT of the thermosensitive structure induced by thermal coupling c1 ; and at the evaluation temperature T E =T nom +ΔTc1 A performance evaluation of the thermal sensitive structure is carried out below.

[0005] Embodiments of the disclosure relate to a method for evaluating a thermally sensitive structure of an integrated circuit design, comprising the following operations: identifying a thermally sensitive structure having a nominal temperature T nom a thermosensitive structure; identifying a first heat generating structure within a first thermal coupling distance of the thermosensitive structure; and calculating an operating temperature T of the heat generating structure. oph Calculate the temperature ΔT of the thermosensitive structure induced by thermal coupling with the first heat-generating structure h ; Identify a heat dissipation structure within the second thermal coupling distance of the thermal sensitive structure; calculate the operating temperature T of the heat dissipation structure opc ; Calculate the temperature ΔT of the heat-sensitive structure induced by thermal coupling with the heat dissipation structure c ; and at the adjusted temperature T E =T nom +ΔT h +ΔT c Thermosensitive structures are evaluated below.

[0006] Embodiments of the disclosure relate to a method for evaluating a thermally sensitive structure, comprising the following operations: identifying a thermally sensitive structure in an integrated circuit design layout, the thermally sensitive structure having a nominal operating temperature T nom ; Calculate the nominal operating temperature T in the thermal coupling volume oph1 The nominal operating temperature of the thermosensitive structure induced by the thermal coupling between the first heat-generating structure and the thermosensitive structure increases by ΔT h1 ; and at the evaluation temperature T E =T nom +ΔT h1 The functional parameters of the thermosensitive structure were evaluated.

[0007] Embodiments of the disclosure relate to a method for evaluating a thermally sensitive structure of an integrated circuit design, comprising the following operations: identifying the thermally sensitive structure; calculating a nominal operating temperature T of the thermally sensitive structure under a first test procedure applied to the integrated circuit design; nom ; Identify the first heat dissipation structure within the first thermal coupling volume of the thermally sensitive structure; calculate the nominal operating temperature T of the first heat dissipation structure under the first test procedure applied to the integrated circuit design opc1 ; Calculated by the nominal operating temperature T opc1 The first heat dissipation structure and at the nominal operating temperature T nom The temperature ΔT of the thermosensitive structure induced by the thermal coupling between the thermosensitive structures c1 ; and at the evaluation temperature T E The performance of the thermosensitive structure is evaluated at the temperature T E At least equal to T nom +ΔT c1 .

[0008] Embodiments of the disclosure relate to a method for evaluating a thermally sensitive structure of an integrated circuit design, comprising the following operations: identifying a thermally sensitive structure having a nominal temperature T nom a thermosensitive structure; running a pseudo three-dimensional analysis of any structure and material falling within the range of the thermocouple structure to define a thermocouple volume; identifying a heat generating structure within the first thermocouple volume of the thermosensitive structure; calculating the operating temperature T of the heat generating structure oph ; Calculate the temperature ΔT of the thermosensitive structure induced by thermal coupling with the heat-generating structure h ; Identify the heat dissipation structure within the thermal coupling volume of the thermally sensitive structure; calculate the operating temperature T of the heat dissipation structure opc ; Calculate the temperature ΔT of the heat-sensitive structure induced by thermal coupling with the heat dissipation structure c ; and at the adjusted temperature T E =T nom +ΔT h +ΔT c The thermally sensitive structure is evaluated; and design finalization data for producing a mask is generated after the thermally coupled structure passes the evaluation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0010] Figure 1 It is a schematic diagram of the electromigration (EM) process within a metal line;

[0011] Figure 2 is a schematic diagram of thermal coupling between components in some embodiments;

[0012] Figure 3 is a schematic diagram of an EM tool that may be used for operation of an EM verification method according to some embodiments;

[0013] Figure 4 is a plan view of an active region (AR) according to some embodiments (in some embodiments, the active region is an oxide definition (OD) region in which transistors and other functional semiconductor elements are formed);

[0014] Figure 5A and Figure 5B is a cross-sectional view of an assessment of thermal coupling between components in some embodiments;

[0015] Fig. 6A is a flow chart of a method for performing self-heating aware EM assessment according to some embodiments;

[0016] Figure 6B is a flow chart of a method for performing thermally-aware EM assessment according to some embodiments;

[0017] Fig. 7A is a plan view of an evaluation of thermal coupling between a target and a heat generating component according to some embodiments;

[0018] Figure 7B is a plan view of an evaluation of thermal coupling between a target and a heat sink according to some embodiments;

[0019] Figure 8 is a cross-sectional view of an evaluation of thermal coupling between a front end (FE) component and a back end (BE) component according to some embodiments;

[0020] 9A to 9D is a perspective view of EM evaluation results according to some embodiments;

[0021] Fig.10 is a table including a floor plan of thermally aware EM evaluation according to some embodiments;

[0022] Fig.11 is a schematic diagram of an electronic process control (EPC) system that may be used in the operation of an EM verification method according to some embodiments.

[0023]

Explanation of symbols

[0024] 100 Conductive line segments

[0025] 102 Conductive circuit

[0026] 104 Metal Atoms

[0027] 106 Electronics

[0028] 200 Semiconductor Structure

[0029] 202 FinFET Structure

[0030] 204 Hi-R Structure

[0031] 206 Conductive Circuit

[0032] 208 ILD structure

[0033] 300 EM Tools

[0034] 302 Integrated Circuit Design Layout Database

[0035] 304 Generate simulated design layout

[0036] 306 Component Temperature Equation

[0037] 308 Calculation of FinFET / AR / OD Self-Heating ΔT

[0038] 310 Pseudo 3D thermal model

[0039] 312 Calculating the Self-Heating ΔT of Conductive Circuits

[0040] 314 Calculation of Self-Heating ΔT of Hi-R Structure

[0041] 316 Run IR / EM analysis on the regulated conductive line temperature

[0042] 318 Generate design finalization data file corresponding to EM analysis

[0043] 400 Active Area Structure

[0044] 402 Diffusion Area

[0045] 404 Polysilicon on First Diffusion Edge (PODE) Structure

[0046] 406 first conductor M1

[0047] 408 second conductor M2

[0048] 410 The third conductor M3

[0049] 412 Second PODE Structure

[0050] 500 Semiconductor components

[0051] 502 Active Area

[0052] 504 Conductive circuit Ma

[0053] 506 Conductive Circuit Mb

[0054] 508 Conductive Circuit Mc

[0055] 510 Conductive Circuit

[0056] 512 Hi-R Structure

[0057] 514 Hi-R Impact Area

[0058] 516 Active Area Influence Range

[0059] 518 Semiconducting materials

[0060] 600 Methods

[0061] 600' Method

[0062] 602 Operation

[0063] 604 Operation

[0064] 604' Operation

[0065] 606 Operation

[0066] 608 Operation

[0067] 610 Operation

[0068] 612 Operation

[0069] 613 Operation

[0070] 614 Operation

[0071] 614' Operation

[0072] 616 Operation

[0073] 616' Operation

[0074] 618 Operation

[0075] 618' Operation

[0076] 620 Operation

[0077] 620' Operation

[0078] 700 parts

[0079] 702 Target Active Area

[0080] 704 Impact Area

[0081] 706 Affected Area

[0082] 708 Active Area

[0083] 710 Active Area

[0084] 712 Active Area

[0085] 714 Active Area

[0086] 716 Active Area

[0087] 718 Active Area

[0088] 720 Active Area

[0089] 722 Metal No. 0 (M0)

[0090] 724 Metal No. 1 (M1)

[0091] 726 Metal (M2)

[0092] 728 Affected Area

[0093] 730 Horizontal Influence Range

[0094] 732 Affected Area

[0095] 734 Horizontal Influence Range

[0096] 736 Affected Area

[0097] 800 parts

[0098] 802 Target Active Area

[0099] 804 Through hole / contact

[0100] 806 Conductive pattern M0

[0101] 808 Through Hole

[0102] 810 Conductive pattern M1

[0103] 812 Through Hole

[0104] 814 Conductive pattern M2

[0105] 816 Through Hole

[0106] 816' Through Hole

[0107] 818 Top Conductive Pattern MX

[0108] 820 ILD material

[0109] 822 Impact area / impact window

[0110] 824 Impact Volume

[0111] 1100 Electronic Process Control (EPC) System

[0112] 1102 Processor

[0113] 1104 Computer readable storage media

[0114] 1106 Computer Program Code

[0115] 1108 Process Control Data

[0116] 1110 User Interface

[0117] 1112 I / O interface

[0118] 1114 Network Interface

[0119] 1116 Network

[0120] 1118 Bus DETAILED DESCRIPTION

[0121] The description of the exemplary embodiments is intended to be read in conjunction with the accompanying drawings, which are to be considered as part of the entire written description. The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are described below to simplify the disclosure. Of course, these are merely examples and are not restrictive. Other components, values, operations, materials, arrangements, etc. can be conceived. For example, forming a first feature above or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature can be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0122] Additionally, spatially relative terms such as "below," "below," "lower," "above," "upper," etc. may be used herein to simplify the description to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device / element in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0123] Semiconductor devices tend to increase in temperature during use due to self-heating effects (SHE). These SHEs limit the performance capabilities and operating life of the affected semiconductor devices. For example, self-heating effects in semiconductor devices such as fin field effect transistors (FinFETs) will tend to reduce device performance and reliability.

[0124] Therefore, some FinFET integrated circuit designs utilize conductive lines and interconnecting vias as heat dissipation conduits for controlling the temperature of active structures. However, such heat dissipation techniques increase the operating temperature of the conductive lines. When coupled with the inherent current / resistance (IR) heating (also known as Ohmic or Joule heating) of the conductive lines, heating from other active components increases the risk of accelerated EM-related failures. Component designers have sought to address to some extent the increased EM risk caused by SHE in the conductive lines by modifying the integrated circuit design and / or operating parameters, but such design compensations tend to reduce density, reduce efficiency, and / or increase the size of the resulting semiconductor components.

[0125] FinFET processes and resulting semiconductor devices tend to offer power, performance, and area advantages over planar semiconductor devices. However, FinFET integrated circuit designs tend to exhibit greater local current density, which in turn leads to greater EM failure issues in conductive lines including signal and power rail interconnects within FinFET semiconductor devices.

[0126] In some cases, a FinFET semiconductor device includes a substrate in which an active region is formed, in which a source and a drain are formed; a guard ring; a plurality of conductive wiring layers separated by an interlayer dielectric (ILD) material layer; and vias formed through the ILD material to establish electrical connections to and between the conductive wiring layers. Depending on the specific integrated circuit design, heat generated in the active region of the semiconductor device will reach the portion of the conductive wiring layer that is within the influence of the active region and, to some extent, pass through the vias that connect the conductive wiring to the active region.

[0127] Because the heat dissipation paths available in FinFET integrated circuit designs are limited by the fin structure, there will be areas and / or structures in the integrated circuit design where SHE results in elevated operating temperatures that increase the likelihood of accelerated EM degradation. In some particularly thermally sensitive integrated circuit designs, a temperature increase of as little as 10°C can increase EM degradation by 50%. Problems with SHE tend to increase with shrinking feature sizes associated with more advanced processes and / or high speed / high performance integrated circuit designs.

[0128] EM occurs when an electric current flows through a conducting line and the electrons transfer part of their momentum to the atoms, tending to push the atoms in the direction of the electron flow. Figure 1As shown in FIG. 1 , the conductive line segment 100 includes a conductive line 102, the conductive line 102 including a plurality of metal atoms 104 selected from the group consisting of metals such as aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), platinum (Pt), cobalt (Co), and in some embodiments one or more alloy metals or other elements including nickel (Ni), nitrogen (N) and silicon (Si), the plurality of metal atoms 104 having been patterned to form a conductive path for electrons 106 to move between a cathode and an anode. Repeated momentum transfer from electrons 106 to metal atoms 104 during operation of the semiconductor device will gradually displace the metal atoms from their original positions, thereby increasing the non-uniformity of the conductive line 102.

[0129] In those areas where the movement of the metal atoms 104 of the conductive traces reduces the cross-section of the conductive traces 102, the current density will increase and further exacerbate the SHE and EM in the thinned areas. The conductive traces 102 containing such thinned areas will exhibit increased resistance and will generally result in reduced efficiency and ultimately voids or open circuits. Conversely, in those areas where the movement of the metal atoms 104 of the conductive traces 102 increases the cross-section of the conductive traces 102, the thickened areas (e.g., protrusions) will tend to stress the surrounding materials and ultimately compromise the structural integrity of the surrounding materials and / or create shorts to adjacent conductive traces or other conductors.

[0130] To help reduce or eliminate EM-induced failures, design rules associated with the manufacturing process will include EM rules to limit the average current density through the conductive lines and take into account the temperature of the conductive lines during the expected operation of the semiconductor device. Integrated circuit designs that pass all applicable EM rules are approved for EM verification and design finalization.

[0131] In advanced FinFET processes, the SHE will raise the temperature of the transistor structure by a certain amount ΔT. At least a portion of the SHE that generates ΔT will then be transferred to the conductive lines via direct contact with the transistor and via conduction through intervening materials (e.g., ILD materials / layers). In addition to the SHE associated with the FinFET structure, in some embodiments, other high resistance elements (Hi-R) present on the semiconductor element will also contribute to the heating of the conductive lines.

[0132] EM assessment methods that do not identify and compensate for elevated operating temperatures of conductive lines caused or resulting from thermal coupling with SHE elements within semiconductor components have an increased risk of underestimating the operating temperatures of the conductive lines. Underestimation of the operating temperatures of the conductive lines will in turn produce overly optimistic EM assessment results that will tend to overestimate the average life of semiconductor components manufactured according to the design and result in premature field failures of the affected semiconductor components.

[0133] To improve EM evaluation methods, EM evaluation should identify and take into account those portions of the integrated circuit design where a SHE is expected to increase the operating temperature of at least a portion of the conductive lines.

[0134] In some embodiments, the self-heating aware EM assessment method will include using equation-based component temperature calculations; using a pseudo 3D thermal model to estimate the thermal coupling range and effects of the component to the metal and produce an adjusted (or nominal) conductive line temperature; and performing an EM confirmation check at the adjusted metal temperature to compensate for SHE and improve the accuracy of the EM assessment.

[0135] In some embodiments, the self-heating-aware EM assessment method will provide more accurate local temperature calculations within an integrated circuit design compared to other EM assessment methods; more accurate thermally-aware EM assessment results during the design phase; reduced risk of premature product failure; shortened simulation run times using equation-based component temperature calculations; and shortened EM simulation run times using pseudo 3D thermal models instead of full 3D thermal modeling.

[0136] In some embodiments, the self-heating aware EM assessment takes into account various thermal effects. Figure 2 In an embodiment of the present invention, three thermal effects are considered during EM evaluation, the three thermal effects including FinFET element self-heating; Hi-R element self-heating; and conductive line self-heating. Figure 2 , semiconductor structure 200 includes FinFET structure 202 and Hi-R structure 204, both of which are embedded in ILD structure 208 and will generate heat during operation of the semiconductor device. A portion of the heat generated in FinFET structure 202 and Hi-R structure 204 will then be transferred to conductive line 206 via thermal coupling through intervening materials (not shown). In addition to the heat transferred from FinFET structure 202 and Hi-R structure 204, conductive line 206 will also experience a certain degree of self-heating as a function of the current carried by the conductive line. In some embodiments, the cumulative thermal effects of these three heat sources are then used to calculate an adjusted metal temperature, which will be used for EM evaluation.

[0137] In accordance with Figure 3In some embodiments, the EM tool 300 includes a database 302 or other data storage device for storing design data corresponding to an integrated circuit layout, which is then used to generate a simulated design layout 304. The simulated design layout 304 is then used in conjunction with a component temperature equation retrieved from a memory 306 to calculate 308 an expected temperature increment ΔT for at least a portion of heat generating components (e.g., FinFETs and Hi-R structures) identified in the simulated design layout.

[0138] In some embodiments, the ΔT of the FinFET structure is calculated using the following device temperature equation, Eq. 1:

[0139] ΔT=R THC ×Finger 效应 ×Fin 效应 ×Power 每个鳍片·每个指状物 Eq.1

[0140] In some embodiments, the relevant values ​​and / or parameters included in the component temperature equation are provided by the manufacturer, incorporated into applicable design rules, or extracted from the integrated circuit layout and include:

[0141] R THC : Thermal resistance value (usually provided by the manufacturer);

[0142] The number of fins: determined by the integrated circuit layout;

[0143] Number of fingers: determined by the integrated circuit layout;

[0144] The power (watts) per fin per finger (usually provided by the manufacturer);

[0145] Finger effect = number of fingers;

[0146] Fin effect = number of fins.

[0147] In some embodiments, the device temperature equations are provided as part of design tools provided by semiconductor device manufacturers, including, for example, simulation program with integrated circuit emphasis (SPICE) models corresponding to specific manufacturing processes.

[0148] In some embodiments, ΔT of the active region is calculated AR is a function of the individual ΔT calculations for each structure incorporated into a particular active region. Figure 4 In some embodiments, the ΔT of the active region structure 400 ARwill be a function of ΔT calculation of the first polysilicon over diffusion edge (PODE) structure 404, the first conductor M1 406, the second conductor M2 408, the third conductor M3 410 and the second PODE structure 412 formed on the diffusion region 402. This function is represented by Eq. 2 as shown below.

[0149] ΔT OD =f(ΔT PODE1 ,ΔT M1 ,ΔT M2 ,ΔT M3 ,ΔT PODE2 ) Eq.2

[0150] In some embodiments, this accumulated ΔT OD This will then be used in subsequent calculations to assess the magnitude of the thermal coupling between the active region and adjacent thermally sensitive structures (eg, conductive traces).

[0151] Using the pseudo 3D thermal model retrieved from the memory 310, the EM tool 300 then calculates the expected temperature increase ΔT of the conductive lines 312 and Hi-R structures 314 identified in the integrated circuit layout due to self-heating. The EM tool 300 then uses the ΔT data of the temperature-sensitive structures and the adjacent heat-generating structures to calculate an adjusted operating temperature TE of the temperature-sensitive structures (e.g., conductive lines) during operation of the semiconductor device based on the integrated circuit layout.

[0152] In some embodiments, the pseudo 3D thermal model will include a plurality of coefficients, such as a, b, c, d, which will be specific to each of the materials and / or layers incorporated in the integrated circuit design being analyzed and to the specific manufacturing process that will be used to produce semiconductor devices according to the integrated circuit design. In some embodiments, the ΔT of a thermally sensitive structure (e.g., a conductive line) will be a function of the self-heating of the thermally sensitive structure and the heat contribution from other heat-generating structures in the vicinity of the thermally sensitive structure. In some embodiments, for example, the ΔT of a conductive line will be calculated according to Eq. 3 provided below:

[0153] ΔT con =ΔT rms +f(a,b,ΔT ch ,c,d,ΔT hi-R ,ΔT 其它_元件 ,...) Eq.3

[0154] In some embodiments, including ΔT 金属 The relevant values ​​and / or parameters in the equation are provided by the manufacturer and incorporated into the applicable design rules, or extracted from the integrated circuit layout and include:

[0155] ΔT rms : Current-induced heating of metals;

[0156] ΔT ch : FinFET components self-heating;

[0157] ΔT hi-R : Hi-R element self-heating;

[0158] ΔT 其他_元件 : Self-heating of the component from other components.

[0159] For ΔT according to Eq.3 con For calculation purposes, other components will include, for example, bipolar junction transistors (BJTs), diodes and resistors that are thermally coupled to the conductive line being analyzed. The thermal coefficients a, b, c and d are provided for each layer and / or each material and reflect:

[0160] a = derating factor (or de-rating factor) value, reflecting operation below maximum capacity;

[0161] b=ΔT rms and ΔT ch Function [f(ΔT rms ,ΔT ch )];

[0162] c = layer effect related to the layer / material;

[0163] d = layer / material dependent temperature distribution.

[0164] Subsequently, the EM tool 300 runs an EM analysis 316 using the adjusted TE of the thermally sensitive structures (eg, conductive lines) to provide a more accurate analysis of the expected performance of the semiconductor device. In some embodiments, the EM tool will generate a design finalization data file 318 corresponding to the integrated circuit layout that passed the EM analysis.

[0165] In some embodiments, the range (i.e., the influence range or thermal coupling range) within which thermal coupling between the heat generating structure and the heat sensitive structure is expected to occur is limited by the horizontal distance (i.e., the influence range or thermal coupling range from the relevant heat generating structure). Figure 5AIn some embodiments, the semiconductor device 500 includes a plurality of heat-sensitive structures, such as a conductive layer, including, for example, a conductive line Ma 504, a conductive line Mb 506, a conductive line Mc 508, and a conductive line Md 508; and two heat-generating structures, namely, an active region 502 and a Hi-R structure 512, which are arranged in a dielectric and / or semiconductive material 518. With respect to the structure 512, the Hi-R influence range 514 is set to Aμm, and with respect to the active region 502, the active region influence range 516 is set to Bμm. Subsequently, the Hi-R and active region influence ranges are vertically projected through the structure 500 to define the Hi-R influence area and the active region influence area.

[0166] ΔT of the thermosensitive structure according to Eq.3 con The calculation includes contributions to the Hi-R influence area and active region influence area based on the locations of the conductive traces 504, 506, 508, 510. Figure 5A In some embodiments, the ΔT of the conductive line 504 con The ΔT of the conductive line 506 will include the thermal contributions from the active region influence area and the Hi-R influence area. con The ΔT of the conductive line 508 will not include the heat contribution from the active region influence area or the Hi-R influence area. con will include the heat contribution from only the active region affected area, and the ΔT of the conductive line 510 con The heat contribution from only the Hi-R affected area will be included.

[0167] In some embodiments, the range over which thermal coupling between the heat generating structure and the heat sensitive structure is expected to occur, i.e., the range of influence, is defined by the distance extending from the relevant heat generating structure. Figure 5B In some embodiments, the semiconductor device 500 includes a plurality of heat-sensitive structures, namely, conductive lines Ma 504, conductive lines Mb 506, conductive lines Mc 508, and conductive lines Md 508; and two heat-generating structures, namely, active region 502 and Hi-R structure 512, which are arranged in dielectric and / or semiconductive material 518. With respect to structure 512, Hi-R influence range 514 is set to Aμm, and with respect to active region 502, active region influence range 516 is set to Bμm. Subsequently, the Hi-R and active region influence ranges are rotated through structure 500 to define the Hi-R influence area and the active region influence area.

[0168] ΔT of the thermosensitive structure according to Eq.3 con The calculation includes contributions to the Hi-R influence area and active region influence area based on the locations of the conductive traces 504, 506, 508, 510. Figure 5B In the embodiment, the ΔT of the conductive line 504 con Including the heat contribution from both the active region influence area and the Hi-R influence area, the ΔT of the conductive line 506 con Excluding the heat contribution from the active region influence area or the Hi-R influence area, the ΔT of the conductive line 508 con The heat contribution from the active region influence area or the Hi-R influence area is not included, and the ΔT of the conductive line 510 is con Includes heat contribution from Hi-R affected area only.

[0169] In accordance with Figure 5A and / or Figure 5B In some embodiments, the areas of influence associated with two or more heat generating structures at least partially overlap to define a combined area of ​​influence.

[0170] Fig. 6A 6 is a flow chart of a method 600 for improving the accuracy of EM evaluations performed in connection with integrated circuit designs by accounting for the degrading effects of temperature rises generated by heat generating structures (i.e., structures that are expected to have operating temperatures higher than those of temperature sensitive structures that are located within a heating affected area (an area with known or expected thermal coupling) associated with a particular heat generating structure). In some embodiments, evaluating the SHE of the heat generating structures will indicate that the performance and / or lifetime of the temperature sensitive structures will be degraded due to the proximity and operating temperature of the heat generating structures. By identifying and compensating for the additional heat radiated from the heat generating structures, EM evaluations according to some embodiments will provide a more pessimistic and more accurate estimate of the expected performance of the semiconductor device, thereby increasing the likelihood that the semiconductor device will meet or exceed customer expectations.

[0171] In accordance with Fig. 6AIn some embodiments of the method, in operation 602, one or more temperature sensitive structures (TSS) (e.g., transistors, conductive lines, and other structures whose performance and / or lifetime will be degraded by increased operating temperatures) are identified during a structural and / or operational review of an integrated circuit design layout being evaluated. In operation 604, neighboring structures of the temperature sensitive structures (e.g., surrounding and / or adjacent to the temperature sensitive structures) are evaluated to be identified as heat generating structures (HGS). In order to be identified as heat generating structures, the neighboring structures will exhibit at least the following characteristics: 1) the operating temperature meets or exceeds a predetermined temperature level that is higher than the expected operating temperature of the temperature sensitive structure, and 2) the location is within the area of ​​influence defined by the temperature sensitive structure (or by the heat generating structure), which allows thermal coupling between the heat generating structure and the temperature sensitive structure. The neighboring structures that have or exhibit an operating temperature and location sufficient to meet the described characteristics are then identified as heat generating structures.

[0172] Operation 606 involves a query regarding the extent to which neighboring structures (PS) have been successfully evaluated for potential identification as heat generating structures. If less than all neighboring structures have been evaluated, the method 600 branches from operation 606 to operation 608 to identify the next neighboring structure to be evaluated as a heat generating structure and returns to operation 604 to evaluate the next neighboring structure. When all neighboring structures that may be identified as heat generating structures have been evaluated, the method 600 branches to operation 610 to calculate the ΔT contribution from each identified temperature sensitive structure to the operating temperature of the temperature sensitive structure.

[0173] Operation 612 involves a query regarding the extent to which temperature sensitive structures (TSS) in the integrated circuit design have been successfully evaluated and potentially identified as heat generating structures. If less than all temperature sensitive structures on the integrated circuit design have been identified, the method 600 operation branches from operation 612 to operation 613. During operation 613, the next temperature sensitive structure on the integrated circuit design is identified. Subsequently, the identification in operation 613 returns to operation 604 to identify heat generating structures proximate to the next temperature sensitive structure.

[0174] During optional operation 614, according to Figure 6BThe method detailed in evaluates the influence of adjacent heat sink elements (e.g., surrounding and / or adjacent temperature sensitive structures) in order to provide a more accurately regulated temperature taking into account the heating and cooling effects of structures proximate to the temperature sensitive structures. In operation 614, the adjacent structures are evaluated for identification as heat sink elements (HSE). In order to be identified as heat sink elements, the adjacent structures will exhibit at least the following characteristics: 1) an operating temperature that meets or exceeds a predetermined temperature difference below the expected operating temperature of the temperature sensitive structure, and 2) a location within an area of ​​influence defined by the temperature sensitive structure (or by the heat sink element) that allows thermal coupling between the adjacent heat sink element and the temperature sensitive structure. Adjacent structures that have or exhibit an operating temperature and location sufficient to meet the recited characteristics are then identified as heat sink elements.

[0175] At operation 616, an EM evaluation is run using an adjusted temperature T'H that takes into account heating effects or a fully adjusted temperature T" that takes into account heating and cooling effects on temperature sensitive structures to determine whether the evaluated integrated circuit design layout meets lifetime and performance goals for the particular design. In some embodiments, for integrated circuit design layouts that pass the EM evaluation at operation 616, a design finalization data file corresponding to the qualified integrated circuit design layout is generated at optional operation 618. For those integrated circuit design layouts for which the design finalization data file is generated, the design finalization data file is used at optional operation 620 to manufacture semiconductor devices based on the qualified integrated circuit design layout.

[0176] Figure 6B Flowchart of method 600' for improving the accuracy of EM evaluations performed in connection with integrated circuit design by taking into account the temperature regulating effects of heat dissipating elements (HSEs) (i.e., elements or structures that are expected to operate at lower temperatures than adjacent heat generating structures and / or temperature sensitive structures). In some embodiments, taking into account the effects of heat dissipating structures will help compensate for thermal coupling between heat sensitive structures and heat generating structures and / or SHEs of heat sensitive structures, thereby providing a lower and more accurate estimate of the operating temperature of the heat sensitive structures and improving the accuracy of subsequent EM evaluations.

[0177] In accordance with Figure 6BIn an embodiment of the method, in operation 602, one or more temperature sensitive structures (TSS) (e.g., transistors, conductive lines, and other structures where increased operating temperature will degrade performance and / or lifetime) are identified during a structural and / or operational review of an integrated circuit design layout being evaluated. In operation 604', structures adjacent to (e.g., surrounding and / or close to) the temperature sensitive structures are evaluated for potential identification as heat dissipation elements (HSEs). In order to be identified as heat dissipation elements, the adjacent structures will exhibit at least the following characteristics: 1) an operating temperature that is a predetermined temperature level lower than the expected operating temperature of the temperature sensitive structure, and 2) a physical proximity that allows thermal coupling between the adjacent heat dissipation element and the temperature sensitive structure. Adjacent structures having or exhibiting an operating temperature and location sufficient to meet the noted characteristics are then identified as heat dissipation elements.

[0178] Operation 606 involves a query as to the extent to which neighboring structures have been successfully evaluated for potential identification as heat dissipation elements. If less than all neighboring structures have been evaluated, method 600 branches from operation 606 to operation 608 to identify the next neighboring structure to be evaluated as a heat dissipation element and returns to operation 604' to evaluate the next neighboring structure. When all neighboring structures that may be identified as heat dissipation structures have been evaluated, method 600 branches to operation 610 to calculate the ΔT contribution from each identified heat dissipation element to the operating temperature of the temperature sensitive structure.

[0179] Operation 612 involves a query regarding the extent to which temperature sensitive structures in the integrated circuit design have been successfully evaluated and potentially identified as heat generating structures. If less than all temperature sensitive structures on the integrated circuit design have been identified, the method 600 operation branches from operation 612 to operation 613. During operation 613, the next temperature sensitive structure on the integrated circuit design is identified. Subsequently, the identification in operation 613 returns to operation 604' to identify thermal elements proximate to the next temperature sensitive structure.

[0180] During optional operation 614', according to Fig. 6A The method detailed in evaluates the impact of heat dissipation elements proximate to temperature sensitive structures in order to provide a more realistic fully regulated temperature taking into account the heating and cooling effects of structures proximate to the temperature sensitive structures.

[0181] In some embodiments, in operation 616', an EM evaluation is run using an adjusted temperature T'C that takes into account cooling effects on temperature sensitive structures to determine whether the evaluated integrated circuit design layout meets lifetime and performance goals for a particular design. In some embodiments, for integrated circuit design layouts that pass the EM evaluation of operation 616', a design finalization data file corresponding to the qualified integrated circuit design layout is generated in optional operation 618'. For those integrated circuit design layouts for which the design finalization data file is generated, the design finalization data file is used in optional operation 620' to manufacture semiconductor devices based on the qualified integrated circuit design layout.

[0182] In some embodiments, the evaluation of adjacent structures includes identifying each structure adjacent to the thermosensitive structure as a heat generating structure, a heat dissipating element, or a neutral structure that forms part of a transmission path for thermal coupling between the thermosensitive structure and other structures and / or elements. In some embodiments, the temperature effects of both adjacent structures identified as heat generating structures and adjacent structures identified as heat dissipating elements on the thermosensitive structure are jointly evaluated to produce a fully regulated temperature T", which is then used in the EM evaluation.

[0183] In some embodiments, according to Fig. 7A In the portion 700 of the integrated circuit design layout, a temperature sensitive structure (e.g., a target active region 702) is associated with a plurality of surrounding structures including additional active regions 708, 710, 712, 714, 716, 718, and 720 and conductive traces including metal 0 M0 722, metal 1 M1 724, and metal 2 M2 726. In some embodiments, identification of neighboring structures is based on a range of influence 704 extending X μm horizontally from the target active region 702 to define an area of ​​influence, which is then projected vertically to define a volume of influence.

[0184] The area of ​​influence 706 is defined as a horizontal area within the range of influence of the periphery of the target active region. The area of ​​influence 706 is projected vertically, or rotated around the longitudinal axis of the target active region to define the volume of influence. The surrounding structures that fall within the volume of influence or are at least partially located within the volume of influence have the potential to affect the target active region and are referred to as adjacent structures. In some embodiments, each of the adjacent structures is then subsequently evaluated to be identified as a heating structure or heat dissipation element relative to the target active region. In some embodiments, before the adjacent structure is identified as a heating structure or heat dissipation element, the temperature difference between the estimated operating temperature of the target active region 702 and the adjacent structure must exceed a predetermined temperature difference.

[0185] exist Fig. 7AIn the example, active regions 708, 712, 716 exhibit sufficient temperature differences and are used to calculate the adjusted and / or fully adjusted operating temperature of the target active region, which is used in subsequent EM evaluations.

[0186] In accordance with Fig. 7A In some embodiments, Eq. 4 is used to calculate the heat dissipation effect of neighboring active regions (i.e., those active regions surrounding the target active region, or portions thereof), where:

[0187] Within the influence range X around the target active area;

[0188] thermally coupled to a target active region via one or more interposer layers or one or more materials; and

[0189] Being sufficiently "cooled" means having an expected operating temperature that is at least a predetermined value (° C.) or percentage lower than the expected operating temperature of the target active region.

[0190]

[0191] ΔT c h: temperature of the original active area without heat dissipation effect;

[0192] ΔT ch_p_FE : Active area temperature with front-end (FE) cooling effect;

[0193] area t_AR : The area of ​​the target active region;

[0194] area 邻近_AR : Effective adjacent connection AR heat dissipation area;

[0195] Σ_AR: (RF of all adjacent connected ARs AR *area 邻近_AR ) and;

[0196] RF AR : Fitting factors for active area heat dissipation on silicon.

[0197] In some embodiments, according to Figure 7B In the portion 700 of the integrated circuit design layout, a temperature sensitive structure (e.g., a target active region 702) is associated with a plurality of surrounding structures including additional active regions 708, 710, 712, 714, 716, 718, and 720 and conductive lines including metal 0 (M0) 722, metal 1 (M1) 724, and metal (M2) 726. Fig. 7A The embodiments reflected in the examples are different. Figure 7BIn some embodiments, neighboring structures are identified based on a specific range of influence of each surrounding structure relative to the target active region 702. Thus, those neighboring structures that exhibit a greater temperature difference relative to the target active region 702 (or neighboring structures that are separated from the target active region by a more thermally conductive material) have a correspondingly larger range of influence than other neighboring structures. Figure 7B As shown, active region 708 has a horizontal range of influence 726 of Z1 μm defining an area of ​​influence 728 , active region 712 has a horizontal range of influence 730 of Z2 μm defining an area of ​​influence 732 , and active region 716 has a horizontal range of influence 734 of Z3 μm defining an area of ​​influence 736 .

[0198] In accordance with Figure 7B In some embodiments, the influence areas 728, 732, and 736 are used to identify surrounding structures whose horizontal influence range covers at least a portion of the target active area 702 as neighboring structures. In some embodiments, the temperature difference between the estimated operating temperature of the target active area 702 and the neighboring structure must exceed a predetermined level before the neighboring structure is identified as a heat generating structure or a heat dissipating element.

[0199] exist Figure 7B , active regions 708, 712, 716 exhibit temperature differences exceeding a predetermined level and an area of ​​influence that overlaps a portion of the target active region 702 and will be used to calculate the conditioned and / or fully conditioned operating temperature of the target active region, which will be used in subsequent EM evaluations.

[0200] In accordance with Figure 7B In some embodiments, Eq. 5 is used to calculate the heat dissipation effect of neighboring active regions (i.e., those active regions surrounding the target active region, or portions thereof), where:

[0201] Within the sphere of influence Z of the perimeter of each adjacent active region;

[0202] thermally coupled to a target active region via one or more interposer layers or one or more materials; and

[0203] Being sufficiently "cooled" means having an expected operating temperature that is at least a predetermined value (° C.) or percentage lower than the expected operating temperature of the target active region.

[0204]

[0205] ΔT ch : The temperature of the original active area without heat dissipation effect;

[0206] ΔT ch_p_FE: Active area temperature with front-end (FE) cooling effect;

[0207] area t_AR : The area of ​​the target active region;

[0208] area 邻近_AR : Effective heat dissipation area adjacent to the active area of ​​the connection;

[0209] Σ_AR: (RF of all neighboring active regions AR *area 邻近_AR ) and;

[0210] RF AR : Fitting factors for active area heat dissipation on silicon.

[0211] In addition to the adjacent active regions, the target active region will be affected by the proximity of one or more back end (BE) or BEOL structures (particularly conductive lines) that exhibit greater thermal conductivity than the insulating material surrounding and separating the target active region and the adjacent active regions. In some embodiments, the heat dissipation equation Eq. 6 will be used to identify and determine the contribution (if any) of the adjacent BE structures (conductive lines) to the operating temperature of the target active region. The adjacent BE structures are those BE structures that are within the influence distance of the target active region and are thermally coupled to the target active region. In some embodiments, the final active region temperature will be calculated using Eq. 7, where ΔTch_p is a function of the initial target active region temperature (which combines SHE and thermal coupling to other structures), the heat dissipation effect attributable to the FE structures, and the heat dissipation effect attributable to the BE structures.

[0212]

[0213] ΔT ch_p =f(ΔT ch ,ΔT ch_p_FE ,ΔT ch_p_BE ) Eq.7

[0214] ΔT ch : The temperature of the original active area without heat dissipation effect;

[0215] ΔT ch_p : Active area temperature with two heat dissipation effects;

[0216] ΔT ch_p_FE : Active area temperature with FE heat dissipation effect;

[0217] ΔT ch_p_BE : active region temperature with BE effect;

[0218] area t_AR : The area of ​​the target active region;

[0219] area m : effective metal heat dissipation area of ​​the metal layer (m);

[0220] Σ_m:M0~MX(RF m *area m ) and;

[0221] RF m : Fitting factor of metal heat dissipation on silicon basis.

[0222] For example, considering SHE during EM evaluation helps prevent an integrated circuit design layout from being characterized as being more resistant to EM effects than the corresponding semiconductor component will actually achieve in operation, thereby helping to prevent unforeseen and premature field failures of the semiconductor component. However, considering only SHE produces a worst-case scenario for the evaluation. In some integrated circuit design layouts, other nearby or adjacent structures will provide a heat sinking function that will mitigate SHE, provide a more accurate estimate of the operating temperature of temperature-sensitive structures, and reduce the need for unnecessary redesign, thereby improving the thermal performance of the resulting semiconductor component.

[0223] Therefore, an EM verification method that takes into account SHE and heat dissipation effects on temperature sensitive structures and / or functions helps to improve the accuracy of integrated circuit design layout analysis. By improving the accuracy of integrated circuit design layout analysis, embodiments of the method will increase the confidence that semiconductor components manufactured according to a specific integrated circuit design layout will perform as expected and maintain satisfactory performance during the design life of the semiconductor component.

[0224] The efficiency of EM verification methods that take into account the thermal effects of a particular integrated circuit design layout is improved by utilizing equation-based thermal evaluation, thereby avoiding slower, more time-consuming and computationally resource-intensive thermal modeling. The efficiency of some embodiments of the verification method is further improved by utilizing pseudo three-dimensional models to evaluate thermal coupling between various components including front-end of line (FEOL) and back-end of line (BEOL) structures.

[0225] In some embodiments, the BE structure, especially the conductive trace, is the focus of the EM evaluation. In some embodiments, the EM tool used to generate the final conductive trace temperature will be calculated by considering the ambient temperature T Env (or initial temperature T0) and ΔT calculated according to Eq.8 金属 To determine the final T 金属 In some embodiments, the final T is then evaluated using a temperature rating factor provided by the manufacturer or obtained from another source. 金属In some embodiments, the temperature rating factor will be associated with a specific integrated circuit design layout, while in other embodiments, the temperature rating factor will be associated with a specific manufacturing process that will be used to produce the semiconductor device. Typically, the final T 金属 The value (or more generally, the nominal temperature T nom ) the higher the temperature rating factor a particular design will receive.

[0226] T 金属 =T Env +ΔT 金属 Eq.8

[0227] In some embodiments, the EM method detailed above will be applied to any integrated circuit design layout and / or semiconductor manufacturing process where SHE is expected to be a factor. In some embodiments, the integrated circuit design layout will include FinFET devices and / or other planar or more complex structure semiconductor manufacturing processes.

[0228] In some embodiments, the self-heating-aware EM assessment identifies those areas, if any, in the integrated circuit design layout where SHE results in localized heating, such as "hot spots," which will degrade the overall EM performance and / or lifetime of semiconductor components manufactured according to the integrated circuit design. In some embodiments, the initial self-heating-aware EM assessment is combined with the heat dissipation-aware EM assessment to determine whether one or more surrounding structures can mitigate the previously identified self-heating effects and / or thermal coupling effects and thereby improve the EM performance of the integrated circuit design layout.

[0229] In some embodiments, performing a thermally-aware EM assessment utilizes an electronic design automation (EDA) (also known as electronic computer-aided design (ECAD)) tool to identify potential heat dissipation structures in an integrated circuit design layout. In some embodiments, the EDA tool is configured to identify potential hot spots and heat dissipation structures from an integrated circuit design layout database (DB). Potential heat dissipation structures include, for example, active areas, guard rings, conductive lines, vias, and other structures that are within a predetermined influence range of the identified hot spots or temperature-sensitive structures. In some embodiments, the integrated circuit design layout DB will utilize the open artwork system interchange standard (OASIS) or another language for representing integrated circuit design layouts.

[0230] In some embodiments, the evaluation of potential heat dissipation structures will include consideration of parameters including, for example, structure dimensions, material properties, intervening materials, environmental conditions, and expected (calculated) operating temperatures. In some embodiments, the EDA tool is configured to calculate the total heat dissipation effect attributable to the identified heat dissipation structures, and to provide temperature adjustments (reductions) to hot spot temperatures. In some embodiments, the EDA tool will utilize temperature adjustments to determine the EM performance of the integrated circuit design layout.

[0231] In some embodiments, the thermally-aware EM verification method will provide more accurate local temperature calculations within an integrated circuit design layout; more accurate thermally-aware EM evaluation results during the design phase; reduced risk of premature product failure and / or over-design; reduced simulation run times using equation-based component temperature calculations; and reduced EM simulation run times using pseudo 3D thermal models instead of full 3D thermal modeling.

[0232] In some embodiments, the BE structures, particularly the conductive lines and vias, will serve as heat sinks for temperature sensitive FE structures (e.g., active regions). Figure 8 800, the target active area 802 has an impact area 810 and is connected to the conductive pattern M0 806 via a via / contact 804. The conductive pattern M0 is in turn connected to the conductive pattern M1 810 via a via 808, and the conductive pattern M1 is connected to the conductive pattern M2 814 via a via 812. The conductive pattern M2 is connected to the upper conductive pattern via a via 816. Each conductive pattern is separated by an ILD material 820. The top conductive pattern MX 818 is connected to the lower conductive pattern via a via 816'.

[0233] The influence range 810 will then be used to define an influence area (or influence window) 822, which includes the target active region and the surrounding area within X μm from the target active region 802. The influence area 822 will then be used to define an influence volume 824 that will include at least a portion of the adjacent structure. In some embodiments, each of the conductive patterns 806, 810, 814, 818 will have a corresponding portion located within the influence volume 824, where the corresponding portion has a corresponding area AREA M0 、AREA M1 、AREA M2 、AREA MX Each portion of the conductive pattern that falls within the window of influence defined by extending the influence range 810 from the perimeter of the target active area will have a corresponding length, area, volume, and T that will determine the degree of heat dissipation activity in the target active area. 金属 .

[0234] 9A to 9D are transformed perspective views of the results of EM evaluations performed according to some embodiments using different techniques and / or methods. Fig.9A is a basic EM evaluation that does not include consideration of any heat sink effects and therefore presents a hot spot near the center of the integrated circuit design. Fig. 9B is the result of an EM evaluation that evaluates the presence of a compensating guard ring (Front End of Line (FEOL) heat sink structure) and reflects Fig.9A The temperature of the hot spots found in the Fig. 9C is the result of an EM evaluation that compensates for the presence of conductive (metal) patterns above the active area (back-end of line (BEOL) heatsink structures) and reflects Fig.9A The temperature of the hot spots found in the Fig.9D is the result of an EM evaluation that compensates for the presence of guard rings and conductive patterns (conductive lines) above the active area (FEOL and BEOL heat dissipation structures) and is reflected in Fig.9A The temperature of the hot spot found in Fig. 9B or Fig. 9C The results are even greater.

[0235] Fig.10 is a table including a transformation of the results of EM evaluations performed according to some embodiments, including thermal analysis performed in calculating ΔT for the indicated features on a portion of an integrated circuit design layout. Fig.10 As reflected, the heat dissipation structure adjacent to the thermally sensitive structure reduces the calculated ΔT of the thermally sensitive structure by 2.4°C (from 12°C to 9.6°C) compared to the ΔT value obtained without considering the effect of the heat dissipation structure. The reduction in ΔT will in turn improve the EM evaluation results of the integrated circuit design layout.

[0236] Fig.11 1 is a block diagram of an electronic process control (EPC) system 1100 according to some embodiments. According to some embodiments, the method described herein for generating a cell layout diagram according to one or more embodiments may be implemented, for example, using the EPC system 1100. In some embodiments, the EPC system 1100 is a general-purpose computing device that includes a hardware processor 1102 and a non-transitory computer-readable storage medium 1104. In addition, the storage medium 1104 is encoded with, i.e., stores, a computer program code (or instructions) 1106, i.e., a set of executable instructions. The execution of the computer program code 1106 by the hardware processor 1102 represents (at least in part) an EPC tool that implements, for example, part or all of the methods described herein according to one or more (hereinafter, the processes and / or methods mentioned).

[0237] The hardware processor 1102 is electrically coupled to the computer readable storage medium 1104 via a bus 1118. The hardware processor 1102 is also electrically coupled to the I / O interface 1112 via the bus 1118. The network interface 1114 is also electrically connected to the hardware processor 1102 via the bus 1118. The network interface 1114 is connected to a network 1116, so that the hardware processor 1102 and the computer readable storage medium 1104 can be connected to external components via the network 1116. The hardware processor 1102 is configured to execute the computer program code 1106 encoded in the computer readable storage medium 1104 so that the EPC system 1100 can be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the hardware processor 1102 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0238] In one or more embodiments, the computer-readable storage medium 1104 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1104 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1104 includes compact disk - read only memory (CD-ROM), compact disk - read / write (CD-R / W), and / or digital video disk (DVD).

[0239] In one or more embodiments, the storage medium 1104 stores computer program code 1106 configured to enable the EPC system 1100 (where such execution represents (at least in part) an EPC tool) to perform some or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 1104 also stores information that facilitates the performance of some or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 1104 stores process control data 1108, which in some embodiments includes control algorithms, process variables and constants, target ranges, set points, and codes for enabling control of various processes based on statistical process control (SPC) and / or model predictive control (MPC).

[0240] The EPC system 1100 includes an I / O interface 1112. The I / O interface 1112 is coupled to external circuits. In one or more embodiments, the I / O interface 1112 includes a keyboard, a keypad, a mouse, a trackball, a touchpad, a touch screen, and / or cursor direction keys for transmitting information and commands to the hardware processor 1102.

[0241] The EPC system 1100 also includes a network interface 1114 coupled to the hardware processor 1102. The network interface 1114 allows the EPC system 1100 to communicate with a network 1116 to which one or more other computer systems are connected. The network interface 1114 includes a wireless network interface, such as a BLUETOOT h , WIFI, WIMAX, GPRS or WCDMA; or wired network interface, such as ET h ERNET, USB or IEEE-1364. In one or more embodiments, part or all of the processes and / or methods mentioned are implemented in two or more EPC systems 1100.

[0242] The EPC system 1100 is configured to receive information via an I / O interface 1112. The information received via the I / O interface 1112 includes one or more of instructions, data, design rules, process execution history, target ranges, set points, and / or other parameters for processing by the hardware processor 1102. The information is transmitted to the hardware processor 1102 via a bus 1118. The EPC system 1100 is configured to receive information related to a user interface (UI) via the I / O interface 1112. The information is stored in a computer readable medium 1104 as a user interface (UI) 1110.

[0243] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the processes and / or methods mentioned is implemented as a software application that is part of an EPC tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the EPC system 1100.

[0244] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of the following: optical disks (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROM, RAM, memory cards), etc.

[0245] In some embodiments, a method for evaluating a thermally sensitive structure of an integrated circuit design layout is performed by one or more processors and utilizes operations including: identifying a thermally sensitive structure in the integrated circuit design, the thermally sensitive structure having a nominal temperature T nom ; Identify the first heating structure within the thermal coupling range of the thermosensitive structure; Calculate the operating temperature T of the first heating structure oph1 ; Calculated by and at operating temperature T oph1 The temperature of the thermosensitive structure induced by the thermal coupling of the first heat-generating structure increases by ΔT h1 ; and at the evaluation temperature T E =T nom +ΔT h Evaluation of heat-sensitive structures was carried out under

[0246] In some embodiments, the above method also includes the following additional operations: identifying a second heat generating structure within the thermal coupling range of the thermosensitive structure; calculating the operating temperature T of the second heat generating structure; oph2 ; Calculated by and at operating temperature T oph2 The ΔT of the thermosensitive structure induced by thermal coupling of the second heat-generating structure h2 ; and at the evaluation temperature T E =T nom +ΔT h1 +ΔT h2 Thermosensitive structures are evaluated below.

[0247] In some embodiments, in the above method, the thermosensitive structure includes a conductive line, and evaluating the thermosensitive structure includes performing electromigration analysis on the conductive line.

[0248] In some embodiments, in the above method, the first heat generating structure is a FinFET structure.

[0249] In some embodiments, in the above method, the second heat generating structure is a high resistance (Hi-R) structure.

[0250] In some embodiments, in the above method, the second heat generating structure is non-metallic.

[0251] In some embodiments, the above method also includes the following additional operations: identifying a first heat dissipation element within the thermal coupling range of the thermally sensitive structure; calculating the operating temperature T of the first heat dissipation element; opc1 ; Calculated by and at operating temperature T opc1 The first heat sink element is thermally coupled and induces a ΔT of the thermally sensitive structure c1 ; and at the evaluation temperature T E =T nom +ΔT h1 +ΔT h2 +ΔT c1 Thermosensitive structures are evaluated below.

[0252] In some embodiments, the method further comprises the following additional operations: verifying that the thermal sensitive structure is qualified for evaluation; and manufacturing a semiconductor device according to the integrated circuit design layout.

[0253] In some embodiments, the thermally sensitive structure is a conductive line, and the evaluation includes electromigration analysis of the conductive line. In some embodiments, the first heat generating structure is a FinFET structure, the second heat generating structure is a high resistance (Hi-R) structure, and / or the second heat generating structure is non-metallic. Some embodiments of the method will also include the following additional operations: obtaining an integrated circuit design from a database of integrated circuit designs; generating a pseudo 3D model of the integrated circuit design; and / or obtaining thermal coupling data of the integrated circuit design.

[0254] In some embodiments, a method for evaluating a thermally sensitive structure of an integrated circuit design layout will utilize operations including: identifying a thermally sensitive structure; calculating a nominal temperature T nom ; Identify the first heat dissipation structure within the first thermal coupling range of the thermosensitive structure; calculate the operating temperature T of the heat dissipation structure opc1 ; Calculate the operating temperature T of the heat dissipation structure opc1 ΔTc of the thermosensitive structure induced by thermal coupling; and at the evaluation temperature T E =T nom +ΔT c1 The performance of the thermosensitive structure was evaluated below.

[0255] In some embodiments, the above method also includes the following additional operations: identifying a second heat dissipation structure within a second thermal coupling range of the thermosensitive structure; calculating an operating temperature T of the second heat dissipation structure; opc2 ; Calculated by and at operating temperature T opc2 The second heat dissipation structure is thermally coupled and the ΔT induced by the thermal sensitive structure c2 ; and at the evaluation temperature T E =T nom +ΔT c1 +ΔT c2 Evaluation of heat-sensitive structures was carried out under

[0256] In some embodiments, in the above method, the thermally sensitive structure is a FinFET device; and performing the performance evaluation includes performing a performance analysis on the FinFET device.

[0257] In some embodiments, in the above method, the first thermal coupling range and the second thermal coupling range are different.

[0258] In some embodiments, in the above method, the nominal temperature T is calculated nom Includes the self-heating effect ΔT on the thermosensitive structure and the ambient temperature condition T Env The analysis of T nom =T Env +ΔT.

[0259] In some embodiments, in the above method, the first heat dissipation structure is an active region.

[0260] In some embodiments, in the above method, the first heat dissipation structure is a part of the metal pattern.

[0261] In some embodiments, the method also includes the following additional operations: obtaining design data corresponding to the integrated circuit design from an integrated circuit design database; and analyzing the design data to identify the thermally sensitive structure and the first heat dissipation structure.

[0262] In some embodiments, the method also includes the following additional operations: identifying a plurality of conductive layers in the integrated circuit design; and obtaining a plurality of thermal coefficients associated with each of the conductive layers, wherein the thermal coefficients include derating factors, layer effects, and temperature distributions.

[0263] In some embodiments, the thermally sensitive structure is a FinFET device and the performance evaluation includes performing a performance analysis on the FinFET device. In some embodiments, the first thermal coupling range and the second thermal coupling range are different. Some embodiments of the method will also include the following additional operations: analyzing the self-heating effect ΔT of the thermally sensitive structure and the ambient temperature condition T Env To calculate the nominal temperature T nom , where T nom =T Env+ΔT. In some embodiments, the first heat dissipation structure is a portion of an oxide defined (OD) region or a metal pattern. Some embodiments of the method will also include the following additional operations: obtaining design data corresponding to the integrated circuit design from a database of integrated circuit designs and analyzing the design data to identify a thermally sensitive structure and a first heat dissipation structure within the integrated circuit design layout; identifying a plurality of conductive layers in the integrated circuit design; and obtaining a plurality of thermal coefficients associated with each of the plurality of conductive layers, wherein the thermal coefficients include derating factors, layer effects, and temperature distributions.

[0264] In some embodiments, a method for evaluating a thermally sensitive structure of an integrated circuit design may include the following operations: identifying a thermally sensitive structure having a nominal temperature T nom a thermosensitive structure; identifying a first heat generating structure within a first thermal coupling range of the thermosensitive structure; and calculating an operating temperature T of the heat generating structure. oph ; Calculate the ΔT of the thermosensitive structure induced by thermal coupling with the heat-generating structure h ; Identify the heat dissipation structure within the second thermal coupling range of the thermosensitive structure; calculate the operating temperature T of the heat dissipation structure opc Calculate the ΔT of the heat-sensitive structure induced by thermal coupling with the heat dissipation structure c ; and at the adjusted temperature T E =T nom +ΔT h +ΔT c Thermosensitive structures are evaluated below.

[0265] In some embodiments, in the above methods, the evaluating will include electromigration and / or performance analysis.

[0266] In some embodiments, the method also includes the following additional operations: determining whether the integrated circuit design is evaluated to be qualified; and if the integrated circuit design is evaluated to be qualified, generating a new design finalization file, which is used to manufacture semiconductor devices according to the integrated circuit design.

[0267] The present disclosure provides embodiments of methods for improving EM verification methods in conjunction with analysis of integrated circuit designs by taking into account SHE and thermal coupling between heat generating structures (e.g., FinFET elements) and temperature sensitive structures (i.e., conductive lines) to provide a more accurate estimate of the performance and lifetime of semiconductor elements manufactured according to such integrated circuit designs. Although the subject matter has been described in terms of exemplary embodiments, the invention is not limited thereto. Rather, the appended claims should be broadly interpreted to include other variations and embodiments that may be made by those skilled in the art.

[0268] The features of several embodiments have been previously summarized so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they may readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for evaluating a heat-sensitive structure, characterized in that: include: A thermally sensitive structure is identified in an integrated circuit design layout, the thermally sensitive structure having a nominal temperature T nom ; Identifying a first heat generating structure within a thermal coupling distance of the thermosensitive structure; Calculate an operating temperature T of the first heating structure oph1 ; Calculated by the operating temperature T oph1 The first heat generating structure is thermally coupled to the thermosensitive structure and induces a temperature rise ΔT of the thermosensitive structure. h1 ;as well as At an evaluation temperature T E =T nom +ΔT h1 The thermosensitive structure was evaluated below.

2. The method of evaluating the thermosensitive structure as claimed in claim 1, further comprising: Identifying a second heat generating structure within the thermal coupling range of the thermosensitive structure; Calculate an operating temperature T of the second heating structure oph2 ; Calculated by the operating temperature T oph2 The second heat generating structure is thermally coupled to induce a temperature rise ΔT of the thermosensitive structure. h2 ;as well as At the evaluation temperature T E =T nom +ΔT h1 +ΔT h2 The thermosensitive structure was evaluated below.

3. The method for evaluating the heat-sensitive structure as claimed in claim 1, wherein the heat-sensitive structure comprises a conductive circuit, and Evaluation of the thermosensitive structure includes: An electromigration analysis is performed on the conductive line. 4 . The method of evaluating the thermally sensitive structure as claimed in claim 1 , wherein the first heat generating structure is a FinFET structure. 5 . The method for evaluating the thermally sensitive structure as claimed in claim 2 , wherein the second heat generating structure is a high resistance structure.

6. The method for evaluating the heat-sensitive structure as claimed in claim 2, wherein the second heat-generating structure is a non-metal.

7. The method of evaluating the heat-sensitive structure as claimed in claim 2, further comprising: Identifying a first heat sink within the thermal coupling range of the thermosensitive structure; Calculate an operating temperature T of the first heat dissipation element opc1 ; Calculated by the operating temperature T opc1 The first heat dissipation element is thermally coupled to induce a temperature ΔT of the thermosensitive structure c1 ;as well as At the evaluation temperature T E =T nom +ΔT h1 +ΔT h2 +ΔT c1 The thermosensitive structure was evaluated below.

8. The method of evaluating the thermosensitive structure as claimed in claim 1, further comprising: verifying that the thermosensitive structure qualifies for the evaluation; and A semiconductor device is manufactured according to the integrated circuit design layout.

9. A method for evaluating a thermally sensitive structure of an integrated circuit design, characterized in that: Include: identifying the heat-sensitive structure; Calculate a nominal temperature T nom ; Identifying a first heat dissipation structure within a first thermal coupling distance of the thermosensitive structure; Calculate the operating temperature T of the heat dissipation structure opc1 ; Calculate the operating temperature T of the heat dissipation structure by opc1 The temperature ΔT of the thermosensitive structure induced by thermal coupling c1 ;as well as At an evaluation temperature T E =T nom +ΔT c1 A performance evaluation of the thermosensitive structure is performed below.

10. The method of evaluating the thermally sensitive structure of the integrated circuit design as claimed in claim 9, further comprising: Identifying a second heat dissipation structure within a second thermal coupling distance of the thermosensitive structure; Calculate an operating temperature T of the second heat dissipation structure opc2 ; Calculated by the operating temperature T opc2 The second heat dissipation structure is thermally coupled to induce a temperature ΔT of the thermosensitive structure c2 ;as well as At the evaluation temperature T E =T nom +ΔT c1 +ΔT c2 The thermosensitive structure was evaluated below.

11. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 9, wherein the thermally sensitive structure is a FinFET device; and The performance evaluation includes: A performance analysis of the FinFET device is performed. 12 . The method of claim 10 , wherein the first thermal coupling distance and the second thermal coupling distance are different.

13. The method of evaluating the thermally sensitive structure of the integrated circuit design as claimed in claim 10, wherein the nominal temperature T is calculated nom include: A self-heating effect ΔT of the thermosensitive structure and multiple ambient temperature conditions T Env An analysis of nom =T Env +ΔT.

14. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 9, wherein the first heat dissipation structure is an active region. 15 . The method of evaluating the thermally sensitive structure of the integrated circuit design as claimed in claim 9 , wherein the first heat dissipation structure is a portion of a metal pattern.

16. The method of evaluating the thermally sensitive structure of the integrated circuit design as claimed in claim 9, further comprising: Obtaining design data corresponding to the integrated circuit design from an integrated circuit design database; and The design data is analyzed to identify the thermally sensitive structure and the first heat dissipation structure.

17. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 10, further comprising: identifying a plurality of conductive layers in the integrated circuit design; and A plurality of thermal coefficients associated with each of the plurality of conductive layers are obtained, wherein the plurality of thermal coefficients include a derating factor, a layer effect, and a temperature distribution.

18. A method for evaluating a thermally sensitive structure of an integrated circuit design, characterized in that: Include: Identify a nominal temperature T nom A heat-sensitive structure; Identifying a first heat generating structure within a first thermal coupling distance of the thermosensitive structure; Calculate an operating temperature T of the heat generating structure oph ; Calculate a temperature ΔT of the thermosensitive structure induced by thermal coupling with the first heat generating structure h ; Identifying a heat dissipation structure within a second thermal coupling distance of the thermosensitive structure; Calculate an operating temperature T of the heat dissipation structure opc ; Calculate a temperature ΔT of the heat-sensitive structure induced by thermal coupling with the heat dissipation structure c ; as well as At a regulated temperature T E =T nom +ΔT h +ΔT c The following is an evaluation of the thermosensitive structure.

19. The method of claim 18, wherein the evaluation comprises an electromigration analysis.

20. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 19, further comprising: It is determined whether the integrated circuit design passes the electromigration analysis, and if the integrated circuit design passes, a new design finalization file is generated, and the new design finalization file is used to manufacture a semiconductor device according to the integrated circuit design.

21. A method for evaluating a heat-sensitive structure, characterized in that Include: A thermally sensitive structure is identified in an integrated circuit design layout, the thermally sensitive structure having a nominal operating temperature T nom ; Calculate the nominal operating temperature T in a thermally coupled volume oph1 A nominal operating temperature increase ΔT of the thermosensitive structure induced by thermal coupling between a first heat generating structure and the thermosensitive structure h1 ; At an evaluation temperature T E =T nom +ΔT h1 Evaluating a functional parameter of the thermosensitive structure; as well as The thermal coupling volume further includes a nominal operating temperature T oph2 A second heating structure.

22. The method of evaluating the thermosensitive structure of claim 21, further comprising: Calculate a nominal operating temperature rise ΔT of the thermosensitive structure induced by thermal coupling between the second heat generating structure and the thermosensitive structure h2 ;as well as At the evaluation temperature T E =T nom +ΔT h2 The thermosensitive structure was evaluated below.

23. The method of evaluating the thermosensitive structure of claim 21, further comprising: identifying a conductive trace as the heat-sensitive structure; and The thermally sensitive structure is evaluated, including an electromigration analysis of the conductive lines.

24. The method of evaluating the thermosensitive structure of claim 21, further comprising: A fin field effect transistor structure is identified as the first heat generating structure.

25. The method of evaluating the thermosensitive structure of claim 22, further comprising: A high resistance structure is identified as the second heat generating structure.

26. The method of evaluating the thermosensitive structure of claim 22, further comprising: A non-metallic structure is identified as the second heat generating structure.

27. The method of evaluating the thermosensitive structure of claim 22, further comprising: Calculate the nominal operating temperature T in the thermal coupling volume opc1 A nominal operating temperature of the thermally sensitive structure is reduced by ΔT induced by thermal coupling between a first heat dissipation structure and the thermally sensitive structure. c1 ;as well as At the evaluation temperature T E =T nom +ΔT h1 +ΔT h2 +ΔT c1 The thermosensitive structure was evaluated below.

28. The method of evaluating the thermosensitive structure of claim 21, further comprising: verifying that the thermosensitive structure qualifies for the evaluation; and A semiconductor device is manufactured according to the integrated circuit design layout.

29. A method for evaluating a thermally sensitive structure of an integrated circuit design, characterized in that: Include: identifying the heat-sensitive structure; Calculate a nominal operating temperature T of the thermal sensitive structure under a first test program applied to the integrated circuit design nom ; identifying a first heat dissipation structure within a first thermal coupling volume of the thermally sensitive structure; Calculate a nominal operating temperature T of the first heat dissipation structure when the first test program is applied to the integrated circuit design opc1 ; identifying a second heat dissipation structure within a second thermal coupling volume of the thermally sensitive structure; Calculate an operating temperature T of the second heat dissipation structure opc2 ; Calculated by the nominal operating temperature T opc1 The first heat dissipation structure and the nominal operating temperature T nom The temperature ΔT of the thermosensitive structure is induced by the thermal coupling between the thermosensitive structure c1 ;as well as At an evaluation temperature T E The performance of the thermosensitive structure is evaluated at a temperature T E At least equal to T nom +ΔT c1 .

30. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 29, further comprising: Calculate the thermal coupling to the operating temperature T opc2 The second heat dissipation structure induces a temperature ΔT of the thermosensitive structure c2 ;as well as At the evaluation temperature T E =T nom +ΔT c1 +ΔT c2 The performance evaluation of the thermosensitive structure is carried out below.

31. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 29, further comprising: identifying a FinFET device as a thermal coupling structure; and The performance evaluation includes performing a performance analysis on the FinFET device.

32. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 30, further comprising: defining a first thermocouple volume; and Define a second thermocouple volume; The volume of the first thermocouple is not equal to the volume of the second thermocouple.

33. The method of evaluating the thermally sensitive structure of the integrated circuit design as claimed in claim 30, wherein the nominal operating temperature T is calculated nom include: A self-heating effect ΔT of the thermosensitive structure and multiple ambient temperature conditions T Env An analysis of nom =T Env +ΔT.

34. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 29, further comprising: An active area is identified as the first heat dissipation structure.

35. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 29, further comprising: A portion of a metal pattern is identified as the first heat dissipation structure.

36. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 29, further comprising: Obtaining design data corresponding to the integrated circuit design from an integrated circuit design database; and The design data is analyzed to identify the thermally sensitive structure and the first heat dissipation structure.

37. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 30, further comprising: identifying a plurality of conductive layers in the integrated circuit design; and A plurality of thermal coefficients associated with each of the plurality of conductive layers are obtained, wherein the plurality of thermal coefficients include a derating factor, a layer effect, and a temperature distribution.

38. A method for evaluating a thermally sensitive structure of an integrated circuit design, characterized in that: Include: Identify a nominal temperature T nom A heat-sensitive structure; running a pseudo three-dimensional analysis of any structures and materials falling within the range of the thermally sensitive structure to define a thermal coupling volume; identifying a heat generating structure within the thermal coupling volume of the thermosensitive structure; Calculate an operating temperature T of the heat generating structure oph ; Calculate a temperature ΔT of the heat-sensitive structure induced by thermal coupling with the heat-generating structure h ; identifying a heat dissipation structure within the thermal coupling volume of the thermally sensitive structure; Calculate an operating temperature T of the heat dissipation structure opc ; Calculate a temperature ΔT of the heat-sensitive structure induced by thermal coupling with the heat dissipation structure c ; At a regulated temperature T E =T nom +ΔT h +ΔT c An evaluation is performed on the heat-sensitive structure; and After the thermal coupling structure passes the evaluation, design finalization data for generating a mask is generated.

39. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 38, further comprising: An electromigration analysis was performed as the evaluation of the thermal sensitive structure.

40. The method of evaluating the thermally sensitive structure of the integrated circuit design of claim 39, further comprising: It is determined whether the integrated circuit design passes the electromigration analysis, and if the integrated circuit design passes, a new design finalization file is generated, and the new design finalization file is used to manufacture a semiconductor device according to the integrated circuit design.

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