Integrated Ultra-Long Time Constant Time Measurement Device and Manufacturing Process

Abstract

Embodiments of the present disclosure relate to an integrated ultra-long time constant time measurement device and a manufacturing process. An integrated ultra-long time constant time measurement device includes basic capacitive elements connected in series. Each basic capacitive element is formed by a stack of a first conductive region, a dielectric layer, and a second conductive region, and the dielectric layer has a thickness suitable for allowing charges to flow through direct tunneling. The first conductive region is received in a trench extending downward from the front surface of the semiconductor substrate into the semiconductor substrate. The dielectric layer is located on the first surface of the semiconductor substrate, particularly on a portion of the first conductive region in the trench. The second conductive region is located on the dielectric layer.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to French Patent Application No. 1857842, filed on Aug. 31, 2018, the content of which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments and implementations generally relate to integrated circuits and, more particularly, to the fabrication of ultra-long time constant time measurement devices. Background Art

[0004] Ultra-long time constant (ULTC) time measurement circuits are qualified to measure application ranges on the order of tens of minutes to several hours.

[0005] In many applications, it is desirable to have information representing the time elapsed between two events, whether its precise or approximate measurement.

[0006] An example of this application relates to anti-fraud measures, where the system is locked for a long enough time to make it a deterrent. These preventive measures apply to semi-invasive attacks (e.g., analytical techniques using fault injection) or non-invasive attacks (such as brute force attacks or side channel attacks). Generally, this type of attack is based on self-learning methods that implement multiple repeated iterations and precise synchronization.

[0007] In this case, locking the system for a duration of about one hour or several tens of minutes is sufficient to deter fraudsters from using this method.

[0008] This type of prevention by locking the system has the advantages of being temporary and non-destructive, for example in the case where a fault or operating error is detected as a fraud attempt.

[0009] Of course, it is desirable that the deactivation of the system does not disrupt the operation of measuring the locked duration.

[0010] For example, in U.S. Patent No. 8,872,177 (see also FR 2981190A1), which is incorporated herein by reference, an electronic device has been proposed, where the time elapsed between two events is determined by measuring the remaining charge of a pre-charged capacitive storage element connected to a series of charge flow capacitive elements having leakage in a dielectric space. The remaining charge of the capacitive storage element represents the time elapsed during discharge.

[0011] According to the teachings of U.S. Patent No. 8,872,177, the dielectric space of the capacitive element includes a thick dielectric layer that does not leak and a thinner leakage region to allow charge to leak through tunneling, and is thus produced for the purpose of controlling the size of the above-mentioned leakage region.

[0012] One disadvantage is that, in practice, the leakage region is surrounded by a thick dielectric layer, especially a silicon ONO (oxide nitride oxide) layer, which uses a non-negligible total substrate area and imposes high granularity design rules, i.e., its minimum size is relatively large and its example volume is large.

[0013] However, it is desirable to reduce the footprint of the integrated circuit.

[0014] Therefore, there is a need for an ultra-long time constant time measurement device and measure that can measure the passage of time on the order of tens of minutes to several days without a power supply, is substantially independent of temperature, and also has a minimized coverage area. SUMMARY OF THE INVENTION

[0015] According to one aspect, an integrated ultra-long time constant time measurement device is proposed, which includes a plurality of basic capacitive elements connected in series, a capacitive storage element, the capacitive storage element being connected to one end of the series-connected basic capacitive elements and capable of being charged, the series-connected basic capacitive elements being configured to discharge the charged capacitive storage element and transmit a physical quantity to at least one node of the series-connected basic capacitive elements, the physical quantity representing the discharge of the capacitive storage element and the duration elapsed between the start of the discharge operation of the capacitive storage element and the moment when the physical quantity is transmitted, wherein each basic capacitive element includes a stack of a first conductive region, a dielectric layer, and a second conductive region, the dielectric layer having a thickness suitable for allowing charge to flow through direct tunneling effect, wherein the first conductive region is received in a trench extending downward from the front surface of the semiconductor substrate into the substrate, the dielectric layer is located on the front surface of the substrate, and the second conductive region is located on the dielectric layer.

[0016] Therefore, since the entire interface of the dielectric layer positioned between the two conductive regions has a thickness suitable for allowing charge to cycle through direct tunneling effect, such an embodiment does not cause a large area loss. Specifically, an area of 1 / 3.5 relative to the above-mentioned reference ultra-long time constant time measurement device technology has been obtained.

[0017] Furthermore, it is actually advantageous to measure the quantity representing the discharge of the capacitive storage element at at least one node of the series-connected basic capacitive elements rather than directly at the terminals of the capacitive storage element.

[0018] According to one embodiment, the above-mentioned stack of the first conductive region, the dielectric layer, and the second conductive region of each basic capacitive element is positioned facing a part of the trench that houses the first conductive region on the above-mentioned front surface.

[0019] This allows for the use of the area to be optimized.

[0020] According to one embodiment, the basic capacitive elements are alternately electrically connected in series with each other through a second conductive region shared by two consecutive basic capacitive elements or through a first conductive region shared by two consecutive basic capacitive elements.

[0021] This allows for the use of the area to be optimized.

[0022] According to one embodiment in which the semiconductor substrate includes electrically isolated regions extending vertically from the front surface into the substrate, the above-mentioned trenches accommodating the first conductive regions of each basic capacitive element pass through the electrically isolated regions.

[0023] This makes it possible, for example, to prevent current leakage into the substrate without providing another thickness of dielectric facing the substrate for this purpose.

[0024] According to one embodiment, a plurality of basic capacitive elements connected in series are positioned in a semiconductor well that is accommodated in the substrate and includes a first contact and a second contact, which are electrically connected through a circuit path passing through the well, the circuit path including a portion positioned between the bottom of the trench and the bottom of the well, and the device further includes a detection circuit configured to detect an electrical discontinuity in the well between the first contact and the second contact.

[0025] Thus, if an electrical discontinuity is detected in the well between the first contact and the second contact, which would indicate etching of the substrate from the back surface, the detection circuit will be able to, for example, command preventive or disruptive countermeasures against such etching.

[0026] There is proposed a method for measuring a duration, which includes the following operations: charging a capacitive storage element of the device as described above, discharging the charged capacitive storage element through a plurality of basic capacitive elements connected in series, and acquiring the above-mentioned physical quantity at at least one node of the plurality of basic capacitive elements connected in series, the physical quantity representing the discharge of the capacitive storage element and representing the above-mentioned duration elapsed between the start of the discharge operation of the capacitive storage element and the moment when the physical quantity is acquired.

[0027] According to another aspect, there is proposed a method for manufacturing an integrated ultra-long time constant time measurement device, which includes: an operation of forming trenches extending downward from the front surface of the semiconductor substrate into the substrate; an operation of forming first conductive regions accommodated in the above-mentioned trenches; an operation of forming a dielectric layer on the front surface, the dielectric layer having a thickness suitable for allowing charge to flow through direct tunneling; an operation of forming second conductive regions on the above-mentioned dielectric layer, the corresponding stacks of the first conductive regions, the dielectric layer, and the second conductive regions forming a plurality of basic capacitive elements connected in series, and the process further includes: an operation of forming a capacitive storage element connected to one end of the plurality of basic capacitive elements connected in series.

[0028] According to one implementation, the operations of forming the dielectric layer and the second conductive region are positioned facing a corresponding portion of the width of the trench that houses the first conductive region on the front side.

[0029] According to one implementation, the operations of forming the trench and the corresponding first conductive region and the operations of forming the dielectric layer and the corresponding second conductive region are positioned relative to each other such that a plurality of basic capacitive elements electrically connected in series with each other are alternately formed through the second conductive region shared by two consecutive basic capacitive elements or through the first conductive region shared by two consecutive basic capacitive elements.

[0030] According to one implementation, the process includes an operation of forming an electrically isolated region extending vertically from the front side into the substrate, and the operation of forming the trench that houses the first conductive region is implemented through the electrically isolated region.

[0031] According to one implementation, the process includes a previous operation of forming a semiconductor well in the substrate, and operations of forming a first contact and a second contact, the contacts being electrically connected through a circuit path passing through the well, the circuit path including a portion positioned between the bottom of the trench and the bottom of the well, and the process further includes an operation of detecting an electrical discontinuity in the well between the first contact and the second contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Other advantages and features of the present invention will become apparent by studying the detailed description of the completely non-limiting embodiments and implementations and the drawings, in which:

[0033] Figure 1 An embodiment of an ultra-long time constant time measurement device is shown;

[0034] Figure 2 is Figure 1 A circuit diagram of the application of the shown embodiment;

[0035] Figure 3 and 4 A variant of the ultra-long time constant time measurement device is shown, which includes a detection circuit configured to detect an electrical discontinuity; and

[0036] Figure 5 Shows the manufacturing steps for manufacturing a time measurement device such as Figures 1 - 4 The one shown. DETAILED DESCRIPTION

[0037] Figure 1 An example of an embodiment of an ultra-long time constant time measurement device 10 is shown.

[0038] Device 10 belongs to an integrated circuit fabricated on a semiconductor substrate 1 (e.g., a p-doped silicon substrate). In the present specification, device 10 is formed in a portion of substrate 1 that is doped with a conductive type opposite to that of the remainder of the substrate. This doped portion forms a semiconductor well 2, i.e., a single well; in this case, the term "substrate" may be hereinafter referred to in order to denote the portion located in well 2, particularly with respect to the electrical isolation regions STI and trenches TR.

[0039] The standard orthogonal coordinate system is oriented in the vertical direction Z, the horizontal direction X, and the direction Y perpendicular to the cross-section (XZ) of the figure. Figure 1 。

[0040] Device 10 includes a plurality of basic capacitive elements C31, C32, C33, ……, C3n connected in series electrically.

[0041] Each basic capacitive element C31 - C3n includes a stack of a first conductive region P1, a dielectric layer DI, and a second conductive region P2. For example, the first conductive region P1 and the second conductive region P2 may be formed of conductive polysilicon, and the dielectric layer DI is made of silicon oxide.

[0042] The thickness of the dielectric layer DI is appropriate, particularly according to the dielectric constant of the material used, to allow charges to circulate through direct tunneling effect, particularly under the conditions described hereinafter with reference to Figure 2 the conditions described.

[0043] In each basic capacitive element C31 - C3n, the first conductive region P1 is received in a trench TR. Each trench TR extends from the front face FA of the semiconductor substrate downward (in the Z direction) into the substrate, while the dielectric layer DI is located on the front face FA of the substrate, and the second conductive region P2 is located on the dielectric layer DI.

[0044] In the present specification, the front face FA is located in the XY plane.

[0045] Each trench TR includes an insulating sheath OX on its sides and bottom.

[0046] Different from the prior art, such an embodiment can be obtained by following the design rules for the logic part of the integrated circuit, which limit, for example, the width of the strip of the second conductive region P2 to 0.04 μm and the spacing between two such strips to 0.10 μm, and limit the width of the trench TR to 0.11 μm and the spacing between two trenches to 0.11 μm. According to these design rules, the area of the embodiment of the basic capacitive element is less than 0.1 μm 2 , which can be expressed as an area that is 1 / 3.5 of the area of the basic capacitive element based on the prior art.

[0047] InFigure 1 In the example shown, the stack of the first conductive region P1, the dielectric layer DI, and the second conductive region P2 of each basic capacitive element C31 - C3n is positioned facing a part of the width of the trench TR that houses the first conductive region P1. Here, the width W of the "exposed" surface of the first conductive region P1 positioned on the front face FA is represented. Specifically, the dielectric layer and the second conductive region P2 are stacked on the peripheral portion at the surface of the first conductive region P1 in the direction X of the width W.

[0048] In this example, this allows the above-mentioned plurality of basic capacitive elements to be electrically connected in series with each other while optimizing the amount of area consumed. The basic capacitive elements are alternately connected via the second conductive region P2 shared by two consecutive basic capacitive elements C3i - 1, C3i (where i is an integer such that 2 ≤ i ≤ n - 1) or via the first conductive region P1 shared by two consecutive basic capacitive elements C3i, C3i + 1 (where i is an integer such that 2 ≤ i ≤ n - 1).

[0049] Specifically, the basic capacitive element C31 is directly connected in series with the basic capacitive element C32 via the second conductive region P2 shared with the basic capacitive element C32 (i.e., the region P2 provided with the contact node F1 here). Next, the basic capacitive element C32 is directly connected in series with the basic capacitive element C33 via the first conductive region P1 shared with the basic capacitive element C33 (i.e., the region P1 provided with the contact node F2). The consecutive basic capacitive elements are connected to each other in this way via the common second conductive region P2 or the first conductive region P1. Between two consecutive basic capacitive elements C3j, C3j + 1 (where j is an integer such that 1 ≤ j ≤ n - 1), each node of the plurality of basic capacitive elements connected in series here includes a contact node Fj, which is intended to transmit a measured value of the charge of the basic capacitive elements C31 - C3n.

[0050] A configuration can be envisaged in which the stack of the first conductive region P1, the dielectric layer DI, and the second conductive region P2 of each basic capacitive element C31 - C3n is positioned facing the entire width W of the trench TR in the X direction at the surface of the first conductive region P1. Thus, the similar stack of the next basic capacitive element is offset along the direction Y on the same first conductive region P1. For example, when viewed from above in the plane XY, this configuration defines a path that takes a pleated or stepped shape or any other shape.

[0051] The basic capacitive elements C31 - C3n connected to each other in this way form a series of capacitive elements C3, also known as the "current element C3". A first contact node 17 is formed at one end of the series of capacitive elements C3, and a second contact node 18 is formed at the other end of the series of capacitive elements C3.

[0052] The meaning of "fabricating a contact node" is, for example, the silicidation of a silicon film to allow ohmic coupling to be applied thereto.

[0053] Furthermore, in this embodiment, the semiconductor substrate 1 includes an electrically isolated region STI extending vertically (in the Z direction) into the substrate from the front face FA. The electrically isolated region STI is, for example, a shallow trench isolation. Thus, the trench TR accommodating the first conductive region P1 of each basic capacitive element passes through the electrically isolated region STI.

[0054] The trench TR extends further vertically downward into the substrate 1 than the electrically isolated region STI. Thus, the isolation envelope OX can be positioned, for example, only on the part of the side face of the trench TR facing the substrate 1.

[0055] Figure 2 is a circuit diagram of an application of the device 10 referred to above Figure 1 described, Figure 1 and 2 common reference numerals in denote the same elements.

[0056] The device 10 also particularly includes a capacitive storage element C1 that can be charged and is connected to the first end 17 of the series of capacitive elements C3 of the basic capacitive element. The series of capacitive elements C3 is configured to discharge the charged capacitive storage element C1 and transmit a measured value representing the discharge of the capacitive storage element C1 to at least one of the nodes F1 - Fn - 1 of the series of capacitive elements C3.

[0057] Thus, the device 10 includes a first capacitive element C1, a first electrode 11 of the first capacitive element C1 is connected to a floating node F, and a second electrode 12 of the first capacitive element C1 is connected to a terminal 13 for applying a potential. The device 10 also includes a second capacitive element C2, a first electrode 14 of the second capacitive element C2 is connected to the node F, and a second electrode 15 of the second capacitive element C2 is connected to a terminal 16 for applying a potential.

[0058] The circuit 10 includes a series of capacitive elements C3 having elementary capacitive elements C31, C32, C33, ……, C3n. A first node 17 of the series of capacitive elements C3 is connected to node F at one end of the series of capacitive elements C3, and a second node 18 of the series of capacitive elements C3 is connected to a terminal 19 for applying a potential at the other end of the series of capacitive elements C3. The dielectric space of each elementary capacitive element C31 - C3n is designed to exhibit non - negligible leakage over time due to its dielectric constant and / or its thickness. The capacitive element C1 has a charge - holding capacity higher than the equivalent capacitance of the series of capacitive elements C3, and the capacitive element C2 has a charge - holding capacity higher than that of the series of capacitive elements C3 but lower than that of the element C1.

[0059] The inventors have observed that when elementary capacitive elements are connected in series, when leaking through tunneling, the resistance seen by the charge increases proportionally to the number of elementary capacitive elements, resulting in an exponential decrease in the speed of discharging the storage element C1.

[0060] One function of the capacitive element C1 (storage element) is to store charge. One function of the series of capacitive elements C3 having elementary capacitive elements C31 - C3n (flow elements) is to discharge the storage element C1 relatively slowly with respect to a direct connection of its electrode 11 to ground. One function of the capacitive element C2 is to allow charge to be injected into the capacitive element C1 while avoiding the stress of directly charging the storage element C1 by the flow element C3 by applying a supply voltage between node F and terminal 13.

[0061] In the step of initializing the charge - holding phase, terminals 13 and 19 are at a reference potential, for example, ground potential. A high supply potential (positive voltage with respect to ground) is applied to terminal 16, causing the capacitive element C1 to charge.

[0062] As a variant, to charge the element C1, terminal 19 can be grounded, and terminals 16 and 13 are placed at positive and negative potentials with respect to ground, respectively.

[0063] When the supply voltage is no longer applied between terminals 16 and 13, for example, when the circuit is no longer powered, the storage element C1 discharges in a controlled manner (relatively slowly) through the flow element C3. It should be noted that a controlled discharge phase can also be provided when the circuit is still powered.

[0064] During the discharge phase, terminals 13, 16, and 19 can be suspended or placed at the same reference potential, for example, ground potential.

[0065] In the reading step, after the discharge phase, the residual charge of the storage element C1 is measured (the device must be powered for the measurement operation). The residual charge of the element C1 is considered to represent the time elapsed between the end of the initialization step and the reading step.

[0066] If needed, a re-initialization (reset) step can be provided to fully discharge the storage element C1 through the capacitive element C2. For this purpose, terminals 19 and 16 can be grounded, and terminal 13 is at a high power supply potential. As a variant, terminal 19 can be grounded, and terminals 13 and 16 are placed at positive and negative potentials respectively with respect to ground.

[0067] An accelerated controlled discharge phase can also be provided for discharging the storage element C1 (through the flow element C3), for example for testing the time measurement circuit. For this purpose, terminal 19 can be grounded, and terminals 13 and 16 can be biased at the same potential that is positive with respect to ground, for example a potential between the ground potential and the high power supply potential.

[0068] In Figure 2 the example, a plurality of comparators CPj (where j is an integer such that 1 ≤ j ≤ n - 1) are connected to the intermediate node Fj of the flow element C3. In the reading phase, each comparator CPj receives as input the potential of the node Fj shared by the capacitive elements C3j and C3j+1, and compares this potential with a threshold. In an example of an embodiment, the same comparison threshold is set for all comparators, for example, when the storage element C1 is charged, this threshold is lower than the potential adopted by the node Fn-1. Each comparator CPj transmits binary information through the output terminal Oj. When the storage element C1 discharges, the comparators will switch one by one starting from the comparator CPn-1. The binary word formed by the set of binary information available at the terminals Oj (n - 1 bits) provides information related to the charging state of the storage element C1, and thus provides information related to the time elapsed since the start of the discharge phase of the element C1. Compared with the circuit for measuring the residual charge of the terminal directly connected to the element C1, this measurement circuit has the advantage of simple design.

[0069] For the circuit 10 to operate properly, the node F and the intermediate nodes Fj are preferably floating nodes, that is, nodes separated from any terminal to which an electric potential is applied by a dielectric space, rather than nodes directly connected to an unisolated region of the semiconductor substrate of the chip (in this case, leakage into the substrate may dominate over leakage through the flow element C3).

[0070] As an example of an embodiment, the dielectric spaces of various capacitive elements C1, C2, C3 can be formed of silicon oxide. In this example, the thickness of the dielectric layer of the capacitive storage element C1 can be between 150 and 200, the thickness of the dielectric layer of the capacitive element C2 can be between 70 and 100, and the thickness of the dielectric layer of the basic capacitive charge flow elements C31 - C3n can be on the order of 20.

[0071] In any case, due to the thickness of the dielectrics used, the capacitive elements C1 and C2 exhibit negligible parasitic leakage (leakage through their dielectric spaces) relative to the flow element C3.

[0072] Figure 3 and 4 Two variants of an example of an embodiment are shown, in which the ultra-long time constant time measurement device 10 includes a detection circuit DET configured to detect an electrical discontinuity in the well 2 between a first contact 301 / 401 and a second contact 302 / 402.

[0073] Specifically, since the time measurement device can be used to prevent fraud attempts through reverse engineering, such as attempts to retrieve proprietary information, this example of an embodiment adds additional protection to the device, for example in the case where a fraudster has detected the time measurement device and grounded the structure to cause it to discharge instantaneously.

[0074] In this embodiment, the device 10 is located in a semiconductor well 2 accommodated in a semiconductor substrate 1.

[0075] In Figure 3 variant, the semiconductor well 2 is a single well, i.e., a well having a conductivity type opposite to that of the semiconductor substrate 1. Thus, the well 2 and the substrate 1 are electrically isolated by a pn junction that particularly defines the bottom of the well 2.

[0076] In Figure 4 variant, the semiconductor well 2 is a triple well, i.e., a well having the same conductivity type as the semiconductor substrate 1, such as p-type conductivity. The well 2 and the substrate 1 are vertically electrically isolated by a buried semiconductor layer NISO of the opposite conductivity type (e.g., n-type conductivity) and laterally electrically isolated by a semiconductor axis NW that also has the opposite conductivity type. Thus, the p-n and n-p (or n-p and p-n, depending on the fully reverse conductivity type) junctions allow the well 2 and the substrate 1 to be electrically isolated for both positive and negative biasing. The p-n junction between the well 2 and the buried semiconductor region 5 defines the bottom of the well 2.

[0077] In both variants, the semiconductor well 2 includes a first contact 301 / 401 and a second contact 302 / 402 that are electrically connected via a circuit path through the well 2. The circuit path passes between the bottom of the trench TR that houses the first conductive region P1 and the bottom of the corresponding well 2. Thus, the circuit path includes a portion that is positioned between the bottom of the trench TR and the bottom of the well 2.

[0078] If etching 310 / 410 is performed from the back side of the substrate 1 down to near the bottom of the trench TR, the circuit will be damaged. Thus, measuring the continuity between the first contact 301 / 401 and the second contact 302 / 402 allows such etching 310 / 410 to be easily detected.

[0079] To this end, the detection circuit DET is configured to measure the continuity between the first contact 301 / 401 and the second contact 302 / 102. Thus, the detection circuit DET is capable of generating a discontinuity revealing signal, for example when an attack from the back side is performed.

[0080] For example, the discontinuity revealing signal can be used to trigger a countermeasure device for preventing such an attack.

[0081] Figure 5 Schematically shows the manufacturing steps of a time measurement device such as described above with reference to Figures 1 - 4 the description.

[0082] In an initial step 51, for example, the well 2 is prepared in a semiconductor substrate 1 having a front side FA.

[0083] Step 52 includes the operation of forming an electrically isolated region STI that extends vertically from the front side FA into the substrate 1. For example, this step is implemented according to a process for forming shallow trench isolation.

[0084] Step 53 includes the operation of forming a trench TR that extends from the front side FA of the semiconductor substrate down into the substrate 1. The operation of forming the trench TR is achieved through the electrically isolated region STI.

[0085] Step 53 may include a dry etching for etching the trench TR in the well 2 of the substrate 1. The design rules controlling this etching 53 may, for example, define a minimum width of the trench as 0.11 μm and a minimum spacing between two trenches as 0.11 μm.

[0086] Step 53 may further include the operation of forming an insulating envelope OX at least on portions of the bottom and sides of the trench surrounded by the well 2.

[0087] Step 54 includes an operation of forming a first conductive region P1 accommodated in the above-described trench TR. The operation of forming the first conductive region P1 may include an operation of depositing polysilicon, followed by a chemical mechanical polishing operation to remove excess material beyond the level of the front face FA.

[0088] Step 55 includes an operation of forming a dielectric layer DI located on the front face FA, particularly positioned on a corresponding portion of the surface facing the first conductive region P1 on the front face FA.

[0089] The thickness of the dielectric layer DI is suitable to allow charge to flow through the direct tunneling effect; for example, the operation of forming the dielectric layer DI may include an operation of growing an oxide layer partially or completely for the gate of a MOS transistor intended for logic operations.

[0090] Step 56 includes an operation of forming a second conductive region P2 located on the above-described dielectric layer DI. The operation of forming the second conductive layer P2 may also include an operation of depositing polysilicon, followed by a dry etching (e.g., the same etching used to define a MOS transistor intended for logic operations). The design rules controlling this operation 53 may, for example, define the minimum width of the strip of the second conductive region P2 as 0.04 μm and the minimum spacing between two strips as 0.10 μm.

[0091] Form individual stacks of the first conductive region P1, the dielectric layer DI, and the second conductive region P2 in order to obtain a plurality of basic capacitive elements C31 - C3n connected in series.

[0092] To this end, steps 53, 54, 55, and 56 may be arranged relative to each other so as to alternately form a plurality of basic capacitive elements C31 - C3n connected in series with each other through the second conductive region P2 shared by two consecutive basic capacitive elements or through the first conductive region P1 shared by two consecutive basic capacitive elements.

[0093] Step 57 also includes an operation of forming a capacitive storage element C1 that can be charged and connected to the first end 17 of the series C3 of basic capacitive elements, thus allowing the acquisition of the Figure 2 ultra-long time constant time measurement device 10 of the type described above.

[0094] In operation, the previously charged capacitive storage element C1 is discharged through the series C3 of basic capacitive elements, and a measured value representing the discharge of the capacitive storage element C1 is provided at at least one node F1 - Fn - 1 of the series of capacitive elements C3, enabling the measurement of a time span on the order of several tens of minutes to several days.

[0095] In addition, the process may also include a prior operation of forming a semiconductor well 2 in the substrate 1 (e.g., in step 51) and an operation of forming first contacts 301, 401 and second contacts 302, 402 electrically connected by a circuit path in the well 2, the circuit path including a portion positioned between the bottom of the trench TR and the bottom of the well 2. Thus, step 58 may include an operation DET of detecting an electrical discontinuity in the well 2 between the first contacts 301 / 401 and the second contacts 302 / 402 so as to enable the disclosure of an attack by etching the integrated circuit from the back side.

[0096] Advantageously, the process may be implemented simultaneously with a process for manufacturing a buried vertical gate transistor, for example, a process for a memory cell belonging to a non-volatile memory. Of course, in the case where the integrated circuit is intended to include a buried vertical gate transistor, this implementation is advantageous, where the process described above with reference to steps 51 to 58 can be implemented independently.

[0097] In the non-volatile memory NVM portion of the same substrate 1 prepared in the initial step 51, an isolation region STI is generated simultaneously with step 52 in step 62.

[0098] Step 63, which is carried out simultaneously with step 53, includes an operation of forming a vertical gate GV trench intended to accommodate a conductive vertical gate region P1, the trench extending from the first face (4) of the substrate 1 down into the substrate 1. Step 63 includes an operation of forming a dielectric envelope on the bottom and sides of the vertical gate GV trench.

[0099] Step 64, which is executed simultaneously with step 54, includes an operation of forming a conductive gate region PG accommodated in the above-mentioned vertical gate GV trench.

[0100] Thus, when the steps of implanting the drain region, particularly at the edge of the vertical gate GV and at the position of the front face 4 of the substrate 1, upstream or downstream, are completed, and when the operation of forming a buried source region in the bottom of the vertical gate GV trench and in the well 2 is completed, a buried vertical gate transistor TEGV is obtained in step 65.

[0101] In addition, the present invention is not limited to these embodiments, but includes all its variants; for example, it is conceivable to use a charge flow device of the proposed type in any circuit suitable for holding charge in order to measure time, rather than as described with reference to Figure 2 described.

Claims

1. An integrated ultra-long time constant time measurement device, comprising: A plurality of basic capacitive elements connected in series, A capacitive storage element, which is connected to one end of the plurality of basic capacitive elements connected in series and is configured to be charged, A semiconductor well, which is accommodated in a semiconductor substrate at a position where the plurality of basic capacitive elements connected in series are located, A first contact and a second contact, which are electrically connected through a circuit path passing through the semiconductor well, and the circuit path includes a portion located between the bottom of a trench and the bottom of the well, A detection circuit, which is configured to detect an electrical discontinuity in the semiconductor well between the first contact and the second contact, Wherein the plurality of basic capacitive elements connected in series are configured to discharge the charged capacitive storage element and transmit a physical quantity to at least one node of the plurality of basic capacitive elements connected in series, the physical quantity representing the amount of discharge of the capacitive storage element and representing the duration elapsed between the start of the discharge operation of the capacitive storage element and the moment when the physical quantity is transmitted, Wherein each basic capacitive element includes: A stack of a first conductive region, a dielectric layer, and a second conductive region, the dielectric layer having a thickness suitable for allowing charge to flow through direct tunneling effect, Wherein the first conductive region is accommodated in a trench extending from the front surface of the semiconductor substrate into the substrate, and Wherein the dielectric layer is located on the front surface of the semiconductor substrate, and the second conductive region is located on the dielectric layer.

2. The device according to claim 1, wherein the stack is positioned facing a part of the width of the trench accommodating the first conductive region on the front surface.

3. The device according to claim 1, wherein the series connection of the plurality of basic capacitive elements is alternately constituted by a second conductive region shared by two consecutive basic capacitive elements and a first conductive region shared by two consecutive basic capacitive elements.

4. The device according to claim 1, wherein the semiconductor substrate includes an electrically isolated region extending vertically from the front surface into the semiconductor substrate, and the trench accommodating the first conductive region of each basic capacitive element passes through the electrically isolated region.

5. A method for measuring a duration, comprising: Charging a capacitive storage element; Discharging the charged capacitive storage element through a plurality of basic capacitive elements connected in series; Obtaining a physical quantity at at least one node of the plurality of basic capacitive elements connected in series, the physical quantity representing the amount of discharge of the capacitive storage element and representing the duration elapsed between the start of the discharge operation of the capacitive storage element and the moment when the physical quantity is transmitted; And Detecting an electrical discontinuity in a semiconductor well between a first contact and a second contact, wherein the semiconductor well is accommodated in a semiconductor substrate at a location where the plurality of basic capacitive elements connected in series are positioned, and wherein the first contact and the second contact are electrically connected by a circuit path passing through the semiconductor well, the circuit path including a portion positioned between the bottom of a trench and the bottom of the well; wherein each basic capacitive element comprises: a stack of a first conductive region, a dielectric layer, and a second conductive region, the dielectric layer having a thickness suitable for allowing charge to flow through direct tunneling; wherein the first conductive region is accommodated in a trench extending from the front side of the semiconductor substrate into the substrate; and wherein the dielectric layer is located on the front side of the semiconductor substrate, and the second conductive region is located on the dielectric layer.

6. A method for manufacturing an integrated ultra-long time constant time measurement device, comprising: forming a semiconductor well in a semiconductor substrate; and forming a first contact and a second contact connected by a circuit path, the circuit path including a portion of the semiconductor well positioned between the bottom of a trench and the bottom of the semiconductor well; forming a trench extending from the front side of the semiconductor substrate into the semiconductor substrate; forming a first conductive region accommodated in the trench; forming a dielectric layer located on the front side, the dielectric layer having a thickness suitable for allowing charge to flow through direct tunneling; forming a second conductive region located on the dielectric layer; wherein corresponding stacks of the first conductive region, the dielectric layer, and the second conductive region form a plurality of basic capacitive elements connected in series; forming a capacitive storage element connected to one end of the plurality of basic capacitive elements connected in series; and providing a circuit connected to the first contact and the second contact and configured to detect an electrical discontinuity in the well between the first contact and the second contact.

7. The method according to claim 6, wherein the dielectric layer and the second conductive region are positioned facing respective portions of the width of the trench accommodating the first conductive region on the front side.

8. The method according to claim 6, wherein the series connection of the plurality of basic capacitive elements is alternately constituted by a second conductive region shared by two consecutive basic capacitive elements and a first conductive region shared by two consecutive basic capacitive elements.

9. The method according to claim 6 further comprises: Forming an electrically isolated region extending vertically from the front side into the substrate, and wherein forming the trench accommodating the first conductive region includes: forming the trench to extend into and through the electrically isolated region.

10. A method for measuring a duration, comprising: charging a capacitive storage element; discharging the charged capacitive storage element through a plurality of basic capacitive elements connected in series; Obtaining a physical quantity at at least one node of the plurality of serially-connected basic capacitive elements, the physical quantity representing the amount of discharge of the capacitive storage element, and representing the duration elapsed between the start of the discharge operation of the capacitive storage element and the moment when the physical quantity is transmitted; And Detecting an electrical discontinuity in a semiconductor well between a first contact and a second contact, wherein the semiconductor well is accommodated in a semiconductor substrate at a position where the plurality of serially-connected basic capacitive elements are located, and wherein the first contact and the second contact are electrically connected by a circuit path passing through the semiconductor well, the circuit path including a portion positioned between the bottom of the trench and the bottom of the well.

11. The method according to claim 10, wherein each basic capacitive element comprises: A stack of a first conductive region, a dielectric layer, and a second conductive region, the dielectric layer having a thickness suitable for allowing charge to flow through direct tunneling effect, Wherein the first conductive region is accommodated in a trench extending from the front surface of the semiconductor substrate into the substrate, and Wherein the dielectric layer is located on the front surface of the semiconductor substrate, and the second conductive region is located on the dielectric layer.

12. An integrated circuit, comprising: A semiconductor substrate having a front surface; A first trench and a second trench extending from the front surface into the semiconductor substrate; A first conductive region accommodated in each of the first trench and the second trench and insulated from the semiconductor substrate by an insulating liner; A dielectric layer extending above the front surface of the semiconductor substrate and also partially above the first conductive region in the first trench and at least partially above the first conductive region in the second trench; Wherein the dielectric layer has a thickness suitable for allowing charge to flow through direct tunneling effect; A second conductive region on the dielectric layer; Wherein the first conductive region, the dielectric layer, and the second conductive region in the first trench form a first capacitor; And Wherein the first conductive region, the dielectric layer, and the second conductive region in the second trench form a second capacitor serially connected to the first capacitor; A semiconductor well accommodated in the semiconductor substrate; A first contact and a second contact, the first contact and the second contact being electrically connected by a circuit path passing through the semiconductor well, the circuit path including a portion positioned between the bottoms of the first trench and the second trench and the bottom of the semiconductor well; And A detection circuit configured to detect an electrical discontinuity in the semiconductor well between the first contact and the second contact.

13. The integrated circuit according to claim 12 further comprises: An electrically isolated region extending vertically from the front surface into the semiconductor substrate, wherein the first trench and the second trench pass through the electrically isolated region.

14. The integrated circuit according to claim 12, further comprising: A capacitive storage element electrically coupled to the first conductive region of one of the first capacitor and the second capacitor; The series-connected first capacitor and the second capacitor are configured to discharge the capacitive storage element by an amount and generate a signal at the second conductive region, the signal representing the discharge of the capacitive storage element and the duration elapsed since the start of the operation of discharging the capacitive storage element.

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