A reference circuit under low power supply voltage

Abstract

This invention provides a reference circuit for low power supply voltage, including a voltage generation unit, a near-zero temperature coefficient current source unit, and a level shifting unit. The near-zero temperature coefficient current source unit includes: a negative feedback voltage regulation unit, a current sharing unit, a first positive temperature coefficient current unit, a first negative temperature coefficient voltage unit, a first negative temperature coefficient current unit, a second negative temperature coefficient voltage unit, and a second negative temperature coefficient current unit. Zero temperature coefficient can be achieved by designing the resistance ratio of the first negative temperature coefficient current unit to the second negative temperature coefficient current unit; a smaller power supply operating voltage can be achieved by designing the voltage across the current sharing unit.

Description

Technical Field

[0001] The present invention relates to the field of analog circuits, and more particularly to a reference circuit under low power supply voltage. Background Art

[0002] A reference circuit (reference voltage circuit), also called a reference voltage source, is a circuit that can provide a stable output voltage when the process, power supply voltage, and temperature change. Reference voltage sources are widely used in circuits such as data converters, smart sensors, and power converters.

[0003] Conventional reference circuits generally use bandgap circuit design. Since the bandgap voltage is generally around 1.21~1.22V, the output voltage is 1.21~1.22V, which requires the lowest power supply voltage to be greater than this voltage plus at least one Vds voltage to work. Generally, Vds needs to be at least 0.1V, so generally this circuit requires a power supply voltage greater than 1.31V. In some applications, it is necessary to work at a lower power supply voltage, so improvements are needed. Summary of the invention

[0004] The technical solution adopted by the present invention to solve the above technical problems is, on the one hand, to provide a reference circuit under low power supply voltage, comprising:

[0005] A voltage generating unit and an approximately zero temperature coefficient current source unit, wherein:

[0006] The voltage generating unit is coupled between the voltage input terminal and the voltage output terminal of the reference circuit, and generates an output voltage for the reference circuit through the voltage generating unit;

[0007] The approximately zero temperature coefficient current source unit is coupled between the output terminal of the voltage generating unit and the ground level, and the approximately zero temperature coefficient current source unit generates a stable current for the reference circuit when the temperature changes.

[0008] Preferably, the reference circuit further includes:

[0009] A level shifting unit is coupled between the output end of the voltage generating unit and the voltage output end of the reference circuit, and between the zero temperature coefficient current source unit and the ground level. The level shifting unit changes the output voltage of the reference circuit from an output voltage relative to the internal part of the device to an output voltage relative to the ground level.

[0010] Preferably, the reference circuit, wherein the approximately zero temperature coefficient current source unit includes a negative feedback voltage regulation unit, an equal current unit, a first positive temperature coefficient current unit, a first negative temperature coefficient voltage unit, a first negative temperature coefficient current unit, a second negative temperature coefficient voltage unit, and a second negative temperature coefficient current unit, wherein:

[0011] The negative feedback voltage regulating unit is connected to the input end and each output branch of the current-sharing unit, and is used to switch the current flowing to the current-sharing unit on and off, and to ensure that the voltages at the output ends of each output branch of the current-sharing unit are equal;

[0012] The current-sharing unit ensures that the current passing through each current output terminal is equal;

[0013] One end of the first positive temperature coefficient current unit and one end of the first negative temperature coefficient current unit are connected in parallel to the first output branch of the averaging current unit, the first positive temperature coefficient current unit provides a positive temperature coefficient current, and the first positive temperature coefficient current unit provides a negative temperature coefficient current; the first negative temperature coefficient voltage unit is connected to the other end of the first positive temperature coefficient current unit to provide a negative temperature coefficient voltage;

[0014] The second negative temperature coefficient voltage unit and a section of the second negative temperature coefficient current unit are connected in parallel to the second output branch of the current-sharing unit, the first positive temperature coefficient current unit provides a positive temperature coefficient current, and the first positive temperature coefficient current unit provides a negative temperature coefficient current;

[0015] The first positive temperature coefficient current unit, the first negative temperature coefficient voltage unit, the second negative temperature coefficient voltage unit, and another section of the second negative temperature coefficient current unit are connected to each other and grounded.

[0016] Specifically, the reference circuit further includes:

[0017] The mismatch voltage storage and compensation unit is coupled to the negative feedback voltage regulating unit, and stores and eliminates the input mismatch voltage generated by the negative feedback voltage regulating unit.

[0018] More specifically, the mismatch voltage storage and compensation unit includes a capacitor group, a first switch group, and a second switch group, wherein;

[0019] A capacitor group, coupled to the negative feedback voltage regulating unit, for storing and releasing an input mismatch voltage generated by the negative feedback voltage regulating unit;

[0020] The first switch group is coupled to the capacitor group and the negative feedback voltage regulating unit, the second switch group is connected in series to an input end of the negative feedback voltage regulating unit, the second switch group is controlled by the first clock, and the second switch group is controlled by the second clock; when the first clock is at a high level, the first switch group is turned on, and the input mismatch voltage of the negative feedback voltage regulating unit is stored in the capacitor group; when the second clock is at a high level, the second switch group is turned on, and the voltage stored in the capacitor group is released to eliminate the influence of the input mismatch voltage of the negative feedback voltage regulating unit; when the first clock is at a low level, the first switch group is cut off, and when the second clock is at a low level, the second switch group is cut off; the first clock and the second clock are non-overlapping clocks, and when one is at a high level, the other is at a low level.

[0021] Further specifically, it also includes, when a mismatched input voltage is generated in other units of the reference circuit, increasing the number of capacitors so that the added capacitors are coupled to the mismatched input voltage terminals of the other units, increasing the number of switches, and the added switches are connected between the added capacitors and the other units, the added capacitors and the added switches play the same role as the capacitor group and the switch group, and the control of the added capacitors and the added switches is the same as the method of the capacitor group and the switch group.

[0022] Specifically, the reference circuit is characterized in that the approximate zero temperature coefficient current source unit adjusts the ratio of the resistance value of the first positive temperature coefficient current unit to the resistance value of the first negative temperature coefficient voltage unit according to the ratio between the positive temperature coefficient of the voltage on the first positive temperature coefficient current unit and the negative temperature coefficient of the voltage on the first negative temperature coefficient voltage unit, thereby providing an output voltage with an approximate zero temperature coefficient.

[0023] Specifically, the reference circuit is characterized in that the internal resistance value of the current-sharing unit is lowered so that the lower limit of the power supply voltage range in which the reference circuit operates is reduced.

[0024] Specifically, the reference circuit is characterized in that the negative feedback voltage regulation unit includes an operational amplifier and a MOS tube; the MOS tube is a PMOS tube or an NMOS tube; the operational amplifier structure of the operational amplifier includes: using a bipolar transistor as an input pair tube.

[0025] Specifically, the reference circuit is characterized in that the first negative temperature coefficient voltage unit and the second negative temperature coefficient voltage unit include bipolar transistors, and the bipolar transistors are PNP type or NPN type.

[0026] On the other hand, a reference circuit under low power supply voltage is provided, characterized in that it includes:

[0027] A first operational amplifier, a first driving control tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a sixth resistor, a seventh resistor, a first bipolar transistor, and a second bipolar transistor; wherein

[0028] The voltage input end of the reference circuit is coupled to one end of a fourth resistor; the other end of the fourth resistor is coupled to the output end of the reference circuit and the first connection electrode of the first driving control tube;

[0029] One end of the second resistor and one end of the third resistor are coupled to the second connection electrode of the first driving control tube;

[0030] The base and collector of the first bipolar transistor are coupled together, the base and collector of the second bipolar transistor are coupled together,

[0031] The other end of the third resistor, the first input end of the first operational amplifier, and one end of the first resistor and the sixth resistor are coupled to the first clamping node; the other end of the first resistor is coupled to the emitter or collector of the first bipolar transistor;

[0032] The other end of the second resistor, the second input end of the first operational amplifier, one end of the seventh resistor, and the emitter or collector of the second bipolar transistor are coupled to the second clamping node;

[0033] The output terminal of the first operational amplifier is coupled to the control electrode of the first driving control tube;

[0034] The collector or emitter of the first bipolar transistor and the second bipolar transistor, the other end of the sixth resistor, and the other end of the seventh resistor are coupled to the ground.

[0035] Preferably, the reference circuit further includes a fifth resistor, an eighth resistor, a second operational amplifier, and a second drive control tube, wherein:

[0036] The input end of the reference circuit is coupled to the fourth resistor and one end of the fifth resistor; the other end of the fourth resistor is not directly connected to the output end of the reference circuit, and the other end of the fourth resistor is also coupled to the second input end of the second operational amplifier, and the other end of the fifth resistor is connected to the first input end of the second operational amplifier and the first connecting electrode of the second drive control tube; the output end of the second operational amplifier is connected to the control electrode of the second drive control tube; the second connecting electrode of the second drive control tube is connected to one end of the eighth resistor and the output end of the reference circuit; the other end of the eighth resistor is coupled to the ground.

[0037] Specifically, the reference circuit is characterized in that:

[0038] The first drive control tube and the second drive control tube are PMOS transistors, the source of the PMOS transistor is the first connection electrode of each drive control tube, the drain of the PMOS transistor is the second connection electrode of the drive control, and the gate of the PMOS transistor is the control electrode of the drive control; or, the first drive control tube and the second drive control tube are NMOS transistors, the drain of the NMOS transistor is the first connection electrode of the drive control, the source of the NMOS transistor is the second connection electrode of the drive control, and the gate of the NMOS transistor is the control electrode of the drive control tube;

[0039] The first bipolar transistor and the second bipolar transistor are PNP bipolar transistors, the emitter of the first bipolar transistor is coupled to the first resistor, the collector of the first bipolar transistor is coupled to the ground, the emitter of the second bipolar transistor is coupled to the second resistor, and the collector of the second bipolar transistor is coupled to the ground; or, the first bipolar transistor and the second bipolar transistor are NPN bipolar transistors, the collector of the first bipolar transistor is coupled to the first resistor, the collector of the first bipolar transistor is coupled to the ground, the collector of the second bipolar transistor is coupled to the second resistor, and the collector of the second bipolar transistor is coupled to the ground;

[0040] The first input terminal of the first operational amplifier and the second operational amplifier is a positive input terminal or a negative input terminal, and the second input terminal is a negative input terminal or a positive input terminal.

[0041] Specifically, the reference circuit further includes a first operational amplifier mismatch voltage compensation unit, coupled to the first input terminal and the second input terminal of the first operational amplifier, which includes a first operational amplifier mismatch compensation switch group and a first capacitor, wherein: when the first operational amplifier mismatch compensation switch group is in a first switch combination state, the first capacitor is coupled between the first input terminal and the second input terminal of the operational amplifier to store and release the input mismatch voltage generated by the operational amplifier; when the first operational amplifier mismatch compensation switch group is in a second switch combination state, the first capacitor is coupled in series to the first input terminal or the second input terminal of the first operational amplifier;

[0042] The second operational amplifier mismatch voltage compensation unit is coupled to the first input terminal and the second input terminal of the second operational amplifier, and includes a second operational amplifier mismatch compensation switch group and a second capacitor, wherein: when the second operational amplifier mismatch compensation switch group is in a first switch combination state, the second capacitor is coupled between the first input terminal and the second input terminal of the second operational amplifier to store and release the input mismatch voltage generated by the second operational amplifier, and when the second operational amplifier mismatch compensation switch group is in a second switch combination state, the second capacitor is coupled in series to the first input terminal or the second input terminal of the second operational amplifier.

[0043] More specifically, the reference circuit further includes a seventh switch coupled between the output terminal of the reference circuit and the second connection electrode of the second drive control tube, and a third capacitor coupled between the output terminal of the reference circuit and ground.

[0044] When the first op amp mismatch compensation switch group and the second op amp mismatch compensation switch group are in the first switch combination state, the seventh switch is turned off.

[0045] When the first op amp mismatch compensation switch group and the second op amp mismatch compensation switch group are in the second switch combination state, the seventh switch is turned on.

[0046] The seventh switch is turned on after a first predetermined time delay after the first op amp mismatch compensation switch group and the second op amp mismatch compensation switch group enter the second switch combination state.

[0047] More specifically, the reference circuit, wherein:

[0048] The first op amp mismatch compensation switch group includes a first switch, a second switch, and a third switch;

[0049] The second op amp mismatch compensation switch group includes a fourth switch, a fifth switch, and a sixth switch;

[0050] One end of the first switch is connected to one end of the first resistor, and the other end of the first switch is connected to one end of the first capacitor and one end of the second switch; the other end of the first capacitor is connected to the positive input end of the first operational amplifier and one end of the third switch; the other end of the second switch is connected to the other end of the third switch and one end of the seventh resistor;

[0051] One end of the fourth switch is connected to the other end of the fourth resistor, and the other end of the fourth switch is connected to one end of the second capacitor and one end of the sixth switch; the other end of the sixth switch is connected to the negative input end of the second operational amplifier and one end of the fifth switch; the other end of the fifth switch is connected to the other end of the fifth resistor and the other end of the second capacitor; the negative input end of the second operational amplifier is not directly connected to the other end of the fifth resistor;

[0052] The first switch, the third switch, the fourth switch, and the fifth switch are controlled by a first clock, and the second switch and the sixth switch are controlled by a second clock. When the first clock is at a first level and the second clock is at a second level, the first switch, the third switch, the fourth switch, and the fifth switch are turned on, and the second switch and the sixth switch are turned off. At this time, the first op amp mismatch compensation switch group and the second op amp mismatch compensation switch group are in a first switch combination state;

[0053] When the first clock is at the second level, the second clock is at the first level, at this time the first switch, the third switch, the fourth switch, and the fifth switch are turned off, and the second switch and the sixth switch are turned on, and at this time the first op amp mismatch compensation switch group and the second op amp mismatch compensation switch group are in the second switch combination state.

[0054] The embodiment of the present invention provides a reference circuit under low power supply voltage, which can achieve a smaller power supply operating voltage by designing the voltage on the resistor in the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A structural diagram of a reference circuit under low power supply voltage provided by an embodiment of the present invention;

[0056] Figure 2 A structural diagram of an approximately zero temperature coefficient current source unit of a reference circuit under low power supply voltage provided by an embodiment of the present invention;

[0057] Figure 3 A structural diagram of a reference circuit under low power supply voltage provided by another embodiment of the present invention;

[0058] Figure 4 A circuit diagram of a reference circuit under low power supply voltage provided by one embodiment of the present invention;

[0059] Figure 5 A circuit diagram of a second implementation scheme of a reference circuit under low power supply voltage provided by an embodiment of the present invention;

[0060] Figure 6 A circuit diagram of a third implementation scheme of a reference circuit under low power supply voltage provided by an embodiment of the present invention;

[0061] Figure 7 A clock waveform diagram of a third implementation scheme of a reference circuit under low power supply voltage provided by an embodiment of the present invention;

[0062] Figure 8 A circuit diagram of a fourth implementation scheme of a reference circuit under low power supply voltage provided by an embodiment of the present invention;

[0063] Fig. 9 A circuit diagram of a fifth implementation scheme of a reference circuit under low power supply voltage provided by an embodiment of the present invention;

[0064] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] Figure 1 A structural diagram of a reference circuit under low power supply voltage provided by an embodiment of the present invention is shown in the figure, which includes a voltage generating unit and an approximately zero temperature coefficient current source unit.

[0067] A voltage generating unit, coupled between a voltage input terminal and a voltage output terminal of the reference circuit, and generating an output voltage for the reference circuit through the voltage generating unit;

[0068] The approximately zero temperature coefficient current source unit is coupled between the output terminal of the voltage generating unit and the ground level. The approximately zero temperature coefficient current source unit generates a stable current for the reference circuit when the temperature changes.

[0069] The operating principle of the reference circuit is that since the near-zero temperature coefficient current source unit provides a stable current when the temperature changes, when the temperature changes, the input voltage provided by the voltage input terminal of the reference circuit passes through the voltage of the voltage generating unit, and when the internal resistance-temperature characteristics of the near-zero temperature coefficient current source and the voltage generating unit are similar, the resistance effect can be ignored, thereby outputting a stable voltage. Therefore, it should be noted that the resistance elements used in the near-zero temperature coefficient current source and the voltage generating unit should be of the same type and have similar temperature coefficients.

[0070] Figure 2 A structural diagram of an approximately zero temperature coefficient current source unit of a reference circuit under low power supply voltage provided by an embodiment of the present invention;

[0071] As shown in the figure, the approximate zero temperature coefficient current source unit includes: a negative feedback voltage regulation unit, an equal current unit, a first positive temperature coefficient current unit, a first negative temperature coefficient voltage unit, a first negative temperature coefficient current unit, a second negative temperature coefficient voltage unit, and a second negative temperature coefficient current unit.

[0072] The negative feedback voltage regulating unit is connected to the input end and each output branch of the current-sharing unit, and is used to switch the current input to the current-sharing unit on and off, and to ensure that the voltages at the output ends of each output branch of the current-sharing unit are equal.

[0073] The current-sharing unit ensures that the current passing through each current output terminal is equal;

[0074] One end of the first positive temperature coefficient current unit and the first negative temperature coefficient current unit are connected in parallel to the first output branch of the averaging current unit, the first positive temperature coefficient current unit provides a positive temperature coefficient current, and the first positive temperature coefficient current unit provides a negative temperature coefficient current; the first negative temperature coefficient voltage unit is connected to the other end of the first positive temperature coefficient current unit to provide a negative temperature coefficient voltage;

[0075] A second negative temperature coefficient voltage unit and a section of a second negative temperature coefficient current unit are connected in parallel to a second output branch of the current-sharing unit, the first positive temperature coefficient current unit provides a positive temperature coefficient current, and the first positive temperature coefficient current unit provides a negative temperature coefficient current;

[0076] The first positive temperature coefficient current unit, the first negative temperature coefficient voltage unit, the second negative temperature coefficient voltage unit, and another section of the second negative temperature coefficient current unit are connected to each other and grounded.

[0077] The operating principle of the approximate zero temperature coefficient current source unit is as follows: the negative feedback voltage regulating unit is used to ensure that the voltages of the two output branches of the current-sharing module are equal, the current-sharing module is used to ensure that the output currents of its two output branches are equal, and the second output branch of the current-sharing module (including the second negative temperature coefficient voltage unit and the second negative temperature coefficient current unit) is used to ensure that the voltage of the first positive temperature coefficient current unit in its first output path is equal to the difference between the voltage on the second negative temperature coefficient voltage unit and the voltage on the first negative temperature coefficient voltage unit, and the temperature coefficient of the voltage difference is a positive temperature coefficient. At the same time, the voltage on the first negative temperature coefficient current unit in the first output branch is equal to the voltage on the second negative temperature coefficient voltage unit, and the temperature coefficient of the voltage is a negative temperature coefficient. That is, the current changes through the first negative temperature coefficient current unit and the first positive temperature coefficient current unit due to temperature changes will be opposite, and one will increase while the other will decrease. Because the total current passing through the first branch can be approximately unchanged by the offset between the two. Specifically, the offset between the two is performed by adjusting the ratio of the internal resistance of the first negative temperature coefficient current unit and the first positive temperature coefficient current unit.

[0078] Figure 3 A structural diagram of a reference circuit under low power supply voltage provided by another embodiment of the present invention;

[0079] As shown in the figure, Figure 1 Based on the structure shown in the embodiment, a level shift unit is further included, and the level shift unit is coupled to the output end of the voltage generating unit and the output end of the approximately zero temperature coefficient current source unit, and its output end outputs the output voltage of the reference circuit. Its function is to change the output voltage of the reference circuit from an output voltage relative to the internal output voltage of the device to an output voltage relative to the ground level.

[0080] Figure 4 A circuit diagram of a reference circuit under low power supply voltage is provided for one embodiment of the present invention. This embodiment is a specific circuit designed using the aforementioned reference circuit structure.

[0081] As shown in the figure, in this embodiment, the voltage generating unit is composed of a fourth resistor R4, the negative feedback voltage regulating unit is composed of an operational amplifier OP1 and a first PMOS tube MP1 (the MOS tube here functions as a driving control tube), the current sharing unit is composed of a second resistor R2 and a third resistor R3, the first positive temperature coefficient current unit is composed of a first resistor R1, the first negative temperature coefficient current unit is composed of a sixth resistor R6, the second negative temperature coefficient current unit is composed of a seventh resistor R7, the first negative temperature coefficient voltage unit is composed of a first bipolar transistor Q1, and the second negative temperature coefficient voltage unit is composed of a second bipolar transistor Q2.

[0082] Figure 4 The output voltage of the reference circuit provided in the embodiment is a high-precision reference voltage relative to the power supply voltage VIN, that is, the voltage of VIN-VO is relatively accurate, and can be compensated to a zero temperature coefficient voltage by adjusting the resistance in the reference circuit. As shown in the figure, the operational amplifier OP1 adjusts the VP and VN voltages to be equal through negative feedback, so the VP voltage is equal to the V BE2 , the voltage on resistor R1 is ΔV BE =V BE2 -V BE1 , thus forming a positive temperature coefficient voltage. The current of R1 is equal to ΔV BE / R1, where R1 is the resistance value of resistor R1. Since the voltages of the VP node and the VN node are both equal to V BE2 , which is the base-emitter voltage of Q2, so the current in R6 is equal to V BE2 / R6, R7 current is equal to V BE2 / R7, where R6 is the resistance value of resistor R6, and R7 is the resistance value of resistor R7. Since the VP voltage is equal to the VN voltage, and the voltage at the other end of R3 and R2 is the same, they are connected together, and the resistance values ​​of R2 and R3 are designed to be equal, so the current of R3 is equal to the current of R2. According to Kirchhoff's law, the current flowing through R3 is equal to the sum of the current flowing through R1 and the current flowing through R6. Therefore, we can get:

[0083]

[0084] Wherein R1 is the resistance value of resistor R1, and R6 is the resistance value of R6.

[0085] Better temperature compensation can be achieved by designing R1 and R6 appropriately.

[0086]

[0087] Specifically, for example, V BE The temperature coefficient is a negative temperature coefficient, ΔV BE The temperature coefficient is positive, and V BE Temperature coefficient (for example, for every 20 degrees Celsius increase in temperature, V BE The absolute value of the reduction of 42mV is ΔV BE Temperature coefficient (for example, ΔV for every 20°C increase in temperature) BE Increase 7mV) by 6 times, then design R6 / R1 to be 6, which can offset the temperature coefficients of the two and achieve zero temperature coefficient.

[0088] Since the current in R3 is equal to the current in R2, the current in R4 is equal to twice the current in R3, and the voltage across R4 is equal to:

[0089]

[0090] In another embodiment, further, in order to achieve a relatively low power supply operating voltage, the resistance values ​​of R3 and R2 are selected to be relatively small, so that the voltage on R3 and R2 can be designed to be as small as possible, and at the same time, the resistance value of R4 can be designed to be relatively small, so that the voltage on R4 will also be relatively low.

[0091] In another embodiment, according to reasonable design, the voltage on R3 and R2 is designed to be 50mV, the voltage on R4 is also designed to be 50mV, the source-drain voltage of MP1 is designed to be 100mV, and the Vbe voltage of Q2 is 600mV, so that the entire circuit can operate at about 800mV (50+50+100+600=800mV).

[0092] In addition, in order to improve accuracy, an op amp structure with a relatively small input mismatch voltage is used. Figure 1 The OP in the circuit should adopt a structure with relatively small input offset voltage.

[0093] In another embodiment, a bipolar transistor is used as the structure of the input pair. The reason is due to the characteristics of the device itself. When the MOS device is manufactured, factors such as the complex structure, gate oxide thickness, channel doping concentration, and gate oxide quality will affect its input offset voltage. Bipolar transistors are better matched because of their simple structure. In addition, the bipolar transistor used as the input pair in this embodiment is different from the aforementioned Q1 and Q2. The Q1 and Q2 are usually a type of bipolar transistor parasitic in the MOS process, and their current amplification factor is small, which is not suitable for the input pair of operational amplifiers. Generally, the bipolar transistor used for the input pair needs to be modified in the MOS process, and additional photolithography steps are added to manufacture special high-gain bipolar transistors, and the manufacturing cost is relatively high.

[0094] Figure 5 A circuit diagram of a second implementation scheme of a reference circuit under low power supply voltage provided by an embodiment of the present invention.

[0095] As another specific circuit scheme designed using the aforementioned reference circuit structure, Figure 4 Compared with the scheme shown in the figure, the scheme of this embodiment adds a level shift unit, which is coupled to the output end of the voltage generating unit and the ground end of the approximately zero temperature coefficient current source unit. The output voltage of its output end is the output voltage of the reference circuit, and its function is to change the output voltage of the reference circuit from the output voltage relative to the internal output voltage of the device to the output voltage relative to the ground level. The unit is composed of a fifth resistor R5, an eighth resistor R8, a second operational amplifier OP2, and a second PMOS tube MP2.

[0096] Specifically, Figure 4 The output voltage achieved by the scheme shown is the VO voltage relative to VDD (the internal operating voltage of the device). Figure 5 The output voltage achieved by the scheme shown is the VO voltage relative to the ground level. Figure 5 As shown, OP2 uses negative feedback to make the voltage at point A equal to the voltage at point B, so the voltage at resistor R5 is equal to the voltage at resistor R4:

[0097]

[0098] According to Kirchhoff's law, the current on resistor R8 is equal to the current on resistor R5.

[0099] From this the voltage across R8 (which is equal to VO) can be calculated:

[0100]

[0101] Wherein, ΔVBE is the difference between the base-emitter voltage of Q2 and the base-emitter voltage of Q1, and VBE is the base-emitter voltage of Q2. It can be seen that in the scheme described in this embodiment, by designing a reasonable ratio of R1 and R6, a voltage value with a zero temperature coefficient can also be designed, and its value is relatively accurate. At the same time, the output voltage of the reference circuit changes from an output voltage relative to the internal of the device to an output voltage relative to the ground level.

[0102] Figure 6 A circuit diagram of a third implementation scheme of a reference circuit under low power supply voltage provided by an embodiment of the present invention. Figure 5 Compared with the embodiment shown, a mismatch voltage storage and compensation unit is added. The unit is coupled to the negative feedback voltage regulating unit and is used to store and eliminate the input mismatch voltage generated by the negative feedback voltage regulating unit.

[0103] In one embodiment, the mismatch voltage storage and compensation unit includes a capacitor group, a first switch group, and a second switch group, wherein;

[0104] A capacitor group, coupled to the negative feedback voltage regulating unit, for storing and releasing an input mismatch voltage generated by the negative feedback voltage regulating unit;

[0105] The first switch group is coupled to the capacitor group and the negative feedback voltage regulating unit. When the first clock is at a high level, the first switch group is turned on to store the input mismatch voltage of the negative feedback voltage regulating unit in the capacitor group; when the second clock is at a high level, the second switch group is turned on to release the voltage stored in the capacitor group to eliminate the influence of the input mismatch voltage of the negative feedback voltage regulating unit; when the first clock is at a low level, the first switch group is cut off, and when the second clock is at a low level, the second switch group is cut off; the first clock and the second clock are non-overlapping clocks, and when one is at a high level, the other is at a low level.

[0106] In a specific embodiment (such as Figure 6 ), the first switch group includes switches K1, K3, K4, and K5, the second switch group includes switches K2 and K6, the capacitor group includes capacitors C1 and C2, and this embodiment also includes a switch K7 and a capacitor C3.

[0107] and Figure 5 Compared with the scheme shown, Figure 6 The scheme shown achieves storage and cancellation of the op amp input offset voltage, so a smaller V R2 、V R3 、V R4 , where V R2 is the voltage on resistor R2, V R3 is the voltage on resistor R3, V R4 is the voltage on resistor R4. Figure 6In the scheme shown, CK1 and CK2 are non-overlapping clocks. When CK1 is at a high level, switches K1, K3, K4, and K5 are turned on. At this time, the input mismatch voltage of OP1 is stored on capacitor C1, and the input mismatch voltage of OP2 is stored on capacitor C2; when CK2 is at a high level, capacitor C1 is connected in series to the positive input path of OP1, so as to eliminate the influence of the input mismatch voltage of OP1; when CK2 is at a high level, switches K2 and K6 are turned on, and capacitor C2 is connected in series to the negative input end of OP2, so as to eliminate the influence of the input mismatch voltage of OP2. When CK3 is at a high level, switch K7 is turned on, and the voltage on resistor R8 is sampled on capacitor C3, so as to obtain a more accurate voltage signal VO. It can be seen from the above that the addition of K7 and C3 is to adjust the accuracy of the output voltage. Similar to this, all fine-tuning performed on the overall creative work of the present invention and not exceeding the overall framework of the present invention should be within the scope of protection of the present invention application.

[0108] Figure 7 Shows Figure 6 The waveforms of CK1, CK2, and CK3 in the scheme shown in the figure are as follows. CK1 and CK2 are non-overlapping clocks. It should be noted that the rising edge of CK3 should be delayed by Td1 time than the rising edge of CK2, Td1 should be greater than or equal to the delay time required for the operational amplifier to stabilize, and the falling edge of CK3 should be ahead of the falling edge of CK2 by Td2 time. Td2 time can be designed to be greater than or equal to 1 nanosecond to avoid erroneous sampling after CK2 is turned off.

[0109] Figure 8 Another embodiment of the present invention is shown. Figure 4 The embodiment shown in the figure replaces the PNP bipolar transistors of Q1 and Q2 with Figure 8 The NPN bipolar transistor in the embodiment is replaced, and adaptive modification is made to the circuit. This adaptive modification has no principle change and belongs to the common sense in the field, so it will not be repeated here. After the replacement, this embodiment also uses VBE and ΔVBE to realize the idea of ​​the present invention.

[0110] In another embodiment, Figure 4 The P-type MOS tube MP1 in the embodiment shown (the MOS tube here functions as a driving control tube) is replaced by Figure 8 In the embodiment, the positive and negative input terminals of the operational amplifier OP1 need to be inverted (e.g. Figure 8 shown).

[0111] In another embodiment, Figure 5 The P-type MOS tube MP1 in the embodiment shown is replaced by Figure 8In the embodiment, the positive and negative input terminals of the operational amplifier OP2 need to be inverted (e.g. Figure 8 shown).

[0112] Fig. 9 Another embodiment of the present invention is shown. Figure 6 Compared with the embodiment shown in the figure, Figure 6 Switches K1, K2, K3 are replaced with Fig. 9 In the connection mode, in this embodiment, when CK1 is at a high level, switches K1 and K3 are turned on, and the offset voltage of the operational amplifier OP1 is stored on the capacitor C1; when CK2 is at a high level, switch K2 is turned on, and the capacitor C1 is connected in series to the path of the negative phase input terminal of the operational amplifier OP1 (for comparison, Figure 6 In the figure, it is connected in series in the path of the positive input terminal of the operational amplifier).

[0113] In another embodiment, the comparison Figure 6 In the embodiment shown, the switches K4, K5, and K6 are replaced by Fig. 9 When CK1 is at a high level, switches K4 and K5 are turned on, and the offset voltage of the operational amplifier OP2 is stored on capacitor C2; when CK2 is at a high level, switch K6 is turned on, and capacitor C2 is connected in series to the path of the non-inverting input terminal of the operational amplifier OP2 (for comparison, Figure 6 In the figure, it is connected in series in the path of the negative input terminal of the operational amplifier).

[0114] According to the design framework provided by the present invention, a series of embodiments can also be generated.

[0115] In one embodiment, a reference circuit (such as Figure 4 shown), including:

[0116] A first operational amplifier, a first drive control tube (implemented by MP1 in the figure), a first resistor, a second resistor, a third resistor, a fourth resistor, a sixth resistor, a seventh resistor, a first bipolar transistor, and a second bipolar transistor; wherein

[0117] The voltage input end of the reference circuit is coupled to one end of a fourth resistor; the other end of the fourth resistor is coupled to the output end of the reference circuit and the first connection electrode of the first driving control tube;

[0118] One end of the second resistor and one end of the third resistor are coupled to the second connection electrode of the first driving control tube;

[0119] The base and collector of the first bipolar transistor are coupled together, the base and collector of the second bipolar transistor are coupled together,

[0120] The other end of the third resistor, the first input end of the first operational amplifier, and one end of the first resistor and the sixth resistor are coupled to the first clamping node; the other end of the first resistor is coupled to the emitter or collector of the first bipolar transistor;

[0121] The other end of the second resistor, the second input end of the first operational amplifier, one end of the seventh resistor, and the emitter or collector of the second bipolar transistor are coupled to the second clamping node;

[0122] The output terminal of the first operational amplifier is coupled to the control electrode of the first driving control tube;

[0123] The collector or emitter of the first bipolar transistor and the second bipolar transistor, the other end of the sixth resistor, and the other end of the seventh resistor are coupled to the ground.

[0124] In another embodiment, the reference circuit further includes (eg Figure 5 As shown), a fifth resistor, an eighth resistor, a second operational amplifier, and a second drive control tube (implemented by MP2 in the figure), wherein:

[0125] The input end of the reference circuit is coupled to the fourth resistor and one end of the fifth resistor; the other end of the fourth resistor is not directly connected to the output end of the reference circuit, and the other end of the fourth resistor is also coupled to the second input end of the second operational amplifier, and the other end of the fifth resistor is connected to the first input end of the second operational amplifier and the first connecting electrode of the second drive control tube; the output end of the second operational amplifier is connected to the control electrode of the second drive control tube; the second connecting electrode of the second drive control tube is connected to one end of the eighth resistor and the output end of the reference circuit; the other end of the eighth resistor is coupled to the ground.

[0126] In another embodiment (such as Figure 6 As shown), the reference circuit also includes a first operational amplifier mismatch voltage compensation unit, coupled to the first input terminal and the second input terminal of the first operational amplifier, which includes a first operational amplifier mismatch compensation switch group and a first capacitor, wherein: when the first operational amplifier mismatch compensation switch group is in a first switch combination state, the first capacitor is coupled between the first input terminal and the second input terminal of the operational amplifier to store and release the input mismatch voltage generated by the operational amplifier; when the first operational amplifier mismatch compensation switch group is in a second switch combination state, the first capacitor is coupled in series to the first input terminal or the second input terminal of the first operational amplifier;

[0127] The second operational amplifier mismatch voltage compensation unit is coupled to the first input terminal and the second input terminal of the second operational amplifier, and includes a second operational amplifier mismatch compensation switch group and a second capacitor, wherein: when the second operational amplifier mismatch compensation switch group is in a first switch combination state, the second capacitor is coupled between the first input terminal and the second input terminal of the second operational amplifier to store and release the input mismatch voltage generated by the second operational amplifier, and when the second operational amplifier mismatch compensation switch group is in a second switch combination state, the second capacitor is coupled in series to the first input terminal or the second input terminal of the second operational amplifier.

[0128] In another embodiment, the reference circuit further includes a seventh switch coupled between the output terminal of the reference circuit and the second connection electrode of the second drive control tube, and a third capacitor coupled between the output terminal of the reference circuit and ground.

[0129] When the first op amp mismatch compensation switch group and the second op amp mismatch compensation switch group are in the first switch combination state, the seventh switch is turned off.

[0130] When the first op amp mismatch compensation switch group and the second op amp mismatch compensation switch group are in the second switch combination state, the seventh switch is turned on.

[0131] The seventh switch is turned on after a first predetermined time delay after the first op amp mismatch compensation switch group and the second op amp mismatch compensation switch group enter the second switch combination state.

[0132] In another embodiment,

[0133] The first op amp mismatch compensation switch group includes a first switch, a second switch, and a third switch;

[0134] The second op amp mismatch compensation switch group includes a fourth switch, a fifth switch, and a sixth switch;

[0135] One end of the first switch is connected to one end of the first resistor, and the other end of the first switch is connected to one end of the first capacitor and one end of the second switch; the other end of the first capacitor is connected to the positive input end of the first operational amplifier and one end of the third switch; the other end of the second switch is connected to the other end of the third switch and one end of the seventh resistor;

[0136] One end of the fourth switch is connected to the other end of the fourth resistor, and the other end of the fourth switch is connected to one end of the second capacitor and one end of the sixth switch; the other end of the sixth switch is connected to the negative input end of the second operational amplifier and one end of the fifth switch; the other end of the fifth switch is connected to the other end of the fifth resistor and the other end of the second capacitor; the negative input end of the second operational amplifier is not directly connected to the other end of the fifth resistor;

[0137] The first switch, the third switch, the fourth switch, and the fifth switch are controlled by a first clock, and the second switch and the sixth switch are controlled by a second clock. When the first clock is at a first level and the second clock is at a second level, the first switch, the third switch, the fourth switch, and the fifth switch are turned on, and the second switch and the sixth switch are turned off. At this time, the first op amp mismatch compensation switch group and the second op amp mismatch compensation switch group are in a first switch combination state;

[0138] When the first clock is at the second level, the second clock is at the first level, at this time the first switch, the third switch, the fourth switch, and the fifth switch are turned off, and the second switch and the sixth switch are turned on, and at this time the first op amp mismatch compensation switch group and the second op amp mismatch compensation switch group are in the second switch combination state.

[0139] In one embodiment (such as Figure 6 As shown), the first drive control tube and the second drive control tube are PMOS transistors, the source of the PMOS transistor is the first connection electrode of each drive control tube, the drain of the PMOS transistor is the second connection electrode of the drive control, and the gate of the PMOS transistor is the control electrode of the drive control; in another embodiment (as shown Figure 6 As shown), the first drive control tube and the second drive control tube are NMOS transistors, the drain of the NMOS transistor is the first connection electrode of the drive control, the source of the NMOS transistor is the second connection electrode of the drive control, and the gate of the NMOS transistor is the control electrode of the drive control tube;

[0140] In one embodiment (such as Figure 8 As shown), the first bipolar transistor and the second bipolar transistor are PNP bipolar transistors, the emitter of the first bipolar transistor is coupled to the first resistor, and the collector thereof is coupled to the ground, the emitter of the second bipolar transistor is coupled to the second resistor, and the collector thereof is coupled to the ground; in another embodiment (as shown Figure 6 As shown), the first bipolar transistor and the second bipolar transistor are NPN bipolar transistors, the collector of the first bipolar transistor is coupled to the first resistor, and the collector thereof is coupled to the ground, and the collector of the second bipolar transistor is coupled to the second resistor, and the collector thereof is coupled to the ground;

[0141] The first input terminal of the first operational amplifier and the second operational amplifier is a positive input terminal or a negative input terminal thereof, and the second input terminal thereof is a negative input terminal or a positive input terminal, that is, a reflection input terminal of the first input terminal.

[0142] It can be seen from the above embodiments that, according to the aforementioned design principles and structural framework, specific implementations can produce different connection methods and component selections, which are in line with the design principles and structural framework provided by the present invention and should all fall within the limited scope of the solutions of the present invention.

[0143] It can be seen from the above embodiments that by using a reference circuit under a low power supply voltage disclosed in the present invention, a zero temperature coefficient can be achieved by designing the ratio of the internal resistors R6 / R1; and a smaller power supply operating voltage can be achieved by designing the voltages on the internal resistors R2 and R3.

[0144] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A reference circuit under low power supply voltage, characterized in that include: A voltage generating unit, a nearly zero temperature coefficient current source unit, a level shifting unit, and a mismatch voltage storage and compensation unit, wherein: The voltage generating unit is coupled between the voltage input terminal and the voltage output terminal of the reference circuit, and generates an output voltage for the reference circuit through the voltage generating unit; The approximately zero temperature coefficient current source unit is coupled between the output terminal of the voltage generating unit and the ground level, and the approximately zero temperature coefficient current source unit generates a stable current for the reference circuit when the temperature changes; The level shift unit is coupled between the output terminal of the voltage generating unit and the voltage output terminal of the reference circuit, and is coupled between the zero temperature coefficient current source unit and the ground level, and the level shift unit changes the output voltage of the reference circuit from an output voltage relative to the internal of the device to an output voltage relative to the ground level; The approximately zero temperature coefficient current source unit includes a negative feedback voltage regulating unit, an equal current unit, a first positive temperature coefficient current unit, a first negative temperature coefficient voltage unit, a first negative temperature coefficient current unit, a second negative temperature coefficient voltage unit, and a second negative temperature coefficient current unit, wherein: The negative feedback voltage regulating unit is connected to the input end and each output branch of the current-sharing unit, and is used to switch the current flowing to the current-sharing unit on and off, and to ensure that the voltages at the output ends of each output branch of the current-sharing unit are equal; The approximately zero temperature coefficient current source unit adjusts the ratio of the resistance value of the first positive temperature coefficient current unit to the resistance value of the first negative temperature coefficient voltage unit according to the ratio between the positive temperature coefficient of the voltage on the first positive temperature coefficient current unit and the negative temperature coefficient of the voltage on the first negative temperature coefficient voltage unit, so as to provide an output voltage with an approximately zero temperature coefficient; Lowering the internal resistance value of the current-sharing unit so as to reduce the lower limit of the power supply voltage range within which the reference circuit operates; The current-sharing unit ensures that the current passing through each current output terminal is equal; One end of the first positive temperature coefficient current unit and one end of the first negative temperature coefficient current unit are connected in parallel to the first output branch of the averaging current unit, the first positive temperature coefficient current unit provides a positive temperature coefficient current, and the first positive temperature coefficient current unit provides a negative temperature coefficient current; the first negative temperature coefficient voltage unit is connected to the other end of the first positive temperature coefficient current unit to provide a negative temperature coefficient voltage; The second negative temperature coefficient voltage unit and a section of the second negative temperature coefficient current unit are connected in parallel to the second output branch of the current-sharing unit, the first positive temperature coefficient current unit provides a positive temperature coefficient current, and the first positive temperature coefficient current unit provides a negative temperature coefficient current; The first positive temperature coefficient current unit, the first negative temperature coefficient voltage unit, the second negative temperature coefficient voltage unit, and another section of the second negative temperature coefficient current unit are connected to each other and grounded; The mismatch voltage storage and compensation unit is coupled to the negative feedback voltage regulating unit, and stores and eliminates the input mismatch voltage generated by the negative feedback voltage regulating unit.

2. The reference circuit according to claim 1, characterized in that: The negative feedback voltage regulating unit comprises an operational amplifier and a MOS tube; the MOS tube is a PMOS tube or an NMOS tube; the operational amplifier structure of the operational amplifier comprises: using a bipolar transistor as an input pair tube.

3. The reference circuit according to claim 1, characterized in that: The first negative temperature coefficient voltage unit and the second negative temperature coefficient voltage unit include bipolar transistors, and the bipolar transistors are PNP type or NPN type.

4. The reference circuit according to claim 1, wherein the mismatch voltage storage and compensation unit comprises a capacitor group, a first switch group, and a second switch group, wherein; A capacitor group, coupled to the negative feedback voltage regulating unit, for storing and releasing an input mismatch voltage generated by the negative feedback voltage regulating unit; The first switch group is coupled to the capacitor group and the negative feedback voltage regulating unit, the second switch group is connected in series to an input end of the negative feedback voltage regulating unit, the second switch group is controlled by the first clock, and the second switch group is controlled by the second clock; when the first clock is at a high level, the first switch group is turned on, and the input mismatch voltage of the negative feedback voltage regulating unit is stored in the capacitor group; when the second clock is at a high level, the second switch group is turned on, and the voltage stored in the capacitor group is released to eliminate the influence of the input mismatch voltage of the negative feedback voltage regulating unit; when the first clock is at a low level, the first switch group is cut off, and when the second clock is at a low level, the second switch group is cut off; the first clock and the second clock are non-overlapping clocks, and when one is at a high level, the other is at a low level.

5. The reference circuit according to claim 4 further includes, when a mismatched input voltage is generated in other units of the reference circuit, increasing the number of capacitors so that the added capacitors are coupled to the mismatched input voltage terminals of the other units, increasing the number of switches, the added switches being connected between the added capacitors and the other units, the added capacitors and the added switches playing the same role as the capacitor group and the switch group in claim 4, and the control of the added capacitors and the added switches being the same as the method of the capacitor group and the switch group in claim 4.

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