Structure and method for SiC-based protection devices

Abstract

The invention is entitled "Structure and method for SiC-based protection devices." The invention provides a device that can include a P-N diode formed within a SiC substrate. The device can include an N-type region formed within the SiC substrate, a P-type region formed in an upper portion of the N-type region; and an implanted N-type layer disposed between the P-type region and the N-type region.

Description

Technical Field

[0001] Statement Regarding Federally Sponsored Research

[0002] This invention was completed with government support under Contract No. W911NF-15-2-0088, awarded by the Ministry of Defense. The government has certain rights to this invention.

[0003] The embodiments disclosed herein relate to protection devices in general, and particularly to SiC-based TVS diodes. Background Technology

[0004] Transient voltage suppressor (TVS) diodes are protection diodes designed to protect electronic circuits from voltage transients. A voltage transient is a surge of electrical energy with a short duration. During normal operation, TVS diodes are designed to minimize leakage current and capacitance. During a voltage transient, the TVS diode is triggered to safely release the surge current. The peak power (PP) of a TVS diode varies depending on the pulse width (t). d Characterized and reported in the product datasheet. Commercially available TVS diodes are based on silicon (Si) technology. Si TVS diodes are designed with different breakdown voltages and power ratings to meet the protection requirements of different applications. For a given breakdown voltage, the peak power rating of a TVS diode increases by increasing the die size. TVS diodes with larger die sizes have higher current handling capabilities and therefore higher peak power ratings.

[0005] For some applications, TVS diodes are expected to operate at high ambient temperatures. At high temperatures, Si TVS diodes exhibit high leakage current, limiting their maximum operating temperature. At high temperatures, the peak power handling capability of Si diodes decreases. In some implementations, multiple Si TVS diodes can be connected in series to minimize the power handling of each Si TVS diode. Using multiple Si TVS diodes requires higher circuit protection costs. The breakdown voltage of commercially available Si TVS diodes is limited from a few volts to approximately 600V or lower. For applications requiring higher breakdown voltage, multiple Si TVS diodes are used in series; this configuration reduces the diode's peak power rating.

[0006] In view of the foregoing, silicon carbide (SiC) based TVS diodes have been explored as a replacement for Si TVS diodes. The use of silicon carbide (SiC) based TVS diodes is expected to address some of the shortcomings of Si TVS diodes. First, due to the large bandgap of SiC (3.26 eV vs. 1.1 eV for Si), SiC has a lower intrinsic carrier concentration compared to Si. The lower intrinsic carrier concentration allows SiC diodes to operate at higher temperatures compared to Si diodes with lower leakage current. Due to its superior material properties, SiC TVS diodes are expected to have higher peak power ratings compared to Si TVS diodes.

[0007] Known SiC based TVS diodes can employ a similar architecture as silicon TVS diodes. An N-type substrate can be formed with the body of the TVS diode, while an N-type epitaxial layer (epi layer) is formed on the N-type substrate. A highly doped P-type region can then be formed on the N-type epi layer, with a P / N junction formed between the N-type epi layer and the P-type region defining the characteristics of the TVS diode. In some embodiments, a junction termination region can be formed around the perimeter of the P-type region. Notably, further improvements to SiC TVS diodes can help enable commercialization of the technology. In view of the foregoing, the present disclosure is provided. SUMMARY

[0008] This Summary is provided to introduce some concepts in a simplified form that are further described below in the DETAILED DESCRIPTION. This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used in determining the scope of the claimed subject matter.

[0009] In one embodiment, a device is provided. The device can include a P-N diode formed within a SiC substrate. The device can include an N-type region formed within the SiC substrate, a P-type region formed in an upper portion of the N-type region; and an implanted N-type layer disposed between the P-type region and the N-type region.

[0010] In another embodiment, a method of forming a SiC TVS diode can include providing an N-type region in a SiC substrate. The method can include implanting P-type ions to form a P-type region extending from a first surface of the N-type region. The method can further include forming an implanted N-type layer by implanting N-type ions under the P-type region, wherein the implanted N-type layer is disposed between the P-type region and the N-type region.

[0011] In additional embodiments, SiC TVS devices are provided. The SiC TVS devices can include a bulk substrate region including N-type SiC having a first dopant level. The SiC TVS devices can include an epitaxial SiC layer disposed on the bulk substrate region and including N-type SiC material having a second dopant level. The SiC TVS devices can include a P-type region formed in an upper portion of the epitaxial SiC layer; and an implanted N-type layer disposed within the epitaxial SiC layer below the P-type region, the implanted N-type layer including a third dopant level that is greater than the second dopant level. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 A unidirectional SiC TVS diode is shown in accordance with embodiments of the present disclosure;

[0013] Figure 2 An embodiment of a TVS diode is shown arranged in accordance with additional embodiments of the present disclosure;

[0014] Figure 3 A TVS diode is shown in accordance with yet additional embodiments of the present disclosure;

[0015] Figure 4 Another TVS diode is shown in accordance with yet additional embodiments of the present disclosure;

[0016] Figure 5 A TVS diode is shown in accordance with still further embodiments of the present disclosure;

[0017] Figure 6 A TVS diode is shown in accordance with additional embodiments of the present disclosure;

[0018] Figures 7A-7J A process flow for assembling a TVS diode is shown in accordance with embodiments of the present disclosure; and

[0019] Figure 8 An exemplary process flow 800 is shown in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] Exemplary embodiments will now be described below in greater detail in connection with the drawings, in which embodiments are shown. The exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout the drawings, like numbers refer to like elements.

[0021] Various embodiments provide novel SiC devices, such as TVS diodes.

[0022] Figure 1A unidirectional SiC TVS diode in accordance with embodiments of the present disclosure is shown as TVS diode 100. This structure of TVS diode 100 corresponds to a P / N diode formed within a SiC substrate 101. Notably, various portions of TVS diode 100 are not necessarily drawn to scale, including the thickness of various regions along the Z-axis of the illustrated Cartesian coordinate system. The TVS diode can be formed based on a bulk SiC substrate having a thickness in the range of 100 pm to 375 pm. In this case, the embodiments are not limited. In Figure 1 In an example, TVS diode 100 includes an N-type region 103 that includes a bulk substrate region 102, which can have a thickness of, for example, 100 pm to 375 pm. N-type region 103 can also include an epitaxial SiC layer 104 disposed on bulk substrate region 102. Epitaxial SiC layer 104 can be formed of a similar or identical N-type SiC material as bulk substrate region 102. For example, bulk substrate region 102 can be formed of a known hexagonal SiC polytype having a high bandgap such as -3.2 eV. Epitaxial SiC layer 104 can be grown as a hexagonal polytype, where the difference between epitaxial SiC layer 104 and bulk substrate region 102 is the level of N-type dopant. In other embodiments, epitaxial SiC layer 104 can be omitted, as discussed further below. In various embodiments, the thickness of epitaxial SiC layer 104 can be adjusted to adjust the electrical properties of TVS diode 100, with a representative thickness range being between 1 pm and 10 pm. In this case, the embodiments are not limited.

[0023] TVS diode 100 also includes a P-type region 106 formed in an upper portion of epitaxial SiC layer 104. P-type region 106 can be defined by a masking process to occupy a selected portion of upper surface 105, and can extend a few microns into SiC substrate 101. TVS diode 100 can also include an implanted N-type layer 108 disposed within epitaxial SiC layer below P-type region, the implanted N-type layer including a third dopant level that is greater than the second dopant level.

[0024] TVS diode 100 can also include an anode contact 110 disposed on P-type region 106, and a backside contact 114 disposed on a back surface 112 of SiC substrate 101 in contact with N-type region 103.

[0025] As Figure 1As shown, the P-type region 106 includes a lower surface 107, where the lower surface 107 extends a first distance Dl between a first end 109 and a second end 111. The lower surface 107 can be used to define a P / N junction between the P-type region 106 and the N-type region 103. The breakdown voltage of the TVS diode 100 is defined by the breakdown voltage of the P-N diode formed between the P-type region 106 and the implanted N-type layer 108. In various embodiments, the doping concentration of the P-type region 106 can be fixed, while the breakdown voltage can be modulated by varying the implant dose forming the N-type layer 108, and thus the doping concentration of the implanted N-type layer 108.

[0026] As background, the breakdown voltage of a P-N junction diode occurs when the electric field across the P-N junction exceeds a critical breakdown electric field. The electric field across the P-N junction is determined by the doping concentrations of the P-type region and the N-type region. In the TVS diode 100, the breakdown voltage can be determined by the doping concentrations of the P-type region 106 and the implanted N-type layer 108. For a given P-type region doping concentration, as the doping concentration of the implanted N-type layer 108 increases, the breakdown voltage of the TVS diode decreases. The doping concentration of the epitaxial SiC layer 104 is lower than the doping concentration of the implanted N-type layer 108. As a result, the epitaxial SiC layer 104 does not affect the breakdown voltage of the low voltage TVS diode structure.

[0027] Notably, for a TVS diode structure having a low breakdown voltage, where the doping concentration of the N-implant region needs to be greater than the doping concentration of the N- substrate region, the TVS diode can be fabricated on a wafer (substrate) that does not have an N-type epitaxial region. This latter approach can be advantageous for reducing the manufacturing cost of the low voltage TVS diode structure.

[0028] To ensure proper device breakdown, the implanted N-type layer 108 can not extend along the entire lower surface 107. In the example shown, the implanted N-type layer 108 extends along the lower surface 107 a second distance D2 that is less than the first distance Dl. Notably, the implanted N-type layer 108 is offset from the first end 109 and the second end 111. Figure 1

[0029] In various embodiments, the doping concentration of the bulk substrate region 102 is approximately 10 18 cm -3 , while the doping concentration of the epitaxial SiC layer 104 is in the range of 10 14 cm -3 to 10 17 cm -3 .

[0030] ​The doping concentration of the epitaxial SiC layer 104 can be selected such that the breakdown voltage of the PN diode formed between the P-type region 106 and the epitaxial SiC layer is higher than that of the PN diode formed between the P-type region 106 and the implanted N-type layer 108. Ohmic metallization can be used to contact the P-type region 106, as represented by the anode contact 110. In various embodiments, the metallization scheme may include nickel (Ni) or titanium (Ti) based contacts. In one example, Ni contacts can be used to contact the N-type region 103 on the surface 112 of the SiC substrate 102.

[0031] In some implementations of low-voltage SiC TVS for achieving a breakdown voltage of 30V, for example, the peak doping concentration of the p-type region 106 can be approximately 10. 20 cm -3 The doping concentration of the implanted N-type layer 108 can be approximately 10. 18 cm -3 For the TVS diode 100 to operate correctly, the doping concentration of the epitaxial SiC layer 104 is arranged to be lower than the doping concentration of the implanted N-type layer 108. For example, the doping concentration of the epitaxial SiC layer 104 can be approximately 10. 16 cm -3 .

[0032] Turn now Figure 2 An embodiment of a TVS diode 120 arranged according to an additional embodiment of the present disclosure is shown. The TVS diode 120 may share the same components as the TVS diode 100, except that a junction termination extension region (JTE region) is added, as shown in JTE region 116. JTE region 116 is disposed within the epitaxial SiC layer 104, surrounding the P-type region 106, and forming an interface region with a portion of the epitaxial SiC layer 104. Notably, the P-type region 106 may have a first P-doping level, wherein the JTE region 116 is formed by a P-type dopant having a second P-doping level lower than the first P-doping level. According to embodiments of the present disclosure, the JTE region 116 can be defined by an ion implantation operation to create a region for surrounding the P-type region 106 with a lower doping concentration of P-dopant. In some embodiments, the doping concentration of the JTE region 116 is approximately 10. 17 cm -3 In this way, the JTE region 116 can reduce the surface electric field at the edge of the device to ensure that the TVS diode 120 does not break down below the target value.

[0033] Turn now Figure 3 The diagram shows a TVS diode 130 according to another embodiment of the present disclosure. Figure 3 Implementation plan sharing and Figure 2features of TVS diode 120, additional features are not present in TVS diode 120, including an optional barrier layer, shown as a metal layer structure, denoted as barrier metal layer 122, disposed above anode contact 110. TVS diode 130 also includes a metallization region 126 formed within a window defined by a field oxide region, shown as field oxide layer 124. According to some embodiments, barrier metal layer 122 can be Ti or a combination of Ti and titanium nitride (TiN). Metallization region 126 can be an aluminum copper alloy material in some embodiments, and can have a thickness greater than 1 micron, such as 4 microns in particular embodiments. TVS diode 130 can also include a passivation layer 128 disposed above metallization region 126. An example of a suitable material system for passivation layer 128 is phosphosilicate glass (PSG) and silicon nitride (SiNx x ). In one example, the thickness of PSG can be 500 nm, while the thickness of SiNx can be 850 nm. These embodiments are not limited in this regard, however. Figure 3 As shown, a polymer layer 132, such as polyimide, is disposed above passivation layer 128. Polymer layer 132 and passivation layer 128 can be subsequently provided with openings (not shown) to allow for electrical contact and assembly with TVS diode 130. A solderable front side metallization layer containing nickel / gold or nickel / palladium / gold can also be present above metallization region 126. Notably, in embodiments of Figure 1 and Figure 2 , similar metallization and passivation schemes can be added to the respective TVS diodes, or another known suitable metallization scheme, to facilitate contacting the TVS diodes.

[0034] In the embodiments discussed above, where an epitaxial SiC layer 104 is provided, the doping levels and thicknesses of the various regions can be readily adjusted to yield a target breakdown voltage greater than 20 V and less than 650 V. In particular embodiments, the doping concentration of the epitaxial SiC layer 104 region is less than the doping concentration of the implanted N-type layer 108. The doping concentration and thickness of the implanted N-type layer 108 can be > 10 16 cm -3 and less than 10 pm, respectively. The doping level of P-type region 106 can be greater than 10 18 cm -3 , and in particular embodiments is approximately 10 20 cm -3 . Likewise, the doping level of the implanted N-type layer can be 10 18 cm -3where the precise value is determined by the target breakdown voltage of the SiC P-N diode. Further, according to some embodiments, the thickness of the bulk substrate region 102 can be 350 pm or less. Notably, the implanted N-type layer 108 can be confined within the P-type region 106. In one implementation, the implanted N-type layer 108 is spaced 10 pm from the edge of the P-type region 106. In other embodiments, the implanted N-type layer 108 can be spaced 5 pm from the edge of the P-type region 106. In such cases, the embodiments are not limited. Generally, the N-type layer is spaced from the edge of the P-type region 106 to ensure that the N-type implanted layer 108 is contained within the P-type region 106.

[0035] Turning now to Figure 4 , a TVS diode 140 according to further embodiments of the disclosure is shown. Figure 4 Embodiments of the TVS diode 140 share features similar to those of the TVS diode 130 of Figure 3 , except that the TVS diode 140 does not include the JTE region 116.

[0036] Turning now to Figure 5 , a TVS diode 150 according to further embodiments of the disclosure is shown. Figure 4 Embodiments of the TVS diode 150 share features similar to those of the TVS diode 140 of Figure 4 , except that the TVS diode 150 does not include the SiC epitaxial layer 104. The doping concentration of the implanted N-type layer 108 can be adjusted to account for the absence of the SiC epitaxial layer 104.

[0037] As an example, for a substrate having a resistivity of 0.02 ohm-cm in the bulk substrate region 102, the corresponding dopant concentration of the N-type dopant is approximately 1.6 x 1018cm-3. Thus, the doping concentration of the implanted N-type layer 108 can be greater than 1.6 x 1018cm-3. According to some embodiments, the resulting P / N diode having the structure can exhibit a breakdown voltage greater than 20 V and less than 100 V. 18 cm -3 . Thus, the doping concentration of the implanted N-type layer 108 can be greater than 1.6 x 1018cm-3. According to some embodiments, the resulting P / N diode having the structure can exhibit a breakdown voltage greater than 20 V and less than 100 V. 18 cm -3 . Thus, the doping concentration of the implanted N-type layer 108 can be greater than 1.6 x 1018cm-3. According to some embodiments, the resulting P / N diode having the structure can exhibit a breakdown voltage greater than 20 V and less than 100 V. Figure 5

[0038] Turning now to Figure 6 , a TVS diode 160 according to further embodiments of the disclosure is shown. Figure 6 Embodiments of the TVS diode 160 share features similar to those of the TVS diode 150 of Figure 5 ​Similar to the characteristics of the TVS diode 150, the JTE region 116 discussed above is added. The doping process of the JTE region 116 can be adjusted by taking into account the doping concentration of the P-type region 106 and the doping concentration of the bulk substrate region 102. It is worth noting that the concentration of the P-type dopant in the JTE region 116 is set to be lower than that in the P-type region 106. Furthermore, since the JTE region 116 can be formed by ion implantation, the implantation schedule used to form the JTE region 116 can be adjusted to compensate for the doping concentration of the pre-existing N-type dopant in the bulk substrate region 102. This is because the concentration of the N-type dopant in the bulk substrate region 102 is relatively high, such as 1.6 × 10⁻⁶. 18 cm -3 Therefore, the implantation dose of P-type ions used to form JTE region 116 will be adjusted to produce approximately 10 17 cm -3 The net P-type dopant concentration. Therefore, P-type ion implantation can introduce a concentration greater than 1.6 × 10⁻⁶. 18 The total dopant concentration is used to compensate for the concentration of active N-type dopant in the N-type dopant in the bulk substrate region 102. For comparison, in... Figure 2 In one embodiment, the JTE region is formed by implantation into the SiC epitaxial layer 104, and the N-type dopant concentration in the region of the SiC substrate 101 implanted with P-type ions can be approximately 10. 16 cm -3 Therefore, in order to generate approximately 10 in JTE region 116 17 cm -3 The net P-type dopant concentration, Figure 2 In the implementation scheme, the total dopant concentration of the P-type material can be slightly higher, such as 1.5 × 10⁻⁶. 17 cm -3 To compensate 10 16 cm -3 The concentration of N-type dopant.

[0039] Turn now Figures 7A-7J The diagram illustrates a process flow for assembling a TVS diode according to an embodiment of the present disclosure. This process flow can be specifically applied to the formation of the aforementioned TVS diode 130. Figure 7A As shown in the figure, a SiC substrate 101 is provided, which includes a bulk substrate region 102 and a SiC epitaxial layer 104.

[0040] exist Figure 7B In this embodiment, a first injection mask 180 is provided, which defines a first aperture 181 that exposes a first portion of the N-type region 103, specifically a first portion of the SiC epitaxial layer 104. Figure 7BIn the example of FIG. 1, an implant of P-type dopant species has occurred, resulting in the formation of P-type region 106. The ion energy used to implant the P-type dopant ions can be tailored to a target thickness of P-type region 106, such as a depth of a few microns. The location and lateral dimensions of P-type region 106 are defined by first aperture 181. A suitable material for first implant mask 180 is silicon oxide, while the thickness of silicon oxide can be tailored to contain ions to prevent implantation into epitaxial SiC layer 104 underneath first implant mask 180.

[0041] In the example of FIG. 1, an implant of P-type dopant species has occurred, resulting in the formation of P-type region 106. The ion energy used to implant the P-type dopant ions can be tailored to a target thickness of P-type region 106, such as a depth of a few microns. The location and lateral dimensions of P-type region 106 are defined by first aperture 181. A suitable material for first implant mask 180 is silicon oxide, while the thickness of silicon oxide can be tailored to contain ions to prevent implantation into epitaxial SiC layer 104 underneath first implant mask 180. Figure 7C In the example of FIG. 1, an implant of P-type dopant species has occurred, resulting in the formation of P-type region 106. The ion energy used to implant the P-type dopant ions can be tailored to a target thickness of P-type region 106, such as a depth of a few microns. The location and lateral dimensions of P-type region 106 are defined by first aperture 181. A suitable material for first implant mask 180 is silicon oxide, while the thickness of silicon oxide can be tailored to contain ions to prevent implantation into epitaxial SiC layer 104 underneath first implant mask 180. Figure 7C In the example of FIG. 1, an implant of P-type dopant species has occurred, resulting in the formation of P-type region 106. The ion energy used to implant the P-type dopant ions can be tailored to a target thickness of P-type region 106, such as a depth of a few microns. The location and lateral dimensions of P-type region 106 are defined by first aperture 181. A suitable material for first implant mask 180 is silicon oxide, while the thickness of silicon oxide can be tailored to contain ions to prevent implantation into epitaxial SiC layer 104 underneath first implant mask 180.

[0042] In the example of FIG. 1, an implant of P-type dopant species has occurred, resulting in the formation of P-type region 106. The ion energy used to implant the P-type dopant ions can be tailored to a target thickness of P-type region 106, such as a depth of a few microns. The location and lateral dimensions of P-type region 106 are defined by first aperture 181. A suitable material for first implant mask 180 is silicon oxide, while the thickness of silicon oxide can be tailored to contain ions to prevent implantation into epitaxial SiC layer 104 underneath first implant mask 180. Figure 7D In the example of FIG. 1, an implant of P-type dopant species has occurred, resulting in the formation of P-type region 106. The ion energy used to implant the P-type dopant ions can be tailored to a target thickness of P-type region 106, such as a depth of a few microns. The location and lateral dimensions of P-type region 106 are defined by first aperture 181. A suitable material for first implant mask 180 is silicon oxide, while the thickness of silicon oxide can be tailored to contain ions to prevent implantation into epitaxial SiC layer 104 underneath first implant mask 180. Figure 7D In the example of FIG. 1, an implant of P-type dopant species has occurred, resulting in the formation of P-type region 106. The ion energy used to implant the P-type dopant ions can be tailored to a target thickness of P-type region 106, such as a depth of a few microns. The location and lateral dimensions of P-type region 106 are defined by first aperture 181. A suitable material for first implant mask 180 is silicon oxide, while the thickness of silicon oxide can be tailored to contain ions to prevent implantation into epitaxial SiC layer 104 underneath first implant mask 180. Figure 7DAfter the instance is completed, the activation annealing procedure can be executed to activate the instance. Figures 7B-7D The procedure defines the N-dopants and P-dopants in each region.

[0043] In various non-limiting embodiments, the depth D of the P-type region 106 P It can be from 0.5μm to 2μm, while the width W of the P-type region 106 P The width can vary depending on the diode application, ranging from several hundred micrometers to several millimeters. A larger P+ width will result in a larger overall TVS diode die size, which helps the TVS to have the higher power capability required for some applications. In various other non-limiting embodiments, a width W... N The injected N-type layer 108 can be offset from the edge of the P-type region 106 by 5 μm to 10 μm (see the dashed area showing the offset). The offset ensures that the breakdown voltage is controlled and the device does not break down prematurely at the P+ junction corner.

[0044] exist Figure 7E In the subsequent example shown, an oxide layer, represented by field oxide layer 124, has been deposited. The field oxide can undergo known densification annealing and patterning to form apertures 185 over the P-type region 106, as shown.

[0045] exist Figure 7F In the subsequent example shown, the anode contact 110 and the back contact 114 have been deposited and annealed to form an ohmic contact with the semiconductor region of the TVS diode.

[0046] exist Figure 7G In the subsequent example shown, the barrier metal layer 122 and the metallization region 126 have been deposited, patterned, and etched to form the contact structure shown. Figure 7H In the subsequent example shown, the passivation layer 128 has been deposited, patterned, and etched to form the structure shown. Figure 7I In the subsequent examples shown, polymer layer 132 has been deposited, developed, and cured. Figure 7J In the subsequent example shown, as illustrated, the final metal layer 134 has been deposited on the back surface.

[0047] In various additional embodiments, any of the aforementioned TVS devices can be manufactured according to the following specifications: A) Net doping concentration of the P-type region 106: 10 18 cm -3 Up to 10 20 cm -3 B) Net doping concentration of P-type JTE region 116: 1 × 10⁻⁶ 17 cm -3 Up to 5×10 17 cm -3; C) Net Doping Concentration of N Epitaxial Layer: 1 x 1014cm-2to 5 x 1016cm-2; and D) Net Doping Concentration of Implanted N Region: 1 x 1014cm-2to 5 x 1016cm-2. 14 cm -3 to 5 x 1016cm 17 cm -3 to 5 x 1016cm 16 cm -3 to 5 x 1016cm 18 cm -3 . This range of doping concentrations will result in devices with breakdown voltage ranging from 15V to 600V.

[0048] In summary, the present embodiments provide various advantages over Si-based TVS devices. The SiC-based TVS diodes of the present embodiments provide the ability to design the breakdown voltage in a semiconductor die in a range of voltages such as greater than 15V up to 600V, while avoiding the need to connect multiple dies in series, as in the case of Si diodes for higher voltages. The present embodiments also provide a more robust diode for high temperature operation, with reduced leakage compared to Si TVS diodes.

[0049] Figure 8 An exemplary process flow 800 in accordance with an embodiment of the present disclosure is shown. At block 802, an N-type region is provided in a SiC substrate. The N-type region can include a bulk substrate region having a first doping level and an epitaxial SiC layer having a second doping level less than the first doping level.

[0050] At block 804, an operation of implanting P-type ions to form a P-type region extending from a first surface of the N-type region is performed. At block 806, an implanted N-type layer is formed by implanting N-type ions below the P-type region. The implanted N-type layer can be disposed between the P-type region and the N-type region accordingly.

[0051] While devices and methods associated with TVS diodes have been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes can be made and equivalents can be substituted for elements without departing from the spirit and scope of the claims of the present application. In addition, many modifications can be made to adapt a particular situation or material to the teachings of the disclosure without departing from its scope. Therefore, the claims should not be construed as limited to any one particular embodiment, but rather to the full scope of the claims. Accordingly, the claims are not to be construed as being limited to any one particular embodiment, but rather to the full scope of the claims.

Claims

1. A SiC transient voltage suppressor device, comprising: A PN diode formed within a SiC substrate and comprising: An N-type region is formed within the SiC substrate; A P-type region is formed in the upper portion of the N-type region, the P-type region having a first P-doping level and extending along the upper surface of the SiC substrate; An injected N-type layer, wherein the injected N-type layer is disposed between the P-type region and the N-type region; and A junction termination extension region is disposed around the P-type region and forms an interface region with the N-type region. The junction termination extension region includes a P-type dopant having a second P-doping level lower than the first P-doping level. Anode contact, which is disposed on the P-type region; Back contact, the back contact is disposed on the back surface of the SiC substrate and contacts the N-type region; A field oxide region, wherein the field oxide region defines a window above the P-type region; A metal layer structure, wherein the metal layer structure is configured to contact the anode contact; A passivation layer is disposed above the metal layer structure; and A polymer layer is disposed above the metal layer structure. The polymer layer and the passivation layer define openings for contacting the metal layer structure.

2. The SiC transient voltage suppressor device according to claim 1, wherein, The first P-doping level is 10. 20 cm -3 And wherein the second P doping level is 10. 17 cm -3 .

3. The SiC transient voltage suppressor device according to claim 1, wherein, The P-type region includes a lower surface that extends a first distance between a first end and a second end, wherein the injected N-type layer extends along the lower surface a second distance less than the first distance and is offset from the first end and the second end.

4. The SiC transient voltage suppressor device according to claim 2, wherein, The P-type region includes a lower surface, wherein the injected N-type layer extends along the lower surface and is offset from the junction terminal extension region.

5. The SiC transient voltage suppressor device according to claim 1, comprising a breakdown voltage greater than 20V and less than 650V.

6. The SiC transient voltage suppressor device according to claim 1, wherein the N-type region includes a bulk substrate region, and wherein, The injected N-type layer is formed within the bulk substrate region.

7. The SiC transient voltage suppressor device according to claim 6, wherein the PN diode has a breakdown voltage greater than 20V and less than 100V.

8. A method for forming a SiC transient voltage suppressor diode, comprising: An N-type region is provided in a SiC substrate, the N-type region having a first surface defining a surface of the SiC substrate; P-type ions are implanted to form a P-type region having a first P-doping level and extending along a first surface of the N-type region; An implanted N-type layer is formed by implanting N-type ions below the P-type region, the implanted N-type layer being disposed between the P-type region and the N-type region; A junction termination extension region is formed by implanting a P-type dopant around the P-type region within the N-type region, wherein the junction termination extension region includes a second P-doping level that is lower than the first P-doping level. Anode contacts are formed on the P-type region; Forming back contact points on the back surface of the SiC substrate to contact the N-type region; A field oxide region is formed above the P-type region, defining a window; A metal layer structure is formed that is configured to contact the anode contact; A passivation layer is formed on top of the metal layer structure; as well as A polymer layer is formed on top of the metal layer structure. The polymer layer and the passivation layer define openings for contacting the metal layer structure.

9. The method according to claim 8, wherein, The first P-doping level is 10. 20 cm -3 And wherein the second P doping level is 10. 17 cm -3 .

10. The method according to claim 8, wherein, The formation of the implanted N-type layer includes implanting the N-type ions through a first implantation mask, wherein the formation of the P-type region includes implanting the P-type ions through a second implantation mask, wherein the second implantation mask is arranged such that the P-type region extends a first distance between a first end and a second end, and wherein the first implantation mask is arranged such that the implanted N-type layer extends a second distance less than the first distance and is offset from the first end and the second end.

11. The method of claim 9, wherein forming the implanted N-type layer comprises implanting the N-type ions through a first implantation mask, wherein forming the junction termination extension region comprises implanting the P-type ions through a junction termination extension mask, wherein the junction termination extension mask is arranged such that the P-type region extends between a first end and a second end by a first distance, and wherein the first implantation mask is arranged such that the implanted N-type layer extends by a second distance less than the first distance and is offset from the first end and the second end.

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