Testing methods for integrated circuit chips and fuses

Abstract

The present disclosure is about a test method for an integrated circuit chip and a fuse, comprising: a substrate, a multi-layer conductive layer, a dielectric layer, a fuse and a latch circuit; wherein a dielectric layer is arranged between adjacent conductive layers, a dielectric layer is arranged between the substrate and the conductive layer adjacent thereto, and a contact hole is arranged on the dielectric layer; the fuse is located on the first conductive layer, the first conductive layer is the conductive layer located at the topmost layer among the multi-layer conductive layers, wherein the layer close to the substrate is the bottom layer, and the layer far from the substrate is the top layer; the latch circuit is arranged on the substrate and connected to the fuse. When testing the integrated circuit chip, the latch effect is triggered, so that the current in the latch circuit increases continuously until the fuse is blown, thereby achieving the fusing of the fuse during the test. And when testing multiple fuses, it is only necessary to sequentially trigger the latch circuit of each fuse, thereby improving the test efficiency and saving the test time.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a method for testing an integrated circuit chip and a fuse. Background Art

[0002] With the development and progress of technology, integrated circuits are used more and more widely, and a large number of fuses are often included in the integrated circuits.

[0003] Currently, fuses used in integrated circuits are generally gate oxide fuses, which are in an open circuit state before being blown. When the gate oxide fuse is blown, a large voltage difference needs to be applied between the conductive gate and the heavily doped layer to blow the fuse.

[0004] When testing integrated circuits, fuses need to be tested. Gate oxide fuses have low melting efficiency, resulting in long testing time and low testing efficiency.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The purpose of the present disclosure is to provide a method for testing an integrated circuit chip and a fuse, thereby overcoming the problems of long integrated circuit testing time and low testing efficiency caused by the limitations and defects of related technologies to at least a certain extent.

[0007] According to one aspect of the present disclosure, there is provided an integrated circuit chip, comprising:

[0008] substrate;

[0009] A multilayer conductive layer, wherein a dielectric layer is disposed between adjacent conductive layers, a dielectric layer is disposed between the substrate and the conductive layer adjacent thereto, and a contact hole is disposed on the dielectric layer;

[0010] A fuse is located on a first conductive layer, wherein the first conductive layer is a conductive layer located at the top of a plurality of conductive layers, wherein a layer close to the substrate is a bottom layer, and a layer far from the substrate is an upper layer;

[0011] The latch circuit is arranged in the substrate and connected to the fuse.

[0012] According to an embodiment of the present disclosure, a first through hole is provided on the first conductive layer, and the fuse is located in the through hole.

[0013] According to an embodiment of the present disclosure, the integrated circuit chip further includes:

[0014] The connector is located in the contact hole of the dielectric layer and is used to connect the conductive layers on both sides of the dielectric layer.

[0015] According to an embodiment of the present disclosure, the first conductive layer is used to connect to a power source and to receive a power signal.

[0016] According to an embodiment of the present disclosure, a circuit break detection device is connected to the second conductive layer, and the circuit break detection device is used to detect whether the fuse is blown, and the second conductive layer is a conductive layer located between the first conductive layer and the substrate.

[0017] According to an embodiment of the present disclosure, the fuse is a metal fuse.

[0018] According to an embodiment of the present disclosure, the plurality of conductive layers and the substrate are arranged parallel to each other.

[0019] According to an embodiment of the present disclosure, the fuse is a fuse wire, and a resistance of the fuse wire is greater than a resistance of the first conductive layer and a resistance of the connector.

[0020] According to an embodiment of the present disclosure, a width of the fuse is smaller than a width of the first conductive layer.

[0021] According to an embodiment of the present disclosure, the thickness of the fuse is smaller than the thickness of the first conductive layer.

[0022] According to an embodiment of the present disclosure, the integrated circuit chip further includes:

[0023] The passivation layer is located on a side of the first conductive layer away from the substrate.

[0024] According to another aspect of the present disclosure, a method for testing an integrated circuit chip fuse is provided, comprising:

[0025] Triggering the latch effect of the latch circuit and outputting a fuse current;

[0026] The fusing current flows through the connector, the conductive layer and the fuse, and blows the fuse.

[0027] According to one embodiment of the present disclosure, the testing method further includes:

[0028] Detecting whether the fuse is blown;

[0029] If the fuse is blown, a first signal is output;

[0030] If the fuse is not blown, a second signal is output.

[0031] The present invention provides an integrated circuit chip, in which a fuse is arranged on a first electrical layer, and the fuse is connected to a latch circuit. When the integrated circuit chip is tested, the latch effect is triggered, so that the current in the latch circuit is continuously increased until the fuse is blown, thereby achieving the fusing of the fuse during the test. When testing multiple fuses, it is only necessary to sequentially trigger the latch circuit of each fuse, thereby improving the test efficiency and saving the test time.

[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0034] Figure 1 A schematic structural diagram of an integrated circuit chip provided by an exemplary embodiment of the present disclosure.

[0035] Figure 2 A fuse connection schematic diagram is provided for an exemplary embodiment of the present disclosure.

[0036] Figure 3 A top view of a fuse and a conductive layer provided for an exemplary embodiment of the present disclosure.

[0037] Figure 4 A schematic cross-sectional view of a fuse provided by an exemplary embodiment of the present disclosure.

[0038] Figure 5 A schematic structural diagram of a CMOS device provided by an exemplary embodiment of the present disclosure.

[0039] Figure 6 for Figure 5 The equivalent circuit of the parasitic latch circuit of the CMOS device is shown.

[0040] Figure 7 A schematic structural diagram of another CMOS device provided by an exemplary embodiment of the present disclosure.

[0041] Figure 8 for Figure 6 The equivalent circuit of the parasitic latch circuit of the CMOS device is shown.

[0042] Fig. 9 A latch circuit trigger signal diagram is provided for an exemplary embodiment of the present disclosure.

[0043] Fig.10 A flow chart of a method for detecting an integrated circuit chip fuse is provided for an exemplary embodiment of the present disclosure.

[0044] Fig.11 A flow chart of another integrated circuit chip fuse detection method provided by an exemplary embodiment of the present disclosure.

[0045] In the figure:

[0046] 100, substrate; 200, conductive layer; 210, first conductive layer; 220, second conductive layer; 300, dielectric layer; 400, fuse; 500, latch circuit; 600, connector; 700, passivation layer. DETAILED DESCRIPTION

[0047] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0048] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0049] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0050] In the related art, gate oxide fuses are usually used in integrated circuits. Gate oxide fuses are in an open circuit state before they are blown. When they are blown, a large voltage difference needs to be applied between the conductive gate and the heavily doped layer to blow the fuse. When testing fuses, for multiple fuses, it is often necessary to first perform a blow test on one of the fuses. When one fuse is blown, another fuse is blown, resulting in a long test time and low test efficiency.

[0051] In this exemplary embodiment, an integrated circuit chip is first provided, such as Figure 1 As shown, the integrated circuit chip includes: a substrate 100, a multi-layer conductive layer 200, a fuse 400 and a latch circuit 500;

[0052] A dielectric layer 300 is disposed between adjacent conductive layers 200 , a dielectric layer 300 is disposed between the substrate 100 and the adjacent conductive layer 200 , and a contact hole is disposed on the dielectric layer 300 ;

[0053] The fuse 400 is located on the first conductive layer 210, wherein the first conductive layer 210 is the uppermost conductive layer 200 among the multiple conductive layers 200, wherein the layer close to the substrate 100 is the bottom layer and the layer far from the substrate 100 is the upper layer;

[0054] The latch circuit 500 is disposed in the substrate 100 and connected to the fuse 400 . After the latch effect is triggered, the current in the latch circuit 500 increases continuously and blows the fuse 400 .

[0055] An integrated circuit chip provided by the embodiment of the present disclosure has a fuse 400 disposed on a first conductive layer, and the fuse 400 is connected to a latch circuit 500. When the integrated circuit chip is tested, the latch effect is triggered, so that the current in the latch circuit 500 increases continuously until the fuse 400 is blown, thereby achieving the blowing of the fuse 400 during the test. When testing multiple fuses 400, it is only necessary to sequentially trigger the latch circuit 500 of each fuse 400, thereby improving the test efficiency and saving the test time.

[0056] Furthermore, since the dielectric layer 300 is an insulating layer, in order to achieve electrical connection between the multiple conductive layers 200, the integrated circuit chip provided by the embodiment of the present disclosure may also include a connector 600, and the connector 600 is located in a contact hole in the dielectric layer 300. The connector 600 is used to connect the conductive layers 200 on the upper and lower sides of the dielectric layer 300 where it is located. The dielectric layer 300 located at the bottom layer has its lower side in contact with the substrate 100, and its upper side in contact with the second conductive layer 220. The latch circuit 500 is arranged in the substrate 100, and the contact hole on the dielectric layer 300 in contact with the substrate 100 is correspondingly arranged with the latch circuit 500, and the conductive layer 200 and the latch circuit 500 are connected through the connector 600 in the contact hole.

[0057] The connector 600 may be a connecting wire, a conductive connecting block, etc., which is not specifically limited in the embodiment of the present disclosure.

[0058] The integrated circuit chip provided by the embodiment of the present disclosure further includes a passivation layer 700, which is located on the surface of the first conductive layer 210 away from the substrate 100. The first conductive layer 210 is located at the uppermost layer of the multi-layer conductive layer 200. The passivation layer 700 is used to prevent contamination of the surface of the integrated circuit chip and protect the conductive layer 200.

[0059] A first through hole is provided on the first conductive layer 210, and the fuse 400 is located in the through hole. The first conductive layer 210 is connected to a power supply for receiving a power supply signal. The power supply signal can be a high level or a low level. The power supply, the fuse 400 and the latch circuit 500 form a fuse 400 detection circuit. When the fuse 400 is tested, the latch effect is triggered by the trigger signal, the current in the latch circuit 500 increases continuously, and the current flowing through the fuse 400 increases continuously until the fuse 400 is blown.

[0060] In practical applications, the fuse 400 and the first conductive layer 210 may also be an integrated structure. By etching the first conductive layer 210 , the thickness of the first conductive layer 210 at the position of the fuse 400 is reduced to form the fuse 400 .

[0061] The second conductive layer 220 is connected with a circuit breaking detection device for detecting whether the fuse 400 is blown. The second conductive layer 220 is a conductive layer 200 located between the first conductive layer 210 and the substrate 100. The circuit breaking detection device may be a latch circuit or other circuit breaking detection circuits.

[0062] For example, Figure 1As shown, an integrated circuit chip includes three conductive layers 200, and a fuse 400 is arranged in the topmost first conductive layer 210. A connector 600 is arranged in the contact hole of the dielectric layer 300, and a latch circuit 500 is arranged in the substrate 100. The latch circuit 500 is connected to the connector 600 in the dielectric layer 300 contacting the substrate 100. Through the conductive layer 200 and the connector 600 thereon, the connection with the fuse 400 is finally achieved.

[0063] Furthermore, in order to ensure that when the latch effect is triggered, the current in the circuit continues to increase, the fuse 400 is blown without damaging other devices. In the embodiment of the present disclosure, the fuse 400 and the connector 600 can be made of the same conductive material. At this time, the resistance of the fuse 400 needs to be greater than the resistance of the connector 600 and the resistance of the first conductive layer 210, so as to ensure that the fuse 400 is blown first when the fuse is blown, and other devices are not damaged.

[0064] For example, Figure 3 and Figure 4 As shown, the width d of the fuse 400 can be designed to be smaller than the width D of the first conductive layer 210. The width of the fuse 400 can be 50nm to 300nm, the length L of the fuse 400 is 50nm to 300nm, the height Z of the fuse 400 is 100nm to 350nm, and the width 2d of the first conductive layer 210 is <D<3d。

[0065] The multiple conductive layers 200 are arranged in parallel with each other, and the conductive layers 200 and the substrate 100 are arranged in parallel, wherein the conductive layer 200 is a metal conductive layer, and its material can be copper or aluminum, and the connector 600 is a metal connector. The fuse 400 can be a fuse or other fuse, and the material of the fuse can be the same as or different from that of the connector 600. The thickness of the fuse is less than the thickness of the first conductive layer 210.

[0066] The latch circuit described in the embodiment of the present disclosure may be a parasitic circuit generated by the latch effect of a CMOS device. For example, in a feasible implementation of the present disclosure, Figure 5 The parasitic circuit generated by the CMOS device shown in the figure. The CMOS includes a substrate Su, on which NMOS and PMOS are arranged. The NMOS includes a P-type silicon substrate Su with a low doping concentration, that is, the P well PW shown in the figure, and two heavily doped N+ regions and one heavily doped P+ region are made on the P well PW. The PMOS includes an N-type silicon substrate Su with a low doping concentration, that is, the N well NW shown in the figure, and two heavily doped P+ regions and one heavily doped N+ region are made on the N well NW.

[0067] In CMOS, due to the latch effect, a first parasitic transistor Q1 and a second parasitic transistor Q2 are formed. The first emitter and the second emitter of the first parasitic transistor Q1 are connected to a high level, the collector is connected to a low level, and the base receives a first trigger signal; the collector of the second parasitic transistor Q2 is connected to the base of the first transistor, the collector is connected to a high level, the base is connected to the collector of the first parasitic transistor Q1, the base receives the second trigger signal, and the first emitter and the second emitter are connected to a low level to form a latch circuit.

[0068] The equivalent circuit of the latch circuit is as follows Figure 6 As shown, the fuse can be connected to the first emitter of the first parasitic transistor Q1, one end of the fuse Fu is connected to the first emitter of the first parasitic transistor Q1, and the other end is connected to the power supply. Correspondingly, in CMOS, the fuse Fu is connected to the source of PMOS. When the latching effect of CMOS is triggered, the current in the latch circuit continues to increase, and the current flowing through the fuse Fu also continues to increase, and finally the fuse Fu is blown. Of course, the fuse can also be set at the second emitter of the first parasitic transistor Q1, the first emitter of the second parasitic transistor Q2, or the second emitter of the second parasitic transistor Q2.

[0069] In practical applications, the substrate can be provided with Figure 5 The CMOS shown in the figure, during detection, triggers the latch effect of the CMOS through a trigger signal, so that the current flowing through the fuse increases continuously and burns the fuse. The trigger signal can be an overshoot signal or an undershoot signal at the trigger end of the latch circuit. For example, Figure 6 In the circuit shown in , the first receiving terminal G1 is set at the base of the second parasitic transistor Q2, the second receiving terminal G2 is set at the base of the first parasitic transistor Q1, the third receiving terminal G3 is set at the high level end, and the fourth receiving terminal G4 is set at the low level end. Fig.10 The trigger signal shown triggers the latch circuit.

[0070] In another feasible embodiment of the present disclosure, the Figure 7 The structure shown produces a latch circuit such as Figure 7As shown, the structure includes a substrate Su, on which an N-type region and a P-type region, namely, an N-well NW and a P-well PW, are arranged. Heavily doped P+ and N+ are made on the N-well NW, and heavily doped P+ and N+ are made on the P-well PW. A third parasitic transistor Q3 and a fourth parasitic transistor Q4 are formed on the structure, wherein the emitter of the third parasitic transistor Q3 is connected to a high level, the collector is connected to a low level, and the base receives a first trigger signal; the collector of the fourth parasitic transistor Q4 is connected to the base of the third transistor, the collector is connected to a high level, the base is connected to the collector of the first parasitic transistor Q1, the base receives a second trigger signal, and the emitter is connected to a low level, forming a latch circuit. In the latch circuit, when the trigger signal is received, the current in the latch circuit gradually increases.

[0071] Figure 8 for Figure 7 The equivalent circuit diagram of the parasitic circuit and the fuse Fu is as follows: Figure 8 As shown, the fuse Fu can be connected to the emitter of the third parasitic transistor Q3. One end of the fuse Fu is connected to the emitter of the third parasitic transistor Q3, and the other end is connected to the power supply. Correspondingly, the P+ end on the N-type region. When the latching effect is triggered, the current in the latch circuit continues to increase, and the current flowing through the fuse Fu also continues to increase, and finally the fuse Fu is blown. Of course, the fuse can also be set at the emitter of the fourth parasitic transistor Q4.

[0072] In practical applications, the substrate can be provided with Figure 7 The structure shown, during detection, triggers the latching effect of the CMOS through a trigger signal, so that the current flowing through the fuse increases continuously and the fuse is blown. The trigger signal can be an overshoot signal or an undershoot signal at the trigger end of the latch circuit.

[0073] This exemplary embodiment also provides a method for testing an integrated circuit chip fuse, such as Fig.10 , the method comprises the following steps:

[0074] Step S1, triggering the latch effect of the latch circuit to output a fusing current;

[0075] Step S2, the fusing current flows through the connector, the conductive layer and the fuse to blow the fuse.

[0076] By triggering the latch effect of the latch circuit, the fuse current output by the latch circuit is continuously increased, thereby quickly blowing the fuse, saving detection time. When multiple fuses are tested, it is only necessary to sequentially trigger the latch circuit to ensure the blowing of the fuses, avoiding the need to detect the current fuse before blowing another fuse in the related art, saving detection time and improving detection efficiency.

[0077] Optional, such as Fig.11 As shown, the integrated circuit chip fuse detection method provided by the embodiment of the present disclosure may further include, after step S2:

[0078] Step S3, detecting whether the fuse is blown;

[0079] Step S4, if the fuse is blown, outputting a first signal;

[0080] Step S5: if the fuse is not blown, output a second signal.

[0081] In step S3, whether the fuse is blown can be detected by a circuit breaking detection device, such as a latching circuit; in step S4, if the fuse is blown, the entire circuit is open, and the circuit breaking detection device outputs a first signal to indicate that the fuse has been blown; in step S5, if the fuse is blown, a second signal is output, and the second signal is used to indicate that the fuse is unqualified or the circuit is faulty.

[0082] By detecting whether the fuse is blown, and outputting a first signal when the fuse is blown, and outputting a second signal when the fuse is not blown, the fuse test result is easy to obtain, avoiding the problem that the fuse test result cannot be directly obtained due to the fuse being located inside the integrated circuit chip.

[0083] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. An integrated circuit chip, characterized in that: include: substrate; A multilayer conductive layer, wherein a dielectric layer is disposed between adjacent conductive layers, a dielectric layer is disposed between the substrate and the conductive layer adjacent thereto, and a contact hole is disposed on the dielectric layer; A connector, located in the contact hole of the dielectric layer, for connecting the conductive layers on both sides of the dielectric layer; A fuse is located on a first conductive layer, wherein the first conductive layer is the uppermost conductive layer among multiple conductive layers, wherein the layer close to the substrate is the bottom layer, and the layer far from the substrate is the upper layer; a first through hole is provided on the first conductive layer, and the fuse is located in the first through hole, or the fuse and the first conductive layer are an integrated structure; A latch circuit is arranged in the substrate, the connector in the dielectric layer in contact with the substrate is arranged corresponding to the latch circuit, and the latch circuit is connected to the fuse through the connector and the multi-layer conductive layer; The fuse is a fuse wire, and a thickness of the fuse wire is smaller than a thickness of the first conductive layer.

2. The integrated circuit chip according to claim 1, wherein: The first conductive layer is used for connecting to a power source and receiving a power signal.

3. The integrated circuit chip according to claim 1, wherein: The second conductive layer is connected to a circuit breaking detection device, and the circuit breaking detection device is used to detect whether the fuse is blown. The second conductive layer is a conductive layer located between the first conductive layer and the substrate.

4. The integrated circuit chip according to claim 1, wherein: The fuse is a metal fuse.

5. The integrated circuit chip according to claim 1, wherein: The plurality of conductive layers and the substrate are arranged parallel to each other.

6. The integrated circuit chip according to claim 1, wherein: The resistance of the fuse is greater than the resistance of the first conductive layer and the resistance of the connector.

7. The integrated circuit chip according to claim 6, wherein: A width of the fuse is smaller than a width of the first conductive layer.

8. The integrated circuit chip according to any one of claims 1 to 7, characterized in that: The integrated circuit chip further comprises: The passivation layer is located on a side of the first conductive layer away from the substrate.

9. A method for testing an integrated circuit chip fuse, using the integrated circuit chip according to any one of claims 1 to 7, characterized in that: include: Triggering the latch effect of the latch circuit and outputting a fuse current; The fusing current flows through the connector, the conductive layer and the fuse, and blows the fuse.

10. The testing method according to claim 9, characterized in that: Also includes: Detecting whether the fuse is blown; If the fuse is blown, a first signal is output; If the fuse is not blown, a second signal is output.

Images