Display device

Abstract

A display device is provided. The display device has a display area and a non-display area surrounding the display area. The display device includes, in the non-display area: a first power line; a driving circuit on a layer above the first power line; and a second power line electrically connected to the first power line and on the same layer as an electrode on which the driving circuit is disposed.

Description

Technical Field

[0001] Aspects of the present invention relate to a display device. Background Art

[0002] A display device such as an organic light emitting display and a liquid crystal display includes a plurality of pixels disposed in a display area and a driving circuit and power lines disposed in a non-display area.

[0003] Since the demand for a compact and high-resolution display device has recently increased, the relative amount of space occupied by the driving circuit and power lines in the non-display area has increased. Accordingly, there is a need for an efficient spatial layout between the driving circuit and the wiring. Summary of the Invention

[0004] Aspects of embodiments are directed to a display device having a reduced or minimized non-display area.

[0005] Additional aspects will be set forth in part in the description which follows, will become apparent from the description, or may be learned by practice of the presented embodiments.

[0006] According to some embodiments, there is provided a display device having a display area and a non-display area surrounding the display area, the display device including in the non-display area: a first power line; a driving circuit on a layer above the first power line; and a second power line electrically connected to the first power line and on the same layer as an electrode on which the driving circuit is disposed.

[0007] In some embodiments, the display device further includes: a display device disposed in the display area and including a pixel electrode, a counter electrode, and an emission layer between the pixel electrode and the counter electrode.

[0008] In some embodiments, the counter electrode is electrically connected to the first power line and the second power line.

[0009] In some embodiments, the first power line overlaps a part of the driving circuit.

[0010] In some embodiments, the second power line overlaps a part of the first power line.

[0011] In some embodiments, the driving circuit includes at least one thin film transistor, and the second power line is on the same layer as at least one of a gate electrode, a source electrode, and a drain electrode of at least one thin film transistor of the driving circuit.

[0012] In some embodiments, the display device further includes: a first connection electrode on a layer between the first power line and the second power line, the first connection electrode electrically connecting the first power line to the second power line.

[0013] In some embodiments, the display device further includes: a second connection electrode, on a layer above the second power line and electrically connecting the second power line to the counter electrode.

[0014] In some embodiments, the display device in the display area further includes: a shielding layer, on the same layer on which the first power line is disposed; and a pixel circuit, on a layer above the shielding layer and at least partially overlapping with the shielding layer.

[0015] In some embodiments, the shielding layer is electrically connected to one electrode of the pixel circuit.

[0016] In some embodiments, the display device further includes: an organic layer and an inorganic layer between the first power line and the driving circuit.

[0017] In some embodiments, the display device further includes: a third power line, separated from the first power line on the same layer on which the first power line is disposed.

[0018] In some embodiments, the display device further includes: a fourth power line, separated from the second power line on the same layer on which the second power line is disposed.

[0019] According to some embodiments, there is provided a display device including: a substrate including a display area and a non-display area; pixels in the display area and including a pixel circuit and a display device; at least one power line in the non-display area; and a driving circuit in the non-display area and at least partially overlapping with the at least one power line.

[0020] In some embodiments, the at least one power line includes: a first power line on a layer below the driving circuit; and a second power line on the same layer on which one electrode of the driving circuit is disposed and electrically connected to the first power line.

[0021] In some embodiments, the first power line and the second power line are electrically connected to one electrode of the display device of the pixel.

[0022] In some embodiments, the driving circuit includes at least one thin film transistor, and the second power line is on the same layer on which at least one of the gate electrode, source electrode, and drain electrode of the at least one thin film transistor of the driving circuit is disposed.

[0023] In some embodiments, the display device further includes: a connection electrode between the first power line and the second power line and electrically connecting the first power line to the second power line.

[0024] In some embodiments, the substrate includes: a first organic layer; a first inorganic layer located on the first organic layer; a second organic layer located on the first inorganic layer; and a second inorganic layer located on the second organic layer, wherein a first power line is located between the first organic layer and the second organic layer, and wherein a driving circuit is located above the second inorganic layer.

[0025] In some embodiments, the display device further includes: a shielding layer located on a layer below the pixel, wherein the shielding layer is located on the same layer on which the first power line is disposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] These and / or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment;

[0028] Figure 2 is Figure 1 the circuit diagram of the pixel shown in;

[0029] Figure 3 is along Figure 1 the cross-sectional view taken along line I-I' of;

[0030] Figures 4A to 4G is a schematic cross-sectional view showing a method of manufacturing a Figure 3 display device; and

[0031] Figures 5 to 9 is along Figure 1 the cross-sectional view of a display device according to other exemplary embodiments taken along line I-I'. DETAILED DESCRIPTION

[0032] The present disclosure admits of various suitable alterations and numerous embodiments, and some embodiments will be shown in the drawings and described in detail in the written description. Hereinafter, the effects and features of the present disclosure and the methods for realizing them will be described more fully with reference to the drawings, in which some embodiments of the present disclosure are shown. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0033] It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, the layer, region or component may be formed directly or indirectly on the other layer, region or component. That is, for example, there may be intermediate layers, intermediate regions or intermediate components.

[0034] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, without departing from the spirit and scope of the inventive concept, the first element, first component, first region, first layer or first section discussed below may be referred to as a second element, second component, second region, second layer or second section.

[0035] For ease of description, spatial relative terms such as "below", "beneath", "lower", "under", "above", "upper", etc. may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "below" or "beneath" or "under" other elements or features will then be oriented "above" the other elements or features. Thus, the example terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein should be interpreted accordingly. Further, it will be understood that when a layer is referred to as being "between" two layers, that layer can be the only layer between the two layers, or there may also be one or more intervening layers.

[0036] The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the inventive concept. As used herein, unless the context clearly dictates otherwise, the singular forms are also intended to include the plural forms. It will also be understood that the terms "comprises", "comprising", "includes" and / or "including" when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] For the purposes of the present disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as being only X, only Y, only Z, or any combination of two or more of X, Y and Z, such as, by way of example, XYZ, XYY, YZ and ZZ.

[0038] In addition, when describing embodiments of the inventive concept, the use of "may" indicates "one or more embodiments of the inventive concept". Additionally, the term "exemplary" is intended to indicate an example or illustration.

[0039] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to", or "adjacent to" another element or layer, the element or layer can be directly on, directly connected to, directly coupled to, or directly adjacent to the other element or layer, or there can be one or more intervening elements or layers. When an element or layer is referred to as being "directly on", "directly connected to", "directly coupled to", or "immediately adjacent to" another element or layer, there are no intervening elements or layers.

[0040] As used herein, the terms "use" and its variations can be considered synonymous with the terms "utilize" and its variations, respectively.

[0041] The driving circuit and / or any other related devices or components according to embodiments of the present invention described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a suitable combination of software, firmware, and hardware. For example, various components of the driving circuit can be formed on one integrated circuit (IC) chip or on multiple separate IC chips. Additionally, various components of the driving circuit can be implemented on a flexible printed circuit film, tape carrier package (TCP), printed circuit board (PCB), or various components of the driving circuit can be formed on the same substrate. Further, various components of the driving circuit can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components for performing the various functions described herein. The computer program instructions are stored in a memory, which can be implemented using a standard memory device such as, for example, random access memory (RAM) in a computing device. The computer program instructions can also be stored in other non-transitory computer-readable media such as, for example, CD-ROMs, flash drives, etc. Additionally, those skilled in the art will recognize that, without departing from the scope of the exemplary embodiments of the present invention, the functions of various computing devices can be combined into or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0042] For convenience of explanation, the dimensions of elements in the drawings may be exaggerated. In other words, since the dimensions and thicknesses of components in the drawings are arbitrarily shown for convenience of explanation, the following embodiments are not limited thereto.

[0043] When a certain embodiment can be implemented differently, a specific process order may be executed in an order different from the described order. For example, two consecutively described processes may be executed substantially simultaneously or in an order opposite to the described order.

[0044] One or more embodiments disclosed will be described in more detail below with reference to the accompanying drawings. Regardless of the figure numbers, the same or corresponding components are given the same reference numerals, and repeated explanations may not be provided.

[0045] Figure 1 is a schematic diagram of a display device 10 according to an exemplary embodiment.

[0046] Referring to Figure 1 , the substrate 100 of the display device 10 may include a display area DA and a non-display area NA around (e.g., surrounding / framing the display area DA) the display area DA. In the display area DA of the substrate 100, a plurality of pixels PX may be arranged. In the non-display area NA of the substrate 100, a driving circuit DRV and various wirings for transmitting electrical signals may be provided.

[0047] The display device 10 may be a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoretic display, an electro-wetting display, etc. Hereinafter, an organic light emitting display will be described as an example.

[0048] The substrate 100 may include a pair of sides parallel to each other in a first direction and a pair of sides parallel to each other in a second direction. The substrate 100 may have an approximate rectangular shape as shown in Figure 1 , but the embodiment is not limited thereto. For example, the substrate 100 may be set to various suitable shapes, such as a closed polygon including straight edges, a circular or elliptical shape both including curved edges, a semi-circular or semi-elliptical shape both including straight edges and curved edges, etc. According to an embodiment, when the substrate 100 has straight edges, at least some of the corners of each of the foregoing shapes may be curved. For example, when the substrate 100 has a substantially rectangular shape, the intersection portion between adjacent straight edges may be replaced by a curve having a specific curvature. In other words, the vertex portions in other cases of the rectangular shape may be formed as curved edges, the curved edges including both ends connected to adjacent two straight edges and having a specific curvature. The curvature may be set differently according to the position of the curve of the substrate 100. For example, the curvature may change according to, for example, the starting position of the curve and the length of the curve.

[0049] The display area DA may have a shape corresponding to the shape of the substrate 100. For example, being similar to the shape of the substrate 100, the display area DA may be set to various suitable shapes, such as a closed polygon including straight edges, a circular or elliptical shape both including curved edges, a semi-circular or semi-elliptical shape both including straight edges and curved edges, etc. According to an embodiment, when the display area DA has straight edges, at least some of the corners of each of the foregoing shapes may be curved.

[0050] In the display area DA, a plurality of pixels PX may be arranged in a first direction and a second direction according to a specific pattern (e.g., arranged in a matrix form). Each pixel PX may include a display device and a pixel circuit electrically connected to the display device. The pixel circuit may include at least one thin film transistor (TFT) and at least one capacitor. The display device may be an organic light emitting device (OLED). The display area DA is an area for displaying an image.

[0051] The non-display area NA is an area where the pixels PX are not arranged and thus is an area where an image is not displayed. In the non-display area NA, a driving circuit DRV for driving the pixels PX may be arranged. The driving circuit DRV may include at least one of a scan driving unit (e.g., a scan driver) that provides a scan signal to the pixels PX, a data driving unit (e.g., a data driver) that provides a data signal to the pixels PX, and a controller that controls the scan driving unit and the data driving unit.

[0052] The driving circuit DRV may be directly mounted on the substrate 100. The driving circuit DRV may be formed on the substrate 100 in parallel with (e.g., simultaneously with) the formation of the pixels PX. According to another embodiment, the driving circuit DRV may be formed on a specific chip and then mounted on the substrate 100, or may be mounted on a specific printed circuit board (PCB) and then connected to the substrate 100 via a connection member.

[0053] A packaging member including one or more thin films may be arranged on the substrate 100. According to an embodiment, the packaging member may include a plurality of thin films and may prevent external moisture and / or air from penetrating into the display area DA or may significantly reduce its incidence rate. The packaging member may cover the display area DA and may extend to the non-display area NA. The packaging member may include at least one inorganic layer containing an inorganic material and at least one organic layer containing an organic material. According to some embodiments, the packaging member may have a structure in which a first inorganic layer, an organic layer, and a second inorganic layer are stacked on one another.

[0054] Various suitable functional layers, such as a black matrix, a color filter, a polarization layer for reducing external light reflection, and / or a touch screen layer including touch electrodes, may be disposed on the encapsulation member. A window may be disposed on the encapsulation member and may be bonded to the encapsulation member via a pressure-sensitive adhesive (PSA).

[0055] Figure 2 is Figure 1 the circuit diagram of the pixel PX shown in

[0056] Referring to Figure 2 , the pixel PX may include a first transistor T1, a second transistor T2, and a capacitor Cst.

[0057] The first transistor T1 includes a first electrode receiving a first power supply voltage ELVDD and a second electrode connected to the first electrode of the OLED. The gate electrode of the first transistor T1 is connected to the second electrode of the second transistor T2. The gate electrode of the second transistor T2 is connected to the scan line SL, and the first electrode of the second transistor T2 is connected to the data line DL. The capacitor Cst has a first electrode connected to the gate electrode of the first transistor T1 and a second electrode receiving the first power supply voltage ELVDD. The second power supply voltage ELVSS may be lower than the first power supply voltage ELVDD.

[0058] Although Figure 2 a single pixel PX in

[0059] Figure 3 is Figure 1 a cross-sectional view taken along the line I-I' of

[0060] Referring to Figure 3 , a plurality of pixels PX may be disposed in the display area DA of the substrate 100, and the driving circuit DRV, the power unit, and the dam DAM may be disposed in the non-display area NA of the substrate 100. The power unit includes a plurality of power lines for supplying voltage to the pixels PX and / or the driving circuit DRV.

[0061] The substrate 100 can be a flexible substrate. For example, the substrate 100 can be a plastic substrate. The substrate 100 can be an insulating substrate including an organic material. The substrate 100 can have a structure in which a first layer 101, a second layer 102, a third layer 103, and a fourth layer 104 are sequentially stacked. Compared with a flexible substrate formed of only one organic material, the flexible substrate having such a stacked structure can have a low oxygen permeability rate and a low moisture permeability rate, and can have high durability. The substrate 100 can be a transparent substrate, that is, a light-transmitting substrate.

[0062] The first thickness of the first layer 101 can be equal to the third thickness of the third layer 103. The second thickness of the second layer 102 can be equal to the fourth thickness of the fourth layer 104. The first thickness of the first layer 101 and the third thickness of the third layer 103 can be greater than the second thickness of the second layer 102 and the fourth thickness of the fourth layer 104.

[0063] The first layer 101 and the third layer 103 can be organic layers including an organic material. The first layer 101 and the third layer 103 can include polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), cellulose triacetate (CTA or TAC), cellulose acetate propionate (CAP), etc.

[0064] The second layer 102 and the fourth layer 104 can be inorganic layers including an inorganic material. The second layer 102 and the fourth layer 104 can include silicon oxide (SiO 2 ), silicon nitride (SiN x ), etc. Both the second layer 102 and the fourth layer 104 can be a single layer or multiple layers. In the multiple layers, silicon oxide (SiO 2 ) and silicon nitride (SiN x ) are alternately and repeatedly stacked with each other. The second layer 102 and the fourth layer 104 can be used as a barrier layer to prevent moisture and / or oxygen from penetrating into the substrate 100 or significantly reduce its occurrence rate.

[0065] A buffer layer 110 can also be formed on the substrate 100. The buffer layer 110 can be formed of at least one of an inorganic layer and an organic layer. For example, the buffer layer 110 can perform a function of blocking the penetration of impurity elements through the substrate 100 and planarizing the surface of the substrate 100, and can be formed of an inorganic material such as silicon oxide (SiO 2 ) and / or silicon nitride (SiN x ) in a single-layer or multi-layer structure. The buffer layer 110 can be formed on the fourth layer 104 which is the uppermost layer of the substrate 100. In some examples, the buffer layer 110 can be omitted.

[0066] Pixels PX in the display area DA may include a transistor TFTd, a capacitor Cst, and an OLED as a display device.

[0067] The transistor TFTd of the pixel PX may include a semiconductor layer 121, a gate electrode 122, a source electrode 123, and a drain electrode 124. The transistor TFTd may be a driving transistor among a plurality of transistors included in the pixel PX. The transistor TFTd may be a TFT.

[0068] The semiconductor layer 121 may be disposed on the buffer layer 110. The semiconductor layer 121 may include various suitable materials. For example, the semiconductor layer 121 may include an inorganic semiconductor material such as amorphous silicon, crystalline silicon, etc. As another example, the semiconductor layer 121 may contain an oxide semiconductor or an organic semiconductor material. The semiconductor layer 121 may include a source region and a drain region, and a channel region, the source region and the drain region being at both ends of the semiconductor layer 121, and the channel region facing the gate electrode 122 and located between the source region and the drain region.

[0069] The gate electrode 122 may be disposed above the semiconductor layer 121. The gate electrode 122 may include various suitable conductive materials. For example, the gate electrode 122 may include at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) in a single-layer or multi-layer structure.

[0070] The first insulating layer 111 may be between the semiconductor layer 121 and the gate electrode 122. The first insulating layer 111 may be an inorganic insulating layer. The first insulating layer 111 may be formed of at least one insulating material selected from SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、Ta 2 O 5 、HfO 2 、ZrO 2 、barium strontium titanate (BST), and lead zirconate titanate (PZT) in a single-layer or multi-layer structure.

[0071] The source electrode 123 and the drain electrode 124 that are in contact with opposite ends of the semiconductor layer 121 may be disposed on the gate electrode 122. The source electrode 123 and the drain electrode 124 may include various suitable conductive materials. For example, both the source electrode 123 and the drain electrode 124 may be formed of at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) in a single-layer or multi-layer structure. The source electrode 123 and the drain electrode 124 may be in contact with the semiconductor layer 121 through contact openings (or contact holes) formed in the first insulating layer 111 and the second insulating layer 112 and exposing opposite ends of the semiconductor layer 121, respectively.

[0072] The second insulating layer 112 and the third insulating layer 113 may be disposed between each of the source electrode 123 and the drain electrode 124 and the gate electrode 122. The second insulating layer 112 and the third insulating layer 113 may be inorganic insulating layers. Both the second insulating layer 112 and the third insulating layer 113 may be formed of at least one of SiO 2 , SiN x , SiON, Al 2 O 3 , TiO 2 , Ta 2 O 5 , HfO 2 , ZrO 2 , BST, and PZT in a single-layer or multi-layer structure.

[0073] The shielding layer 151 may be disposed under the transistor TFTd, and at least a part of the shielding layer 151 overlaps with the semiconductor layer 121. The shielding layer 151 may be included on the second layer 102 of the substrate 100 and may be located between the second layer 102 and the third layer 103. The shielding layer 151 may be electrically connected to one electrode of the transistor TFTd, for example, connected to the source electrode 123. The shielding layer 151 may be in contact with the first connection electrode 125 extending from the source electrode 123 and may thus be connected to the source electrode 123.

[0074] The shielding layer 151 may include at least one of aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), tungsten (W), titanium (Ti), and their alloys, and may be formed in a single-layer or multi-layer structure. According to an embodiment, the shielding layer 151 may be a multi-layer structure including Mo. According to another embodiment, the shielding layer 151 may be a three-layer structure having a first layer, a second layer on the first layer, and a third layer on the second layer, where the first layer and the third layer include Ti and the second layer includes Al.

[0075] The capacitor Cst may include a first capacitor electrode 141 and a second capacitor electrode 142. The second insulating layer 112 may be disposed between the first capacitor electrode 141 and the second capacitor electrode 142. The first capacitor electrode 141 may include the same or substantially the same material as the gate electrode 122 of the transistor TFTd. The first capacitor electrode 141 may be formed of at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) in a single-layer or multi-layer structure. The second capacitor electrode 142 may be formed of at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) in a single-layer or multi-layer structure. The third insulating layer 113 may be disposed on the second capacitor electrode 142.

[0076] The fourth insulating layer 114 may be disposed on the source electrode 123 and the drain electrode 124. The fourth insulating layer 114 may be an organic insulating layer. The fourth insulating layer 114 may include a polyacrylic acid compound, a polyimide compound, a fluorocarbon compound (such as Teflon), a benzocyclobutene compound, etc. A protective layer may also be included as an inorganic insulating layer between each of the source electrode 123 and the drain electrode 124 and the fourth insulating layer 114. The fourth insulating layer 114 may include a via opening (or via) that exposes one of the source electrode 123 and the drain electrode 124.

[0077] The OLED may be located on the fourth insulating layer 114. The OLED may include a pixel electrode 131, a counter electrode 133 opposite to the pixel electrode 131, and an intermediate layer 132 between the pixel electrode 131 and the counter electrode 133.

[0078] The pixel electrode 131 may be electrically connected to the drain electrode 124 through a via. The pixel electrode 131 may be a reflective layer including a reflective conductive material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a mixture thereof. According to an embodiment, the pixel electrode 131 may be a layer including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3) A transparent conductive layer made of at least one transparent conductive oxide selected from indium gallium oxide (IGO) and aluminum zinc oxide (AZO). According to an embodiment, the pixel electrode 131 may be a stack of a reflective layer and a transparent conductive layer.

[0079] The fifth insulating layer 115 may be disposed on the fourth insulating layer 114. The fifth insulating layer 115 may cover the edge of the pixel electrode 131 and may define a pixel through an opening including exposing a part of the pixel electrode 131. The fifth insulating layer 115 may be an organic insulating layer. The fifth insulating layer 115 may include a polyacrylic acid compound, a polyimide compound, a fluorocarbon compound (such as Teflon), a benzocyclobutadiene compound, etc.

[0080] The intermediate layer 132 includes at least an emission layer (EML), and in addition to the EML, may further include at least one functional layer among a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). The EML may be a red emission layer, a green emission layer, or a blue emission layer. In some embodiments, in order to emit white light, the EML has a multilayer structure in which a red emission layer, a green emission layer, and a blue emission layer are stacked, or has a single-layer structure including a red emission material, a green emission material, and a blue emission material.

[0081] The counter electrode 133 may be formed of various suitable conductive materials. For example, the counter electrode 133 may include a semi-transmissive reflective layer containing at least one of lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), and silver (Ag), or may include a light-transmissive metal oxide such as ITO, IZO, or ZnO, and the counter electrode 133 may be formed as a single layer or a multilayer. The counter electrode 133 may extend to the upper surface of the fifth insulating layer 115 in the display area DA and the non-display area NA and may be in contact with the first power line 301a and the second power line 301b.

[0082] The driving circuit DRV may include at least one transistor constituting the above-described controller, the above-described data driving unit, and the above-described scanning driving unit. For the convenience of explanation, Figure 3 It is shown that the driving circuit DRV includes a single transistor TFTn. However, the embodiment is not limited thereto, and the driving circuit DRV may further include a plurality of transistors and other devices. The transistor TFTn may include a semiconductor layer 201, a gate electrode 202, a source electrode 203, and a drain electrode 204. The transistor TFTn may be a TFT. The cross-sectional structure of the transistor TFTn included in the driving circuit DRV is the same as or substantially the same as the cross-sectional structure of the transistor TFTd included in the pixel PX, so its description may not be repeated.

[0083] Multiple power lines included in a power unit may include a second power voltage line 301 that supplies a second power voltage ELVSS to pixels PX, a first driving voltage line 302 and a second driving voltage line 303 that supply a driving voltage to a driving circuit DRV, and at least one DC voltage line 304 that supplies a direct current (DC) voltage to the pixels PX and / or the driving circuit DRV. The first driving voltage supplied by the first driving voltage line 302 may be higher than the second driving voltage supplied by the second driving voltage line 303. The power unit may further include a first power voltage line that supplies a first power voltage ELVDD. According to an embodiment, the power unit may be located between the driving circuit DRV and a dam DAM. According to another embodiment, at least a portion of the power unit (e.g., at least some of the multiple power lines) may overlap with the driving circuit DRV.

[0084] The second power voltage line 301 may supply the second power voltage ELVSS to the pixels PX. The second power voltage line 301 may surround all or a portion of a display area DA. The second power voltage line 301 may include a first power line 301a and a second power line 301b.

[0085] The first power line 301a may be between a first layer 101 and a third layer 103 of a substrate 100. The first power line 301a may be on a second layer 102 of the substrate 100. The first power line 301a may be on the same layer on which a shielding layer 151 is disposed and may include a material that is the same as or substantially the same as the material included in the shielding layer 151. The first power line 301a may include at least one of aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), tungsten (W), titanium (Ti), and alloys thereof, and may be formed as a single layer or multiple layers. According to an embodiment, the first power line 301a may be a multi-layer structure including Mo. According to an embodiment, the first power line 301a may be a three-layer structure having a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, where the first layer and the third layer include Ti and the second layer includes Al.

[0086] The third layer 103 and a fourth layer 104 of the substrate 100 may cover an edge of the first power line 301a and may have an opening OP1 that exposes a portion of the first power line 301a. A buffer layer 110, a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113 (hereinafter referred to as an inorganic insulating layer 116) may cover the edge of the first power line 301a and may have an opening OP2 that exposes a portion of the first power line 301a. The inorganic insulating layer 116 may cover an upper surface of the third layer 103 and the fourth layer 104 and an inner surface of the opening OP1. Although in Figure 3The buffer layer 110 of the inorganic insulating layer 116 contacts the edge of the first power line 301a, but at least one layer included in the inorganic insulating layer 116 may contact the edge of the first power line 301a.

[0087] The opening OP2 of the inorganic insulating layer 116 may be superimposed on the opening OP1 of the substrate 100. The opening OP2 may be smaller than the opening OP1. The width of the opening OP2 may be narrower than the width of the opening OP1. However, the embodiment is not limited thereto, and the inner surface of the opening OP2 may coincide with the inner surface of the opening OP1.

[0088] A part of the edge of the first power line 301a may be covered by the fourth insulating layer 114. The fourth insulating layer 114 may cover a part of the inner surface of the opening OP2. However, the embodiment is not limited thereto, and the fourth insulating layer 114 may exist only outside the opening OP2.

[0089] The second power line 301b may be formed on the same layer on which the active electrode 123 and the drain electrode 124 are formed, and may include the same or substantially the same material as that included in the source electrode 123 and the drain electrode 124. The fourth insulating layer 114 may include an opening OP3 that exposes a part of the second power line 301b.

[0090] The first power line 301a and the second power line 301b may be electrically connected to the counter electrode 133. The first power line 301a may contact the counter electrode 133 through the opening OP2, and the second power line 301b may contact the counter electrode 133 through the opening OP3.

[0091] When the second power supply voltage line 301 is arranged as a single power line on the same layer as an electrode on which the driving circuit DRV is arranged in the non-display area NA, a non-display area NA having the same or substantially the same width as the second power supply voltage line 301 is required. However, according to the embodiment, since the second power supply voltage line 301 includes the first power line 301a and the second power line 301b located on different layers, and the first power line 301a is arranged on the layer below the second power line 301b and the driving circuit DRV, the width of the second power line 301b can be reduced and the width of the first power line 301a can be increased. Therefore, the degree of freedom of the width of the second power supply voltage line 301 can be increased, and at the same time, the non-display area NA can be reduced.

[0092] The first driving voltage line 302, the second driving voltage line 303, and the DC voltage line 304 may be formed on the same layer on which the first power line 301a is formed, and may include the same or substantially the same material as that included in the first power line 301a.

[0093] According to an embodiment, since some power lines of the power unit (e.g., power lines 301a, 302, 303, and 304) are arranged between the first layer 101 and the third layer 103 of the substrate 100, the power lines 301a, 302, 303, and 304 can reduce or minimize the influence of the electric field on the transistors of the driving circuit DRV.

[0094] The dam DAM can be provided at the outermost part of the non-display area NA. Although Figures 4E - 4G the dam DAM in

[0095] is formed of a material the same as or substantially the same as that of the fourth insulating layer 114 in a single-layer structure, the embodiment is not limited thereto, and the dam DAM can be formed of a material the same as or substantially the same as that of the fourth insulating layer 114 and / or the fifth insulating layer 115 in a single-layer or multi-layer structure.

[0096] Figures 4A to 4G is a schematic cross-sectional view showing a method of manufacturing Figure 3 the display device 10.

[0097] Referring to Figure 4A , the first layer 101 of an organic material and the second layer 102 of an inorganic material can be sequentially stacked on a support substrate, and a shielding layer 151 of the display area DA and the first power line 301a, the first driving voltage line 302, the second driving voltage line 303, and the DC voltage line 304 included in the power unit in the non-display area NA can be formed on the second layer 102. Subsequently, the support substrate can be removed.

[0098] The third layer 103 of an organic material and the fourth layer 104 of an inorganic material can be sequentially stacked on the shielding layer 151 and the power unit, and then, the third layer 103 and the fourth layer 104 can be patterned to form an opening OP1 that partially exposes the upper surface of the first power line 301a.

[0099] According to an embodiment, the inner surface of the opening OP1 can be flat. According to another embodiment, the inner surface of the opening OP1 can be concave as shown in the enlarged view X. The third layer 103 and the fourth layer 104 can be patterned by etching. When the third layer 103 and the fourth layer 104 are over-etched, the inner surface of the opening OP1 can have a concave shape.

[0100] Now, the first layer 101 to the fourth layer 104 are referred to as the substrate 100.

[0101] Reference Figure 4B As shown in Figure 4B , a buffer layer 110 may be formed on a substrate 100, and a semiconductor layer 121 including a transistor TFTd in a pixel PX and a semiconductor layer 201 including a transistor TFTn in a driving circuit DRV may be formed on the buffer layer 110.

[0102] A first insulating layer 111 may be formed on the semiconductor layers 121 and 201, and a gate electrode 122 of the transistor TFTd, a gate electrode 202 of the transistor TFTn, and a first capacitor electrode 141 of a capacitor Cst may be formed on the first insulating layer 111.

[0103] A second insulating layer 112 covering the gate electrodes 122 and 202 and the first capacitor electrode 141 may be formed on the first insulating layer 111, and a second capacitor electrode 142 may be formed on the second insulating layer 112. A third insulating layer 113 may be formed on the second capacitor electrode 142.

[0104] Reference Figure 4C As shown in Figure 4C , the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may be patterned such that contact holes CH1 exposing source and drain regions of the semiconductor layer 121 and contact holes CH3 exposing source and drain regions of the semiconductor layer 201 are formed in the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. The third layer 103 and the fourth layer 104 of the substrate 100 and an inorganic insulating layer 116 may be patterned such that a contact hole CH2 partially exposing the upper surface of a shielding layer 151 is formed in the third layer 103, the fourth layer 104, and the inorganic insulating layer 116. The inorganic insulating layer 116 may be patterned such that an opening OP2 partially exposing the upper surface of a first power line 301a is formed in the inorganic insulating layer 116.

[0105] Reference Figure 4D As shown in Figure 4D , a source electrode 123 and a drain electrode 124, a source electrode 203 and a drain electrode 204, and a second power line 301b may be formed on the third insulating layer 113. The source electrode 123 and the drain electrode 124 are in contact with the semiconductor layer 121 of the transistor TFTd through the contact hole CH1, and the source electrode 203 and the drain electrode 204 are in contact with the semiconductor layer 201 of the transistor TFTn through the contact hole CH3. A first connection electrode 125 may also be formed on the third insulating layer 113. The first connection electrode 125 extends from the source electrode 123 of the transistor TFTd and is in contact with the shielding layer 151 through the contact hole CH2.

[0106] Reference Figure 4E, a fourth insulating layer 114 may be formed on the third insulating layer 113, and the fourth insulating layer 114 covers at least a part of the upper surfaces of the source electrodes 123 and 203, the drain electrodes 124 and 204, the second power line 301b, and the first power line 301a that are exposed through the opening OP2.

[0107] A dam DAM may be formed of the material of the fourth insulating layer 114 on the outermost portion of the substrate 100.

[0108] Referring Figure 4F , the fourth insulating layer 114 may be patterned such that a via VIA exposing a part of the drain electrode 124 of the transistor TFTd and an opening OP3 exposing a part of the upper surface of the second power line 301b may be formed in the fourth insulating layer 114. The portion of the fourth insulating layer 114 existing on the upper surface of the first power line 301a may be removed. The fourth insulating layer 114 may eliminate the step between the insulating layers below it.

[0109] Referring Figure 4G , a pixel electrode 131 may be formed on the fourth insulating layer 114, and a fifth insulating layer 115 covering the pixel electrode 131 may be formed on the fourth insulating layer 114. The fifth insulating layer 115 may be patterned such that an opening OP4 exposing a part of the pixel electrode 131 may be formed in the fifth insulating layer 115. The fifth insulating layer 115 may not cover the first power line 301a and the second power line 301b.

[0110] Thereafter, as Figure 3 shown, an intermediate layer 132 and a counter electrode 133 may be sequentially formed in the opening OP4 exposing the pixel electrode 131. The counter electrode 133 may extend to the non-display area NA and may contact the upper surface of the second power line 301b exposed through the opening OP3 and the exposed upper surface of the first power line 301a.

[0111] Figures 5 to 9 is a cross-sectional view of a display device according to another embodiment taken along the line I-I’. The structures identical to those of the above-described embodiment may not be described here. Figure 1 The embodiment of

[0112] Figure 5 differs from the embodiment of Figure 3 in that two or more openings OP2 are included in the portion of the inorganic insulating layer 116 existing on the first power line 301a. The counter electrode 133 may contact the first power line 301a through the two or more openings OP2. The fourth insulating layer 114 may cover a partial side surface of the opening OP2.

[0113] Figure 6The embodiment of Figure 3 The embodiment of is different in that: The second power line 301b is located on the same layer as the gate electrode 202 of the transistor TFTn included in the driving circuit DRV located thereon. In Figure 3 In the embodiment of, the second power line 301b is located on the same layer as the source electrode 203 and the drain electrode 204 of the transistor TFTn included in the driving circuit DRV located thereon.

[0114] Referring to Figure 6 , the second power line 301b can be formed on the same layer as the gate electrode 202 of the transistor TFTn included in the driving circuit DRV formed thereon, and can include the same or substantially the same material as the material included in the gate electrode 202. In the second insulating layer 112 to the fourth insulating layer 114, an opening OP3 can be formed to expose a part of the upper surface of the second power line 301b. The electrode layer extending from the counter electrode 133 can contact the second power line 301b through the opening OP3 and can contact the exposed upper surface of the first power line 301a.

[0115] Figure 7 The embodiment of Figure 3 The embodiment of is different in that: The second connection electrode 315 is electrically connected to the first power line 301a and the second power line 301b, and the counter electrode 133 contacts the second power line 301b. The second connection electrode 315 can be formed of the same or substantially the same material as the material for forming the gate electrodes 122 and 202 on the same layer as the gate electrodes 122 and 202 are formed. The second connection electrode 315 can be disposed on the first insulating layer 111. The second connection electrode 315 can contact the first power line 301a through a contact hole exposing the first power line 301a formed by patterning the third layer 103 and the fourth layer 104 of the substrate 100, the buffer layer 110, and the first insulating layer 111. The second power line 301b can contact the second connection electrode 315 through a contact hole exposing the second connection electrode 315 formed by patterning the second insulating layer 112 and the third insulating layer 113.

[0116] Although in Figure 7 the embodiment of the second power line 301b is stacked with the second connection electrode 315 and the first power line 301a, the embodiment is not limited thereto. For example, the second connection electrode 315 may or may not be stacked with the first power line 301a, and the second power line 301b may or may not be stacked with at least one of the second connection electrode 315 and the first power line 301a.

[0117] Figure 8 The embodiment of Figure 6The embodiment is different in that: the first power line 301a is located on the same layer on which the shielding layer 151 is positioned, and the second power line 301b, the first driving voltage line 302, the second driving voltage line 303, and the DC voltage line 304 are located on the same layer on which the source electrodes 123 and 203 and the drain electrodes 124 and 204 are positioned.

[0118] At least some of the power lines arranged on the same layer on which the source electrodes 123 and 203 and the drain electrodes 124 and 204 are arranged may overlap a part of the first power line 301a.

[0119] Figure 9 The embodiment of Figure 7 The embodiment is different from the embodiment of

[0120] The third connection electrode 325 may be formed of the same or substantially the same material as the material used for forming the pixel electrode 131 on the same layer on which the pixel electrode 131 is formed. The third connection electrode 325 may be arranged on the fourth insulating layer 114. The third connection electrode 325 may be in contact with the second power line 301b through a contact hole exposing the second power line 301b formed by patterning the fourth insulating layer 114. The third connection electrode 325 may be in contact with the counter electrode 133 through a contact hole exposing the third connection electrode 325 formed by patterning the fifth insulating layer 115. Thus, the first power line 301a and the second power line 301b may be electrically connected to the counter electrode 133. The third connection electrode 325 may or may not overlap at least one of the second power line 301b, the second connection electrode 315, and the first power line 301a.

[0121] According to the embodiment, the non-display area can be reduced by arranging at least some of the power lines in the non-display area on the layer below the driving circuit.

[0122] Therefore, a display device with a reduced or minimized non-display area can be provided.

[0123] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for the purpose of limiting the invention. Unless otherwise specified, the description of the features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments.

[0124] Although one or more embodiments have been described with reference to the figures, those of ordinary skill in the art will understand that various suitable changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the claims and their equivalents.

Claims

1. A display device, the display device having a display area including pixels and a non-display area surrounding the display area, the display device in the non-display area comprises: a first power line for supplying a power supply voltage to the pixels; a driving circuit located on a layer above the first power line; and a second power line electrically connected to the first power line and located on the same layer on which one electrode of the driving circuit is disposed.

2. The display device according to claim 1, the display device further comprises: a display device located in the display area and including a pixel electrode, a counter electrode, and an emission layer located between the pixel electrode and the counter electrode.

3. The display device according to claim 2, wherein, the counter electrode is electrically connected to the first power line and the second power line.

4. The display device according to claim 1, wherein, the first power line overlaps with a part of the driving circuit.

5. The display device according to claim 1, wherein, the second power line overlaps with a part of the first power line.

6. The display device according to claim 1, wherein, the driving circuit includes at least one thin film transistor, and wherein the second power line is located on the same layer on which at least one of a gate electrode, a source electrode, and a drain electrode of the at least one thin film transistor of the driving circuit is disposed.

7. The display device according to claim 1, the display device further comprises: a first connection electrode located on a layer between the first power line and the second power line, the first connection electrode electrically connecting the first power line to the second power line.

8. The display device according to claim 2, the display device further comprises: a second connection electrode located on a layer above the second power line and electrically connecting the second power line to the counter electrode.

9. The display device according to claim 1, the display device in the display area comprises: a shielding layer located on the same layer on which the first power line is disposed; and a pixel circuit located on a layer above the shielding layer and at least partially overlapping with the shielding layer.

10. The display device according to claim 9, wherein, the shielding layer is electrically connected to one electrode of the pixel circuit.

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