Wafer-level packaging detection structure and method

Abstract

The present invention relates to the field of packaging detection technology, and to a wafer-level packaging detection structure and method. By setting a test pad on the packaged chip and detecting an independent back-gold block connected to the test pad through a test machine, it is possible to quickly detect whether the back-gold metal in the TSV hole and the pad are sufficiently connected during the packaging process. If a batch abnormality occurs, production can be stopped in time to avoid the batch abnormality, thereby playing a role in quality monitoring.

Description

Technical Field

[0001] The present invention relates to the technical field of packaging detection, and in particular to a wafer-level packaging detection structure and method. Background Art

[0002] All ground pads of existing wafers are generally interconnected during integrated circuit manufacturing, and subsequent packaging processing also connects all ground pads together. When some ground pads are not connected, it is generally impossible to identify through finished product testing and appearance inspection, and many defective products will be produced without foreseeable. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a wafer-level packaging detection structure and method that can quickly detect whether the connection between the back gold metal in the TSV hole and the pad is sufficient during the packaging process, avoid batch abnormalities, and play a role in quality monitoring.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention to solve the technical problems is:

[0005] A wafer-level packaging detection structure and method, the specific steps include:

[0006] S1: at least two test pads are arranged on the packaged chip, and every two test pads are connected to each other through an internal circuit;

[0007] S2: Open a TSV hole on the silicon substrate of the packaged chip so that the bottom of the TSV hole partially or completely leaks out of the test pad

[0008] S3: An independent back gold layer is set on the TSV hole as a probe contact point, and the independent back gold layer is not connected to the chip back gold block on the chip surface;

[0009] S4: The packaged chip is tested by contacting the probe contact points with two probes connected to the test machine respectively, and the conduction condition between the two test pads is tested.

[0010] Preferably, in step S1, the test pad is synchronously arranged with the integrated circuit in the packaged chip, and the test pad is not connected to the integrated circuit.

[0011] Preferably, in step S2, the silicon substrate above the test pad is removed to form a TSV hole, so that the bottom of the TSV hole partially or completely leaks out of the test pad, and the TSV hole is trapezoidal in shape, with an upper opening width greater than a lower opening width.

[0012] Preferably, in step S3, an independent back gold block is disposed on the inner wall and edge of the TSV hole, and the independent back gold block may be formed in a circular, square or polygonal shape.

[0013] Preferably, in step S4, the two test pads are connected to each other through an internal circuit. When the two probes of the test machine respectively contact the independent back gold blocks on the two test pads, a test loop is formed between the test machine and the test pads, and the packaged chip is detected by the conduction condition of the test loop.

[0014] Preferably, the test pad is disposed on at least one chip or in a scribe line between two adjacent chips.

[0015] The present invention also includes a wafer-level packaging detection structure, including a detection component, a test circuit and a packaging chip, wherein the test circuit is arranged on the packaging chip, and the detection component is connected to the integrated circuit to detect the conduction condition of the packaging chip;

[0016] The test circuit includes at least two test pads and an internal circuit, and every two test pads are connected via the internal circuit, and the detection component is connected to the two test pads.

[0017] Preferably, the test circuit is arranged on at least one chip on the packaged chip or on a dicing path between two adjacent chips.

[0018] Preferably, a TSV hole is provided on the packaged chip, the bottom of the TSV hole partially or completely leaks out the test pad, and an independent back gold block is provided on the inner wall and edge of the TSV hole, and the independent back gold block is connected to the test pad.

[0019] Preferably, the detection component comprises a test machine and two probes, the two probes are connected to the test machine, and the probes abut against the independent back gold block.

[0020] Beneficial effects of the present invention:

[0021] By setting a test pad on the packaged chip and detecting the independent back gold block connected to the test pad through a test machine, it is possible to quickly detect whether the back gold metal in the TSV hole and the pad are sufficiently connected during the packaging process. If a batch abnormality occurs, production can be stopped in time to avoid batch abnormalities and play a role in quality monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1-Figure 6 It is a schematic flow chart of a wafer-level packaging detection method of the present invention.

[0023] Figure 7 It is a schematic diagram of a wafer-level packaging detection structure of the present invention.

[0024] Explanation of the reference numerals in the figure: 100, chip; 101, test pad; 102, scribe groove; 103, internal circuit; 201, TSV hole; 202, independent back gold block; 203, chip back gold block; 301, test machine; 302, probe; DETAILED DESCRIPTION

[0025] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0026] Reference Figure 1-7 As shown, a wafer-level packaging detection structure and method, the specific steps include:

[0027] S1: at least two test pads 101 are arranged on the packaged chip, and every two test pads 101 are connected to each other through an internal circuit 103;

[0028] S2: Opening a TSV hole 201 on the silicon substrate of the packaged chip so that the bottom of the TSV hole 201 partially or completely leaks out of the test pad 101

[0029] S3: An independent back gold layer is provided on the TSV hole 201 as a contact point for the probe 302, and the independent back gold layer is not connected to the chip back gold block 203 on the chip surface;

[0030] S4: The two probes 302 connected to the test machine 301 contact the contact points of the probes 302 respectively, and the packaged chip is tested through the conduction status between the two test pads 101 .

[0031] By setting a test pad 101 on the packaged chip and detecting the independent back gold block 202 connected to the test pad 101 through the test machine 301, it is possible to quickly detect whether the connection between the back gold metal in the TSV hole 201 and the pad is sufficient during the packaging process. If a batch abnormality occurs, production can be stopped in time to avoid the occurrence of batch abnormalities, thereby playing a role in quality monitoring.

[0032] In step S1 , the test pad 101 is synchronously arranged with the integrated circuit in the packaged chip, and the test pad 101 is not connected to the integrated circuit.

[0033] The packaged core includes multiple chips 100, and the number of test pads 101 arranged on the packaged chip shall not be less than 2, so that the two test pads 101 are connected to each other through the internal circuit 103; the test pads 101 are implemented synchronously with the integrated circuit in the packaged chip without adding additional processes.

[0034] In step S2 , the silicon substrate above the test pad 101 is removed to form a TSV hole 201 , so that the bottom of the TSV hole 201 partially or completely leaks out of the test pad 101 . The TSV hole 201 is trapezoidal in shape, and its upper opening width is greater than the lower opening width.

[0035] In step S3 , an independent back gold block 202 is disposed on the inner wall and edge of the TSV hole 201 . The independent back gold block 202 may be formed in a circular, square or polygonal shape.

[0036] The independent back gold block 202 is arranged on the inner wall and edge of the TSV hole 201. The preferred solution of this embodiment is that the diameter of the independent back gold block 202 is greater than 50um, so that the size requirement of the independent back gold block 202 can be larger than the opening of the TSV hole 201, ensuring that the independent back gold block 202 can be contacted by the probe 302 to complete the detection. Since the TSV hole 201 structure and the independent back gold block 202 are realized simultaneously during the normal TSV and back gold processes, there is no need to add additional processes.

[0037] In step S4, the two test pads 101 are connected to each other through the internal circuit. When the two probes 302 of the test machine 301 contact the independent back gold blocks 202 on the two test pads 101 respectively, a test loop is formed between the test machine 301 and the test pads 101, and the packaged chip is detected by the conduction status of the test loop.

[0038] The test machine 301 obtains the current value in the test loop by detecting the voltage, and then converts the current into a resistance value. By monitoring the resistance value, the connection conduction condition can be monitored. When the resistance value exceeds the set threshold, it can be quickly concluded that the chip or a chip close to the chip is abnormal. Before the subsequent single chip is used, the abnormal chip can be promptly removed.

[0039] Due to the wafer-level processing technology, a wafer is processed in the same environment (such as the same chamber, the same tank of chemicals, etc.). Under normal circumstances, the chips distributed in various places on the wafer are homogeneous and uniform. When a chip is abnormal, the chips in the vicinity of the abnormal chip are likely to have the same abnormal problem.

[0040] The test pad 101 is disposed on at least one chip 100 or in a dicing lane between two adjacent chips 100 .

[0041] The test circuit formed by the test pad 101 and the internal circuit 103 can be set on each chip, or in one or more chips in a packaged chip in an integrated circuit processing lithography window. The present invention can also set the test circuit in the dicing path between two adjacent chips.

[0042] Reference Figure 7 As shown, the present invention also includes a wafer-level packaging detection structure, including a detection component, a test circuit and a packaging chip, wherein the test circuit is arranged on the packaging chip, and the detection component is connected to the integrated circuit to detect the conduction condition of the packaging chip;

[0043] The test circuit includes at least two test pads 101 and an internal circuit 103 , and every two test pads 101 are connected via the internal circuit 103 , and the detection component is connected to the two test pads 101 .

[0044] The test circuit is at least arranged on one chip on the packaged chip or on a dicing path between two adjacent chips.

[0045] The packaged chip is provided with a TSV hole 201 , the bottom of the TSV hole 201 partially or completely leaks out of the test pad 101 , an independent back gold block 202 is provided on the inner wall and edge of the TSV hole 201 , and the independent back gold block 202 is connected to the test pad 101 .

[0046] The TSV hole 201 has a trapezoidal structure, with an upper opening width greater than a lower opening width. The upper opening shape may be circular, square or polygonal, which is beneficial to metal deposition at the bottom and sidewalls of the TSV hole.

[0047] The detection component includes a test machine 301 and two probes 302 . The two probes 302 are connected to the test machine 301 , and the probes 302 abut against the independent backing gold block 202 .

[0048] The shape of the independent gold nugget can be round, square or polygonal.

[0049] At least one test circuit is arranged on one chip; two test circuits are arranged on one chip, and the two test circuits are symmetrically arranged on the chip.

[0050] The above-described embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Equivalent substitutions or changes made by those skilled in the art based on the present invention are within the protection scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A wafer-level packaging detection method, characterized in that: The specific steps include: S1: at least two test pads are arranged on the packaged chip, and every two test pads are connected to each other through an internal circuit; S2: Open a TSV hole on the silicon substrate of the packaged chip so that the bottom of the TSV hole partially or completely leaks out of the test pad S3: An independent back gold layer is set on the TSV hole as a probe contact point, and the independent back gold layer is not connected to the chip back gold block on the chip surface; S4: two probes connected to the test machine are used to contact the probe contact points respectively, and the packaged chip is tested by the conduction condition between the two test pads; In step S2, the silicon substrate above the test pad is removed to form a TSV hole, so that the bottom of the TSV hole partially or completely leaks out of the test pad, and the TSV hole is in a trapezoidal shape, and the upper opening width is greater than the lower opening width; In step S3, an independent back gold block is disposed on the inner wall and edge of the TSV hole, and the shape of the independent back gold block is circular or polygonal; In step S4, the two test pads are connected to each other through the internal circuit. When the two probes of the test machine contact the independent back gold blocks on the two test pads respectively, a test loop is formed between the test machine and the test pads, and the packaged chip is tested through the conduction status of the test loop. The test pad is at least arranged on one chip or in a dicing lane between two adjacent chips.

2. The wafer-level packaging detection method according to claim 1, characterized in that: In step S1, the test pad is synchronously arranged with the integrated circuit in the packaged chip, and the test pad is not connected to the integrated circuit.

3. A wafer-level packaging detection structure, characterized in that: Used to implement the wafer-level packaging detection method according to claim 1 or 2, the wafer-level packaging detection structure comprises a detection component, a test circuit and a packaging chip, the test circuit is arranged on the packaging chip, and the detection component is connected to the integrated circuit to detect the conduction condition of the packaging chip; The test circuit includes at least two test pads and an internal circuit, and every two test pads are connected via the internal circuit, and the detection component is connected to the two test pads; A TSV hole is provided on the packaged chip, and the bottom of the TSV hole partially or completely leaks out the test pad. An independent back gold block is provided on the inner wall and edge of the TSV hole, and the independent back gold block is connected to the test pad; the test circuit is provided on at least one chip on the packaged chip or on the dicing path between two adjacent chips.

4. The wafer-level packaging detection structure according to claim 3, characterized in that: The detection component includes a test machine and two probes. The two probes are connected to the test machine, and the probes are in contact with the independent back gold block.

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