Semiconductor devices

Abstract

A semiconductor device includes: a semiconductor substrate including a chip region and an edge region around the chip region; a lower insulating layer on the semiconductor substrate; a chip pad on the lower insulating layer on the chip region; an upper insulating layer disposed on the lower insulating layer to cover the chip pad, the upper insulating layer and the lower insulating layer including different materials; and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion having a first thickness on the chip region, a second portion having a second thickness on the edge region, and a third portion on the edge region, the third portion extending from the second portion, being spaced apart from the first portion, and having a thickness that decreases away from the second portion. The second thickness is less than the first thickness.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The Korean Patent Application No. 10-2018-0111016, filed on September 17, 2018 with the Korean Intellectual Property Office, and entitled “Semiconductor Device” is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a redistribution pad. Background Art

[0004] A semiconductor package includes a semiconductor chip configured to store a large amount of data and process a large amount of stored data in a short time. The semiconductor chip includes an internal integrated circuit for storing and / or processing data, and a chip pad that allows data to be exchanged between the internal integrated circuit and an external device. With the development of the electronics industry, the demand for semiconductor devices with high integration density and high operating speed is increasing. Summary of the invention

[0005] According to some embodiments, a semiconductor device may include: a semiconductor substrate including a chip region and an edge region surrounding the chip region; a lower insulating layer disposed on the semiconductor substrate; a chip pad disposed on the lower insulating layer on the chip region; an upper insulating layer disposed on the lower insulating layer to cover the chip pad, the upper insulating layer including an insulating material different from that of the lower insulating layer; and a redistribution chip pad located on the chip region to penetrate the upper insulating layer and connected to the chip pad. The upper insulating layer may include a first portion having a first thickness on the chip region; a second portion extending from the first portion and on the edge region, the second portion having a second thickness less than the first thickness; and a third portion extending from the second portion and spaced apart from the first portion, the third portion having a decreasing thickness in a direction away from the second portion.

[0006] According to some embodiments, a semiconductor device may include: a semiconductor substrate including a chip region and an edge region surrounding the chip region; a lower insulating layer disposed on the semiconductor substrate; a chip pad located on the lower insulating layer on the chip region; an upper insulating layer located on the lower insulating layer, the upper insulating layer having a first opening exposing the chip pad on the chip region and a second opening exposing a portion of the lower insulating layer on the edge region; and a redistribution chip pad connected to the chip pad in the first opening. At least a portion of the second opening may have a rounded sidewall. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 A plan view of a substrate including a semiconductor device according to an embodiment is shown.

[0009] Figure 2 Shows Figure 1 An enlarged view of portion "A".

[0010] Figure 3 Shows Figure 2 Schematic plan view of a test element group.

[0011] Figure 4 A flowchart of a method of manufacturing a semiconductor device according to an embodiment is shown.

[0012] FIG. 5A to FIG. 5I Shown along Figure 2 1 is a cross-sectional view of stages in a method of manufacturing a semiconductor device according to an embodiment, taken along line II′.

[0013] Figure 5J Shows Fig.5I An enlarged view of a portion of an edge region of a semiconductor device.

[0014] Figure 6 Shown along Figure 2 1 is a cross-sectional view of a portion of a semiconductor device according to an embodiment, taken along line IIII′.

[0015] Figure 7 , Figure 8 and Fig. 9 A cross-sectional view of a portion of a semiconductor device according to an embodiment is shown.

[0016] Fig. 10A and Fig. 10B Cross-sectional views showing vertical cross sections of a semiconductor device according to an embodiment before and after a process of dividing semiconductor chips.

[0017] Fig.11 A cross-sectional view of a portion of a semiconductor device according to an embodiment is shown.

[0018] Fig.12 An enlarged plan view of a portion of a semiconductor device according to an embodiment is shown.

[0019] Fig.13A and Fig. 13B Shown along Fig.12 1 and 2 are cross-sectional views taken along line III III I′ of FIG. 1 and illustrate vertical cross sections of the semiconductor device according to the embodiment before and after a process of dividing the semiconductor chips.

[0020] Fig.14 and Fig.15 Shown along Fig.122 is a cross-sectional view of a portion of a semiconductor device according to an embodiment, taken along lines IV-IV′ and V-V′.

[0021] Fig.16 An enlarged plan view of a portion of a semiconductor device according to an embodiment is shown.

[0022] Fig.17A and Fig. 17B Shown along Fig.16 1 and 2 , and are cross-sectional views of the semiconductor device according to the embodiment before and after a process of dividing the semiconductor chips, taken along line VI-VI′.

[0023] 18A to 18D Shown along Figure 2 1 is a cross-sectional view of stages in a method of manufacturing a semiconductor device according to an embodiment, taken along line II′.

[0024] Fig.19A A plan view of a semiconductor chip according to an embodiment is shown, the semiconductor chip being a structure separated from a semiconductor device.

[0025] Fig.19B A cross-sectional view of a semiconductor package including a semiconductor chip according to an embodiment is shown. DETAILED DESCRIPTION

[0026] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein and the embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations to those skilled in the art.

[0027] Figure 1 is a diagram showing a semiconductor substrate on which a semiconductor device according to an embodiment is integrated. Figure 2 yes Figure 1 Enlarged view of section "A" in Figure 1. Figure 1 and Figure 2 , the semiconductor substrate 100 may include chip regions 10 on which semiconductor integrated circuits are formed, and scribe line regions 20 between the chip regions 10 .

[0028] The semiconductor substrate 100 may include at least one of a semiconductor material (eg, silicon), an insulating material (eg, glass), a semiconductor material covered with an insulating material, or a conductive material, etc. For example, the semiconductor substrate 100 may be a silicon wafer having a first conductivity type.

[0029] The chip regions 10 may be arranged in a matrix, for example, two-dimensionally arranged in a first direction D1 and a second direction D2 perpendicular to each other. Each of the chip regions 10 may be surrounded by a scribe line region 20 .

[0030] The scribing area 20 may include a plurality of first scribing areas extending along the first direction D1 and a plurality of second scribing areas extending along the second direction D2 to intersect with the first scribing areas. The scribing area 20 may include a cutting area 21 and an edge area 23, wherein the chip area 10 is separated along the cutting area 21, for example, by cutting, etching, applying stress, etc. along a third direction D3 perpendicular to the first direction D1 and the second direction D2 by a saw or a cutter, and the edge area 23 is located between the cutting area 21 and the chip areas 10 on both sides of the cutting area 21. The edge area 23 may surround the corresponding chip area 10, for example, along the first direction D1 and the second direction D2 in a plan view.

[0031] In some embodiments, a semiconductor memory device, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a NAND FLASH memory, a resistive random access memory (RRAM), etc., may be provided on the chip region 10 of the semiconductor substrate 100. In some embodiments, a microelectromechanical system (MEMS) device, an optoelectronic device, a processor (e.g., a CPU or a DSP), etc. may be provided on the chip region 10 of the semiconductor substrate 100. In some embodiments, a standard cell including a semiconductor element (e.g., an OR gate, an AND gate, etc.) may be provided on the chip region 10 of the semiconductor substrate 100. In addition, a chip pad 123a and a redistribution chip pad 141a for inputting data or signals to or outputting data or signals from the semiconductor integrated circuit may be provided on the chip region 10 of the semiconductor substrate 100. The chip pad 123a may be provided on an edge region or a central region of each of the chip regions 10, and the redistribution chip pad 141a may be provided on a region spaced apart from the chip pad 123a along the first direction D1 and / or the second direction D2.

[0032] A test element group 30 and a process monitoring structure 40 may be provided on the scribe line region 20 of the semiconductor substrate 100. The test element group 30 may include at least one test element having a structure substantially the same as that of at least one of the semiconductor integrated circuits on the chip region 10, and the test element group 30 may be used to evaluate electrical characteristics of the semiconductor integrated circuit. The test element group 30 may include, for example, an NMOS FET, a PMOS FET, a resistor, and the like.

[0033] The process monitoring structure 40 may include monitoring patterns (e.g., alignment patterns, overlay patterns, measurement patterns, etc.) for monitoring a process of manufacturing a semiconductor device. In some embodiments, the alignment pattern may be used for alignment between process steps in the manufacturing process and have various shapes, the overlay pattern may be used to check the overlap between the upper pattern and the lower pattern, and the measurement pattern may be used to measure the thickness and line width of the pattern. The process monitoring structure 40 may include process monitoring patterns having various shapes according to their positions.

[0034] In some embodiments, the opening OP may be locally formed in the insulating layer on the scribe line region 20. When viewed in a plan view, the opening OP may overlap the test element group 30 along the third direction D3 but not overlap the process monitoring structure 40.

[0035] Figure 3 It is schematically shown Figure 2 FIG. 3 is a plan view of one of the test element groups 30. Figure 3 , each of the test element groups 30 may include a plurality of test structures 101T and a plurality of test pads 143. The test pads 143 may be connected to the test structures 101T by wires. The test structures 101T may include test elements, each having a substantially identical structure to a corresponding one of the semiconductor integrated circuits formed on the chip region 10. The test structures 101T may include, for example, NMOS FETs, PMOS FETs, resistors, and the like.

[0036] Figure 4 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment. Figure 4 , can be prepared as previously referenced Figure 1 and Figure 2 The semiconductor substrate includes a chip region and a scribe line region (in S10).

[0037] Various processes for manufacturing semiconductor devices may be performed on the semiconductor substrate to form a semiconductor integrated circuit, a process monitoring structure, and a test element group (in S20). In some embodiments, the process monitoring structure may be used to provide a process reference for each manufacturing process, and thus, the semiconductor integrated circuit and the test element group may be formed after the process monitoring structure is formed. In other words, the test element group may be formed on the remaining area of ​​the scribe area not occupied by the process monitoring structure after the process monitoring structure is formed.

[0038] After forming the semiconductor integrated circuit and the test element group, a test process may be performed on the test element group (in S30). In the test process, an electrical signal may be provided to the test element group through the test pad to evaluate electrical characteristics of the semiconductor integrated circuit.

[0039] After the test process, a separation process may be performed along the cutting region of the scribe line region, such as sawing, dicing, etc. As a result, chip regions of the semiconductor substrate on which the semiconductor integrated circuits are formed may be separated from each other (in S40 ).

[0040] Thereafter, a packaging process may be performed on each of the semiconductor chips separated from each other through the separation process (in S50 ). The packaging process may include molding the semiconductor chip and forming external coupling terminals (eg, bumps) on the semiconductor chip.

[0041] FIG. 5A to FIG. 5I It is shown along Figure 2 1 is a cross-sectional view of stages in a method of manufacturing a semiconductor device according to an embodiment, taken along line II′. Figure 5J It is shown Fig.5I An enlarged view of a portion of an edge region of a semiconductor device. Figure 6 It is shown along Figure 2 1 is a cross-sectional view of a portion of a semiconductor device according to an embodiment, taken along line IIII′.

[0042] Reference Figure 2 and Figure 5A , the semiconductor substrate 100 may include a plurality of chip regions 10 and a plurality of scribe regions 20. Each of the scribe regions 20 may include a cutting region 21 at the center and an edge region 23 between the cutting region 21 and the chip region 10 along either side of the cutting region. The scribe region 20 may extend in a first direction D1 or a second direction D2. When the scribe region 20 extends along the first direction D1, the edge region 23 is spaced from the cutting region 21 along the second direction D2 on both sides of the cutting region 21, and vice versa.

[0043] The semiconductor integrated circuit 101 may be formed on the chip region 10 of the semiconductor substrate 100. The semiconductor integrated circuit 101 may include a memory cell array including a switching element, a data storage element, etc., and a logic device including a MOS FET, a capacitor, a resistor, etc. The semiconductor integrated circuit 101 may be covered with an interlayer insulating layer 103. In an embodiment, the interlayer insulating layer 103 may cover the entire top surface of the semiconductor substrate 100. The interlayer insulating layer 103 may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0044] The lower interconnection line 105a connected to the semiconductor integrated circuit 101 may be disposed in the interlayer insulating layer 103 and on the chip region 10. The dummy lower interconnection line 105b may be disposed in the interlayer insulating layer 103 and on the scribe line region 20. The lower interconnection line 105a and the dummy lower interconnection line 105b may be formed of or include at least one of metal materials such as tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), WN, TaN, etc.

[0045] The lower insulating layer 110 may be formed on the interlayer insulating layer 103 to cover the entire top surface of the semiconductor substrate 100, and may include a plurality of insulating layers stacked on the semiconductor substrate 100 along the third direction D3. In some embodiments, the lower insulating layer 110 may be formed of a low-k dielectric material having a dielectric constant lower than that of silicon oxide. The lower insulating layer 110 may have a dielectric constant of about 1.0 to 3.0, and may be formed of or include at least one of an organic material, an inorganic material, or an organic-inorganic hybrid material. In some embodiments, the lower insulating layer 110 may be formed to have a porous structure or a non-porous structure. The lower insulating layer 110 may be formed of, for example, at least one of a silicon oxide material doped with impurities, a low-k organic polymer, and the like. The impurity-doped silicon oxide material may be, for example, a fluorine-doped oxide (e.g., FSG), a carbon-doped oxide, silicon oxide, hydrogen silsesquioxane (HSQ; SiO:H), methyl silsesquioxane (MSQ; SiO:CH3), a-SiOC (SiOC:H), etc. The low-k organic polymer may be, for example, a polyallyl ether resin, a cyclic fluorine resin, a siloxane copolymer, a fluorinated polyallyl ether resin, a polypentafluoroacetylene, a polytetrafluorostyrene resin, a fluorinated polyimide resin, a polynaphthalene fluoride, a polyamide resin, etc. In addition, the lower insulating layer 110 may include, for example, at least two insulating layers vertically stacked along a third direction D3, and a barrier layer between adjacent insulating layers. The barrier layer may be formed of or include at least one of the insulating materials, such as SiN, SiON, SiC, SiCN, SiOCH, SiOC, SiOF, etc.

[0046] The internal interconnect structures 121a and 122a may be formed in the lower insulating layer 110 on the chip region 10. The internal interconnect structures 121a and 122a may be electrically connected to the semiconductor integrated circuit 101. The internal interconnect structures 121a and 122a may include metal lines 121a and metal vias 122a, which are arranged to penetrate the lower insulating layer 110 and connect the metal lines 121a at different levels to each other. The metal lines 121a and the metal vias 122a may include a first metal material, for example, W, aluminum (Al), Ti, Ta, cobalt (Co), and copper (Cu). As an example, the metal lines 121a and the metal vias 122a may be formed of copper (Cu). The metal lines 121a and the metal vias 122a may include a metal nitride layer (for example, TiN, WN, TaN, or TaSiN) used as a barrier metal layer.

[0047] The chip pad 123a may be disposed on the uppermost layer in the lower insulating layer 110 and may be electrically connected to the semiconductor integrated circuit 101 through the internal interconnect structures 121a and 122a. The chip pad 123a may include a data pad for transmitting a data signal, a command / address pad for transmitting a command / address signal, a power pad to which a ground voltage or a power supply voltage is applied, a pad for testing the semiconductor integrated circuit 101, and the like. The chip pad 123a may be formed of or include a second metal material (e.g., W, Al, Ti, Ta, Co, and Cu), wherein the second metal material is different from the first metal material. As an example, the chip pad 123a may be formed of or include aluminum (Al). The chip pad 123a may include a metal nitride layer (e.g., TiN, WN, TaN, or TaSiN) used as a barrier metal layer.

[0048] A dam structure 120 may be formed on the edge region 23 of the semiconductor substrate 100. When viewed in a plan view, the dam structure 120 may be formed to surround each of the chip regions 10, for example, may surround each of the chip regions 10 along the first direction D1 and the second direction D2. When viewed in a plan view, the dam structure 120 may have a ring or closed loop shape. When the internal interconnect structures 121a and 122a are formed on the chip region 10, the dam structure 120 may be formed, and the dam structure 120 may include a metal via penetrating the lower insulating layer 110 and a metal line on the metal via.

[0049] In some embodiments, Figure 2 and Figure 6As shown, the process monitoring structure 40 may be formed on a portion of the scribe line region 20. The process monitoring structure 40 may include a process monitoring pattern disposed in the lower insulating layer 110 on the edge region 23. As an example, the process monitoring pattern may be formed when the chip pad 123a is formed, and the process monitoring pattern may be positioned at substantially the same level as the chip pad 123a, for example, at the same distance from the semiconductor substrate 100 along the third direction D3. As another example, the process monitoring pattern may be formed when the internal interconnect structures 121a and 122a are formed on the chip region 10.

[0050] The upper insulating layer 130 may be formed on the uppermost layer in the lower insulating layer 110 to cover the chip pad 123a and the dam structure 120. In some embodiments, the upper insulating layer 130 may be formed of or include an insulating material having a higher material strength than the lower insulating layer 110. The upper insulating layer 130 may include an insulating material having a higher dielectric constant than the lower insulating layer 110. For example, the upper insulating layer 130 may be formed of or include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and the like. In some embodiments, the upper insulating layer 130 can be formed of or include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), SiCN, high-density plasma (HDP) oxide, tetraethyl orthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), O3-TEOS, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG) material, tonnage silazane (TOSZ), any combination thereof, and the like.

[0051] In some embodiments, the upper insulating layer 130 may include a plurality of insulating layers. As an example, the upper insulating layer 130 may include a first upper insulating layer 131, a second upper insulating layer 133, and a third upper insulating layer 135 sequentially stacked on the lower insulating layer 110 along the third direction D3. Here, the second upper insulating layer 133 may be formed of an insulating material having an etching selectivity relative to the first upper insulating layer 131 and the third upper insulating layer 135, and may be thinner than the first upper insulating layer 131 and the third upper insulating layer 135 along the third direction D3. The first upper insulating layer 131 and the third upper insulating layer 135 may be formed of different insulating materials. The third upper insulating layer 135 may be thicker than the first upper insulating layer 131 along the third direction D3. As an example, the first upper insulating layer 131 may be an HDP oxide layer, the second upper insulating layer 133 may be a silicon nitride layer, and the third upper insulating layer 135 may be a TEOS layer.

[0052] Reference Figure 2and Figure 5B , a first mask pattern MP1 may be formed on the upper insulating layer 130. In some embodiments, the first mask pattern MP1 may have an opening corresponding to the chip pad 123a and a recessed portion corresponding to the scribe line region 20. Forming the first mask pattern MP1 may include coating a photoresist layer on the upper insulating layer 130, performing an exposure process using a mask R having scattering strips SB, and developing the photoresist layer.

[0053] An exposure process of the photoresist layer may be performed by irradiating the photoresist layer with an electron beam or light provided through the mask R. The mask R for the exposure process may include scattering strips SB disposed in an area corresponding to the scribe area 20 of the semiconductor substrate 100. The scattering strips SB of the mask R may include a line and space pattern, an island pattern, or a combination thereof. In some embodiments, at least one of the scattering strips SB of the mask R may be shaped as a rectangular ring when viewed in a plan view.

[0054] In the exposure process, the energy of light incident on the photoresist layer on the scribing area 20 through the scattering strips SB of the mask R may be less than the energy of light incident into the photoresist layer on the chip area 10 through the openings RO of the mask R. The density of the scattering strips SB in a portion of the mask R corresponding to the cutting area 21 may be greater than the density of the scattering strips SB in another portion corresponding to the edge area 23. Therefore, the energy of light incident into the photoresist layer on the cutting area 21 may be greater than the energy of light incident into the photoresist layer on the edge area 23.

[0055] In more detail, the first mask pattern MP1 may include a chip exposure region E0, a first exposure region E1, a second exposure region E2, a third exposure region E3, and a fourth exposure region E4. Here, the first exposure region E1 may be exposed by an electron beam or light having energy or intensity lower than that for the chip exposure region E0, the second exposure region E2 may be exposed by an electron beam or light having energy or intensity lower than that for the first exposure region E1, the third exposure region E3 may be exposed by an electron beam or light having energy or intensity lower than that for the second exposure region E2, and the fourth exposure region E4 may be exposed by an electron beam or light having energy or intensity lower than that for the third exposure region E3.

[0056] The first mask pattern MP1 may have a thickness that decreases along the third direction D3 in a direction from the edge region 23 toward the center of the cutting region 21 (e.g., along the horizontal direction, such as the first direction D1 or the second direction D2). The thickness of the first exposure region E1 of the first mask pattern MP1 may be about 25% to 40% of the thickness of the non-exposure region. The first mask pattern MP1 may have a stepped portion between each two of the first to fourth exposure regions E1, E2, E3, and E4. In addition, the density of the scattering bars SB in the first exposure region E1 may vary in a continuous manner. Therefore, the first exposure region E1 of the first mask pattern MP1 may have a circular surface. Since the density of the scattering bars SB decreases along the horizontal direction (e.g., the first direction D1 or the second direction D2) toward the chip region 10, a recessed region may be formed in the top surface of the third exposure region E3 and the fourth exposure region E4 of the first mask pattern MP1.

[0057] Reference Figure 2 and Figure 5C , first openings OP1 may be formed in the upper insulating layer 130 on the chip region 10, and second openings OP2 may be formed in the upper insulating layer 130 on the scribe region 20. Each first opening OP1 may expose the chip pad 123a and the second opening OP2 may expose a portion of the lower insulating layer 110, respectively.

[0058] The first opening OP1 and the second opening OP2 may be formed by anisotropically etching the upper insulating layer 130 using the first mask pattern MP1 as an etching mask. After the first opening OP1 and the second opening OP2 are formed, the first mask pattern MP1 may be removed.

[0059] The first openings OP1 on the chip region 10 may be formed to have substantially the same size and uniform distance. Each of the first openings OP1 may have a rectangular, square, circular or polygonal shape. The second openings OP2 may have a linear shape extending in the first direction D1 or the second direction D2.

[0060] Since the etching process is performed through the recessed portion of the first mask pattern MP1 (eg, referring to Figure 5B ), and thus the lower insulating layer 110 and the upper insulating layer 130 may be partially removed to form a second opening OP2 on the scribe area 20. On the scribe area 20, the lower insulating layer 110 and the upper insulating layer 130 may have a thickness that decreases in a direction from the edge area 23 toward the cutting area 21. At least a portion of the second opening OP2 may have a circular inner surface RS.

[0061] The thickness of the upper insulating layer 130 along the third direction D3 and exposed to the second opening OP2 may decrease in a direction away from the chip region 10 (e.g., along a horizontal direction, such as the first direction D1 or the second direction D2). Similarly, the thickness of the lower insulating layer 110 along the third direction D3 and exposed to the second opening OP2 may also decrease in a direction away from the chip region 10 (e.g., along a horizontal direction, such as the first direction D1 or the second direction D2).

[0062] On the scribe line region 20, the lower insulating layer 110 may include a first portion having a first lower thickness T1 along the third direction D3 and a second portion having a second lower thickness T2 less than the first lower thickness T1. Here, the first lower thickness T1 of the first portion may be substantially equal to the thickness of the lower insulating layer 110 on the chip region 10. In addition, the second portion may be exposed through the second opening OP2 of the upper insulating layer 130.

[0063] In more detail, Figure 5J As shown, the upper insulating layer 130 may include a first portion 130_1 on the chip region 10, a second portion 130_2 extending from the first portion along the edge region 23, and a third portion RP spaced apart from the first portion 130_1 and extending from the second portion 130_2, that is, the second portion 130_2 is located between the first portion 130_1 and the third portion RP along the horizontal direction (e.g., the first direction D1 or the second direction D2). Here, the first portion 130_1 may have a substantially uniform thickness (hereinafter, the first thickness Ta), the second portion 130_2 may have a second thickness Tb less than the first thickness Ta, and the third portion RP may have a thickness less than the second thickness Tb and decreasing in a direction away from the second portion 130_2 and toward the center of the scribing region 20 (i.e., the cutting region 21). In other words, the third portion RP may have a circular inner surface RS. For the adjacent chip region 10, the upper insulating layer 130 may have a mirror structure along the third direction D3.

[0064] As an example, the second portion 130_2 of the upper insulating layer 130 may be disposed on the dam structure 120. The upper insulating layer 130 may have a first inclined surface S1 between the first portion 130_1 and the second portion 130_2, and a second inclined surface S2 between the second portion 130_2 and the third portion RP. Here, the inclination angle of the first inclined surface S1 may be different from the inclination angle of the second inclined surface S2. In other words, the upper insulating layer 130 may have a first stepped structure between the first portion 130_1 and the second portion 130_2, and a second stepped structure between the second portion 130_2 and the third portion RP.

[0065] In addition, if Figure 6As shown, the upper insulating layer 130 may further include a fourth portion, which is located on the scribe line region 20 and has a thickness substantially the same as the first thickness Ta. Here, the fourth portion may be disposed to cover the process monitoring structure 40.

[0066] The second opening OP2 formed in the upper insulating layer 130 may be spaced apart from the process monitoring structure 40, and a side surface of the second opening OP2 adjacent to the process monitoring structure 40 may also have a rounded shape, such as Figure 6 shown.

[0067] Reference Figure 2 and Figure 5D , a redistribution layer 140 may be formed on the upper insulating layer 130 having the first and second openings OP1 and OP2. The redistribution layer 140 may be formed to partially fill the first and second openings OP1 and may include a portion of the first opening OP1 in contact with the chip pad 123a.

[0068] The redistribution layer 140 may be formed by forming a metal seed layer to conformally cover the upper insulating layer 130 having the first opening OP1 and the second opening OP2 and forming a metal layer on the metal seed layer. The metal seed layer and the metal layer may be formed by a film deposition method, such as an electroplating method, a chemical plating method, and a sputtering method. The redistribution layer 140 may be formed of at least one of Cu, Al, nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), Ti, chromium (Cr), palladium (Pd), indium (In), zinc (Zn), carbon (C), any alloy thereof, etc. As an example, the redistribution layer 140 may be formed of or include aluminum (Al).

[0069] Reference Figure 2 and Figure 5E After forming the redistribution layer 140, a second mask pattern MP2 may be formed on the redistribution layer 140. The second mask pattern MP2 may be locally formed on the chip region 10, particularly on the chip pad 123a. The second mask pattern MP2 may expose the redistribution layer 140 on the scribe line region 20.

[0070] Thereafter, the redistribution layer 140 may be etched using the second mask pattern MP2 as an etching mask. Thus, a redistribution chip pad 141a may be formed in the first opening OP1 on the chip region 10, as shown in FIG. Figure 2 and Fig. 5FDuring the formation of the redistribution chip pad 141a, the redistribution layer 140 may be removed from the scribe line region 20. Therefore, the inner surface of the second opening OP2 may be exposed. Since the second opening OP2 has a circular inner surface RS, etching the redistribution layer 140 may be performed to completely remove the redistribution layer 140 from the scribe line region 20.

[0071] Next, if Fig. 5F As shown, after forming the redistribution chip pad 141a, a passivation layer 153 may be formed on the upper insulating layer 130 to expose a portion of the redistribution chip pad 141a and the scribe line region 20. In some embodiments, before forming the passivation layer 153, a protection layer 151 may be formed on the semiconductor substrate 100 to conformally cover the structure having the redistribution chip pad 141a.

[0072] The protective layer 151 may be, for example, a silicon nitride layer, a silicon oxynitride layer, etc. The passivation layer 153 may be formed of or include at least one of polyimide materials (e.g., photosensitive polyimide (PSPI)). The passivation layer 153 may be formed on the protective layer 151 using a spin coating process and may be patterned by an exposure process without using an additional photoresist layer to expose the protective layer 151 on the redistribution chip pad 141 a and a portion of the protective layer 151 on the scribe area 20.

[0073] Afterwards, refer to Figure 2 and Figure 5G The protective layer 151 exposed by the passivation layer 153 may be etched to expose the redistribution chip pad 141a. The etching process may be performed to remove the protective layer 151 on the inner surface of the second opening OP2 and on the scribe area 20. Therefore, a portion of the lower insulating layer 110 on the scribe area 20 may be exposed.

[0074] If the redistribution chip pad 141a is exposed, reference may be performed Figure 4 After the test process, a separation process may be performed to separate the semiconductor substrate 100 along the scribe line region 20 .

[0075] For details, refer to Figure 2 and 5H , the laser beam may be irradiated on the cutting region 21 of the scribing region 20 through the rear surface of the semiconductor substrate 100. The laser beam may cause a change in the physical properties of the laser spot region SP of the semiconductor substrate 100 irradiated by the laser beam. As an example, the physical strength of the laser spot region may be lower than that of other regions of the semiconductor substrate 100.

[0076] Afterwards, refer to Figure 2 and Fig.5I, the semiconductor substrate 100 may be placed on a film tape, and then the film tape may be forcibly stretched in a horizontal direction, thereby separating the semiconductor substrate 100 along the cutting region 21 of the scribe region 20. In some embodiments, a sawing process may be performed along the cutting region 21 of the scribe region 20 to separate the chip regions 10 from each other. Here, a sawing wheel or a laser beam may be used for the sawing process.

[0077] As a result of the cutting process, the semiconductor substrate 100 may be divided into semiconductor chips separated from each other. Each of the semiconductor chips may include a chip region 10 and an edge region 23 around the chip region 10. After the cutting process of the semiconductor substrate 100, the upper insulating layer 130 on the edge region 23 may have a stepped structure defined by a first portion and a second portion having different thicknesses (i.e., a first thickness and a second thickness). In addition, the lower insulating layer 110 on the edge region 23 may include a first portion having a first lower thickness T1 and a second portion having a second lower thickness T2 less than the first lower thickness T1. As a result of the cutting process, a separation surface SS defined by the semiconductor substrate 100 and the lower insulating layer 110 may be formed.

[0078] In some embodiments, when the semiconductor substrate 100 is divided into the chip region 10, the upper insulating layer 130 having a material strength greater than that of the lower insulating layer 110 may not be on the cutting region 21 except for the region where the process monitoring structure 40 is provided. Therefore, incomplete separation of the semiconductor substrate 100 or peeling in the thin film tape caused by the difference in physical or chemical properties between the lower insulating layer 110 and the upper insulating layer 130 can be prevented. In other words, horizontal cracks along the interface between the lower insulating layer 110 and the upper insulating layer 130 can be prevented. In addition, since the lower insulating layer 110 on the cutting region 21 is thinner than the lower insulating layer 110 on the edge region 23, the separation process of the semiconductor substrate 100 can be easily performed.

[0079] In some embodiments, since the metal material in the redistribution layer does not remain on the edge region 23 after the separation process, processing defects in a subsequent packaging process on the semiconductor chip may be reduced.

[0080] Hereinafter, a semiconductor device according to various embodiments will be described. Figure 4 and FIG. 5A to FIG. 5J The described elements may be identified by similar or identical reference numerals without repeating a repeated description thereof.

[0081] Figure 7 , Figure 8 and Fig. 9 is a cross-sectional view showing a portion of a semiconductor device according to an embodiment.

[0082] Reference Figure 7 After irradiation of the laser beam through the rear surface of the semiconductor substrate 100, the semiconductor substrate 100 may be separated along the scribe line region 20, as shown in FIG. Figure 5H and Figure 5J At this time, the lower insulating layer 110 may be torn. Therefore, the lower insulating layer 110 may have a protruding portion 110P that protrudes laterally from the separation surface SS of the semiconductor device. The protruding portion 110P of the lower insulating layer 110 may have an irregular or uneven shape.

[0083] Reference Figure 8 , the upper insulating layer 130 may include a first portion 130_1 having a first thickness Ta, a second portion 130_2 having a second thickness Tb, and a third portion RP having a decreasing thickness in a direction away from the second portion toward the center, as previously described with reference to Figure 5J The second thickness Tb of the second portion 130_2 may be uniform, and the upper insulating layer 130 may have a first inclined surface S1 between the first portion and the second portion. The thickness of the third portion RP may be continuously reduced from the second thickness Tb, and the upper insulating layer 130 may have a rounded inner surface RS between the second portion and the third portion, for example, Figure 5J Differently, the second inclined surface S2 is continuous with the circular inner surface RS.

[0084] Reference Fig. 9 , the upper insulating layer 130 may have a continuously decreasing thickness (i.e., without a step structure) on the edge region 23. The circular inner surface RS may be continuously formed from the top surface of the upper insulating layer 130 to the top surface of the lower insulating layer 110, for example, along the third direction D3, starting from the edge region 23 that does not overlap the process monitoring structure 40 and the dam structure 120.

[0085] Fig. 10A and Fig. 10B 2 is a cross-sectional view showing a vertical cross section of the semiconductor device according to the embodiment before and after a process of dividing the semiconductor chips. Fig.11 is a cross-sectional view showing a portion of a semiconductor device according to an embodiment.

[0086] Reference Fig. 10A , the dummy metal pattern 123b may be disposed on the lower insulating layer 110 on the scribe line region 20. The dummy metal pattern 123b may be formed when the chip pad 123a is formed on the chip region 10, and may be formed of, for example, aluminum (Al) or include aluminum (Al). The upper insulating layer 130 may have a second opening OP2 in the scribe line region 20 that exposes a portion of the dummy metal pattern 123b.

[0087] The dummy metal structure 120d may be disposed in the lower insulating layer 110 on the scribe line region 20. When viewed in a plan view, for example, along the third direction D3, the dummy metal structure 120d may overlap the dummy metal pattern 123b.

[0088] The dummy metal structure 120d may include dummy metal lines 121b and dummy metal vias 122b alternately stacked along the third direction D3. The dummy metal vias 122b may connect the dummy metal lines 121b disposed at different levels along the third direction D3 to each other. The dummy metal structure 120d may be formed when the internal interconnect structures 121a and 122a are formed on the chip region 10, and may be formed of or include, for example, copper (Cu).

[0089] Reference Fig. 10B After irradiation of the laser beam through the rear surface of the semiconductor substrate, the semiconductor substrate 100 may be cut along the scribe line region 20 to divide the semiconductor substrate 100 into a plurality of semiconductor chips, as shown in FIG. Figure 5H and Fig.5I In this case, a portion of the dummy metal structure 120d and a portion of the dummy metal pattern 123b may remain on the edge region 23. After the cutting process of the semiconductor substrate 100, the upper insulating layer 130 on the edge region 23 may have a stepped structure defined by the first portion 130_1 and the second portion 130_2.

[0090] In addition, in the case where the second opening OP2 of the upper insulating layer 130 exposes a portion of the dummy metal pattern 123b, the dummy metal pattern 123b may be cut irregularly by the separation process of the semiconductor substrate 100, such as Fig.11 Therefore, the dummy metal pattern 123b remaining on the edge region 23 may have a protruding portion 123p protruding laterally from the separation surface SS of the semiconductor device.

[0091] Fig.12 is an enlarged plan view showing a portion of a semiconductor device according to an embodiment. Fig.13A and Fig. 13B It is along Fig.12 1 and 2 are cross-sectional views taken along line III III I′ of FIG. 1 and illustrate vertical cross sections of the semiconductor device according to the embodiment before and after a process of dividing the semiconductor chips. Fig.14 and Fig.15 are respectively along Fig.12 1 is a cross-sectional view taken along lines IV-IV′ and V-V′ of FIG. 1 and illustrates a portion of a semiconductor device according to an embodiment.

[0092] Reference Fig.12 and Fig.13A, the semiconductor substrate 100 may include a chip region 10 and a scribe region 20 between the chip regions 10. The scribe region 20 may include a cutting region 21 and an edge region 23, as described above.

[0093] When the semiconductor integrated circuit 101 is formed on the chip region 10, a plurality of test element groups 30 (for example, see Figure 2 ). The test element group 30 may include various test structures 101T provided for testing the semiconductor integrated circuit 101 .

[0094] In detail, the test structures 101T on the cutting region 21 may be spaced apart from each other in the second direction D2. The test structures 101T may be formed using the process of forming the semiconductor integrated circuit 101 on the chip region. The test structures 101T may include test circuits each having a substantially identical structure to a corresponding one of the semiconductor integrated circuits 101. The lower insulating layer 110 may be formed to cover the semiconductor substrate 100 provided with the semiconductor integrated circuit 101 and the test structures 101T.

[0095] As described above, the upper insulating layer 130 on the scribe area 20 may have the second opening OP2 exposing a portion of the lower insulating layer 110. Here, when viewed in a plan view, for example, along the third direction D3, the second opening OP2 may have a circular inner surface RS and may overlap the test element group 30. The portion of the lower insulating layer 110 exposed by the second opening OP2 may have a second lower thickness that is less than a first lower thickness of the lower insulating layer 110 on the chip area 10.

[0096] Reference Fig. 13B After irradiation of the laser beam through the rear surface of the semiconductor substrate, the semiconductor substrate 100 may be cut along the scribe line region 20 to divide the semiconductor substrate 100 into a plurality of semiconductor chips, as previously described with reference to Figure 5H and Fig.5I In this case, a portion of the test structure 101T may remain on the edge region 23 .

[0097] Reference Fig.12 , Fig.14 and Fig.15 , a connection structure 120c connected to the test structure 101T may be disposed in the lower insulating layer 110 on the scribe line region 20. The connection structure 120c may include a metal line and a metal via, the metal via including the same metal material as the internal interconnection structures 121a and 122a. The uppermost metal line of the connection structure 120c may be disposed as a test pad.

[0098] Redistribution test pads 141b coupled to connection structures 120c through upper insulating layer 130 may be disposed on edge region 23. Redistribution test pads 141b may include redistribution lines 141c extending onto pad portions exposed by passivation layer 153 on the top surface of upper insulating layer 130 and on chip region 10.

[0099] On the scribe line region 20, the upper insulating layer 130 may have a second opening OP2 exposing a portion of the lower insulating layer 110. Fig.14 As shown, a portion of the redistribution test pad 141b may be exposed through the second opening OP2. In addition, a portion of the redistribution test pad 141b may be etched during the formation of the second opening OP2 in the upper insulating layer 130. In other words, the redistribution test pad 141b may have an asymmetric structure. In an embodiment, as shown in FIG. Fig.15 As shown, the redistribution line 141 c may be partially exposed through the second opening OP2 .

[0100] Fig.16 is an enlarged plan view showing a portion of a semiconductor device according to an embodiment. Fig.17A and Fig. 17B is along Fig.16 VI-VI', and shows a vertical cross section of the semiconductor device according to the embodiment before and after the process of dividing the semiconductor chips. Fig.16 and 17A , the process monitoring structure 40 may be disposed on a portion of the scribe line area 20 .

[0101] The process monitoring structure 40 may include a process monitoring pattern on the lower insulating layer 110 and on the scribe line region 20. As an example, the process monitoring pattern may be formed during the formation of the chip pad 123a and may be located at substantially the same level as the chip pad 123a. As another example, the process monitoring pattern may be formed when the internal interconnect structures 121a and 122a are formed on the chip region 10.

[0102] On the scribe line region 20 , the upper insulating layer 130 may cover the process monitoring structure 40 and may have a uniform thickness. The thickness of the upper insulating layer 130 on the process monitoring structure 40 may be substantially equal to the thickness of the upper insulating layer 130 on the chip region 10 .

[0103] Reference Fig. 17B After irradiation of the laser beam through the rear surface of the semiconductor substrate, the semiconductor substrate 100 may be cut along the scribe line region 20 to divide the semiconductor substrate 100 into a plurality of semiconductor chips, as previously described with reference to Figure 5H and Fig.5IHere, a portion 40R of the process monitoring structure may remain on the edge region 23. The upper insulating layer 130 may cover the remaining portion 40R of the process monitoring structure on the edge region 23, and may be formed to have a flat top surface.

[0104] 18A to 18D is along Figure 2 1 is a cross-sectional view taken along line II′ of FIG. 1 and illustrates various stages in a method of manufacturing a semiconductor device according to an embodiment.

[0105] Reference Fig.18A , as referenced Figure 2 and Figure 5A As described above, the semiconductor integrated circuit 101 may be formed on the chip region 10 of the semiconductor substrate 100 , and the test element group and the process monitoring structure may be formed on the scribe line region 20 .

[0106] The lower insulating layer 110 may be stacked on the interlayer insulating layer 103, and the internal interconnection structures 121a and 122a and the dam structure 120 may be formed in the lower insulating layer 110. In addition, a dummy interconnection structure may be further formed in the lower insulating layer 110 on the scribe line region 20.

[0107] The upper insulating layer 130 may cover the entire top surface of the semiconductor substrate 100. For example, the upper insulating layer 130 may be formed on the uppermost layer of the lower insulating layer 110 to cover the chip pad 123a.

[0108] Thereafter, a first opening OP1 may be formed in the upper insulating layer 130 on the chip region 10. Forming the first opening OP1 may include forming a first mask pattern MPa on the upper insulating layer 130 and anisotropically etching the upper insulating layer 130 to expose the chip pad 123a. When forming the first opening OP1, the first mask pattern MPa may cover the scribe line region 20. The first mask pattern MPa may be removed after forming the first opening OP1.

[0109] Reference Fig.18B , a redistribution layer 140 may be formed on the upper insulating layer 130 having the first opening OP1. The redistribution layer 140 may partially fill the first opening OP1, and thus the redistribution layer 140 may contact the chip pad 123a in the first opening OP1. The redistribution layer 140 may have a uniform thickness on the top surface of the upper insulating layer 130.

[0110] After forming the redistribution layer 140, a second mask pattern MPb may be formed on the redistribution layer 140. The second mask pattern MPb may be locally formed on the chip pad 123a.

[0111] Next, the redistribution layer 140 may be patterned using the second mask pattern MPb as an etching mask. For example, the redistribution layer 140 exposed by the second mask pattern MPb may be etched to expose the upper insulating layer 130. As a result of the patterning of the redistribution layer 140, respective redistribution chip pads 141a may be formed in respective first openings OP1 on the chip region 10, as shown in FIG. Fig. 18C During the formation of the redistribution chip pad 141 a on the chip region 10 , the redistribution layer 140 may be completely removed from the scribe line region 20 .

[0112] Afterwards, if Fig. 18C As shown, a passivation layer 153 may be formed on the upper insulating layer 130 to expose a portion of the redistribution chip pad 141a and a portion of the upper insulating layer 130 on the scribe line region 20. In some embodiments, before forming the passivation layer 153, a protection layer 151 may be formed on the semiconductor substrate 100 to conformally cover the structure having the redistribution chip pad 141a.

[0113] In the case of forming the protective layer 151, forming the passivation layer 153 may include forming a passivation material using a coating process and patterning the passivation material using an exposure process without forming an additional photoresist layer. Here, the patterning of the passivation material may be performed to expose a portion of the protective layer 151 on the redistribution chip pad 141a and a portion of the protective layer 151 on the scribe line region 20.

[0114] Next, if Fig.18D As shown, the protective layer 151 exposed by the passivation layer 153 may be etched to expose the redistribution chip pad 141a. In this process, a portion of the protective layer 151 may be removed from the scribe area 20 to expose a portion of the top surface of the upper insulating layer 130 on the scribe area 20. Therefore, the upper insulating layer 130 on the scribe area 20 may be partially exposed or recessed.

[0115] Thereafter, a third mask pattern MPc may be formed on the passivation layer 153 to cover the chip region 10 and expose a portion of the scribe region 20. The third mask pattern MPc may cover the redistribution chip pad 141a and a recessed portion of the upper insulating layer 130 partially covering the edge region 23.

[0116] The upper and lower insulating layers 130 and 110 may be anisotropically etched using the third mask pattern MPc as an etching mask to form second openings OP2 on the scribe line region 20. The second openings OP2 may have a substantially uniform width and expose the interlayer insulating layer 103.

[0117] As a result of forming the second openings OP2, the lower insulating layer 110 may be partially removed from the scribe line region 20. The third mask pattern MPc may be removed after forming the second openings OP2.

[0118] Afterwards, as referenced Figure 5H and Fig.5I As described above, the cutting process of the semiconductor substrate 100 can be performed along the cutting area 21. Since the lower insulating layer 110 and the upper insulating layer 130 on the scribe area 20 are partially removed before the cutting process, it is possible to prevent incomplete cutting, tearing of the thin film, or formation of cracks toward the chip area during the separation process of the semiconductor substrate 100. In addition, since the redistribution layer is completely removed from the scribe area 20 before the lower insulating layer 110 and the upper insulating layer 130 on the scribe area 20 are partially etched, it is possible to prevent the metal material of the redistribution layer from remaining on the edge area 23 after the cutting process.

[0119] Fig.19A is a plan view showing a semiconductor chip that has been separated from a semiconductor device according to an embodiment. Fig.19B is a cross-sectional view showing a semiconductor package including a semiconductor chip according to an embodiment.

[0120] Reference Fig.19A , the semiconductor chip 200 divided by the cutting process of the semiconductor substrate 100 may include a chip region 10 and an edge region 23 around the chip region 10. The remaining test structure 30R and the remaining process monitoring structure 40R may remain in some parts of the edge region 23. A portion of the second opening of the upper insulating layer may remain in the edge region 23. In other words, the upper insulating layer may have a step structure in the edge region 23 of the semiconductor chip 200. As described above, the remaining process monitoring structure 40R may not overlap with the second opening of the upper insulating layer.

[0121] Reference Fig.19B , the semiconductor package 1000 may include a semiconductor chip 200, a package substrate 500, an external coupling terminal 550, and a molding layer 570. In some embodiments, the semiconductor chip 200 may be manufactured by the aforementioned method, and may be mounted on the package substrate 500.

[0122] As described above, the semiconductor chip 200 may include redistribution chip pads 141a exposed by the passivation layer 153. The redistribution chip pads 141a may include data pads for transmitting data signals, command / address pads for transmitting command signals and address signals, and power pads and ground pads to which a ground voltage and a power voltage are applied, respectively.

[0123] The package substrate 500 may be, for example, a printed circuit board, a flexible substrate, a tape substrate, etc. In some embodiments, the package substrate 500 may include a flexible or rigid printed circuit board or a combination thereof on which internal interconnection lines are disposed.

[0124] The package substrate 500 may have a top surface and a bottom surface facing each other, and may include a bonding pad 510, an internal interconnection line ICL, and an external coupling pad 520. The bonding pad 510 may be arranged on the top surface of the package substrate 500, and the external coupling pad 520 may be arranged on the bottom surface of the package substrate 500. The semiconductor chip 200 may be located on the central area of ​​the top surface of the package substrate 500, and an adhesive layer 515 may be provided between the semiconductor chip 200 and the package substrate 500.

[0125] The bonding pads 510 may be connected to the redistribution chip pads 141 a of the semiconductor chip 200 through the wires W. The external coupling pads 520 may be connected to the bonding pads 510 through the internal interconnection lines ICL.

[0126] The molding layer 570 may be disposed on the top surface of the package substrate 500 to cover the semiconductor chip 200. The molding layer 570 may be formed of or include an epoxy molding compound.

[0127] The external coupling terminal 550 may be attached to the external coupling pad 520 disposed on the bottom surface of the package substrate 500. The semiconductor package 1000 may be connected to an external electronic device through the external coupling terminal 550.

[0128] According to some embodiments, the difference in material properties between the lower insulating layer and the upper insulating layer on the scribe line area can be used to partially etch the lower insulating layer and the upper insulating layer on the scribe line area. Therefore, poor processing (e.g., incomplete cutting problem of the semiconductor substrate or peeling problem or cracking problem in the lower insulating layer and the upper insulating layer) can be prevented from occurring during the separation process of the semiconductor substrate. Therefore, the reliability and yield of the semiconductor chips separated by the semiconductor substrate can be improved.

[0129] In addition, a second opening having a circular sidewall can be formed on the scribe line area, and then, a redistribution chip pad can be formed. Therefore, the metal material of the redistribution layer can be prevented from remaining on the scribe line area. Therefore, defects that may occur in the process of packaging individually separated semiconductor chips can be reduced.

[0130] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art when filing this application, unless otherwise specifically noted, the characteristics, features, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the characteristics, features, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device comprising: A semiconductor substrate comprising a chip region and an edge region around the chip region; a lower insulating layer, which is located on the semiconductor substrate; a chip pad located on the lower insulating layer on the chip area; an upper insulating layer, which is located on the lower insulating layer to cover the chip pad, the upper insulating layer comprising an insulating material different from that of the lower insulating layer; and a redistribution chip pad located on the chip region to penetrate the upper insulating layer and connect to the chip pad, The upper insulating layer comprises: A first portion, which is located on the chip area and has a first thickness; a second portion located on the edge region, the second portion extending from the first portion and having a second thickness less than the first thickness; and a third portion located on the edge region, the third portion extending from the second portion, being spaced apart from the first portion, and having a thickness that decreases as it moves away from the second portion, The third portion of the upper insulating layer has a round sidewall.

2. The semiconductor device according to claim 1, wherein: The upper insulating layer has a first inclined surface between the first portion and the second portion and a second inclined surface between the second portion and the third portion, and An inclination angle of the first inclined surface is different from an inclination angle of the second inclined surface.

3. The semiconductor device according to claim 1, wherein The lower insulating layer includes a dielectric material having a lower dielectric constant than that of the upper insulating layer.

4. The semiconductor device according to claim 1, wherein On the edge region, the lower insulating layer includes a first portion having a first lower thickness and a second portion having a second lower thickness less than the first lower thickness.

5. The semiconductor device according to claim 1 , further comprising a dam structure in the lower insulating layer on the edge region, The dam structure is located below the second portion of the upper insulating layer.

6. The semiconductor device according to claim 1, further comprising a test structure on the edge region of the semiconductor substrate, The test structure overlaps the third portion of the upper insulating layer.

7. The semiconductor device according to claim 1 , further comprising a dummy metal pattern on the lower insulating layer on the edge region, in, On the edge region, the upper insulating layer exposes a portion of the dummy metal pattern.

8. The semiconductor device according to claim 7, further comprising a dummy metal structure in the lower insulating layer overlapping the dummy metal pattern, in, The dummy metal structure includes a different metal material from the dummy metal pattern.

9. The semiconductor device according to claim 1, further comprising a process monitoring pattern on the lower insulating layer on the edge region, wherein: The upper insulating layer further includes a fourth portion disposed on the edge region, and The fourth portion has a fourth thickness and covers the process monitoring pattern, wherein the fourth thickness is equal to the first thickness. 10 . The semiconductor device of claim 1 , further comprising a passivation layer covering the first portion of the upper insulating layer and exposing the second portion and the third portion of the upper insulating layer.

11. A semiconductor device comprising: A semiconductor substrate comprising a chip region and an edge region around the chip region; a lower insulating layer, which is located on the semiconductor substrate; a chip pad located on the lower insulating layer on the chip area; an upper insulating layer located on the lower insulating layer, the upper insulating layer having a first opening exposing the chip pad on the chip region and a second opening exposing a portion of the lower insulating layer on the edge region; as well as a redistribution chip pad connected to the chip pad in the first opening, wherein at least a portion of the second opening has a circular sidewall, and The portion of the lower insulating layer on the edge region exposed by the second opening has a circular sidewall extending continuously from the circular sidewall of the second opening.

12. The semiconductor device according to claim 11, wherein: On the edge region, the upper insulating layer includes a first portion having a first thickness and a second portion having a thickness that decreases away from the chip region, and On the chip region, the upper insulating layer has a second thickness greater than the first thickness.

13. The semiconductor device according to claim 11, wherein On the edge region, the lower insulating layer includes a first portion having a first thickness and a second portion having a second thickness smaller than the first thickness.

14. The semiconductor device according to claim 13, wherein: The second opening of the upper insulating layer exposes the second portion of the lower insulating layer.

15. The semiconductor device according to claim 11, wherein: The upper insulating layer includes a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence, The second insulating layer includes an insulating material different from that of the first insulating layer and the third insulating layer, and On the edge region, the third insulating layer has a stepped structure.

16. The semiconductor device according to claim 11, wherein The lower insulating layer includes a dielectric material having a lower dielectric constant than that of the upper insulating layer.

17. The semiconductor device according to claim 11, further comprising a test structure on the edge region of the semiconductor substrate, The second opening of the upper insulating layer overlaps with the test structure.

18. The semiconductor device according to claim 11, further comprising a dummy metal pattern on the lower insulating layer on the edge region, The second opening of the upper insulating layer exposes the dummy metal pattern.

19. The semiconductor device according to claim 18, wherein: The dummy metal pattern is located at the same level as the chip pad.

20. The semiconductor device according to claim 11, further comprising: a test structure on the edge region of the semiconductor substrate; and a redistribution test pad on the lower insulating layer on the edge region and connected to the test structure, The second opening exposes a portion of the redistribution test pad. 21 . The semiconductor device of claim 11 , further comprising a passivation layer on the upper insulating layer on the chip region to expose a portion of the redistribution chip pad and the round sidewall of the upper insulating layer.

22. The semiconductor device according to claim 11, further comprising a process monitoring structure disposed on a portion of the edge region, The upper insulating layer extends in the edge region to cover the process monitoring structure.

23. A semiconductor device comprising: A semiconductor substrate comprising a chip region and an edge region around the chip region; a lower insulating layer, which is located on the semiconductor substrate; a chip pad located on the lower insulating layer on the chip area; an upper insulating layer, which is located on the lower insulating layer to cover the chip pad, the upper insulating layer comprising an insulating material different from that of the lower insulating layer; as well as a redistribution chip pad located on the chip region to penetrate the upper insulating layer and connect to the chip pad, Wherein, the upper insulating layer comprises: A first portion, which is located on the chip area and has a first thickness; a second portion located on the first portion of the edge region, the second portion extending from the first portion and having a second thickness less than the first thickness; and a third portion located on the second portion of the edge region, the third portion extending from the second portion, being spaced apart from the first portion, and having a thickness that decreases as it moves away from the second portion, The third portion of the upper insulating layer has a round sidewall.

24. The semiconductor device according to claim 23, further comprising a process monitoring structure disposed on the first portion of the edge region, Wherein the first portion of the upper insulating layer covers the process monitoring structure.

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