RC trigger support circuit

Abstract

A protection circuit includes a low leakage electrostatic discharge (ESD) protection circuit and at least one support circuit, wherein the at least one support circuit includes: an RC input stage connected between a pad and ground; a driver transistor, the driver transistor being configured to drive multiple components of the at least one support circuit; a series transistor on the input line, the series transistor being configured to act as a high impedance element during an ESD event; and a micro clamp, the micro clamp being configured to short the input line to ground to protect the circuit to be protected during the ESD event.

Description

Technical Field

[0001] Various exemplary embodiments disclosed herein relate to electrostatic discharge (ESD) protection, and more particularly, to a support circuit for use in conjunction with a low leakage ESD protection scheme. Background Art

[0002] Current state-of-the-art ESD protection for low voltage circuits (typically, 5V and lower) may include capacitively triggered rail clamps used in conjunction with ESD diodes. While rail clamps remain the workhorse for contemporary ESD circuits, disadvantages include significant standby leakage. In integrated circuit (IC) designs for low leakage applications, high leakage is unacceptable. As silicon technology advances, this problem tends to get worse as gate length decreases. Moving to smaller sizes, standby leakage for CMOS components such as NMOS transistors increases.

[0003] An alternative to using a track clamp for ESD protection is to use a grounded gate NMOS transistor (GGNMOS transistor) or a low trigger voltage silicon controlled rectifier (LVTSCR) as an ESD protection device. Both devices have a much smaller device width than the track clamp, and therefore have a much lower standby leakage current. However, GGNMOS transistors and LVTSCRs have their own disadvantages. Because they collect the ESD PAD input current, they operate at a higher clamping voltage than the track clamp. This increased clamping voltage during the ESD pulse applies a higher voltage stress to the circuit being protected. The increased voltage stress that occurs using a GGNMOS transistor is enough to risk damaging the circuit being protected. Summary of the invention

[0004] A brief summary of various embodiments is presented below. Some simplifications and omissions may be made in the following summary, which is intended to highlight and introduce some aspects of the various embodiments, rather than to limit the scope of the invention. In later sections, there will be a detailed description of the embodiments sufficient to allow one of ordinary skill in the art to make and use the inventive concepts.

[0005] An embodiment includes a protection circuit comprising a low leakage electrostatic discharge (ESD) protection circuit and at least one support circuit, the at least one support circuit comprising: an RC input stage connected between a pad and ground; a driver transistor configured to drive multiple components of the at least one support circuit; a series transistor on the input line configured to act as a high impedance element during an ESD event; and a micro clamp configured to short the input line to ground to protect the circuit to be protected during the ESD event.

[0006] The source of the series transistor may be connected to the pad, and the drain of the series transistor connected to the circuit to be protected.

[0007] The source of the driver transistor may be connected to the pad, and the drain of the driver transistor is connected to the gate of the micro-clamp.

[0008] The series transistor may be a large-size transistor. The series transistor may be a PMOS transistor.

[0009] The micro clamp may be a small-sized transistor. The micro clamp may be an NMOS transistor.

[0010] During an ESD event, the source of the series transistor and the gate of the series transistor may have substantially the same potential.

[0011] The RC input stage may include a capacitor connected transistor.

[0012] The low leakage ESD protection circuit may include a grounded gate NMOS transistor to sink the ESD pad current to ground.

[0013] The protection circuit may include a second support circuit connected in parallel with the at least one support circuit.

[0014] Embodiments may also include an ESD protection circuit comprising a low leakage electrostatic discharge (ESD) protection circuit and a support circuit, the support circuit comprising: an extended drain (ED) transistor connected to the low leakage ESD protection circuit and a pad; an RC input stage connected between the extended drain transistor and ground; a driver transistor configured to drive multiple components of the support circuit; a micro clamp configured to short the input line to ground to protect the circuit to be protected during an ESD event; and a gate clamp configured to pull down the gate of the ED transistor to configure the ED transistor into a high impedance state.

[0015] The micro-clamp and the gate clamp transistors may be NMOS transistors.

[0016] Embodiments may also include a method for protecting a circuit from an ESD pulse using a support circuit, comprising collecting ESD current pulses using a low leakage ESD protection device, activating an RC trigger circuit using an operating voltage of the low leakage protection device, triggering a driver transistor to activate elements of the support circuit, activating a series transistor to a high impedance state, and turning on a micro clamp transistor to connect an input line to ground and protect the circuit to be protected.

[0017] The method may include activating the series transistor and turning on the micro-clamp substantially simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Additional objects and features of the present invention will be more readily apparent from the following detailed description and the appended claims taken in conjunction with the drawings. Although several embodiments are shown and described, similar reference numerals identify similar parts in each of the figures, wherein:

[0019] Figure 1A shows a protection circuit according to an embodiment described herein;

[0020] Figure 1B Show according to Figure 1A Changes in protection circuits;

[0021] Figure 2 Show according to Figure 1A and 1B Parallel arrangement of protection circuits.

[0022] Figure 3 shows variations of protection circuits according to embodiments described herein; and

[0023] Figure 4 shows a support circuit in combination with a high voltage LDO EDNMOS transistor configured as a source follower according to embodiments described herein; DETAILED DESCRIPTION

[0024] It should be understood that the drawings are only schematic and not drawn to scale. It should also be understood that the same reference numerals are used throughout the drawings to indicate the same or similar parts.

[0025] The description and drawings illustrate the principles of various example embodiments. It will therefore be appreciated that those skilled in the art will be able to design various arrangements, which, although not explicitly described or shown herein, embody the principles of the present invention and are included within their scope. In addition, all examples described herein are primarily intended to be used for teaching purposes to assist readers in understanding the principles of the present invention and the concepts provided by the inventors, thereby deepening this technology, and all examples should be interpreted as not being limited to such specific examples and conditions of narration. In addition, the term "or" as used herein refers to non-exclusive or (i.e., and / or), unless otherwise indicated (e.g., "otherwise" or "or in an alternative"). Moreover, the various embodiments described herein are not necessarily mutually exclusive, because some embodiments may be combined with one or more other embodiments to form new embodiments. For example, descriptors such as "first", "second", "third" are not intended to limit the order of the elements discussed, and are used to distinguish one element from the next element, and are generally interchangeable. Values ​​(e.g., maximum or minimum values) may be predetermined and set to different values ​​based on the application.

[0026] Embodiments described herein include RC triggered circuits that disconnect sensitive circuit blocks from the PAD under stress and temporarily short them to IC ground when an ESD pulse strikes. As described herein, embodiments allow the use of small NMOS transistors or "micro clamps" as part of support circuits and low leakage ESD protection devices for circuit blocks that would normally not withstand the higher clamping voltages of GGNMOS transistors. The term "support circuit" may refer to an RC triggered circuit that has the circuit protected by the "support" itself against an upcoming ESD pulse and the high clamping voltage that is absent as the GGNMOS transistors collect the ESD pulse.

[0027] Table 1 shows typical device width and length (W / L) values ​​and operating voltages for devices such as capacitive rail clamps and GGNMOS transistors designed to protect against 2-ampere current pulses, which may be equivalent to a 3-kV human body model (HBM). The standby leakage of an ESD protection circuit generally depends on the process technology, and typically the standby leakage of the device is linearly proportional to the W / L ratio. Thus, the leakage of a GGNMOS transistor is about 1 / 20 of that of a rail clamp. As indicated, a GGNMOS transistor may have a smaller size in terms of gate length and width, utilizing more less-standby leakage current, but may have a higher voltage during and after triggering.

[0028] Table I

[0029]

[0030] Figure 1A A protection circuit 100 is shown configured as a protection circuit 170 in accordance with embodiments described herein. The protection circuit 100 may be designed as part of an ESD protection scheme, or added to an existing ESD or other circuit that exhibits high voltages at input nodes.

[0031] The GGNMOS transistor 107 uses very little standby leakage current when not activated. During an ESD event, the GGNMOS transistor 107 is designed to turn on and sink the current pulse appearing at the PAD 105 to VSS. However, as indicated in Table 1, when the GGNMOS transistor is in operation, the voltage at the node connected to the PAD 105 remains high, about 10V during the triggering period, and about 7V after the triggering. If not handled, this voltage can damage the circuit 170 to be protected. Through the operation of the GGNMOS transistor 107, the support circuit 110 according to the embodiments described herein can be used to minimize the high voltage that remains unresolved.

[0032] The protection circuit 100 may be configured to handle ESD pulses caused by the human body. ESD pulses may also be applied to the IC during pre-sale verification testing. The protection circuit 100 may receive an initial ESD pulse at the PAD 105. The pulse may initially be directed to the GGNMOS transistor 107 for ESD protection, but as described above, the GGNMOS transistor 107 has a high operating voltage during an ESD event. In order to negate damage to the circuit 170 to be protected, a support circuit 110 may be used.

[0033] The support circuit 110 may include an RC input stage 120 and a driver PMOS transistor 130. The RC input stage 120 includes a resistor 122 in series with an NMOS transistor 125 configured as a capacitor in which the source, drain, and body of the NMOS transistor 125 are connected to VSS. At what may be labeled as a midpoint 127 of the RC input stage 120, the resistor 122 is connected to the gate of the capacitor-connected NMOS transistor 125.

[0034] During normal operation, the voltage at PAD 105 is constant and supplies the operating voltage to the protected circuit 170. Generally speaking, this operating voltage is well controlled to remain below a preset limit in order to ensure that there is no risk of damaging the protected circuit 170. When the protected circuit 170 is not operating, the voltage at PAD 105 is also constant and equal to zero with respect to the circuit VSS PAD 105. In either case, there is no current in the resistor 122, and the potential at PAD 105 and the RC midpoint 127 are equal. This indicates that the RC input stage 120 is not activated. The GGNMOS transistor 107 also remains off.

[0035] During an ESD event, the operation of GGNMOS transistor 107 directs an ESD current pulse to VSS. This includes a rapid increase in the voltage at PAD 105 from zero volts, or from a desired operating voltage, to a voltage (10V in Table 1) during the triggering of GGNMOS transistor 107 during the initial phase of the ESD pulse. After that, the voltage at PAD 105 decreases slightly (to 7V, in Table 1), and then remains stable for the remainder of the ESD pulse. Both of these voltages are higher than the desired operating voltage of the protected circuit 170, and both have the potential to damage the protected circuit 170. The rapid increase in voltage at PAD 105 causes current to flow through resistor 122, and, therefore, causes the potential of PAD 105 to be higher than the potential of RC midpoint 127. This indicates that the RC input stage 120 is activated. The property of the RC input stage 120 is that the voltage at the RC midpoint 127 remains constant over a time interval determined by the mathematical product of the resistance value of the resistor 122 and the capacitance value implemented by the NMOS transistor 125. These two values ​​are deliberately chosen so that the resulting time interval is much longer than the expected duration of the ESD pulse. This means that the RC input stage 120 will remain active over the full expected duration of the ESD pulse, and this active state includes a voltage at the RC midpoint 127 that is lower than the voltage across the PAD 105.

[0036] The RC midpoint 127 of the RC input stage 120 is connected to the gate of a driver PMOS transistor 130. The driver PMOS transistor 130 drives the action of the rest of the support circuit 110. The source 132 of the driver PMOS transistor 130 is connected to the input PAD 105. During normal operation, the potential of the gate 134 of the driver PMOS transistor 130 and the source 132 of the same driver PMOS transistor 130 will be at the supply voltage. Because there is no potential difference, the driver PMOS transistor 130 is therefore in a non-conductive state, and the pull-down resistor 175 ensures that the voltage on the driver output node 137 is low (equal to VSS). As a result, the series PMOS transistor 140 is conductive, which allows the protected circuit 170 to be powered, and the NMOS transistor micro-clamp 150 is non-conductive.

[0037] During an ESD event at PAD 105, the voltage at RC midpoint 127 may rise slightly, but will remain significantly lower than the voltage observed at PAD 105 due to resistor 122. The on-time duration of protection circuit 100 may be controlled by the RC time constant of RC input stage 120. The RC time constant may be designed to be large enough, on the order of hundreds of nanoseconds, to keep support circuit 110 in an "on" state under ESD stress conditions. RC input stage 120 is referred to as a trigger circuit due to its ability to trigger driver PMOS transistor 130 and subsequent circuitry.

[0038] During an ESD event, the voltage on the PAD node 105 rises rapidly. Both the source 132 of the driver PMOS transistor 130 and the source 142 of the series PMOS transistor 140 follow this rapid rise in potential because they are directly connected to the PAD 105. With the high voltage present at the source 132 and the low voltage at the gate 134, the negative gate 134 to source 132 voltage increases, further opening the PMOS channel to allow more current to flow through the driver PMOS transistor 130. This establishes a higher voltage at the driver output node 137. This higher voltage is sufficient to turn on the NMOS transistor micro-clamp 150. The driver output node 137 of the driver PMOS transistor 130 is connected to the gate of the series PMOS transistor 140 and to the gate of the NMOS transistor micro-clamp 150. When a high voltage becomes present at the drain 135 of the driver transistor and on the driver output node 137, the driver PMOS transistor 130 activates the series PMOS transistor 140 and turns on the NMOS transistor micro-clamp 150 substantially simultaneously.

[0039] During an ESD event, the driver output node 137 has a high potential input to the gate 144 of the series PMOS transistor 140. The source 142 of the series PMOS transistor may also have a high PAD potential. The high voltage at the source 142 and at the gate 144 forces a very small gate-source bias on the series PMOS transistor 140, making the series PMOS transistor 140 highly resistive and non-conductive. At the same time, the higher voltage at the driver output node 137 turns on the gate 154 of the NMOS transistor "micro clamp" 150, which shorts the node 160 to be protected to VSS. In this way, the protected circuit 170 is protected from the high voltage that appears on the PAD 105 during the ESD event. When the gate 154 is turned on, any residual operating voltage on the input line 111 is shorted to ground, and a ground path is created for any ESD current or GGNMOS voltage that passes through the high impedance series PMOS transistor 140.

[0040] Figure 1B Show according to Figure 1AThe protection circuit changes. Figure 1B In the embodiment, the pull-down NMOS transistor 180 can be replaced Figure 1A The pull-down resistor 175 may be replaced by a pull-down NMOS transistor 180 to further suppress DC leakage through the trigger circuit.

[0041] In the support circuit 110, the series PMOS transistor 140 and the NMOS transistor micro-clamp 150 can be driven simultaneously during an ESD event. Due to the small gate-source voltage difference, the series PMOS transistor 140 is driven to a high impedance state during ESD, and this high impedance greatly limits the current collected by the NMOS transistor micro-clamp 150. Due to this design, the size of the NMOS transistor micro-clamp 150 can be kept very small, for example, about 20μm gate width. The "small" micro-clamp can be about 20μm to 50μm and include a single gate, or several parallel gates of 10μm each. Therefore, the support circuit 110 can be an enabler for ESD-robust, low standby leakage current products. The size of the series PMOS transistor 140 can be selected as a function of the maximum amount of series resistance that the circuit can tolerate in its supply line, and can be much larger, for example, 1,000μm. The large size includes a gate of about 1,000 μm wide, divided into twenty parallel gates of, for example, 50 μm each. The total gate width is the sum of the widths of all parallel gates. The channel leakage in the series PMOS transistor 140 is fed back from the PAD 105 into the protected circuit 170 and therefore does not increase the standby leakage observed at the PAD 105.

[0042] Figure 2 Show according to Figure 1A and 1B The parallel arrangement 200 of the support circuits 110 of FIG. 200 can reduce the series resistance presented by the series PMOS transistors 140 at the expense of increased supply leakage caused by the increased total number of NMOS transistor micro-clamps 150, one in each support circuit.

[0043] Embodiments may implement these separate support circuits for different circuits 270 and 275 being protected as a way to reduce the total series resistance presented by the series PMOS transistor 140. This will increase standby leakage because each additional support circuit has an NMOS transistor micro-clamp 150 adding to the leakage current of that portion. Embodiments may balance the maximum allowable leakage against the maximum allowable supply line series resistance.

[0044] Figure 3300 according to the embodiments described herein. A second variation is the integration of the support circuit 310 into a pre-existing low dropout (LDO) voltage regulator 340 including a PMOS transistor 345 and a diode 355. In this case, the LDO 340 may be a pre-existing circuit with the circuit 170 to be protected. By combining the support circuit 310 with the LDO 340, the LDO 340 may be used instead of Figure 1A and 1B 340 as a series PMOS transistor in the support circuit 310. This reuse of the LDO regulator 340 reduces the added silicon footprint of the support circuit 310 because the series PMOS transistor 345 can be the largest device in the circuit. Reusing the PMOS transistor LDO 340 as a series PMOS transistor in the support circuit 310 can also allow the support circuit 310 to be added without introducing additional series resistance for the signal or supply lines.

[0045] In operation, the driver PMOS transistor 130 drives the gate 344 of the PMOS transistor LDO 340 through the series diode 355. At the same time, during normal operation, the voltage V_LDO 348 directly drives the gate 344 of the PMOS transistor LDO 340. During ESD, the voltage on the driver output node 137 is driven high (to a voltage equal to PAD), and the voltage on the PMOS transistor LDO gate 344 follows it with a diode voltage drop. As a result, during ESD, the gate-source bias on the PMOS transistor LDO 340 is limited to -0.6V, which can be applied to the PMOS transistor LDO 340 in a high impedance state. Again, the ability to configure the PMOS transistor LDO 340 in a high impedance state allows the use of an extremely small size NMOS transistor micro-clamp 150 as internal ESD protection, and this makes this variation of the support circuit 310 compatible with high to extreme requirements for low standby leakage current. The support circuit 310 can also be configured as shown in Figure 2 The manner shown is arranged in a parallel configuration with another supporting circuit 310.

[0046] Figure 4 A support circuit 410 is shown in combination with an existing circuit such as an LDO 440. In this example, the LDO 440 may be an extended drain (EDNMOS) transistor configured as a source follower. The extended drain 442 may encompass a larger area and / or depth than a standard drain region. The extended drain region may thus be configured to receive and accommodate an increased PAD voltage without destroying the LDO 440. During normal operation, the LDO 440 may be driven by V_LDO 448.

[0047] During an ESD event, the extended drain 442 receives a large amount of high voltage. Part of the ESD current swings through the LDO source follower 440 and activates the RC stage 420 of the support circuit 410. The RC stage 420 can drive two NMOS transistors (through the driver PMOS transistor 430). The NMOS micro clamp 450 is driven by the PMOS driver transistor 430. The NMOS micro clamp 450 is configured to pull the power line 415 down to VSS and directly protect the circuit 170. The second NMOS transistor "gate clamp" 455 is activated by the driver PMOS transistor 430 and pulls down on the gate 444 of the ED-NMOS transistor LDO 440, placing it in a high impedance state. That state is achieved because the V_LDO signal can be configured to have a potential that is substantially the same as or lower than the potential observed on the power line 415 connected to the source terminal 443 of the ED-NMOS transistor LDO 440. The high impedance state places the ED-NMOS transistor LDO 440 in a non-conductive state to further protect the circuit 170. Because the ED-NMOS transistor LDO 440 is placed in a high impedance state and is non-conductive, the gate clamp 455 and the micro-clamp 450 NMOS transistor can be kept small and, therefore, compatible with low leakage requirements. The support circuit 410 can also be configured as in Figure 2 The manner shown is arranged in a parallel configuration with another supporting circuit 410.

[0048] Embodiments can optimize ESD designs for low standby leakage by minimizing leakage current in the primary protection element. One way to do that is by using a snap-back device (GGNMOS transistor or LVTSCR) as the primary protection element. By using a snap-back device, the higher operating voltage required for snap-back ESD protection supports the circuit to be protected.

[0049] The support circuits discussed herein can use components including large series PMOS and small micro clamp NMOS added to existing GGNMOS and other electronic circuits, while the circuit blocks being protected remain essentially unchanged. As a result, the support circuits described herein can be applied with minimal impact on overall part performance and can be added at a later stage in the design process, or as a correction for unexpected ESD problems.

[0050] The support circuits described herein can permit the use of GGNMOS transistors or LVTSRCs as primary ESD protection in designs that would otherwise have to be protected by capacitive rail clamps. This achieves a significant reduction (about 20 times) in standby leakage, since GGNMOS transistors and LVTSCRs generally leak much less than capacitive rail clamps.

[0051] Although various exemplary embodiments have been described in detail with particular reference to specific exemplary aspects of the various exemplary embodiments, it should be understood that the invention is capable of other embodiments and that the details of the invention are capable of modifications in various obvious aspects. As will be readily apparent to those skilled in the art, variations and modifications may be implemented while remaining within the spirit and scope of the invention. Therefore, the foregoing disclosure, description, and figures are for illustrative purposes only and do not limit the invention in any way, the invention being limited only by the claims.

Claims

1. A support circuit, characterized in that: include: a first input node and a second input node; a first output node and a second output node; wherein the first input node is configured to be coupled to an input voltage pad and a first node of an electrostatic discharge (ESD) protection circuit; wherein the second input node is configured to be coupled to a ground voltage pad and a second node of the electrostatic discharge (ESD) protection circuit; wherein the first output node is configured to be coupled to a first node of a circuit to be protected; wherein the second output node is configured to be coupled to a second node of the circuit to be protected; an RC input stage connected between a first input node and a second input node, wherein the RC input stage is configured to generate a trigger signal in response to an ESD event between the first input node and the second input node; a driver transistor coupled to receive the trigger signal from the RC input stage and in response to setting the series transistor to a high impedance state and the micro clamp transistor to a low impedance state; The series transistor includes an input coupled to the first input node and an output coupled to a first output node; as well as The micro-clamp transistor includes an input terminal coupled to the first output node and an output terminal coupled to a second output node.

2. The support circuit according to claim 1, characterized in that: A source of the series transistor is connected to the pad, and a drain of the series transistor is connected to a circuit to be protected.

3. The support circuit according to claim 1, characterized in that: The source of the driver transistor is connected to the pad, and the drain of the driver transistor is connected to the gate of the micro-clamp.

4. The support circuit according to claim 1, characterized in that: The series transistor is a large-size transistor.

5. The supporting circuit according to claim 1, characterized in that: The micro clamp is a small size transistor.

6. The supporting circuit according to claim 1, characterized in that: During an ESD event, the source of the cascade transistor has substantially the same potential as the gate of the cascade transistor.

7. The supporting circuit according to claim 1, characterized in that: The RC input stage includes capacitor-connected transistors.

8. The supporting circuit according to claim 1, characterized in that: The electrostatic discharge (ESD) protection circuit includes a grounded gate NMOS transistor to sink the ESD pad current to ground.

9. An ESD protection circuit, characterized in that: include: A low leakage electrostatic discharge (ESD) protection circuit and a supporting circuit as claimed in any one of claims 1 to 8.

10. A method for protecting a circuit from an ESD event received between an input voltage pad and a ground voltage pad using a support circuit, characterized in that: include: sinking current from the ESD event using an ESD protection device coupled between the input voltage pad and the ground voltage pad; triggering a driver transistor in response to the ESD event using an RC trigger circuit; wherein, in response to the triggering, the driver transistor places the series transistor in a high impedance state and places the micro clamp transistor in a low impedance state; When the series transistor is in the high impedance state, the input voltage pad is blocked from the circuit to be protected; and When the micro clamp transistor is in a low impedance state, the circuit to be protected is short-circuited to the ground voltage pad to protect the circuit to be protected from the influence of ESD events.

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