Transistor with shielding structure, packaging device and manufacturing method thereof

Abstract

A transistor includes a semiconductor substrate having an active device region formed therein and an interconnect structure on a first surface of the semiconductor substrate. The interconnect structure is formed of multiple layers of dielectric material and conductive material. A drain flow path and a gate flow path are formed in the interconnect structure. A shield structure extends over a second surface of the interconnect structure, the shield structure being positioned between the drain flow path and the gate flow path.

Description

Technical Field

[0001] The present invention relates generally to field effect transistors and more particularly to a transistor having a shielding structure for reducing parasitic capacitance and loss caused by encapsulation materials. Background Art

[0002] In semiconductor device manufacturing, integrated circuits are often encapsulated with plastic encapsulation materials that act to prevent physical damage and corrosion, to provide effective heat dissipation, etc. However, the encapsulation material may add significant parasitic feedback capacitance and losses due to the encapsulation material. These parasitic feedback capacitance and losses may adversely affect the performance of transistors within the integrated circuit in terms of gain and stability. Summary of the invention

[0003] According to a first aspect of the present invention, there is provided a transistor, comprising:

[0004] a semiconductor substrate having an active device region formed therein;

[0005] an interconnect structure, the interconnect structure being on the first surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and conductive material, wherein a drain flow channel and a gate flow channel are formed in the interconnect structure; and

[0006] A shield structure extends over the second surface of the interconnect structure, the shield structure being positioned between the drain runner and the gate runner.

[0007] In one or more embodiments, the drain runner and the gate runner are characterized by a first length, and the shield structure is characterized by a second length, the second length of the shield structure being longitudinally aligned with the first length of the drain runner and the gate runner.

[0008] In one or more embodiments, the shielding structure is formed of a conductive material.

[0009] In one or more embodiments, the shielding structure is electrically connected to the source node.

[0010] In one or more embodiments, the shield structure is configured to extend over the second surface of the interconnect structure at a height sufficient to reduce parasitic capacitance between the drain runner and the gate runner.

[0011] In one or more embodiments, the transistor further includes a dielectric protective coating, wherein the dielectric protective coating is formed on the second surface of the interconnect structure, and the shielding structure is encapsulated by the dielectric protective coating.

[0012] In one or more embodiments, the transistor further includes a casing material covering the dielectric protective coating.

[0013] In one or more embodiments, the transistor further includes a shielding flow channel formed in the interconnect structure, the shielding flow channel being positioned between the drain flow channel and the gate flow channel, wherein the shielding structure is formed on the shielding flow channel.

[0014] In one or more embodiments, the interconnect structure includes at least one passivation layer at the second surface of the interconnect structure, a portion of the at least one passivation layer is not present in the shielding channel to expose the shielding channel, and wherein the shielding structure is electrically connected to the shielding channel.

[0015] In one or more embodiments, the interconnect structure includes at least one passivation layer at the second surface of the interconnect structure, wherein the shielding structure is formed on the at least one passivation layer.

[0016] According to a second aspect of the present invention, there is provided a packaging device, comprising:

[0017] a substrate having a mounting surface; and

[0018] a transistor coupled to the mounting surface of the substrate, the transistor comprising:

[0019] a semiconductor substrate having an active device region formed therein;

[0020] an interconnect structure, the interconnect structure being on the first surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and conductive material, wherein a drain flow channel and a gate flow channel are formed in the interconnect structure;

[0021] a shield structure extending over a second surface of the interconnect structure, the shield structure positioned between the drain runner and the gate runner;

[0022] a dielectric protective coating formed on the second surface of the interconnect structure, the shielding structure being encapsulated by the dielectric protective coating; and

[0023] A housing material is formed to cover the dielectric protective coating.

[0024] In one or more embodiments, the drain runner and the gate runner are characterized by a first length, and the shield structure is characterized by a second length, the second length of the shield structure being longitudinally aligned with the first length of the drain runner and the gate runner.

[0025] In one or more embodiments, the shielding structure is formed of a conductive material.

[0026] In one or more embodiments, the shielding structure is electrically connected to a source node of the transistor.

[0027] In one or more embodiments, the shield structure is configured to extend over the second surface of the interconnect structure at a height sufficient to reduce parasitic capacitance between the drain runner and the gate runner.

[0028] According to a third aspect of the present invention, there is provided a method comprising:

[0029] providing a semiconductor substrate having an active device region formed therein and an interconnect structure formed on a first surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and conductive material, wherein a drain flow path and a gate flow path are formed in the interconnect structure; and

[0030] A shield structure is formed extending over a second surface of the interconnect structure, the shield structure being positioned between the drain runner and the gate runner.

[0031] In one or more embodiments, the drain runner and the gate runner are aligned parallel to each other, and the forming operation includes forming the shielding structure along the length of the drain runner and the gate runner.

[0032] In one or more embodiments, the forming operation includes forming the shield structure extending over the second surface of the interconnect structure at a height sufficient to reduce parasitic capacitance between the drain runner and the gate runner.

[0033] In one or more embodiments, the method further includes forming a dielectric protective coating over the second surface of the interconnect structure, the shielding structure being encapsulated by the dielectric protective coating.

[0034] In one or more embodiments, the method further includes forming a shell material layer covering the dielectric protective coating.

[0035] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are used to further illustrate various embodiments and to explain various principles and advantages of the present invention. In the individual views in the accompanying drawings, like reference numerals refer to the same or functionally similar elements. The accompanying drawings are not necessarily drawn to scale, and the accompanying drawings together with the following detailed description are incorporated into and form a part of this specification.

[0037] Figure 1 shows a simplified top view of an example of a transistor having interdigitated drain and gate fingers;

[0038] Figure 2 shows a side cross-sectional view of a portion of a prior art transistor;

[0039] Figure 3 shows a side cross-sectional view of a portion of a prior art transistor after encapsulation with an encapsulation material;

[0040] Figure 4 shows a side cross-sectional view of a portion of a transistor according to one embodiment;

[0041] Figure 5 Shows Figure 4 A plan view of a portion of a transistor;

[0042] Figure 6 illustrates a side cross-sectional view of a portion of a transistor according to another embodiment;

[0043] Figure 7 Shows Figure 5 A plan view of another portion of the transistor;

[0044] Figure 8 illustrates a side cross-sectional view of a portion of a transistor according to another embodiment;

[0045] Fig. 9 A graph showing the generalized difference in parasitic capacitance versus frequency between a prior art transistor and a transistor according to one embodiment;

[0046] Fig.10 shows a top view of a highly simplified packaging device according to another embodiment; and

[0047] Fig.11 A flow chart of a manufacturing process according to another embodiment is shown. DETAILED DESCRIPTION

[0048] In summary, embodiments disclosed herein require a transistor having a shielding structure formed on an interconnect structure of a transistor, a packaging device having such a transistor, and a method for manufacturing a transistor comprising the same. More specifically, embodiments may include a plurality of shielding structures formed by a conductive layer, the plurality of shielding structures strategically positioned above the interconnect structure between the drain flow channel and the gate flow channel of a multi-channel cross-finger transistor. The shielding structure is covered by a dielectric protective coating. Thereafter, the transistor may be encapsulated with an encapsulation material during integrated circuit packaging. The presence of the shielding structure and the dielectric protective coating lifts the encapsulation material away from the gate flow channel and the drain flow channel, thereby reducing the electrical coupling between the gate flow channel and the drain flow channel. The integration of the shielding structure can effectively increase the gain of an active device (e.g., a transistor) by reducing feedback capacitance without degrading stability.

[0049] The following description requires the implementation of a shielding structure above an interconnect structure of a field effect transistor (FET) in a non-limiting manner. Multiple shielding structures can be strategically positioned between drain and gate flow channels of a multi-channel interdigital FET. However, it should be understood that the shielding structure can be implemented in various unipolar transistor technologies and bipolar transistor technologies.

[0050] This disclosure is provided to further explain in an enabling manner the best way to make and use embodiments according to the present invention when applied. This disclosure is further provided to enhance the understanding and appreciation of the inventive principles and advantages of the present disclosure, but is not intended to limit the present invention in any way. The present invention is limited solely by the appended claims, which include any amendments made during the pendency of this application and all equivalents of those claims as published.

[0051] It should be understood that the use of relational terms such as first and second, top and bottom, etc. (if any) is only used to distinguish entities or actions from each other, and does not necessarily require or imply any such actual relationship or order between such entities or actions. In addition, various shading and / or hatching may be used to illustrate some of the figures in the accompanying drawings in order to distinguish different elements produced within each structural layer. These different elements within the structural layers can be produced using current and upcoming micro-machining technologies such as deposition, patterning, etching, etc. Therefore, although different shading and / or hatching are used in the illustrations, different elements within the structural layers can be formed of the same material.

[0052] Figure 1A simplified top view of an example of a transistor 20 having an interdigitated drain channel 22 and a gate channel 24 is shown. That is, the drain channel 22 and the gate channel 24 are closely positioned relative to each other in an alternating arrangement. The gate 26 generally surrounds a drain region (not visible) in a semiconductor substrate 28 of an intrinsic device formed below the drain channel 22 and the gate channel 24. The transistor 20 further includes a plurality of tap interconnects 30 formed of a conductive material (typically metal). The tap interconnects 30 are electrically connected between the gate channel 24 and the gate tap or gate electrode of the gate 26 formed in the semiconductor substrate 28. The transistor 20 may include a shielding channel 32 interposed between each pair of drain channels 22 and gate channels 24, which may reduce some feedback capacitance between the drain channel 22 and the gate channel 24. The interdigitated drain channels 22, the gate channels 24, and the shielding channels 32 may be formed in one or more metal layers above the semiconductor substrate 28.

[0053] Reference now Figure 2 , Figure 2 A side cross-sectional view of a portion of a prior art transistor 34 is shown. The transistor 34 includes a semiconductor substrate 36 having an intrinsic active device region 38, such as a FET, formed therein and generally represented by a dashed box. The details of the active device region 38 are known to those skilled in the art and are therefore not described herein for the sake of brevity. It is necessary to repeat that although FET designs may be discussed herein, various unipolar transistor technologies and bipolar transistor technologies may alternatively be implemented.

[0054] The interconnect structure 40 is formed on the upper surface 42 of the semiconductor substrate 36. Generally, the interconnect structure 40 of the transistor 34 includes a plurality of interdigital first and second flow channels, namely, the drain flow channel 44 and the gate flow channel 46. In addition, the interconnect structure 40 may include a plurality of shielding flow channels 48 interposed between each drain flow channel 44 and the gate flow channel 46. For simplicity of description, Figure 2 Only a single drain flow channel 44, two gate flow channels 46, and two shield flow channels 48 are shown in the side cross-sectional view of FIG. However, it should be understood that transistor 34 may include a plurality of gate flow channels 46, and two shield flow channels 48. Figure 1 The transistor 20 in FIG. 1 shows a plurality of drain channels, gate channels and shield channels. In addition, the gate electrode may be structured as shown in FIG. Figure 1 Also shown is a drain flow channel 44 on the opposite side.

[0055] The interconnect structure 40 can be formed of multiple layers of dielectric materials and conductive materials. In the example shown, the bottom-most first conductive layer 50 (indicated by the black narrow long hatching directed upward and rightward) is appropriately formed on the upper surface 42 of the semiconductor substrate 36 to include the bottom tap section 52 (two are shown) electrically connected to the gate electrode 54 through the conductive via 56. In addition, the first conductive layer 50 includes a bottom drain section 58 (one is shown) electrically connected to the drain region 60 through the conductive via 62. The source silicon through-hole (TSV) 64 extends through the substrate 36 and can be in electrical contact with the tap section 52. Of course, other structures can be formed in the semiconductor substrate 36 and on the upper surface 42 of the semiconductor substrate 36, which are not shown herein for simplicity. The bottom-most first dielectric material layer 66 is formed on the first conductive layer 50. The conductive via 68 can be appropriately formed and extends through the first dielectric material layer 66.

[0056] A second conductive layer 70 (indicated by the downwardly and rightwardly oriented black broad hatching) is suitably formed on the first dielectric material layer 66. The second conductive layer 70 includes a tap interconnection section 72, a drain section 74, and a shield section 76. A second dielectric material layer 78 is formed over the tap interconnection section 72, the drain section 74, and the shield section 76 of the second conductive layer 70, and conductive vias 80 may be suitably formed extending through the second dielectric material layer 78.

[0057] A third conductive layer 82 (indicated by the long and narrow hatching directed rightward and upward) is formed on the second dielectric material layer 78. The third conductive layer 82 includes a tap interconnection section 84, a drain section 86, and a shield section 88. A third dielectric material layer 90 is formed over the tap interconnection section 84, the drain section 86, and the shield section 88, and conductive vias 92 may be appropriately formed, extending through the third dielectric material layer 90.

[0058] A fourth conductive layer 94 (indicated by the wide hatching directed to the right and upward) is formed on the third dielectric material layer 90. The gate runner 46 and the main gate tap transmission line 96 extending from the gate runner 46 are formed in the fourth conductive layer 94. Thus, in summary, the bottom tap segment 52, one or more vias 68, the tap interconnect segment 72, one or more vias 80, the tap interconnect segment 84, one or more vias 92, and the main gate tap transmission line 96 create a single tap interconnect 98 extending through the interconnect structure 40 between the gate electrode 54 and the gate runner 46. The drain segment 100 and the shield segment 102 are also formed in the fourth conductive layer. A fourth dielectric material layer 104 is formed over the main gate transmission line 96, the gate runner 46, the gate segment 100, and the shield segment 102 of the fourth conductive layer 94, and the conductive via 106 may be appropriately formed, extending through the fourth dielectric material layer 104.

[0059] A fifth conductive layer 108 (indicated by the long and narrow hatching directed rightward and downward) is formed on the fourth dielectric material layer 104. In this example, the drain runner 44 and the shield runner 48 are formed in the fifth conductive layer 108. Thereafter, a passivation layer 110 may be formed over the drain runner 44 and the shield runner 48. Thus, in summary, the combination of the drain segment 58, the one or more vias 68, the drain segment 74, the one or more vias 80, the drain segment 86, the one or more vias 92, the drain segment 100, and the one or more vias 106 create a drain pillar 112 that electrically interconnects the drain region 60 of the intrinsic active device region 38 to the drain runner 44. Similarly, in general, the combination of shielding segment 76 connected to one or more conductive vias 80, one of shielding segments 88 connected to one or more conductive vias 92, and one of shielding segments 102 connected to one or more conductive vias 106 produces an interconnected shielding structure 114 (two shown) that is electrically connected to one of the shielding channels 48.

[0060] The interconnect shielding structure 114 may be laterally spaced apart from the drain pillar 112 and located on the opposite side of the drain pillar 112. In addition, the interconnect shielding structure 114 is interposed between the drain pillar 112 and the tap interconnect 98. The gate electrode 54 of the active device region 38 is driven by an input signal, which is tapped from the gate runner 46 via the tap interconnect 98. The interconnect shielding structure 114 formed in the interconnect structure 40 may block the electric field between the tap interconnect 98 and the drain pillar 112 to reduce the feedback capacitance generated by the proximity of the tap interconnect 98 to the drain pillar 112.

[0061] Reference now Figure 3 , Figure 3 A side cross-sectional view of a portion of a prior art transistor 34 after encapsulation with an encapsulation material 116 is shown. Typically, transistor dies (e.g., transistor 34) and other active and passive devices are mounted to a substrate (e.g., a carrier, a lead frame, a printed circuit board, etc.) to produce a multifunctional module or system (e.g., a power amplifier). In the example of a power amplifier, the system is tuned before encapsulation because tuning may require access to matching elements of the system. That is, the power amplifier can be tuned to a specific frequency or a narrow band of radio frequencies to obtain optimal performance using matching elements. Therefore, encapsulation material 116 is used for encapsulation after, for example, tuning the power amplifier including transistor 34. Encapsulation material 116 can be a plastic encapsulant such as is commonly used for high-capacity overmolded integrated circuits or other materials that exhibit dielectric properties.

[0062] As previously described, feedback from the drain to the gate degrades the performance of the transistor. Thus, multiple shields (such as interconnect shield structure 114, field plate, ground shield, etc.) exist in the RF transistor between the drain and the gate up to the top metal layer (e.g., in this example, up to the fifth conductive layer 108). However, another cause of performance degradation and detuning comes from the encapsulation material above the top metal layer, sometimes referred to as the plastic encapsulation effect. That is, the encapsulation material causes a significant amount of coupling between the drain and the gate, in addition to some drain-source coupling and gate-drain coupling.

[0063] exist Figure 3 , a first dashed box represents an effective region 118 of one or more existing barriers (such as interconnect barrier structure 114). A second dashed box represents a coupling region 120 due to the presence of encapsulation material 116. This coupling due to encapsulation material 116 may adversely affect the performance of transistor 34 in terms of gain and stability. The embodiments described herein include features added to the interior of the transistor die to reduce the adverse plastic encapsulation effects on die performance. By lifting the interface between the encapsulation material and the transistor away from the coupling electrode (e.g., away from the drain flow path 44 and the gate flow path 46), the features can improve the transistor's immunity to coupling between the drain and the gate caused by the encapsulation material.

[0064] refer to Figure 4 and Figure 5 , Figure 4 shows a side cross-sectional view of a portion of transistor 122 according to an embodiment, and Figure 5 1 is a plan view of a portion of transistor 122. Transistor 122 includes a semiconductor substrate 124 having a device region 126 formed therein. An interconnect structure 128 is formed on a first outer surface 130 of semiconductor substrate 124. Interconnect structure 128 is formed of multiple layers of dielectric materials 132, 134, 136, 138 and multiple layers of conductive materials 140, 142, 146, 148, 150. For simplicity of illustration, transistor 122 is similar to transistor 34 ( Figure 2 ). Thus, transistor 122 includes a drain pillar 152 (one shown) electrically connected to a drain channel 154 and a tap interconnect 156 electrically connected to a gate channel 158. Additionally, in this example, an interconnect shield structure 160 electrically connected to a shield channel 162 is interposed between the tap interconnect 156 / gate channel 158 and the drain pillar 152 / drain channel 154. At least one passivation layer 164 may be deposited over the drain channel 154 and the shield channel 162. The passivation layer 164 may be a single material layer, or the passivation layer 164 may include more than one material layer, such as an oxide layer and a nitride layer.

[0065] Because transistor 122 and Figure 2 34 of the interconnect structure 128, and therefore, additional features of the multiple layers of dielectric materials 132, 134, 136, 138 formed by the multiple layers of conductive materials 140, 142, 146, 148, 150 and extending through the interconnect structure 128 and sections of each feature are not described in detail herein. In addition, to simplify the description, Figure 4 Only a single drain channel 154, two gate channels 158, and two shield channels 162 are shown in the side cross-sectional view of transistor 122. However, it should be understood that transistor 122 can be configured to include, for example, Figure 1 20 in FIG. 1 . Further, for purposes of illustration, transistor 122 provides an example of a configuration including five conductive layers (sometimes referred to as a five metal layer structure) in interconnect structure 128. However, it should be understood that various alternative transistor structures having more or less than five conductive layers may be envisioned.

[0066] Transistor 122 further includes a shielding structure 166 extending above a second outer surface 168 of interconnect structure 128. In the illustrated embodiment, shielding structure 166 is formed on passivation layer 164. Thus, second outer surface 168 is an exposed upper surface of passivation layer 164. Shielding structures 166 (two are shown) are formed of a conductive material. For example, in some configurations, shielding structure 166 can be formed of copper. However, other suitable materials can be used alternatively to form shielding structure 166.

[0067] like Figure 5 , drain runner 154 and gate runner 158 are characterized by a first length 170, and shield structure 166 is characterized by a second length 172. Second length 172 of shield structure 166 is longitudinally aligned with first length 170 of drain runner 154 and gate runner 158. Figure 5 Shown in highly simplified form, without various cover layers, so that drain and gate runners 154, 158, and shield structure 166 are exposed in order to visualize their parallel orientation relative to each other. The ellipsis indicates that drain and gate runners 154, 158, and shield structure 166 can extend any suitable length depending on the specific transistor design. Additional terminations associated with drain and gate runners 154, 158, and shield runners 166 are not specifically shown to indicate that they can terminate in various configurations depending on the specific transistor design.

[0068] The transistor 122 further includes a dielectric protective coating 174 formed on the second outer surface 168 of the interconnect structure 128. In addition, the dielectric protective coating 174 encapsulates the shield structure 166. The dielectric protective coating 174 formed on the second outer surface 168 of the interconnect structure 128 and encapsulating the shield structure 166 is formed on the second outer surface 168 of the interconnect structure 128. Figure 4 164 is shown as generally horizontal or planar. However, in other embodiments, the dielectric protective coating 174 may not be planar, and instead, may follow the topography of the second outer surface 168 and the shielding structure 166. The dielectric protective coating 174 may be a benzocyclobutene (BCB) low-loss dielectric material. However, other suitable materials may be alternatively implemented as the dielectric protective coating 174.

[0069] exist Figure 4 , transistor 122 is additionally shown with a housing material such as encapsulation material 176 covering dielectric protective coating 174. As discussed above, a transistor die (e.g., transistor 122) can be incorporated into a packaged device such as a multi-function module or system. Additionally, the system can be tuned prior to encapsulation so that matching elements of the system can be accessed. Thus, Figure 4 1 shows a case where transistor 122 is incorporated into a system and has been overmolded with encapsulation material 176 after the system is tuned. Shielding structure 166 is formed of a layer of conductive material that is higher than drain runner 154. That is, shielding structure 166 extends above second outer surface 168 of interconnect structure 128 at a height 178 sufficient to reduce parasitic capacitance between drain runner 154 and gate runner 156 caused by plastic coupling through encapsulation material 146. Additionally, in some embodiments, dielectric protective coating 174 elevates encapsulation material 176 farther from drain runner 154 and gate runner 158 to further reduce electrical coupling therebetween.

[0070] The present invention discusses encapsulants such as overmolded plastic encapsulation material 176. However, in alternative embodiments, the housing material can be a cap material with an air cavity. In this configuration, the presence of shielding structure 166 can also reduce the parasitic capacitance between drain flow path 154 and gate flow path 156 in the air cavity package.

[0071] In some embodiments, shielding structure 166 is electrically connected to source node. In the illustrated embodiment, before dielectric protective coating is deposited, conductive via 180 is formed, extending through passivation layer 164. That is, part of passivation layer 164 is not present in shielding flow channel 162 to expose shielding flow channel 162. Conductive via 180 is formed in these openings that pass through passivation layer 164 to electrically connect shielding structure 166 to shielding flow channel 162 and interconnection shielding structure 160. In addition, during interconnection structure 128 manufacture, interconnection shielding structure 160 can be appropriately connected to system ground. Therefore, conductive via 180 can be regarded as source node of shielding structure 166. However, as discussed below, interconnection shielding structure 160 can be electrically connected to ground by other mechanisms.

[0072] refer to Figure 6 and Figure 7 , Figure 6 shows a side cross-sectional view of a portion of transistor 182 according to another embodiment, and Figure 7 FIG. 1 shows a plan view of another portion of transistor 182. Transistor 182 may include transistor 122 ( Figure 4 and 5 ) combined. Thus, transistor 182 may include a semiconductor substrate (not shown) and an interconnect structure 184 (only a portion of which is shown). In the configuration shown here, transistor 182 again includes a drain channel 186 (one shown), a gate channel 188 (two shown), and a shield channel 190 (two shown). A passivation layer 192 is deposited on the drain channel 186, the shield channel 190, and the topmost dielectric layer 194 of the interconnect structure 184. A shielding structure 196 is formed on the passivation layer 192 covering the shielding channel 190. A dielectric protective coating 198 is formed on a second outer surface 200 of the interconnect structure 184. That is, the dielectric protective coating 198 is formed on the passivation layer 192 and encapsulates the shielding structure 196. In addition, an encapsulation layer 202 is formed on the dielectric protective coating 198.

[0073] and transistor 122 ( Figure 4-5 ), conductive vias are not formed through the passivation layer 192 of the transistor 182 to electrically interconnect the shield structure 196 to its corresponding shield channel 190. Figure 7 , shield structure 196 may extend beyond drain end 204 of drain runner 186. Shield structure 196 generally wraps around drain end 204 of drain runner 186 and converges at source node 206. Source node 206 may extend through interconnect structure 184 to connect to, for example, a ground plane (not shown) of transistor 182, such that shield structure 196 is electrically connected to ground. Figure 7 Shown in highly simplified form, excluding various cover layers, drain runner 186 and shield structure 196 are exposed to visualize their parallel orientation relative to each other and to visualize source node 206. The ellipses indicate that drain runner 186 and shield structure 196 may extend any suitable length depending on the particular transistor design.

[0074] Figure 8 2 shows a side cross-sectional view of a portion of a transistor 208 according to another embodiment. The transistor 208 may include transistors 122 ( Figure 4 and 5 ) and transistor 182 ( Figure 6 and 7) combined. Thus, transistor 208 may include a semiconductor substrate (not shown) and an interconnect structure 210 (only a portion of which is shown). In the configuration shown here, transistor 208 includes a drain channel 212 (one is shown) and a gate channel 214 (two are shown). However, the configuration of transistor 208 does not include a shielding channel. A passivation layer 216 is deposited on the drain channel 212 and the topmost dielectric layer 218 of the interconnect structure 210. A shielding structure 220 is formed on the passivation layer 216 and positioned between the drain channel 212 and the gate channel 214. A dielectric protective coating 222 is formed on a second outer surface 224 of the interconnect structure 210. That is, the dielectric protective coating 222 is formed on the passivation layer 216 and encapsulates the shielding structure 220. In addition, an encapsulation material 226 is formed on the dielectric protective coating 222.

[0075] Figure 8 2 is provided to illustrate a configuration that does not include shielding flow paths in the topmost conductive layer 228 of the interconnect structure 210. Instead, the interconnect structure 210 may be formed by a different interconnect shielding structure (not shown) that is not routed to the topmost conductive layer 228. Alternatively, the interconnect structure 210 may not include Figure 4 The multi-segment interconnect shield structure shown in Figure 4 However, the presence of the shield structure 220 and the dielectric protection coating 222 appropriately positioned between and extending over the drain channel 212 and the gate channel 214 can reduce the electrical coupling between the drain channel 212 and the gate channel 214 caused by the encapsulation material 226.

[0076] Fig. 9 A graph 230 is shown showing the generalized difference in parasitic capacitance with respect to frequency between a prior art transistor and a transistor according to one embodiment. Thus, the horizontal axis 232 of the graph 230 represents frequency, and the vertical axis 234 of the graph 230 represents parasitic gate-drain capacitance (C GD ). The graph 230 is presented to show generalized differences in arbitrary units. Therefore, the actual frequency and measured parasitic capacitance are not provided.

[0077] The first curve 236 shown by the dashed line represents the curve that has not yet been filled with the encapsulating material (e.g. Figure 3 The prior art transistor (eg, Figure 2 The parasitic gate-drain capacitance of transistor 34) over the frequency range. Therefore, Fig. 9 The legend for refers to the first curve 236 as no shielding / air, which indicates that the transistor does not have a dielectric protective coating (e.g., Figure 4 Protective coating 174, Figure 6 Protective coating 198 or Figure 8 The shielding structure (e.g., Figure 4 Shielding structure 166, Figure 6 The shielding structure 196 or Figure 8 Shielding structure 220).

[0078] A second curve 238 shown by a double-dashed line represents the use of an encapsulating material (e.g., Figure 3 A prior art transistor (eg, Figure 2 The parasitic gate-drain capacitance of transistor 34) over the frequency range. Therefore, Fig. 9 The legend of refers to the second curve 238 as no shielding / encapsulant, which also indicates that the transistor does not have a shielding / encapsulant positioned between the drain runner and the gate runner, extending over the drain runner and protected by a dielectric protective coating (e.g., Figure 4 Protective coating 174, Figure 6 Protective coating 198 or Figure 8 The shielding structure (e.g., Figure 4 Shielding structure 166, Figure 6 The shielding structure 196 or Figure 8 Shielding structure 220). However, after the system is tuned, the transistor is now encapsulated in an encapsulation material. A second curve 238 relative to the first curve 236 shows a significant increase in parasitic gate-drain capacitance due to the encapsulation material.

[0079] A third curve 240, shown as a solid line, represents the area that has not yet been encapsulated with an encapsulating material (e.g., Figure 4 Encapsulation materials 176, Figure 6 Encapsulation material 202 or Figure 8 A transistor according to one embodiment (eg, Figure 4 Transistor 122, Figure 6 The transistor 182 or Figure 8 The parasitic gate-drain capacitance of transistor 208) over the frequency range. Therefore, Fig. 9 The legend of FIG. 4 designates the third curve 240 as shield / air, which indicates that the transistor includes a dielectric layer positioned between the drain runner and the gate runner, extending over the drain runner, and protected by a dielectric protective coating (e.g., Figure 4 Protective coating 174, Figure 6 Protective coating 198 or Figure 8 The shielding structure (e.g., Figure 4 Shielding structure 166, Figure 6 The shielding structure 196 or Figure 8It can be observed that the presence of the shielding structure and the dielectric protective coating effectively reduces the parasitic gate-drain capacitance before encapsulating the transistor with the encapsulation material.

[0080] A fourth curve 242 shown as a dashed line represents the use of an encapsulating material (e.g., Figure 4 Encapsulation materials 176, Figure 6 Encapsulation material 202 or Figure 8 After encapsulating the transistor according to one embodiment (eg, Figure 4 Transistor 122, Figure 6 The transistor 182 or Figure 8 The parasitic gate-drain capacitance of transistor 208) over the frequency range. Therefore, Fig. 9 The legend of FIG. 4 refers to fourth curve 242 as shielding / encapsulant, which indicates that the transistor includes a shielding structure (eg, Figure 4 Shielding structure 166, Figure 6 The shielding structure 196 or Figure 8 Shield structure 220) and the transistor is now encapsulated in the encapsulation material after the system is tuned. The fourth curve 242 relative to the third curve 240 shows that there is little difference in the parasitic gate-drain capacitance before or after encapsulation in the encapsulation material. However, both examples of the third curve 240 and the fourth curve 242 show a significant increase in parasitic capacitance relative to the first and second curves. It has been observed that after encapsulation with the encapsulation material, any parasitic gate-shield capacitance (C GS ) and the drain-shield capacitance (C DS ) has insignificant changes. Therefore, the presence of a shielding structure positioned between the drain flow channel and the gate flow channel and extending above the drain flow channel can significantly reduce the electrical coupling between the gate and the drain caused by the encapsulation material, thereby improving the gain and stability of the transistor.

[0081] Fig.10 244 according to another embodiment. The packaged device 244 can be any system or any multi-function module including at least one transistor 246 according to the above embodiments and other active and passive discrete components 248 electrically connected via wire bonds, bond pads, etc., which are not shown for simplicity. For example, the packaged device 244 can be a radio frequency integrated circuit die used in a module (e.g., a system-in-package), discrete, and integrated circuit product. The transistor 246 can be any of the transistors described above (e.g., Figure 4 Transistor 122, Figure 6 Transistor 182, Figure 8The transistor 246 may be implemented in a plurality of transistor technologies, such as laterally diffused metal oxide semiconductor (LDMOS), gallium nitride (GaN), gallium arsenide (GaAs), silicon germanium (SiGe), etc.

[0082] In some configurations, transistor 246 and discrete components 248 may be appropriately coupled to mounting surface 250 of substrate 252 and interconnected to each other in a particular design. After being coupled to substrate 252 and interconnected, the components of packaged device 244 may be tuned, calibrated, or otherwise tested. Thereafter, encapsulation material 254 is used to encapsulate transistor 246 and discrete components 248 to form packaged device 244. Since transistor 246 includes a shielding structure above the drain and gate of the transistor and additionally includes a dielectric protective coating, the plastic encapsulation material (e.g., encapsulation material 254) is raised relatively far from the gate flow path and the drain flow path, thereby reducing the electrical coupling between the gate and the drain. This configuration can advantageously enable the design / tuning of an "air" transistor (non-encapsulation material) without redesigning / tuning a "plastic" transistor (encapsulated transistor).

[0083] Fig.11 256 according to another embodiment. Process 256 may be implemented to form a transistor (e.g., Figure 4 A discrete transistor or a packaged system or multi-function module (e.g., Fig.10 The following process flow is described in terms of a single transistor and a packaged device. Those skilled in the art will recognize that a high-volume manufacturing process may require the simultaneous manufacture of multiple transistors and / or multiple packaged devices on a single wafer.

[0084] At block 258, a transistor is provided. That is, a semiconductor substrate having an active device region formed therein and an interconnect structure formed on a surface of the semiconductor substrate may be provided. Again, the interconnect structure may be formed of multiple layers of dielectric material and conductive material, and one or more gate runners and one or more drain runners may be formed in the interconnect structure.

[0085] At block 260, as above, Figure 4-8 As described in detail in the embodiments of the present invention, a shielding structure is formed above the interconnect structure. Thus, the shielding structure can be formed along the length of the gate flow channel and the drain flow channel. In addition, the shielding structure can be formed to extend above the outer surface of the interconnect structure at a height sufficient to reduce the parasitic capacitance between the drain flow channel and the gate flow channel.

[0086] At block 262, a dielectric protective coating is formed over the exposed outer surface of the interconnect structure. The formation of the dielectric protective coating requires encapsulating the shielding structure with the dielectric protective coating. The dielectric protective coating can be a benzocyclobutene (BCB) low-loss dielectric material. However, other suitable materials can be implemented as the dielectric protective coating alternatively.

[0087] The ellipsis following box 262 of manufacturing process 256 indicates that a number of process operations may be performed after forming the dielectric protective coating according to a particular process flow. These operations may require mounting transistors and other discrete devices onto a substrate (e.g., carrier, PCB, lead frame, etc.), forming interconnects, tuning / calibrating / testing the devices, etc.

[0088] Thereafter, block 264 may be performed. At block 264, the system of discrete transistors or functional circuits may be appropriately encapsulated with an encapsulation material. The encapsulation material may be an overmolded plastic (e.g., epoxy) or a dispensed epoxy encapsulant deposited over the transistors and functional circuits. After block 264, the manufacturing process 256 may end. Alternatively, other process operations may be performed after block 264, such as curing the encapsulation material, testing, further packaging, etc., which are not shown for simplicity.

[0089] Embodiments described herein require a transistor having a shielding structure formed over an interconnect structure of the transistor, a packaged device having such a transistor, and a method of manufacturing a transistor including the same. Embodiments of the transistor include: a semiconductor substrate having an active device region formed therein; an interconnect structure on a first surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and conductive material, wherein a drain flow path and a gate flow path are formed in the interconnect structure; and a shielding structure extending over a second surface of the interconnect structure, the shielding structure being positioned between the drain flow path and the gate flow path.

[0090] An embodiment of a packaged device includes: a substrate having a mounting surface; and a transistor coupled to the mounting surface of the substrate. The transistor includes: a semiconductor substrate having an active device region formed therein; an interconnect structure located on a first surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and conductive material, wherein a drain flow path and a gate flow path are formed in the interconnect structure; and a shield structure extending over a second surface of the interconnect structure, the shield structure being positioned between the drain flow path and the gate flow path. The transistor further includes: a dielectric protective coating formed over the second surface of the interconnect structure, the shield structure being encapsulated by the dielectric protective coating; and an encapsulation layer formed to cover the dielectric protective coating.

[0091] An embodiment of a method includes providing a semiconductor substrate having an active device region formed therein and an interconnect structure formed on a first surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and conductive material, wherein a drain runner and a gate runner are formed in the interconnect structure. The method further includes forming a shield structure extending over a second surface of the interconnect structure, the shield structure being positioned between the drain runner and the gate runner.

[0092] Thus, an embodiment may include a plurality of shielding structures formed by a conductive layer, the plurality of shielding structures being strategically positioned above the interconnect structure between the drain flow channel and the gate flow channel of a multi-channel cross-finger transistor. The shielding structure is covered by a dielectric protective coating. Thereafter, the transistor may be encapsulated with an encapsulation material during integrated circuit packaging. The presence of the shielding structure and the dielectric protective coating lifts the encapsulation material away from the gate flow channel and the drain flow channel, thereby reducing the electrical coupling between the gate flow channel and the drain flow channel. By reducing the feedback capacitance between the drain flow channel and the gate flow channel, the integration of the shielding structure can effectively increase the gain of an active device (e.g., a transistor) without degrading stability.

[0093] This disclosure is intended to explain how to shape and use various embodiments according to the present invention, and is not intended to limit the true, expected and reasonable scope and spirit of the present invention. The above description is not intended to be exhaustive or to limit the present invention to the exact form disclosed. In view of the above teachings, modifications or changes are possible. One or more embodiments are selected and described to provide the best description of the principles of the present invention and its practical application and to enable ordinary technicians in the field to utilize the present invention in various embodiments and together with various modifications as suitable for the specific purpose envisioned. When interpreted according to the scope of fairness, legality and reasonable authorization, all such modifications and changes are within the scope of the present invention determined by the attached claims and all equivalents thereof, and the attached claims may be amended during the pendency of this patent application.

Claims

1. A transistor, characterized in that: include: a semiconductor substrate having an active device region formed therein; an interconnect structure on a first surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and conductive material, wherein a gate flow path is formed in the interconnect structure, and a drain flow path and a shield flow path are formed on the interconnect structure, and wherein the drain flow path and the gate flow path are characterized by a first length; as well as a shield structure formed on the shield runner and extending over a second surface of the interconnect structure, the shield structure positioned between the drain runner and the gate runner, the shield structure being characterized by a second length, the second length of the shield structure being longitudinally aligned with the first length of the drain runner and the gate runner, wherein the transistor further comprises a dielectric protective coating formed on the second surface of the interconnect structure, and the shielding structure is encapsulated by the dielectric protective coating, And wherein the transistor further comprises a casing material, the casing material covering the dielectric protective coating.

2. The transistor according to claim 1, characterized in that The shielding structure is formed of a conductive material.

3. The transistor according to claim 1, characterized in that The shield structure is electrically connected to the source node.

4. The transistor according to claim 1, characterized in that The shield structure is configured to extend over the second surface of the interconnect structure at a height sufficient to reduce parasitic capacitance between the drain runner and the gate runner.

5. The transistor according to claim 1, characterized in that The interconnect structure includes at least one passivation layer at the second surface of the interconnect structure, wherein the shielding structure is formed on the at least one passivation layer.

6. A packaging device, characterized in that: include: a substrate having a mounting surface; as well as a transistor coupled to the mounting surface of the substrate, the transistor comprising: a semiconductor substrate having an active device region formed therein; an interconnect structure on a first surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and conductive material, wherein a gate flow path is formed in the interconnect structure, and a drain flow path and a shield flow path are formed on the interconnect structure, and wherein the drain flow path and the gate flow path are characterized by a first length; a shield structure formed on the shield runner and extending over a second surface of the interconnect structure, the shield structure positioned between the drain runner and the gate runner, the shield structure being characterized by a second length, the second length of the shield structure being longitudinally aligned with the first lengths of the drain runner and the gate runner; a dielectric protective coating formed on the second surface of the interconnect structure, the shielding structure being encapsulated by the dielectric protective coating; and A housing material is formed to cover the dielectric protective coating.

7. A method for manufacturing a packaging device, characterized in that: include: Providing a semiconductor substrate having an active device region formed therein and an interconnect structure formed on a first surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and conductive material, wherein a gate flow path is formed in the interconnect structure, and a drain flow path and a shield flow path are formed on the interconnect structure, and wherein the drain flow path and the gate flow path are characterized by a first length; as well as a shield structure formed extending over a second surface of the interconnect structure, the shield structure formed on the shield runner, the shield structure positioned between the drain runner and the gate runner, the shield structure characterized by a second length, the second length of the shield structure being longitudinally aligned with the first length of the drain runner and the gate runner, wherein the method further comprises forming a dielectric protective coating on the second surface of the interconnect structure, the shielding structure being encapsulated by the dielectric protective coating, And wherein the method further comprises forming a shell material layer covering the dielectric protective coating.

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