Power stage with sequential power transistor gate charging

Abstract

A power stage with sequential power transistor gate charging is described herein. A power stage has: a power transistor coupled between a power supply and a switching node; a charge pump coupled between the power supply and a gate of the power transistor; and a gate driver configured to charge the gate of the power transistor until the gate voltage reaches a predefined voltage and further charge the gate of the power transistor from the charge pump.

Description

Technical Field

[0001] The present disclosure relates to sequential switching of power transistors in a power stage using an integrated charge pump. Background Art

[0002] Compared to PMOS power stages, dual NMOS power stages use less power silicon area and provide faster switching. Compared to bootstrapped power stages that require external capacitors, dual NMOS power stages with integrated charge pumps have lower implementation cost and improved system reliability. Using the charge pump to accumulate the full gate charge Q G The same power is required as in the bootstrap power stage. This power is accumulated corresponding to the gate voltage V from an ideal voltage source. GS The gate charge required power is higher than V DD / V GS times. However, exceeding V DD / V GS , the implementation of the charge pump exhibits low power efficiency, which makes the gate charge transfer inefficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A schematic diagram of a power supply including a converter and a power stage according to aspects of the present disclosure is shown.

[0004] Figure 2 Shows Figure 1 Signal diagram of the sequential switching phase of the power stage.

[0005] Figure 3 A schematic diagram of an exemplary implementation of a power supply including a converter and a power stage with a two-stage gate driver according to aspects of the present disclosure is shown.

[0006] Figure 4A and Figure 4B Shown with Figure 3 Signal diagram associated with an exemplary implementation of .

[0007] Figure 5 Shows Figure 1 Schematic diagram of the implementation of the comparator in the high power level detector.

[0008] Figure 6 A flow chart of a method of charging a power transistor in a power stage according to aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0009] The present disclosure relates to a power stage with an integrated charge pump and sequential high-side turn-on using more than one voltage domain. The power transistor is turned on by sequentially charging the gate of the power transistor in at least two stages, the second stage of which includes charging the gate of the power transistor using the charge pump. The result is reduced high-side switching losses and improved power efficiency.

[0010] Figure 1 A schematic diagram of a power supply including a converter 10 and a power stage 100 according to aspects of the present disclosure is shown. For clarity, the high-side power transistor turn-off circuit and the low-side gate driver are not shown.

[0011] The converter 10 is a DC to DC (DC / DC) converter including an inductor L and a capacitor C. The inductor L is coupled at a switching node N LX With output node N OUT The capacitor C is coupled between the output node N OUT and the source voltage node N SS DC / DC converters are known, and for the sake of brevity, a description of the operation of the converter 10 is omitted here.

[0012] The power stage 100 includes a power transistor SW H 110, integrated charge pump 120 and gate driver 130. The power stage 100 is a dual NMOS power stage, with power transistor SW H 110 is a high-side NMOS transistor, and gate driver 130 is a high-side gate driver.

[0013] Power transistor SW H 110 coupled to the power supply V DD With switch node N LX between.

[0014] The charge pump 120 is coupled to the power supply V DD With power transistor SW H 110, and is also coupled to the power supply V DD With the internally generated voltage V DD -V LDO The charge pump voltage V CP It can be, for example, 2.5V (V CP =V CP_OUT -V DD =2.5V). The charge pump 120 is configured to generate a positive output voltage V CP_OUT , positive output voltage V CP_OUT is the power supply voltage V DD Plus the charge pump voltage V CP (i.e., V CP_OUT =V DD+V CP ). Charge pump output voltage V CP_OUT Used to turn on the high-side NMOS power transistor SW H 110.

[0015] The gate driver 130 includes an output node switch SW1, a power switch SW2, a charge pump switch SW3, and a gate voltage detector 132. The gate driver 130 is configured to receive a command signal CMD_HS, which may be, for example, a pulse width modulation (PWM) signal.

[0016] The output node switch SW1 is coupled to the power transistor SW H The gate of 110 and the output node N OUT The power switch SW2 is coupled between the power transistor SW H 110 gate and power supply V DD The charge pump switch SW3 is coupled between the power transistor SW H between the gate of 110 and the output of the charge pump 120 .

[0017] The gate voltage detector 132 includes a high detector DET_H and a low detector DET_L configured to detect the gate voltage of the power transistor SW. H The voltage at the gate of 110 is used to determine when to switch the switches SW1, SW2, SW3. The low detector DET_L is configured to switch the output node switch SW1. The high detector DET_H is configured to switch the power switch SW2 and the charge pump switch SW3. The gate detector 132 is ultra-fast, for example, less than 1ns. The low detector DET_L needs to have a first threshold voltage V TH1 The fast comparator, the first threshold voltage V TH1 Reference output voltage V OUT The high detector DET_H needs to have a second threshold voltage V TH2 The ultra-fast comparator, the second threshold voltage V TH2 Reference supply voltage V DD The comparator can monitor the power transistor gate voltage, source voltage, or a related voltage, but monitoring the gate is more accurate.

[0018] Figure 2 Shows Figure 1 A signal diagram 200 of a sequential switching phase of the power stage 100 is shown.

[0019] As an overview, in order to turn on the power transistor SW H 110, there is a sequential switching phase during which the power transistor gates are charged by coupling to the corresponding voltage domains:

[0020] Switching phase Q α : Output voltage V OUT , which is generated by a high-efficiency DC / DC converter 10;

[0021] Switching phase Q β : Power supply voltage V DD ;as well as

[0022] Switching phase Q γ : Charge pump voltage V CP_OUT , which is generated by the charge pump 120 of limited efficiency.

[0023] There are at least two switching phases, one of which uses the charge pump voltage V CP_OUT The switching phase Q γ Alternatively, there may be three switching phases, or even additional switching phases.

[0024] Sequential switching and dedicated high-performance detectors (low detector DET_L and high detector DET_H) reduce the turn-on power transistor SW H 110 The power required. The power transistor gate voltage V G The establishment of N is faster. Moreover, the switching node N LX The rising speed increases, and as a result, the switching node N LX The switching speed is reduced, resulting in better power efficiency at high currents.

[0025] Switching phase Q α : Using the output voltage V OUT Charging the gate of the power transistor

[0026] In the switching phase Q α During this period, the gate driver 130 is configured to utilize the output voltage V OUT For power transistor SW H 110 gate charge, as the initial charge in this example, until the gate voltage V G Reaching output voltage V OUT Subtract the first threshold voltage V TH1 .

[0027] More specifically, the power transistor SW H The conduction phase of 110 may start when the control signal CMD_HS goes high. In response to receiving the high command signal CMD_HS, the low detector DET_L of the gate voltage detector 132 is configured to transmit the signal EN_V OUT To close the output node switch SW1, the output node N OUT With power transistor SW H The gate of 110 is connected. The output voltage V obtained from the high efficiency DC / DC converter 10 OUTTo the gate capacitor C g Transmit power. Output voltage V OUT applied via the output node switch SW1 until the gate voltage V G Reaching output voltage V OUT Subtract the first threshold voltage V TH1 Typically, this time corresponds to the power transistor SW H 110 of the Miller Terrace.

[0028] The switching phase Q α The power required can be estimated as:

[0029] P HS_VOUT =V OUT ΔQ G_α ·f SW (Equation 1)

[0030] Assuming that the power efficiency of the converter 10 is 1, fsw is the clock switching frequency, and the output voltage V OUT has a low value, such as 2.5V. Equation 1 shows that the gate charge during the switching phase Q α Parts are delivered with high efficiency.

[0031] Switching phase Q β : Using the power supply voltage V DD Charging the gate of the power transistor

[0032] In the switching phase Q β During this period, the gate driver 130 is configured to receive power from the power supply V DD For power transistor SW H 110 gate charge until the gate voltage V G Reach a predefined voltage. The predefined voltage is equal to the power supply V DD The voltage minus the second threshold voltage V TH2 .

[0033] More specifically, when the above Q α The low detector DET_L detects the gate voltage V G reaches a predefined voltage, that is, the output voltage V OUT Subtract the first threshold voltage V TH1 When the output node switch SW1 is turned off, the output node N OUT (Output voltage V OUT ) and power transistor SW H The gate of 110 is disconnected. Then, the low detector DET_L hands over the control to the high detector DET_H by transmitting the enable signal EN. Then, the gate voltage detector 132 is configured to transmit the signal EN_V DD The power switch SW2 is immediately turned on to switch the power supply V DD With power transistor SWH The gate of 110 is connected. The power switch SW2 remains valid until the power transistor SW H The gate voltage is 110 V G reaches a predefined voltage, i.e., the power supply voltage V DD Subtract the second threshold voltage V TH2 .

[0034] In this switching phase, Q β During this period, directly from the power supply V DD This allows the charge pump 120 to have no load and thus for the switching phase Q γ The start is fully precharged. From the power supply V DD The power required can be estimated as:

[0035] P HS_VDD =V DD ΔQ G_β ·f SW (Equation 2)

[0036] Advantageously, the power P HS_VDD The switching phase Q β leads to faster charging because the supply voltage V DD With large current I VDD , and is responsible for switching node N LX rise time.

[0037] Switching Phase Q γ : Using the charge pump voltage V CP_OUT Charging the gate of the power transistor

[0038] In the switching phase Q γ During this period, the gate driver 130 is configured to further receive power from the charge pump 120 to the power transistor SW H 110, the gate is charged until the power transistor SW H 110 to achieve low on-resistance.

[0039] More specifically, in response to the switching phase Q β The gate voltage V G Reach power supply V DD The voltage minus the second threshold voltage V TH2 , start switching phase Q γ The gate voltage detector 132 turns off the power switch SW2 and transmits a signal EN_CP to close the charge pump switch SW3, thereby turning on the power supply V DD With power transistor SW H The gate of 110 is disconnected, and the charge pump 120 is connected to the power transistor SW H 110 gate connection. Charge pump output voltage V CP_OUTConnect to power transistor SW H 110, and the gate voltage V G Rising to the charge pump output voltage V CP_OUT , the charge pump output voltage V CP_OUT is the power supply voltage V DD Plus the charge pump voltage V CP (V CP_OUT =V DD +V CP ). The charge pump switch SW3 remains closed, but opens when the control signal CMD_HS goes low.

[0040] From the power supply voltage V DD The power required can be estimated as:

[0041]

[0042] The charge pump 120 is fully utilized until the end of the charging cycle, when the clock frequency can be reduced. Since only a portion of the power of the transistor gate charge comes from the charge pump 120, the design of the charge pump 120 can be relaxed, ie, its high frequency switching power can be reduced.

[0043] Figure 3 A schematic diagram of an exemplary implementation of a power supply including a converter 10 and a power stage 300 having a two-stage gate driver 330 according to aspects of the present disclosure is shown.

[0044] The power stage 300 includes a low voltage transistor Q LV_P and Q LV_N , low voltage transistor Q LV_P and Q LV_N is effectively used (e.g., V GS_max =V CP ). The power stage 300 also includes a high voltage transistor Q HV_P , and the gate voltage of G_HS is connected to the high voltage transistor Q HV_P Connect to the drive.

[0045] refer to Figure 4A and Figure 4B Describing the operation of the power stage 300, Figure 4A and Figure 4B Signal diagrams 400A and 400B are shown, respectively.

[0046] When the high-side gate driver 330 is activated, the gate voltage G_HV is set to the power supply voltage V DD Subtract the internally generated voltage V LDO (For example, 24V-2.5V=21.5V). The voltage HS_DRV_G is set to the charge pump output voltage V CP_OUTThis means that the high voltage transistor Q HV_P and low voltage transistor Q LV_N turns on, and the high voltage transistor Q HV_P The source is connected to the power supply V DD .

[0047] The gate voltage G_HS increases until it reaches the detector threshold (i.e., V DD -V TH2 ). At this time, the voltage HS_DRV_G is pulled down to V DD A short time (e.g., 2ns) is used while the gate voltage G_HV remains low. Even if the charge pump output voltage V CP_OUT This also allows the low voltage transistor Q to be reduced suddenly due to the large pulse current. LV_P Here, the power NMOS gate capacitor C g The high value of acts as a buffer and keeps the gate voltage G_HS constant. After this short gating pulse, the low voltage transistor Q LV_P The gate is connected to the power supply V DD , and the charge pump continues to increase its output voltage V CP_OUT As a result, the gate voltage G_HS increases towards its supply voltage V DD The final value of the charge pump voltage V CP Fast rise time, allowing switching node N to LX Fast rise time.

[0048] Figure 5 Shows Figure 1 Schematic diagram of the implementation of a comparator in the high detector DET_H of the power stage 100.

[0049] To provide smooth switching between the power switch SW2 and the charge pump switch SW3, the high-side gate voltage detector 132 performs detection at a high speed, typically less than 1 ns. Figure 5 In the example shown, the high voltage transistor Q1 is connected to the high side power transistor gate G_HS.

[0050] When the enable signal EN is high, the gate of the high voltage transistor Q1 is set to the power supply voltage V DD Subtract the internally generated voltage V LDO (V DD -V LDO ), and node A is connected to the same voltage via transistor Q3. To activate comparator CMP, the current raises the voltage at node A to the switching point of output buffer B0. When gate voltage G_HS exceeds supply voltage V DD Subtract the internally generated voltage V LDO (VDD -V LDO ) exceeds the threshold voltage V of transistor Q1 THP This happens when , at this point, transistor Q1 turns on and increases the voltage at node A.

[0051] The comparator CMP is then disabled, which allows the gate to reach the supply voltage V DD This protects Q1’s gate-source voltage, V GS When the gate voltage G_HS exceeds the power supply voltage V DD When the gate voltage G_HS is close to the supply voltage V DD When , transistor Q2 is turned off.

[0052] The high detector DET_H uses a single transistor to detect the high-side detector threshold V TH2 In addition to its fast response, this detector DET_H is advantageous in its simple implementation with zero bias current. The generation of the signal is essential for sequential switching. This allows for optimal timing of the high-side NMOS gate voltage switching and, therefore, results in a smooth and fast rise to the final charge pump output voltage V CP_OUT .

[0053] Figure 6 FIG. 1 shows a schematic diagram of a power transistor SW in a power stage 100 according to various aspects of the present disclosure. H Flowchart 600 of a method of charging 110 .

[0054] In step 610, the output voltage V of the converter 10 is used to OUT To couple the power supply V DD With switch node N LX The power transistor SW between H 110 gate charge.

[0055] In step 620, the power transistor SW H The gate of 110 is charged until the gate voltage reaches a predefined voltage.

[0056] In step 630, further from the power supply V coupled to DD With power transistor SW H The charge pump 120 between the gates of the power transistor SW H 110 gate charge.

[0057] As described above, there are at least two switching phases, one of which is in step 630 using the charge pump voltage VCP_OUT Alternatively, there may be three switching phases, or even additional switching phases.

[0058] The dual NMOS power stage 100 described herein is an improvement over the bootstrap power stage, which requires external bootstrap capacitors, additional pins on the chip, and associated printed circuit board (PCB) routing. These components of the bootstrap power stage require additional cost and circuit area. Therefore, the dual NMOS power stage 100 results in significant cost reduction.

[0059] The sequential phase switching described herein effectively uses the voltage already available in the dual NMOS power stage 100. As a result, the high-side power transistor switching losses are significantly reduced (e.g., >50%). CP_OUT Switching phase Q γ The high-side power transistor gate voltage V G The gate voltage V G The slow settling of is one of the reasons why the charge pump concept was not adopted earlier.

[0060] Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" merely means as an example, rather than the best or optimal. Therefore, the present disclosure is intended to cover alternatives, modifications, and equivalents that may be included within the scope of the present disclosure.

[0061] Although specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. The present disclosure is intended to cover any adaptation or variation of the specific embodiments discussed herein.

Claims

1. A power stage comprising: a power transistor coupled between the power source and the switching node; a charge pump coupled between the power supply and the gate of the power transistor; as well as The gate driver is configured to sequentially execute the following: charging the gate of the power transistor by delivering power to a gate capacitor of the power transistor using an output voltage of the converter as an initial charge in response to a control signal until the gate voltage reaches the output voltage minus a threshold voltage; charging the gate of the power transistor from the power supply until the gate voltage reaches a predefined voltage; and The gate of the power transistor is further charged from the charge pump.

2. The power stage of claim 1 , wherein the gate driver is further configured to: The gate of the power transistor is charged from the charge pump until the power transistor reaches a low on-resistance. 3 . The power stage of claim 1 , wherein the gate driver is configured to charge the gate of the power transistor from the power supply until the gate voltage reaches the predefined voltage. 4 . The power stage of claim 3 , wherein the predefined voltage is equal to a voltage of the power supply minus the threshold voltage. The power stage of claim 3 , wherein the converter is coupled to the switching node.

6. The power stage of claim 3, wherein the gate driver comprises: a power switch coupled between the gate of the power transistor and the power supply; a charge pump switch coupled between the gate of the power transistor and the charge pump; as well as The gate voltage detector is configured as: closing the power switch to connect the power source to the gate of the power transistor; as well as In response to detecting that the gate voltage reaches the voltage of the power supply minus a threshold voltage, the power switch is opened and the charge pump switch is closed to disconnect the power supply from the gate of the power transistor and connect the charge pump to the gate of the power transistor.

7. The power stage of claim 1 , wherein the gate driver is further configured to: The charge pump is charged while the gate of the power transistor is charged until the gate voltage reaches the predefined voltage.

8. The power stage of claim 1, wherein the converter is coupled to the switching node.

9. The power stage of claim 1 being a dual NMOS power stage and wherein the power transistor is a high-side NMOS transistor and the gate driver is a high-side gate driver.

10. A power stage comprising: a power transistor coupled between the power source and the switching node; a charge pump coupled between the power supply and the gate of the power transistor; as well as The gate driver is configured to sequentially execute the following: charging the gate of the power transistor by transferring power to a gate capacitor of the power transistor using an output voltage of a converter as an initial charge; charging the gate of the power transistor from the power supply until the gate voltage reaches a predefined voltage; as well as The gate of the power transistor is further charged from the charge pump, wherein the gate driver comprises: an output node switch coupled between the gate of the power transistor and an output node; a power switch coupled between the gate of the power transistor and the power supply; a charge pump switch coupled between the gate of the power transistor and the charge pump; and The gate voltage detector is configured as: In response to receiving a command signal, closing the output node switch to connect the output node to the gate of the power transistor; in response to detecting that the gate voltage reaches the output voltage minus a first threshold voltage, opening the output node switch and closing the power switch to disconnect the output node from the gate of the power transistor and connect the power supply to the gate of the power transistor; and In response to detecting that the gate voltage reaches the predefined voltage, which is the voltage of the power supply minus a second threshold voltage, the power switch is opened and the charge pump switch is closed to disconnect the power supply from the gate of the power transistor and connect the charge pump to the gate of the power transistor.

11. A method for charging a power transistor in a power stage, the method sequentially comprising the following steps: charging a gate of the power transistor by delivering power to a gate capacitor of the power transistor using an output voltage generated by the converter as an initial charge and in response to a control signal until the gate voltage reaches the output voltage minus a threshold voltage; charging the gate of the power transistor coupled between the power supply and a switching node from a power supply until the gate voltage reaches a predefined voltage; as well as The gate of the power transistor is further charged from a charge pump coupled between the power supply and the gate of the power transistor. 12 . The method of claim 11 , wherein the gate of the power transistor is charged from the charge pump until the power transistor reaches a low on-resistance.

13. The method of claim 11 , wherein charging the gate of the power transistor until the gate voltage reaches the predefined voltage comprises: The gate of the power transistor is charged from the power supply. The method of claim 13 , wherein the predefined voltage is equal to a voltage of the power supply minus the threshold voltage. The method of claim 13 , wherein the converter is coupled to the switching node.

16. The method according to claim 13, further comprising: closing a power switch to connect the power source to the gate of the power transistor; as well as In response to detecting that the gate voltage reaches the voltage of the power supply minus a threshold voltage, the power switch is opened and a charge pump switch is closed to disconnect the power supply from the gate of the power transistor and connect the charge pump to the gate of the power transistor.

17. The method according to claim 13, further comprising: The charge pump is charged while the gate of the power transistor is charged until the gate voltage reaches the predefined voltage.

18. The method of claim 11, wherein the power stage is a dual NMOS power stage, the power transistor is a high-side NMOS transistor, and the gate driver is a high-side gate driver.

19. A method for charging a power transistor in a power stage, the method sequentially comprising the following steps: In response to receiving the command signal, closing the output node switch to connect the gate of the power transistor to the output node; charging the gate of the power transistor by transferring power to a gate capacitor of the power transistor using an output voltage at the output node of the converter as an initial charge in response to a control signal, in response to detecting that the gate voltage reaches the output voltage minus a first threshold voltage, opening the output node switch and closing a power switch to disconnect the output node from the gate of the power transistor and connect a power source to the gate of the power transistor; charging the gate of the power transistor coupled between the power supply and a switching node from the power supply until the gate voltage reaches a predefined voltage; as well as In response to detecting that the gate voltage reaches the predefined voltage, the predefined voltage being the power supply minus a second threshold voltage, opening the power switch and closing the charge pump switch to disconnect the power supply from the gate of the power transistor and connect a charge pump to the gate of the power transistor; as well as The gate of the power transistor is also charged from the charge pump coupled between the power supply and the gate of the power transistor.

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