Semiconductor devices and semiconductor systems

Abstract

The present invention relates to a semiconductor device, comprising: a monitoring circuit, which receives a first power signal and generates a flag signal by monitoring a second power signal provided to a monitored circuit; a watchdog circuit, which is arranged in the monitoring circuit, receives the first power signal and generates a watchdog signal; and a comparison circuit, which receives the flag signal and the watchdog signal and generates a first signal having a first level in an abnormal state and a second level in a normal state. The second level is different from the first level. The watchdog circuit sets the watchdog signal to a third level when the level of the first power signal is lower than a first reference level. When the watchdog signal has the third level, the comparison circuit allows the first signal to have the first level without considering the level of the flag signal. A semiconductor system is also provided.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2018-0119646 filed on October 8, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a monitoring circuit, an operating method of the monitoring circuit, and a semiconductor system including the same. Background Art

[0003] Electronic devices generally include multiple circuits. If the signals supplied to the multiple circuits of the electronic device are manipulated, then security information contained in the multiple circuits may be disclosed or leaked. For example, if the voltage supplied to a specific circuit is significantly reduced due to, for example, a malicious attack from the outside, then the security of the specific circuit may be weakened or compromised, thereby enabling unauthorized access to the specific circuit.

[0004] In order to ensure and / or guarantee the safety and reliability of the plurality of circuits, the signal applied to each of the plurality of circuits is usually monitored. However, if a device for monitoring the signal applied to each of the plurality of circuits is attacked maliciously from the outside, the device may not be able to correctly monitor the signal applied to each of the plurality of circuits, and thus may not be able to ensure and / or guarantee the safety and reliability of the plurality of circuits. Summary of the invention

[0005] Embodiments of the inventive concept provide a semiconductor device in which a watchdog circuit is placed in a monitoring circuit to ensure operation and safety reliability of a monitored circuit and a semiconductor system including the same.

[0006] Embodiments of the inventive concept also provide a semiconductor device capable of detecting a situation in which the operation and safety reliability of a monitoring circuit are degraded using a watchdog circuit, and a semiconductor system including the semiconductor device.

[0007] An embodiment of the inventive concept provides a semiconductor device, comprising: a monitoring circuit configured to receive a first power signal and generate a flag signal by monitoring a second power signal provided to a monitored circuit; a watchdog circuit, disposed in the monitoring circuit, configured to receive the first power signal and generate a watchdog signal; and a comparison circuit configured to receive the flag signal and the watchdog signal and generate a first signal having a first level in an abnormal state and a second level in a normal state. The second level is different from the first level. The watchdog circuit is configured to set the watchdog signal to a third level when the level of the first power signal is lower than a first reference level. When the watchdog signal has the third level, the comparison circuit is configured to allow the first signal to have the first level without considering the level of the flag signal.

[0008] An embodiment of the inventive concept also provides a semiconductor system, comprising: a processor, receiving a first power signal and a second power signal; and a monitored circuit, disposed in the processor and driven by the second power signal. The processor is configured to monitor the first power signal and generate a watchdog signal having a first level when the level of the first power signal is lower than a first reference level, monitor the second power signal and generate a flag signal, and generate an interrupt signal when the watchdog signal has the first level without considering the level of the flag signal.

[0009] Embodiments of the inventive concept further provide a semiconductor system, comprising: a semiconductor device receiving a first power signal; and a monitored circuit receiving a second power signal. The semiconductor device comprises: a monitoring circuit driven by the first power signal and configured to generate a flag signal by monitoring the second power signal; a watchdog circuit configured to generate a watchdog signal having a first level when the level of the first power signal is lower than a first reference level; and a comparison circuit configured to determine that a current state is an abnormal state without considering the level of the flag signal when the watchdog signal has the first level.

[0010] An embodiment of the inventive concept also provides an operating method of a semiconductor device, comprising: generating a flag signal by a monitoring circuit based on a first power signal provided to a monitored circuit; setting the watchdog signal to a first level by a watchdog circuit when a level of a second power signal provided to the monitoring circuit is lower than a first reference level; setting the watchdog signal to a second level by the watchdog circuit when a level of the second power signal is higher than or the same as the first reference level; and receiving the flag signal and the watchdog signal by a comparison circuit and generating a first signal having a third level in an abnormal state and a fourth level in a normal state by the comparison circuit. When the watchdog signal has the first level, the first signal has a third level regardless of the level of the flag signal.

[0011] An embodiment of the inventive concept provides a semiconductor system, comprising: a power management integrated circuit configured to receive a first power signal and a second power signal; an application processor configured to receive power from the power management integrated circuit; and a monitored circuit, which is disposed in the power management integrated circuit and driven by the second power signal. The power management integrated circuit is configured to monitor the first power signal and generate a watchdog signal having a first level when the level of the first power signal is lower than a first reference level, monitor the second power signal and generate a flag signal, and generate an interrupt signal without considering the level of the flag signal when the watchdog signal has the first level.

[0012] The embodiments of the inventive concept should not be limited to what is described above. The above and other embodiments of the inventive concept will become more apparent to those of ordinary skill in the art to which the inventive concept belongs by referring to the detailed description of the present disclosure provided below. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above-mentioned embodiments as well as other embodiments and features of the inventive concept will become more apparent in view of the following detailed description with reference to the accompanying drawings, in which:

[0014] Figure 1 A block diagram of a semiconductor system according to an embodiment of the inventive concept is shown.

[0015] Figure 2 Show Figure 1 Block diagram of the processor.

[0016] Figure 3 A block diagram of a monitoring device of a semiconductor device as an embodiment according to the inventive concept is shown.

[0017] Figure 4 Show Figure 3 Flowchart of the operation of the monitoring device.

[0018] Figure 5 Show instructions Figure 3 A diagram of the operation of the monitoring device.

[0019] Figure 6 Show instructions Figure 3 A graph of the operation of the monitoring device.

[0020] Figure 7 A block diagram of a semiconductor system according to an embodiment of the inventive concept is shown.

[0021] Figure 8 Show Figure 7A block diagram of a processor and a power management integrated circuit (PMIC).

[0022] Fig. 9 A schematic diagram illustrating a semiconductor system according to an embodiment of the inventive concept.

[0023] Fig.10 Show Fig. 9 Block diagram of an electronic device.

[0024] Fig.11 Show Fig.10 A block diagram of a processor for an automobile.

[0025] Description of Figure Numbers

[0026] 10, 20, 30: semiconductor systems;

[0027] 110: processor;

[0028] 120, 220: Power management integrated circuit;

[0029] 130: Random access memory;

[0030] 140: non-volatile memory;

[0031] 150: bus;

[0032] 160: Camera;

[0033] 170: Display;

[0034] 210: processor;

[0035] 310: Electronic devices;

[0036] 311: Automotive processors;

[0037] 313: communication module;

[0038] 315: memory;

[0039] 320: output device;

[0040] 330: image capturing device;

[0041] 340: Power supply;

[0042] 1010: central processing unit;

[0043] 1020: multimedia system;

[0044] 1030: a multi-level interconnection bus;

[0045] 1040: memory system;

[0046] 1050: peripheral circuit;

[0047] 1060: Monitoring device;

[0048] 1061: monitoring circuit;

[0049] 1062: watchdog circuit;

[0050] 1063: comparison circuit;

[0051] 1065: controller;

[0052] 1070: monitored circuit;

[0053] CS: Third signal;

[0054] FS: marking signal;

[0055] G1: first curve;

[0056] G2: second curve;

[0057] G3: The third curve;

[0058] G4: fourth curve;

[0059] G5: Fifth curve;

[0060] IS: first signal;

[0061] OS: output signal;

[0062] RL1: first reference level;

[0063] RL2: second reference level;

[0064] SS1: first power supply signal;

[0065] SS2: second power supply signal;

[0066] S100, S201, S203, S205, S207, S301, S303, S305, S307, S401, S403, S405, S407: steps;

[0067] t0, t1, t2, t3, t4, t5, t6: time period;

[0068] TS: Second signal;

[0069] Vdd: driving voltage;

[0070] VID: voltage code;

[0071] WS: Watchdog signal. DETAILED DESCRIPTION

[0072] As is conventional in the field of the inventive concept, embodiments may be described and illustrated with respect to blocks that perform one or more functions described. These blocks, which may be referred to herein as units or modules, are physically implemented by analog circuits and / or digital circuits, such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and may be driven by firmware and / or software as appropriate. For example, the circuit may be implemented in one or more semiconductor chips or on substrate supports such as printed circuit boards. The circuits constituting the blocks may be implemented by dedicated hardware or by a processor (e.g., one or more programmed microprocessors and associated circuits) or by a combination of dedicated hardware to perform some functions of the blocks and processors to perform other functions of the blocks. Each block of the embodiment may be physically separated into two or more than two interactive and discrete blocks without departing from the scope of the inventive concept. Similarly, the blocks of the embodiment may be physically combined into more complex blocks without departing from the scope of the inventive concept. Figure 1 A block diagram of a semiconductor system 10 according to some embodiments of the inventive concept is shown. Figure 2 Show Figure 1 A block diagram of processor 110 is shown.

[0073] See also Figure 1 The semiconductor system 10 includes a processor 110, a power management integrated circuit (PMIC) 120, a random access memory (RAM) 130, a nonvolatile memory (NVM) 140, a bus 150, a camera 160, and a display 170, but the present invention is not limited thereto. For example, the semiconductor system 10 may include Figure 1 The components shown in the figure may be used Figure 1 Various modifications are made to the structure of the semiconductor system 10 with respect to the elements shown in FIG.

[0074] The processor 110 includes at least one of a central processing unit (CPU), a graphic processing unit (GPU), an application processor (AP), and a communication processor (CP).

[0075] In some embodiments, processor 110 may be an AP implemented, for example, in a mobile device.

[0076] The PMIC 120 may provide operating voltages to various components of the semiconductor system 10 (including the processor 110) and perform power management on these components. For example, the PMIC 120 may provide a driving voltage (e.g., Figure 3 The PMIC 120 may provide a first power signal SS1 and a second power signal SS2 of the processor 110 and may control the driving voltage as needed. For example, the PMIC 120 may reduce the driving voltage to ensure the operation duration of the processor 110 or may stop providing the driving voltage to save power. In another example, the PMIC 120 may increase the driving voltage to ensure the performance of the processor 110.

[0077] The RAM 130 may load (ie, store) therein software executable by the processor 110 .

[0078] In some embodiments, the RAM 130 may include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), etc., but is not limited thereto.

[0079] The nonvolatile memory 140 may store various data, including data processed by the processor 110. In some embodiments, the nonvolatile memory 140 may include a flash memory, but is not limited thereto.

[0080] In some embodiments, the semiconductor system 10 may be a smart phone, and may include a camera 160 and a display 170 .

[0081] The processor 110 , the PMIC 120 , the RAM 130 , the nonvolatile memory 140 , the camera 160 , and the display 170 are electrically connected to the bus 150 , and thus may exchange data with one another.

[0082] See also Figure 2 The processor 110 of the semiconductor system 10 includes a central processing unit 1010, a multimedia system 1020, a multi-level interconnection bus 1030, a memory system 1040, a peripheral circuit 1050, a monitoring device 1060, and a monitored circuit 1070.

[0083] The central processing unit 1010 may perform operations required to drive the semiconductor system 10. In some embodiments, the central processing unit 1010 may be implemented as a multi-core environment including a plurality of cores.

[0084] The multimedia system 1020 may be used to perform various multimedia functions in the semiconductor system 10. The multimedia system 1020 may include, for example, a three-dimensional (3D) engine module, a video codec, a display system, a camera system, a post-processor, and the like.

[0085] The central processing unit 1010 , the multimedia system 1020 , the memory system 1040 , the peripheral circuit 1050 , the monitoring device 1060 , and the monitored circuit 1070 may communicate data with each other via a multi-level interconnection bus 1030 .

[0086] In some embodiments, the multi-level interconnection bus 1030 may have a multi-level structure. Specifically, a multi-layer advanced high-performance bus (ML-AHB) or a multi-layer advanced extensible interface (ML-AXI) may be used as the multi-level interconnection bus 1030, but the multi-level interconnection bus 1030 is not limited thereto.

[0087] The memory system 1040 may be coupled to an external memory (eg, DRAM) to provide an environment for high-speed operation of the processor 110. In some embodiments, the memory system 1040 may include a separate controller (eg, DRAM controller) for controlling the external memory (eg, DRAM).

[0088] The peripheral circuit 1050 may provide an environment required by the semiconductor system 10 to be connected to an external device such as a main board. Therefore, the peripheral circuit 1050 may have various interfaces compatible with the external device connected to the semiconductor system 10.

[0089] The monitoring device 1060 may be a semiconductor device according to some embodiments of the inventive concept. The monitoring device 1060 may monitor a signal (eg, Figure 3 The second power signal SS2).

[0090] The monitored circuit 1070 may be, for example, a one-time programmable memory (OTP). The monitored circuit 1070 may, for example, perform operations associated with the safety of the semiconductor system 10, but is not limited thereto. Alternatively, the monitored circuit 1070 may be a circuit provided in the processor 110 to perform any operation.

[0091] In the following we will refer to Figures 3 to 6A semiconductor device and its operation according to an embodiment of the inventive concept are described. For the sake of clarity, descriptions of elements or features that have been described above will be omitted.

[0092] Figure 3 A block diagram of a monitoring device 1060 of a semiconductor device according to an embodiment of the inventive concept is shown. Figure 4 A flow chart illustrating the operation of monitoring device 1060 . Figure 5 A diagram illustrating the operation of monitoring device 1060 is shown. Figure 6 A graph illustrating the operation of monitoring device 1060 is shown.

[0093] See also Figure 3 The monitoring device 1060 (which is a semiconductor device according to some embodiments of the inventive concept) includes a monitoring circuit 1061, a watchdog circuit 1062, and a comparison circuit 1063. The semiconductor system according to an embodiment of the inventive concept (ie, Figure 1 and Figure 2 The semiconductor system 10) may include a monitored circuit 1070 and a controller 1065.

[0094] The monitoring circuit 1061 may be provided in the monitoring device 1060. A first power signal SS1 and a second power signal SS2 may be provided to the monitoring circuit 1061. The monitoring circuit 1061 may be driven by the first power signal SS1, for example. The first power signal SS1 may be, for example, a driving voltage of the monitoring circuit 1061. The monitoring circuit 1061 may monitor the second power signal SS2. The second power signal SS2 may be a signal provided to the monitored circuit 1070. The second power signal SS2 may be, for example, a driving voltage of the monitored circuit 1070.

[0095] The monitoring circuit 1061 can monitor the second power signal SS2 in real time when the first power signal SS1 and the second power signal SS2 (which are driving voltages) are respectively provided to the monitoring circuit 1061 and the monitored circuit 1070. The monitoring circuit 1061 can generate a flag signal FS due to the monitoring of the second power signal SS2.

[0096] The watchdog circuit 1062 may be disposed in the monitoring circuit 1061. The first power signal SS1 may be provided to the watchdog circuit 1062. The watchdog circuit 1062 may monitor the first power signal SS1.

[0097] The watchdog circuit 1062 may monitor the first power signal SS1 in real time while providing the first power signal SS1, which is a driving voltage, to the monitoring circuit 1061. The watchdog circuit 1062 may generate a watchdog signal WS due to the monitoring of the first power signal SS1.

[0098] Although generally depicted as being in the monitoring device 1060, the comparison circuit 1063 may be disposed in the monitoring circuit 1061. The comparison circuit 1063 may receive the flag signal FS and the watchdog signal WS. The comparison circuit 1063 compares the flag signal FS and the watchdog signal WS to determine whether the current state is a normal state or an abnormal state.

[0099] The comparison circuit 1063 can generate a first signal IS, a second signal TS and a third signal CS.

[0100] In some embodiments, in an abnormal state, the comparison circuit 1063 may set at least one of the first signal IS, the second signal TS, and the third signal CS to a specific level. In a normal state, the comparison circuit 1063 may set at least one of the first signal IS, the second signal TS, and the third signal CS to a level different from its level in the abnormal state. In other words, the comparison circuit 1063 may selectively change the levels of the first signal IS, the second signal TS, and the third signal CS. For example, when the first signal IS needs to be activated when the abnormal state is established (or detected) while maintaining the normal state, the comparison circuit 1063 may activate the first signal IS by setting the first signal IS to a level different from its level in the normal state. In this example, the levels of the second signal TS and the third signal CS may not be changed, so that the second signal TS and the third signal CS may be maintained as inactive. The normal state and the abnormal state will be described in detail later.

[0101] In some embodiments, in an abnormal state, the comparison circuit 1063 may set the first signal IS to a specific level. In a normal state, the comparison circuit 1063 may set the first signal IS to a level different from its level in the abnormal state. The comparison circuit 1063 may activate at least one of the second signal TS and the third signal CS based on the level of the first signal IS. For example, if the first signal IS is changed to a specific level when the abnormal state is established (or detected) while maintaining the normal state, the comparison circuit 1063 may change at least one of the second signal TS and the third signal CS to a level different from its level in the normal state based on the change in the level of the first signal IS. Therefore, at least one of the second signal TS and the third signal CS may be activated. For example, when the first signal IS switches from a logic low level to a logic high level, the comparison circuit 1063 may activate at least one of the second signal TS and the third signal CS by setting the corresponding signal to a specific level during the period when the first signal IS has a logic high level.

[0102] The first signal IS may be, for example, an interrupt signal. For example, the first signal IS may include information about whether the monitoring circuit 1061 is operating in an abnormal state. For example, when the first signal IS switches from a logic low level to a logic high level, the monitoring circuit 1061 may have determined that the monitoring circuit 1061 is operating in an abnormal state during a period in which the first signal IS has a logic high level.

[0103] The first signal IS may be provided to the controller 1065 .

[0104] The controller 1065 may be disposed outside the monitoring device 1060, but the present invention is not limited thereto. Alternatively, the controller 1065 may be disposed in the monitoring device 1060. In some embodiments, the controller 1065 may not be provided, in which case, for example, the first signal IS may be provided to the central processing unit 1010.

[0105] The controller 1065 may resolve the interruption, for example, by processing the first signal IS.

[0106] The second signal TS may be, for example, a signal that attaches a tag indicating an abnormal state to the output signal OS of the monitored circuit 1070. For example, when the second signal TS has a logic low level (i.e., in a normal state), the comparison circuit 1063 may not attach a tag to the output signal OS of the monitored circuit 1070. For example, when the second signal TS has a logic high level (i.e., in an abnormal state), the comparison circuit 1063 may attach a tag to the output signal OS of the monitored circuit 1070.

[0107] The monitored circuit 1070 may be disposed, for example, outside the monitoring device 1060, but the inventive concept is not limited thereto. Alternatively, the monitored circuit 1070 may be disposed in the monitoring device 1060. The second power supply signal SS2 may be provided to the monitored circuit 1070, and the monitored circuit 1070 may output the output signal OS.

[0108] The third signal CS may be, for example, a signal that changes the output signal OS of the monitored circuit 1070 to a signal that is ensured of safety (ie, a safety signal). Assume that if the output signal OS of the monitored circuit 1070 is, for example, "0000", then the enable Figure 1 The comparison circuit 1063 may not change the output signal OS of the monitored circuit 1070 when the third signal CS has a logic low level (i.e., in a normal state). For example, when the third signal CS has a logic high level (i.e., in an abnormal state), the comparison circuit 1063 may change the output signal OS to "0000".

[0109] In some embodiments, the normal state may be a situation where the first power supply signal SS1 drives the monitoring circuit 1061 and has a level that can ensure the operation and safety reliability of the monitoring circuit 1061. In addition, the normal state may be a situation where the second power supply signal SS2 drives the monitored circuit 1070 and has a level that can ensure the operation and safety reliability of the monitored circuit 1070.

[0110] The abnormal state may be a case where the first power supply signal SS1 has a level that cannot ensure the operation of the monitoring circuit 1061 and the safety and reliability of the monitoring circuit 1061. In addition, the abnormal state may be a case where the second power supply signal SS2 has a level that cannot ensure the operation of the monitored circuit 1070 and the safety and reliability of the monitored circuit 1070.

[0111] The level of operation and safety reliability cannot be ensured with the voltage supplied to each circuit being below a certain level (e.g. Figure 6 The case where the power supply voltage is lower than the voltage required during the lower power mode of each circuit is provided to each circuit corresponds to the case where the first reference level RL1 or the second reference level RL2 of the monitoring circuit 1061 is lower than the voltage required during the lower power mode of each circuit is provided to each circuit. The case where the operation and safety reliability of at least one of the monitoring circuit 1061 and the monitored circuit 1070 cannot be ensured may be, for example, a case where there is a malicious attack for weakening the security of at least one of the monitoring circuit 1061 and the monitored circuit 1070.

[0112] See also Figure 4 In step S100, the first power signal SS1 is provided to the monitoring circuit 1061, which is a semiconductor device according to an embodiment of the inventive concept. In addition, in step S100, the second power signal SS2 is provided to the monitored circuit 1070.

[0113] In step S201 , the watchdog circuit 1062 monitors the first power signal SS1 .

[0114] In step S203 , the watchdog circuit 1062 determines whether the level of the first power signal SS1 is lower than a first reference level.

[0115] In step S205, in the normal state, the watchdog circuit 1062 sets the watchdog signal WS to the fourth level. For example, if the level of the first power signal SS1 is higher than the first reference level or is the same as the first reference level (yes (Y) in step S203), the watchdog circuit 1062 determines that the current state is a normal state. Subsequently, in step S205, the watchdog circuit 1062 sets the level of the watchdog signal WS to the fourth level, and continuously monitors the first power signal SS1 in step S201 while providing the first power signal SS1 to the watchdog circuit 1062.

[0116] In step S207, in the abnormal state, the watchdog circuit 1062 sets the watchdog signal WS to the third level. For example, if the level of the first power signal SS1 is lower than the first reference level (No (N) in step S203), the watchdog circuit 1062 determines that the current state is an abnormal state. Subsequently, in step S207, the watchdog circuit 1062 sets the level of the watchdog signal WS to the third level, and continuously monitors the first power signal SS1 in step S201 while providing the first power signal SS1 to the watchdog circuit 1062.

[0117] For example, if the third level is a logic low level 0, the fourth level may be a logic high level 1. Alternatively, if the third level is a logic high level 1, the fourth level may be a logic low level 0.

[0118] In step S301 , the monitoring circuit 1061 monitors the second power signal SS2 .

[0119] In step S303 , the monitoring circuit 1061 determines whether the level of the second power signal SS2 is lower than a second reference level.

[0120] In step S305, in the normal state, the monitoring circuit 1061 sets the flag signal FS to the second level. For example, if the level of the second power signal SS2 is higher than the second reference level or is the same as the second reference level (yes (Y) in S303), the monitoring circuit 1061 determines that the current state is a normal state. Subsequently, in step S305, the monitoring circuit 1061 sets the level of the flag signal FS to the second level, and continuously monitors the second power signal SS2 in step S301 while providing the second power signal SS2 to the monitored circuit 1070.

[0121] In step S307, in the abnormal state, the monitoring circuit 1061 sets the flag signal FS to the first level. For example, if the level of the second power signal SS2 is lower than the second reference level (No (N) in S303), the monitoring circuit 1061 determines that the current state is an abnormal state. Subsequently, in step S307, the monitoring circuit 1061 sets the level of the flag signal FS to the first level, and continuously monitors the second power signal SS2 in S301 while providing the second power signal SS2 to the monitored circuit 1070.

[0122] For example, if the first level is a logic high level 1, the second level is a logic low level 0. Alternatively, if the first level is a logic low level 0, the second level is a logic high level 1.

[0123] In step S401 , step S403 , step S405 , and step S407 , the comparison circuit 1063 sets the level of at least one of the first signal IS, the second signal TS, and the third signal CS based on the levels of the watchdog signal WS and the flag signal FS.

[0124] For example, in step S401 , the comparison circuit 1063 determines whether the watchdog signal WS has a third level.

[0125] If the watchdog signal WS has the third level (yes (Y) in S401), the comparison circuit 1063 determines that the current state is an abnormal state and sets at least one of the first signal IS, the second signal TS, and the third signal CS to the fifth level in step S403. In other words, if the watchdog signal WS has the third level, the comparison circuit 1063 sets at least one of the first signal IS, the second signal TS, and the third signal CS to the fifth level regardless of the level of the flag signal FS.

[0126] If the watchdog signal WS does not have the third level (No (N) in step S401 ), the comparison circuit 1063 determines whether the flag signal FS has the first level.

[0127] If the flag signal FS has the first level (yes (Y) in step S405), the comparison circuit 1063 determines that the current state is an abnormal state, and sets at least one of the first signal IS, the second signal TS, and the third signal CS to the fifth level. In other words, if the flag signal FS has the first level, the comparison circuit 1063 sets at least one of the first signal IS, the second signal TS, and the third signal CS to the fifth level even if the watchdog signal WS has the fourth level.

[0128] If the flag signal FS does not have the first level (No (N) in step S405 ), the comparison circuit 1063 determines that the current state is a normal state and sets at least one of the first signal IS, the second signal TS, and the third signal CS to a sixth level.

[0129] In short, if the watchdog signal WS has the third level, the comparison circuit 1063 determines that the current state is an abnormal state without considering the level of the flag signal FS. In addition, if the flag signal FS has the first level, the comparison circuit 1063 determines that the current state is an abnormal state without considering the level of the watchdog signal WS.

[0130] For example, if the fifth level is a logic high level 1, the sixth level is a logic low level 0. Alternatively, if the fifth level is a logic low level 0, the sixth level is a logic high level 1.

[0131] In the following we will refer to Figure 5 and Figure 6 The operations of the monitoring circuit 1061 , the watchdog circuit 1062 , and the comparison circuit 1063 are described in further detail.

[0132] See also Figure 6 , the X-axis of the first to fifth curves G1 to G5 represents time (in arbitrary units (AU)). The Y-axis of the first and second curves G1 and G2 may represent voltage. The Y-axis of the third to fifth curves G3 to G5 may represent logic levels.

[0133] See also Figure 5 and Figure 6 , the period from t0 to t1 can be compared with Figure 5 Corresponding to "Case 4".

[0134] For example, as indicated by the first curve G1 depicting the level of the first power signal SS1, during the period from t0 to t1, the level of the first power signal SS1 is higher than the first reference level RL1. Therefore, the watchdog circuit 1062 determines that the period from t0 to t1 is in a normal state and sets the watchdog signal WS to the fourth level “Level 4”. In other words, as indicated by the fourth curve G4 depicting the level of the watchdog signal WS, during the period from t0 to t1, the watchdog signal WS has the fourth level “Level 4”, for example, a logic high level.

[0135] The first reference level RL1 may be a reference direct current (DC) voltage set by the watchdog circuit 1062. For example, the first reference level RL1 is not a voltage supplied from the outside of the watchdog circuit 1062.

[0136] For example, as indicated by the second curve G2 showing the level of the second power signal SS2, during the period from t0 to t1, the level of the second power signal SS2 is higher than the second reference level RL2. Therefore, the monitoring circuit 1061 determines that the period from t0 to t1 is in a normal state and sets the flag signal FS to the second level "Level 2". In other words, as indicated by the third curve G3 showing the level of the flag signal FS, during the period from t0 to t1, the flag signal FS has the second level "Level 2", such as a logic low level.

[0137] The second reference level RL2 may be a reference DC voltage set by the monitoring circuit 1061. For example, the second reference level RL2 is not a voltage supplied from the outside of the monitoring circuit 1061.

[0138] For example, during the period from t0 to t1, the comparison circuit 1063 sets at least one of the first signal IS, the second signal TS, and the third signal CS to the sixth level “Level 6”. In other words, since during the period from t0 to t1, the watchdog signal WS has the fourth level “Level 4” and the flag signal FS has the second level “Level 2”, the comparison circuit 1063 determines that the current state is a normal state. Therefore, the comparison circuit 1063 sets at least one of the first signal IS, the second signal TS, and the third signal CS to the sixth level “Level 6”, for example, a logic low level.

[0139] The period from t1 to t2 can be compared with Figure 5 Corresponding to "Case 2".

[0140] For example, as indicated by the first curve G1, during the period from t1 to t2, the level of the first power supply signal SS1 is higher than the first reference level RL1. Therefore, the watchdog circuit 1062 determines that the period from t1 to t2 is in a normal state and sets the watchdog signal WS to the fourth level "Level 4". In other words, as indicated by the fourth curve G4, during the period from t1 to t2, the watchdog signal WS has the fourth level "Level 4", for example, a logic high level.

[0141] For example, as indicated by the second curve G2, during the period from t1 to t2, the level of the second power supply signal SS2 is lower than the second reference level RL2. Therefore, the monitoring circuit 1061 determines that the period from t1 to t2 is in an abnormal state and sets the flag signal FS to the first level "Level 1". In other words, as indicated by the third curve G3, during the period from t1 to t2, the flag signal FS has the first level "Level 1", such as a logic high level.

[0142] For example, during the period from t1 to t2, the comparison circuit 1063 sets at least one of the first signal IS, the second signal TS, and the third signal CS to the fifth level “Level 5” without considering the level of the watchdog signal WS. In other words, since during the period from t1 to t2, the watchdog signal WS has the fourth level “Level 4” and the flag signal FS has the first level “Level 1”, the comparison circuit 1063 can determine that the current state is an abnormal state. Therefore, the comparison circuit 1063 can set at least one of the first signal IS, the second signal TS, and the third signal CS to the fifth level “Level 5”, for example, a logic high level.

[0143] The period from t3 to t5 can be Figure 5 Corresponding to "Case 3".

[0144] For example, as indicated by the first curve G1, during the period from t3 to t5, the level of the first power supply signal SS1 is lower than the first reference level RL1. Therefore, the watchdog circuit 1062 determines that the period from t3 to t5 is in an abnormal state and sets the watchdog signal WS to the third level "Level 3". In other words, as indicated by the fourth curve G4, during the period from t3 to t5, the watchdog signal WS has the third level "Level 3", for example, a logic low level.

[0145] For example, as indicated by the second curve G2, during the period from t3 to t5, the level of the second power supply signal SS2 is higher than the second reference level RL2. Therefore, the monitoring circuit 1061 determines that the period from t3 to t5 is in a normal state and sets the flag signal FS to the second level "Level 2". In other words, as indicated by the third curve G3, during the period from t3 to t5, the flag signal FS has the second level "Level 2", such as a logic low level.

[0146] For example, during the period from t3 to t5, the comparison circuit 1063 sets at least one of the first signal IS, the second signal TS, and the third signal CS to the fifth level “Level 5”. In other words, since during the period from t3 to t5, the watchdog signal WS has the third level “Level 3” and the flag signal FS has the second level “Level 2”, the comparison circuit 1063 determines that the current state is an abnormal state. Therefore, the comparison circuit 1063 sets at least one of the first signal IS, the second signal TS, and the third signal CS to the fifth level “Level 5”, for example, a logic high level.

[0147] The period from t5 to t6 can be Figure 5 Corresponding to "Case 1".

[0148] For example, as indicated by the first curve G1, during the period from t5 to t6, the level of the first power supply signal SS1 is lower than the first reference level RL1. Therefore, the watchdog circuit 1062 determines that the period from t5 to t6 is in an abnormal state and sets the watchdog signal WS to the third level "Level 3". In other words, as indicated by the fourth curve G4, during the period from t5 to t6, the watchdog signal WS has the third level "Level 3", for example, a logic low level.

[0149] For example, as indicated by the second curve G2, during the period from t5 to t6, the level of the second power supply signal SS2 is lower than the second reference level RL2. Therefore, the monitoring circuit 1061 determines that the period from t5 to t6 is in an abnormal state and sets the flag signal FS to the first level "Level 1". In other words, as indicated by the third curve G3, during the period from t5 to t6, the flag signal FS has the first level "Level 1", such as a logic high level.

[0150] For example, during the period from t5 to t6, the comparison circuit 1063 sets at least one of the first signal IS, the second signal TS, and the third signal CS to the fifth level “Level 5”. In other words, since during the period from t5 to t6, the watchdog signal WS has the third level “Level 3” and the flag signal FS has the first level “Level 1”, the comparison circuit 1063 determines that the current state is an abnormal state. Therefore, the comparison circuit 1063 sets at least one of the first signal IS, the second signal TS, and the third signal CS to the fifth level “Level 5”, for example, a logic high level.

[0151] The semiconductor device (i.e., the monitoring device 1060) according to an embodiment of the inventive concept includes a watchdog circuit 1062, and monitors not only the second power signal SS2 provided to the monitored circuit 1070 but also the first power signal SS1 provided to the monitoring circuit 1061 that monitors the second power signal SS2, and thus can ensure the operation and safety reliability of the monitored circuit 1070 and the operation and safety reliability of the monitoring circuit 1061. Furthermore, since the watchdog circuit 1062 is additionally provided in the monitoring circuit 1061, the monitoring device 1060 can detect any degradation in the reliability of the monitoring circuit 1061.

[0152] In the following we will refer to Figure 7 and Figure 8 A semiconductor system 20 according to an embodiment of the inventive concept is described. For the sake of clarity, descriptions of the same elements or features that have been described above will be omitted.

[0153] Figure 7 A block diagram of a semiconductor system 20 is shown. Figure 8 Show instructions Figure 7 2 is a block diagram of a processor 210 and a PMIC 220.

[0154] See also Figure 7 and Figure 8 The monitoring device 1060 is disposed in the PMIC 220, and the monitoring device 1060 is a semiconductor device according to an embodiment of the inventive concept. Figure 3 The first power signal SS1 and the second power signal SS2 are provided to the PMIC 220 .

[0155] Monitored circuit 1070 is, for example, a circuit disposed in PMIC 220 to perform a specific function.

[0156] Despite Figure 7 and Figure 8 Not shown, but a controller (such as that described above) Figures 3 to 6 The controller 1065 described above may be provided, for example, inside or outside the PMIC 220. Furthermore, as previously mentioned, a controller such as the controller 1065 may not be provided.

[0157] The processor 210 is powered by the PMIC 220. For example, the processor 210 may send a request for a driving voltage Vdd to the PMIC 220. For example, the processor 210 may send a voltage code VID for requesting the driving voltage Vdd to the PMIC 220, and in response to receiving the voltage code VID, the PMIC 220 may provide the driving voltage Vdd to the processor 210.

[0158] In the following we will refer to Figures 9 to 11 A semiconductor system 30 according to an embodiment of the inventive concept is described. For the sake of clarity, descriptions of the same elements or features that have been described above will be omitted.

[0159] Fig. 9 A schematic diagram of a semiconductor system 30 is shown. Fig.10 Show Fig. 9 310 is a block diagram of an electronic device. Fig.11 Show Fig.10 A block diagram of the automotive processor 311 is shown.

[0160] See also Fig. 9 and Fig.10 , the semiconductor system 30 may be a car. The semiconductor system 30 includes, for example, an electronic device 310, an output device 320, an image capture device 330, and a power supply 340, but is not limited thereto. For example, the semiconductor system 30 may include Fig. 9 The components shown in the figure may be used Fig. 9 Various modifications are made to the structure of the semiconductor system 30 from the elements shown in FIG.

[0161] The electronic device 310 may, for example, control the output device 320, the image capture device 330, and the power supply 340. Fig.10 As shown in FIG. 3 , the electronic device 310 may include a vehicle processor 311 , a communication module 313 , and a memory 315 .

[0162] The vehicle processor 311 may perform operations associated with control and / or communication of at least one element of the electronic device 310 or may perform data processing. The vehicle processor 311 may, for example, receive input data from the image capture device 330 and process the input data. The vehicle processor 311 may, for example, use data stored in the memory 315 to perform a specific function.

[0163] The communication module 313 may communicate with an external device (eg, the image capture device 330 and / or the output device 320 ), for example, via wireless communication or wired communication.

[0164] The memory 315 may store data or models output by each element of the electronic device 310 in order to perform a specific operation.

[0165] The output device 320 may perform an operation according to data or a command output by the electronic device 310. The output device 320 may include, for example, a lighting device, an alarm device, and / or a braking device.

[0166] The image capture device 330 may capture an image of the surrounding environment of the semiconductor system 30. The image capture device 330 may include, for example, a 3D camera, a digital camera, a video camera, a thermal sensing camera, a night vision camera, an infrared (IR) camera, an X-ray camera, a sensor, or a combination thereof. The image capture device 330 may include an analog-to-digital converter (ADC) capable of converting an input image into a digital signal. The image capture device 330 may also include a communication module for transmitting the input to an external device (e.g., the electronic device 310).

[0167] The power supply 340 may, for example, transmit power to the semiconductor system 30. The power supply 340 may, for example, be controlled by the electronic device 310. The power supply 340 may include, for example, an engine control device, a crank mechanism, an engine lubrication device, an exhaust device, and the like.

[0168] See also Fig.11 , the vehicle processor 311 may include the Figures 3 to 6 Monitoring device 1060 is described.

[0169] The monitoring device 1060 may be disposed in the vehicle processor 311. Figure 3 The first power signal SS1 and the second power signal SS2 are provided to the vehicle processor 311 .

[0170] The monitored circuit 1070 may be, for example, provided in the vehicle processor 311 to perform operations associated with the safety of the semiconductor system 30. Alternatively, the monitored circuit 1070 may be, for example, provided in the vehicle processor 311 to perform operations associated with the safety of the semiconductor system 30. However, the inventive concept is not limited to these examples. Alternatively, the monitored circuit 1070 may be a circuit provided in the vehicle processor 311 to perform any operation.

[0171] A controller such as the controller 1065 may be provided, for example, inside or outside the vehicle processor 311. As already mentioned above, a controller such as the controller 1065 may not be provided.

[0172] In software implementation, embodiments of the inventive concept (such as the procedures or functions described herein) can be implemented by separate software modules. Each software module can perform one or more functions or operations described herein. Software code can be implemented by a software application written in any suitable programming language.

[0173] Although the inventive concept has been particularly depicted and described with reference to exemplary embodiments of the inventive concept, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the inventive concept as defined in the appended claims. It is therefore contemplated that the embodiments are to be considered in all respects as illustrative and non-restrictive, with reference to the appended claims rather than the foregoing description indicating the scope of the inventive concept.

Claims

1. A semiconductor device comprising: a monitoring circuit configured to receive the first power supply signal and generate a flag signal by monitoring a second power supply signal provided to the monitored circuit; a watchdog circuit, disposed in the monitoring circuit and configured to receive the first power signal and generate a watchdog signal; as well as a comparison circuit configured to receive the flag signal and the watchdog signal and generate a first signal having a first level in an abnormal state and a second level in a normal state, wherein the second level is different from the first level, wherein the watchdog circuit is configured to set the watchdog signal to a third level when the level of the first power signal is lower than a first reference level, and When the watchdog signal has the third level, the comparison circuit is configured to allow the first signal to have the first level regardless of a level of the flag signal.

2. The semiconductor device according to claim 1 , wherein the watchdog circuit is configured to set the watchdog signal to a fourth level when the level of the first power supply signal is higher than the first reference level or is the same as the first reference level, and The monitoring circuit is configured to set the flag signal to a fifth level when the level of the second power signal is lower than a second reference level, and to set the flag signal to a sixth level when the level of the second power signal is higher than the second reference level or is the same as the second reference level, wherein the sixth level is different from the fifth level.

3. The semiconductor device according to claim 2, wherein the abnormal state is a case where the flag signal has any one of the fifth level and the sixth level and the watchdog signal has the third level, and The normal state is a case where the flag signal has the sixth level and the watchdog signal has the fourth level. 4 . The semiconductor device according to claim 3 , wherein when the flag signal has the fifth level, the comparison circuit is configured to allow the first signal to have the first level without considering a level of the watchdog signal. 5 . The semiconductor device according to claim 1 , wherein the first power supply signal is a driving voltage of the monitoring circuit, and the second power supply signal is a driving voltage of the monitored circuit. 6 . The semiconductor device according to claim 1 , wherein the watchdog circuit is configured to monitor the first power supply signal in real time while providing the first power supply signal to the monitoring circuit and generate the watchdog signal.

7. The semiconductor device according to claim 1, wherein the monitored circuit is disposed outside the semiconductor device.

8. A semiconductor system comprising: A processor, receiving a first power signal and a second power signal; as well as a monitored circuit, disposed in the processor and driven by the second power signal, wherein the processor is configured to monitor the first power signal and generate a watchdog signal having a first level when the level of the first power signal is lower than a first reference level, monitor the second power signal and generate a flag signal, and generate an interrupt signal when the watchdog signal has the first level without considering the level of the flag signal, wherein the watchdog signal has a second level when the level of the first power signal is higher than the first reference level or is the same as the first reference level, wherein the second level is different from the first level, and The flag signal has a third level when the level of the second power signal is lower than a second reference level, and has a fourth level when the level of the second power signal is higher than or the same as the second reference level, wherein the fourth level is different from the third level.

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