Memory devices

Abstract

A memory device is provided. The memory device includes: a clock buffer for receiving a master clock signal and providing an internal master clock signal; a data clock buffer for receiving a data clock signal; and a delay control circuit configured to generate delay information based on the data clock signal and provide the delay information to a data input / output circuit. The delay control circuit includes: a frequency divider configured to generate a divided-by-two clock signal based on the data clock signal; a frequency divider configured to generate a divided-by-four clock signal based on a first group of divided-by-two clock signals; a first synchronization detector configured to output a divided-by-two alignment signal indicating whether the second group of divided-by-two clock signals is synchronized with the data clock signal; and a delay selector configured to detect a phase of the divided-by-four clock signal based on the divided-by-two alignment signal and adjust the delay of the master clock signal based on the phase.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0118038 filed on October 4, 2018, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2018-0151160 filed on November 29, 2018, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to memory, and more particularly, to a memory device including a delay control circuit. Background Art

[0004] Dynamic random access memory (DRAM) can receive commands and addresses synchronously with the main clock signal CK. DRAM can also receive or send data synchronously with the data clock signal WCK. DRAM performs two main operations. These operations include: an operation of writing data to a memory cell array included in a core circuit and an operation of reading data from a memory cell array. A control signal for controlling the core circuit generated based on the main clock signal CK and data input to / output from the core circuit based on the data clock signal WCK are provided in different clock domains. Therefore, DRAM synchronizes the main clock signal CK and the data clock signal WCK so that input / output data can be stably latched in response to the control signal. Summary of the invention

[0005] One or more example embodiments provide a memory device including a delay control circuit capable of controlling delay associated with data input / output by using phase information generated in the memory device.

[0006] According to one aspect of an example embodiment, a memory device is provided. The memory device includes: a clock buffer configured to receive a master clock signal and provide an internal master clock signal to a core circuit; a data clock buffer for receiving a data clock signal; and a delay control circuit configured to generate delay information based on the data clock signal and provide the delay information to a data input / output (I / O) circuit. The delay control circuit includes: a first frequency divider, which is configured to generate a plurality of divided-by-two clock signals based on a data clock signal, wherein the plurality of divided-by-two clock signals include a first group of divided-by-two clock signals and a second group of divided-by-two clock signals; a second frequency divider, which is configured to generate a plurality of divided-by-four clock signals based on the first group of divided-by-two clock signals; a first synchronization detector, which is configured to output a plurality of divided-by-two alignment signals indicating whether the second group of divided-by-two clock signals are synchronized with the data clock signal, wherein the plurality of divided-by-two alignment signals are generated based on the phase of the second group of divided-by-two clock signals, and the second group of divided-by-two clock signals are based on the clock synchronization signal; and a delay selector, which is configured to automatically detect the phase of the plurality of divided-by-four clock signals based on the plurality of divided-by-two alignment signals, and adjust the delay of the main clock signal based on the phase of the plurality of divided-by-four clock signals.

[0007] According to one aspect of an example embodiment, a memory device is provided. The memory device includes a memory cell array, the memory cell array including: a plurality of memory bank arrays; a command decoder configured to output a clock synchronization signal based on a clock synchronization command synchronized with a master clock signal; a memory bank control logic configured to generate a plurality of memory bank control signals for controlling the plurality of memory bank arrays based on a memory bank address in an address signal; a clock synchronization circuit configured to generate a plurality of divided-by-two clock signals based on a data clock signal, and output one of the plurality of divided-by-two clock signals as an internal data clock signal; a delay control circuit configured to: generate a plurality of divided-by-four clock signals based on a first plurality of divided-by-two clock signals, generate a plurality of divided-by-two alignment signals indicating whether the plurality of divided-by-two clock signals are synchronized with the data clock signal based on the clock synchronization signal, identify phases of the plurality of divided-by-four clock signals based on the plurality of divided-by-two alignment signals, and adjust a delay associated with the master clock signal based on the phases of the plurality of divided-by-four clock signals to output delay information associated with the internal data clock signal; and a data input / output (I / O) circuit configured to transmit and receive data based on the internal data clock signal and the delay information. Each of the plurality of memory bank arrays includes a plurality of dynamic memory cells coupled to a plurality of word lines and a plurality of bit lines.

[0008] According to one aspect of an example embodiment, a memory device is provided. The memory device includes: at least one buffer die; and a plurality of memory dies stacked on the at least one buffer die and configured to transceive data through a plurality of through silicon vias. At least one of the plurality of memory dies includes a memory cell array, and at least one buffer die includes: a clock synchronization circuit configured to generate a plurality of divided-by-two clock signals based on a data clock signal and output one of the plurality of divided-by-two clock signals as an internal data clock signal; a delay control circuit configured to: generate a plurality of divided-by-four clock signals based on a first group of a plurality of divided-by-two clock signals, generate a plurality of divided-by-two alignment signals indicating whether the plurality of divided-by-two clock signals are synchronized with the data clock signal based on a clock synchronization signal, identify the phases of the plurality of divided-by-four clock signals based on the plurality of divided-by-two alignment signals, adjust the delay of the master clock signal based on the phases of the plurality of divided-by-four clock signals, and output delay information associated with the internal data clock signal; and a data input / output circuit configured to transceive data based on the internal data clock signal and the delay information. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be described in more detail below with reference to the accompanying drawings.

[0010] Figure 1 is a block diagram illustrating a memory system according to one or more example embodiments.

[0011] Figure 2 is a timing diagram for describing the operation of a high-speed data interface according to one or more example embodiments.

[0012] Figure 3 and Figure 4 is a diagram for describing a clock synchronization operation according to one or more example embodiments.

[0013] Figure 5 is a block diagram illustrating a memory device according to one or more example embodiments.

[0014] Figure 6 is a block diagram illustrating a memory device according to one or more example embodiments.

[0015] Figure 7 An example of a first bank array in a memory device according to one or more example embodiments is illustrated.

[0016] Figure 8 is a block diagram illustrating a clock synchronization circuit in a memory device according to one or more example embodiments.

[0017] Fig. 9 is a circuit diagram illustrating a multiplexer circuit according to one or more example embodiments.

[0018] Fig.10 is a block diagram illustrating a delay control circuit according to one or more example embodiments.

[0019] Fig.11 is a block diagram illustrating a delay selector according to one or more example embodiments.

[0020] Fig.12 A second synchronous detector according to one or more example embodiments is shown.

[0021] Fig.13 A third synchronous detector according to one or more example embodiments is shown.

[0022] Fig.14 is a block diagram illustrating a selection circuit according to one or more example embodiments.

[0023] Fig.15 is a circuit diagram illustrating a first delay adjustment circuit according to one or more example embodiments.

[0024] Fig.16 is a block diagram illustrating a selection circuit according to one or more example embodiments.

[0025] Fig.17A , Fig. 17B , Fig. 17C and Fig.17D A timing control diagram of a delay control circuit according to one or more example embodiments is shown.

[0026] Fig.18A , Fig.18B , Fig. 18C and Fig.18D A timing control diagram of a delay control circuit according to one or more example embodiments is shown.

[0027] Fig.19 is a flowchart illustrating a method of operating a memory device according to one or more example embodiments.

[0028] Fig. 20 is a block diagram illustrating a memory device according to one or more example embodiments.

[0029] Fig.21 is a cross-sectional view of a 3D chip structure employing a semiconductor memory device according to one or more example embodiments.

[0030] Fig. 22 is a configuration diagram illustrating a semiconductor package including a memory device according to one or more example embodiments. DETAILED DESCRIPTION

[0031] Various example embodiments will be described more fully below with reference to the accompanying drawings, in which example embodiments are shown. It should be understood that when an element or layer is referred to as "above another element or layer", "above another element or layer", "on another element or layer", "connected to" or "coupled to" another element or layer, the element or layer may be directly above the other element or layer, directly above the other element or layer, directly on the other element or layer, directly connected to or coupled to the other element or layer, or there may be an intermediate element or layer. On the contrary, when an element is referred to as "directly above another element or layer", "directly above another element or layer", "directly on another element or layer", "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer.

[0032] Figure 1 is a block diagram illustrating a memory system according to one or more example embodiments.

[0033] refer to Figure 1 , the memory system 10 may include a memory controller 20 and a memory device 100, such as a semiconductor memory device. The memory system 10 may support data communication between the memory controller 20 and the memory device 100 by using a main clock signal CK and a data clock signal WCK.

[0034] A first clock signal line 11, a command bus 12, an address bus 13, a second clock signal line 14, and a data bus 15 may be connected between the memory controller 20 and the memory device 100. According to example embodiments, the memory system 10 may support data communication based on various clock signals in addition to the main clock signal CK and the data clock signal WCK.

[0035] The master clock signal CK generated by the memory controller 20 can be provided to the memory device 100 through the first clock signal line 11. For example, the master clock signal CK can be provided as a continuous alternating inversion signal together with the inverted master clock signal CKB. With respect to the master clock signal pair CK and CKB, the rising edge / falling edge can be detected relative to the intersection of the master clock signal CK and the inverted master clock signal CKB, thereby increasing the timing accuracy. Herein, the master clock signal CK can be referred to as the first clock signal CK.

[0036] The first clock signal line 11 can transmit a complementary continuous alternating inversion signal based on the master clock signal pair CK and CKB. In this case, the first clock signal line 11 may include two signal lines for transmitting the master clock signal CK and the inverted master clock signal CKB. The clock signal CK described herein may refer to the master clock signal pair CK and CKB. For ease of explanation, the master clock signal pair CK and CKB are referred to as the master clock signal CK.

[0037] The command CMD and the address ADDR provided from the memory controller 20 may be provided to the memory device 100 through the command bus 12 and the address bus 13 , respectively.

[0038] The data clock signal WCK and the data DQ may be transmitted to the data interface between the memory controller 20 and the memory device 100. The data clock signal WCK generated by the memory controller 20 may be provided to the memory device 100 through the second clock signal line 14. The data clock signal WCK may be provided as a continuous alternating inversion signal together with the inverted data clock WCKB. With respect to the data clock signal pair WCK and WCKB, the rising edge / falling edge may be detected relative to the crossing point of the data clock signal WCK and the inverted data clock signal WCKB, thereby increasing the timing accuracy.

[0039] The second clock signal line 14 can transmit a complementary continuous alternating inversion signal based on the data clock signal pair WCK and WCKB. In this case, the second clock signal line 14 can be configured to include two signal lines for transmitting the data clock signal WCK and the inverted data clock signal WCKB. The data clock signal WCK described herein can refer to the data clock signal pair WCK and WCKB. Herein, the data clock signal pair WCK and WCKB can be referred to as the data clock signal WCK.

[0040] The data DQ synchronized with the data clock signal WCK may be transmitted through the data bus 15 connected between the memory controller 20 and the memory device 100. For example, write data DQ corresponding to the burst length BL and provided from the memory controller 20 may be transmitted to the memory device 100 in synchronization with the data clock signal WCK through the data bus 15. Write data DQ corresponding to the burst length BL and read from the memory device 100 may be latched in synchronization with the data clock signal WCK and may be transmitted to the memory controller 20 through the data bus 15.

[0041] If the memory device 100 is implemented with DRAM, the core circuit of the DRAM may not be able to operate at the speed of the high-speed data interface. This is because there is a limit to increasing the frequency of the main clock signal CK transmitted to the core circuit of the DRAM. Therefore, the DRAM can use a method of increasing the data interface speed while maintaining the operating speed of the core circuit of the DRAM.

[0042] Figure 2 is a timing diagram for describing a high-speed data interface operation of a memory device according to one or more example embodiments.

[0043] refer to Figure 1 and Figure 2, the main clock signal CK from the memory controller 20 can be transmitted, and the command CMD and the address signal ADDR can be transmitted based on the main clock signal CK. The data DQ can be transmitted based on the data clock signal WCK. For a high-speed data interface, the frequency of the data clock signal WCK can be set to a multiple of the frequency of the main clock signal CK.

[0044] For example, a data write operation may be performed in the memory device 100. The memory device 100 may receive a master clock signal CK from a time point T1, and may receive a write command CMD and a write address signal ADDR based on the master clock signal CK at a time point T2. In addition, at a time point T2, the memory device 100 may receive write data DQ corresponding to a burst length BL based on a data clock signal WCK.

[0045] In the above, the memory device 100 is described as receiving the write command CMD and the write data DQ at the time point T2. However, it should be understood that the memory device 100 may receive the write command CMD and then may receive the write data DQ after the write delay. The write delay may be expressed as a multiple of the period of the main clock signal CK.

[0046] A data read operation may also be performed in the memory device 100. The memory device 100 may receive a master clock signal CK from a time point T1, and may receive a read command CMD and a read address signal ADDR based on the master clock signal CK at a time point T2. In addition, after receiving the read command CMD, the memory device 100 may receive read data DQ based on the data clock signal WCK after a read delay. The read delay may be expressed as a multiple of a period of the master clock signal CK.

[0047] In a write operation, the memory device 100 may sample the data DQ input from the memory controller 20 by using the data clock signal WCK, and may store the data obtained by the sampling in the memory cell array by using the master clock signal CK. In addition, in a read operation, the memory device 100 may read data from the memory cell array by using the master clock signal CK, and may transmit the read data to the memory controller 20 by using the data clock signal WCK. As described above, the memory device 100 may operate in different clock domains (e.g., multiple time domains).

[0048] In the memory device 100, data transfer is performed between a domain operating based on a master clock signal CK and a domain operating based on a data clock signal WCK. In other words, domain crossing occurs between the master clock signal CK and the data clock signal WCK. Data may be lost due to domain crossing. In order to prevent data loss, a clock synchronization operation between the master clock signal CK and the data clock signal WCK is performed. Figure 3 and Figure 4 The clock synchronization operation between the master clock signal CK and the data clock signal WCK is described.

[0049] Figure 3 and Figure 4 is a diagram for describing clock synchronization operations according to one or more example embodiments. For example, Figure 3 and Figure 4 The clock synchronization operation shown in Figure 1 is implemented in a memory device in .

[0050] Figure 3 An aligned state is shown in which clock synchronization occurs between the master clock signal CK and the data clock signal WCK. Figure 4 A misaligned state is shown where clock synchronization does not occur.

[0051] refer to Figure 3 , the master clock signal CK and the data clock signal WCK may be received by the memory device 100 (see Figure 1 ). The frequency of the data clock signal WCK may be higher than the frequency of the main clock signal CK. For example, the frequency of the data clock signal WCK may be a multiple of the frequency of the main clock signal CK.

[0052] The master clock signal CK may be received from time point T1. A falling edge of the master clock signal CK may be input at time point T1, a rising edge of the master clock signal CK may be input at time point T2, a falling edge of the master clock signal CK may be input at time point T3, a rising edge of the master clock signal CK may be input at time point T4, and a falling edge of the master clock signal CK may be input at time point T5.

[0053] The data clock signal WCK may be received from time point T2. Since the data clock signal WCK is provided together with the corresponding data DQ whenever the write data DQ is input or the read data DQ is output, the data clock signal WCK may be in a deactivated state at time point T1 and then may be activated at time point T2 where the corresponding data DQ is provided.

[0054] When the data clock signal WCK is received at the time point T2, the memory device 100 may divide the data clock signal WCK to generate a plurality of divided data clock signals WCK / 2_0, WCK / 2_90, WCK / 2_180, and WCK / 2_270. In this case, the memory device 100 may divide the data clock signal WCK by two to generate a plurality of divided data clock signals WCK / 2_0, WCK / 2_90, WCK / 2_180, and WCK / 2_270.

[0055] Starting from the time point T2 when the data clock signal WCK is received, a first two-divided data clock signal WCK / 2_0 can be generated to have the same phase as the phase of the main clock signal CK, a second two-divided data clock signal WCK / 2_90 can be generated to have a phase obtained by shifting the phase of the main clock signal CK by 90 degrees, a third two-divided data clock signal WCK / 2_180 can be generated to have a phase obtained by shifting the phase of the main clock signal CK by 180 degrees, and a fourth two-divided data clock signal WCK / 2_270 can be generated to have a phase obtained by shifting the phase of the main clock signal CK by 270 degrees.

[0056] For example, when determining the falling edge of the first divided-by-two data clock signal WCK / 2_0 at the time point T3, the memory device 100 may have an alignment margin including a setup time S of 0.25tCK and a hold time H of 0.25tCK. The memory device 100 may determine the logic level of the first divided-by-two data clock signal WCK / 2_0 based on the falling edge of the main clock signal CK, the setup time S of 0.25tCK and the hold time H of 0.25tCK. When the determined logic level of the first divided-by-two data clock signal WCK / 2_0 is logic low, the memory device 100 may determine the first divided-by-two data clock signal WCK / 2_0 to have a falling edge.

[0057] exist Figure 3 It can be seen that the rising edge of the first divided-by-two data clock signal WCK / 2_0 corresponds to the rising edge of the main clock signal CK, and the falling edge of the first divided-by-two data clock signal WCK / 2_0 corresponds to the falling edge of the main clock signal CK.

[0058] Figure 4 FIG. 2 shows a misaligned state in which clock synchronization does not occur between the master clock signal CK and the data clock signal WCK. Figure 4 At time point T2 when the data clock signal WCK is received, a falling edge of the first divided-by-two data clock signal WCK / 2_0 may be generated, which contrasts with the rising edge of the master clock signal CK at time point T2. At time point T3, a rising edge of the first divided-by-two data clock signal WCK / 2_0 may be generated, which contrasts with the falling edge of the master clock signal CK at time point T3.

[0059] At time point T4, a falling edge of the first divided-by-two data clock signal WCK / 2_0 may be generated, which contrasts with the rising edge of the master clock signal CK at time point T4. In addition, at time point T5, a rising edge of the first divided-by-two data clock signal WCK / 2_0 may be generated, which contrasts with the falling edge of the master clock signal CK at time point T5.

[0060] about Figure 4 , it can be seen that the falling edge of the first divided-by-two data clock signal WCK / 2_0 is generated at a time point corresponding to the rising edge of the master clock signal CK, and the rising edge of the first divided-by-two data clock signal WCK / 2_0 is generated at a time point corresponding to the falling edge of the master clock signal CK. This shows a misaligned state in which clock synchronization does not occur between the master clock signal CK and the data clock signal WCK.

[0061] For example, at time point T3, in order to determine that the first divided-by-two data clock signal WCK / 2_0 is generated to have a rising edge when the main clock signal CK has a falling edge, the memory device 100 may determine the logic level of the first divided-by-two data clock signal WCK / 2_0 based on the falling edge of the main clock signal CK, based on a setup time S of 25% (0.25tCK) of the clock cycle, and a hold time H of 0.25tCK. When the determined logic level of the first divided-by-two data clock signal WCK / 2_0 is logic high, the memory device 100 may determine the first divided-by-two data clock signal WCK / 2_0 to have a rising edge.

[0062] In example embodiments, a method of performing a clock synchronization operation and delay control is performed by using a data clock signal WCK having a variable frequency (eg, a dynamic frequency) to correct a deficiency in an alignment margin in the clock synchronization operation.

[0063] Figure 5 is a block diagram illustrating a memory device according to one or more example embodiments. For example, Figure 5 The memory device 100 shown in FIG. 1 may correspond to Figure 1 The memory device 100 is shown in FIG.

[0064] refer to Figure 5 , the memory device 100 may include a command decoder 110 , a master clock buffer 125 , a core circuit 130 , a data clock buffer 127 , a clock synchronization circuit 300 , a delay control circuit 400 , and a data input / output (I / O) circuit 195 .

[0065] The command decoder 110 can receive commands from the memory controller 20 (see Figure 1 ) receives the command via bus 12 (see Figure 1 ) The command CMD or CMD_SYNC transmitted by the command decoder 110. The command decoder 110 may decode the received command CMD to generate an internal command signal ICMD and a clock synchronization signal ISYNC.

[0066] The command decoder 110 may generate an internal command signal ICMD including a read signal or a write signal according to the received read command or write command. The internal command signal ICMD may be provided to the core circuit 130. The internal command signal ICMD may control a data read operation or a data write operation performed by the core circuit 130.

[0067] The command decoder 110 may generate a clock synchronization signal ISYNC based on the received clock synchronization command CMD_SYNC or the internal master clock signal ICK provided from the master clock buffer 125. The clock synchronization signal ISYNC may be generated as a pulse signal having a period corresponding to the received clock synchronization command CMD_SYNC. The clock synchronization signal ISYNC may be provided to the clock synchronization circuit 300 and the delay control circuit 400.

[0068] The master clock buffer 125 can receive the clock signal from the memory controller 20 through the first clock signal line 11 (see Figure 1 ) The master clock signal CK transmitted by the master clock buffer 125. The master clock buffer 125 may buffer the received master clock signal CK to generate an internal master clock signal ICK and may provide the internal master clock signal ICK to the command decoder 110 and the core circuit 130. The phase of the buffered internal master clock signal ICK may be approximately equal to the phase of the master clock signal CK.

[0069] The core circuit 130 may include a memory cell array 200. In a read operation of the memory device 100, the core circuit 130 may read data from the memory cell array 200 according to an internal command signal ICMD and an internal master clock signal ICK (both of which are read signals). In a write operation of the memory device 100, the core circuit 130 may write data into the memory cell array 200 based on the internal command signal ICMD and the internal master clock signal ICK (both of which are write signals).

[0070] The following will refer to Figure 6 The core circuit 130 is described in more detail.

[0071] The data clock buffer 127 can receive the data from the memory controller 20 through the second clock signal line 14 (see Figure 1 ) The data clock buffer 127 may buffer the received data clock signal WCK to provide the buffered data clock signal WCK to the clock synchronization circuit 300 and the delay control circuit 400.

[0072] The clock synchronization circuit 300 may receive the data clock signal WCK and the clock synchronization signal ISYNC buffered by the data clock buffer 127. The clock synchronization circuit 300 may perform a clock synchronization operation based on the data clock signal WCK and the clock synchronization signal ISYNC buffered by the data clock buffer 127. As a result of the clock synchronization operation, the clock synchronization circuit 300 may generate an internal data clock signal IWCK including a first internal data clock signal, a second internal data clock signal, a third internal data clock signal, and a fourth internal data clock signal. The internal data clock signal IWCK may be provided to the data I / O circuit 195.

[0073] The data I / O circuit 195 may include a data input circuit and a data output circuit. The data input circuit may align and latch the data transmitted through the data bus 15 (see FIG. 1 ) based on the internal data clock signal IWCK. Figure 1 ) to provide write data DIN to the memory cell array 200. The data output circuit may transmit read data DOUT read from the memory cell array 200 as output data DQ to the memory controller 20 based on the internal data clock signal IWCK.

[0074] In a write operation, the data I / O circuit 195 may operate so that write data DQ input from the memory controller 20 is sampled by using the internal data clock signal IWCK, and the data obtained by the sampling is written into the memory cell array 200 by using the internal master clock signal ICK. In addition, in a read operation, the data I / O circuit 195 may operate so that data is read from the memory cell array 200 by using the internal master clock signal ICK, and the read data is transmitted to the memory controller 20 by using the internal data clock signal IWCK.

[0075] The delay control circuit 400 may receive the data clock signal WCK, may generate a plurality of divided-by-two clock signals by dividing the data clock signal WCK by two based on the clock synchronization signal ISYNC, may generate a plurality of divided-by-four clock signals by dividing the first two divided-by-two clock signals by two, may detect the phases of the second two divided-by-two clock signals, may generate a divided-by-two alignment signal indicating whether the divided-by-two clock signal is synchronized with the data clock signal, may detect the phase of the divided-by-four clock signal based on the divided-by-two alignment signal, and may adjust the delay of the main clock signal based on the phase of the divided-by-four clock signal to output the adjusted delay as the delay information LTI of the internal data clock signal IWCK for receiving / transmitting the data DQ. The delay control circuit 400 provides the delay information LTI to the data I / O circuit 195. The data I / O circuit 195 may receive / transmit the data DQ by using the internal data clock signal IWCK according to the delay corresponding to the delay information LTI in the write operation and the read operation.

[0076] In the memory device 100, since the internal main clock signal ICK and the internal data clock signal IWCK are synchronized with each other by the clock synchronization circuit 300, and the delay is controlled based on the synchronized four-frequency clock signal among the four-frequency clock signals, synchronization can be performed between the domain operating based on the internal main clock signal ICK and the domain operating based on the internal data clock signal IWCK. Therefore, the memory device 100 can perform data communication in a high-speed data interface without losing data.

[0077] Figure 6 is a block diagram illustrating a memory device according to one or more example embodiments. For example, Figure 6 The memory device shown in may correspond to Figure 5 The memory device shown in FIG.

[0078] refer to Figure 6 , the memory device 100 includes a control logic circuit 105, an address register 120, a master clock buffer 125, a data clock buffer 127, a bank control logic 129, a refresh counter 145, a row address multiplexer (RAMUX) 140, a column address latch (CA LATCH) 150, a row decoder 160, a column decoder 170, a memory cell array 200, a sense amplifier unit 185, an I / O gating circuit 190, an error correction code (ECC) engine 290, a data I / O circuit 195, a clock synchronization circuit 300, and a delay control circuit 400. The row decoder 160, the column decoder 170, the memory cell array 200, the sense amplifier unit 185, and the I / O gating circuit 190 may be included in Figure 5 In the core circuit 130.

[0079] The memory cell array 200 includes first to eighth bank arrays 210 to 280. The row decoder 160 includes first to eighth bank row decoders 160a to 160h respectively coupled to the first to eighth bank arrays 210 to 280, the column decoder 170 includes first to eighth bank column decoders 170a to 170h respectively coupled to the first to eighth bank arrays 210 to 280, and the sense amplifier unit 185 includes first to eighth bank sense amplifiers 185a to 185h respectively coupled to the first to eighth bank arrays 210 to 280. Each of the first to eighth bank arrays 210 to 280 includes a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL.

[0080] The address register 120 receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 20. The address register 120 provides the received bank address BANK_ADDR to the bank control logic 129, provides the received row address ROW_ADDR to the row address multiplexer 140, and provides the received column address COL_ADDR to the column address latch 150.

[0081] The bank control logic 129 generates a bank control signal based on the bank address BANK_ADDR, activates one of the first to eighth bank row decoders 160a-160h corresponding to the bank address BANK_ADDR based on the bank control signal, and activates one of the first to eighth bank column decoders 170a-170h corresponding to the bank address BANK_ADDR based on the bank control signal.

[0082] The row address multiplexer 140 receives the row address ROW_ADDR from the address register 120 and receives the refresh row address REF_ADDR from the refresh counter 145. The row address multiplexer 140 selectively outputs the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 140 is applied to the first to eighth bank row decoders 160a to 160h.

[0083] The refresh counter 145 may sequentially output the refresh row address REF_ADDR under the control of the control logic circuit 105 .

[0084] One of the first to eighth bank row decoders 160a-160h activated by the bank control logic 129 decodes the row address RA output from the row address multiplexer 140 and activates the word line WL corresponding to the row address RA. For example, the activated bank row decoder applies a word line driving voltage to the word line WL corresponding to the row address RA.

[0085] The column address latch 150 receives the column address COL_ADDR from the address register 120 and temporarily stores the received column address COL_ADDR. In some example embodiments, for example, in a burst mode, the column address latch 150 generates a column address incremented from the received column address COL_ADDR. The column address latch 150 applies the temporarily stored or generated column address to the first to eighth bank column decoders 170a-170h. An activated bank column decoder among the first to eighth bank column decoders 170a-170h activates a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I / O gating circuit 190.

[0086] The I / O selection circuit 190 includes a circuit for selecting input / output data, and also includes input data masking logic, a read data latch for storing data output from the first memory array to the eighth memory array 210~280, and a write driver for writing data to the first memory array to the eighth memory array 210~280.

[0087] The code word CW read from one of the first to eighth memory bank arrays 210-280 is read by a sense amplifier coupled to the one memory bank array from which data is to be read, and is stored in the read data latch. The code word CW stored in the read data latch can be provided as data DOUT to the data I / O circuit 195 after the ECC engine 290 performs ECC decoding on the code word CW.

[0088] Data DIN to be written into one of the first to eighth bank arrays 210 ˜ 280 may be provided from the data I / O circuit 195 to the ECC engine 290 , and the ECC engine 290 may perform ECC encoding on the data DIN.

[0089] The control logic circuit 105 may control the operation of the memory device 100. For example, the control logic circuit 105 may generate a control signal for the memory device 100 so as to perform a write operation or a read operation. The control logic circuit 105 includes a command decoder 110 that decodes a command CMD received from the memory controller 20 and a mode register 112 that sets an operation mode of the memory device 100. For example, the command decoder 110 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The command decoder 110 may generate a clock synchronization signal ISYNC by decoding a clock synchronization command CMD_SYNC.

[0090] Figure 7 An example of a first memory bank array in a memory device according to one or more example embodiments is shown. For example, Figure 7 The first bank array can be Figure 6 implemented in a memory device.

[0091] refer to Figure 7 The first memory bank array 210 includes a plurality of word lines WL1-WLm (m is a natural number greater than 2), a plurality of bit lines BTL1-BTLn (n is a natural number greater than 2), and a plurality of dynamic memory cells MC disposed at intersections between the word lines WL1-WLm and the bit lines BTL1-BTLn. Each of the dynamic memory cells MC includes a cell transistor coupled to one of the word lines WL1-WLm and one of the bit lines BTL1-BTLn, and a cell capacitor coupled to the cell transistor.

[0092] Figure 8 is a block diagram illustrating a clock synchronization circuit according to one or more example embodiments. For example, the clock synchronization circuit may be Figure 5 implemented in a memory device.

[0093] refer to Figure 8 The clock synchronization circuit 300 can divide the data clock signal WCK to generate a plurality of divided-by-two clock signals WCK / 2_0, WCK / 2_90, WCK / 2_180 and WCK / 2_270, and can generate an internal data clock signal IWCK synchronized with the internal master clock signal ICK based on the clock synchronization signal ISYNC.

[0094] The clock synchronization circuit 300 may include a multi-phase generator 320 , a first phase detector 331 , a second phase detector 332 , and a multiplexer circuit 340 .

[0095] The multi-phase generator 320 can shift the phase of the data clock signal WCK by 0 degrees, 90 degrees, 180 degrees, and 270 degrees by using a frequency divider to generate the first to fourth divided-by-two clock signals WCK / 2_0, WCK / 2_90, WCK / 2_180, and WCK / 2_270. For example, the multi-phase generator 320 can generate the first to fourth divided-by-two clock signals WCK / 2_0, WCK / 2_90, WCK / 2_180, and WCK / 2_270, which have phases obtained by phase-shifting the output of the frequency divider receiving the data clock signal WCK as an input by 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively.

[0096] Based on the second divided-by-two clock signal WCK / 2_90, the first phase detector 331 may latch the clock synchronization signal ISYNC to generate the first phase detection signal PDS_90. Based on the fourth divided-by-two clock signal WCK / 2_270, the second phase detector 332 may latch the clock synchronization signal ISYNC to generate the second phase detection signal PDS_270.

[0097] The first phase detector 331 may include a flip-flop that latches the clock synchronization signal ISYNC based on the second divided-by-two clock signal WCK / 2_90 to output the first phase detection signal PDS_90. The second phase detector 332 may include a flip-flop that latches the clock synchronization signal ISYNC based on the fourth divided-by-two clock signal WCK / 2_270 to output the second phase detection signal PDS_270.

[0098] Since the clock synchronization signal ISYNC is generated in association with the internal master clock signal ICK, the second divided-by-two clock signal WCK / 2_90 aligned with the clock synchronization signal ISYNC may be a signal synchronized with the internal master clock signal ICK.

[0099] Fig. 9 is a circuit diagram showing an example of a multiplexer circuit according to one or more example embodiments. For example, Fig. 9 The multiplexer circuit can be Figure 8 The clock synchronization circuit is shown.

[0100] refer to Fig. 9, the multiplexer circuit 340 may include first to fourth multiplexers 341, 343, 345, and 347. The first multiplexer 341 may receive the first divided-by-two clock signal WCK / 2_0 through the first input terminal I1, and may receive the third divided-by-two clock signal WCK / 2_180 through the second input terminal I2, the third divided-by-two clock signal WCK / 2_180 being in a state where its phase is reversed by 180 degrees relative to the first divided-by-two clock signal WCK / 2_0. The first multiplexer 341 may select one signal from among the first divided-by-two clock signal WCK / 2_0 at the first input terminal I1 and the third divided-by-two clock signal WCK / 2_180 at the second input terminal I2 based on the first phase detection signal PDS_90 and the second phase detection signal PDS_270. The first multiplexer 341 may output the selected signal as the first internal data clock signal IWCK / 2_0.

[0101] For example, when the first phase detection signal PDS_90 is at a logic high level and the second phase detection signal PDS_270 is at a logic low level, the first multiplexer 341 may select the first divided-by-two clock signal WCK / 2_0 at the first input terminal I1 as the first internal data clock signal IWCK / 2_0 for output. On the other hand, when the first phase detection signal PDS_90 is at a logic high level and the second phase detection signal PDS_270 is at a logic high level, the first multiplexer 341 may select the third divided-by-two clock signal WCK / 2_180 at the second input terminal I2 as the first internal data clock signal IWCK / 2_0 for output.

[0102] The second multiplexer 343 may receive the second divided-by-two clock signal WCK / 2_90 through the first input terminal I1, and may receive the fourth divided-by-two clock signal WCK / 2_270 through the second input terminal I2, the fourth divided-by-two clock signal WCK / 2_270 being in a state where its phase is reversed by 180 degrees relative to the second divided-by-two clock signal WCK / 2_90. The second multiplexer 343 may select one signal from among the second divided-by-two clock signal WCK / 2_90 and the fourth divided-by-two clock signal WCK / 2_270 based on the first phase detection signal PDS_90 and the second phase detection signal PDS_270 to output as the second internal data clock signal IWCK / 2_90.

[0103] The third multiplexer 345 may receive the third divided-by-two clock signal WCK / 2_180 through the first input terminal I1, and may receive the first divided-by-two clock signal WCK / 2_0 through the second input terminal I2, the first divided-by-two clock signal WCK / 2_0 being in a state where its phase is inverted by 180 degrees relative to the third divided-by-two clock signal WCK / 2_180. The third multiplexer 345 may select one signal from the third divided-by-two clock signal WCK / 2_180 and the first divided-by-two clock signal WCK / 2_0 based on the first phase detection signal PDS_90 and the second phase detection signal PDS_270 to output as the third internal data clock signal IWCK / 2_180.

[0104] The fourth multiplexer 347 may receive the fourth divided-by-two clock signal WCK / 2_270 through the first input terminal I1, and may receive the second divided-by-two clock signal WCK / 2_90 through the second input terminal I2, the second divided-by-two clock signal WCK / 2_90 being in a state where its phase is inverted by 180 degrees relative to the fourth divided-by-two clock signal WCK / 2_270. The fourth multiplexer 347 may select one signal from the fourth divided-by-two clock signal WCK / 2_270 and the second divided-by-two clock signal WCK / 2_90 based on the first phase detection signal PDS_90 and the second phase detection signal PDS_270 to output as the fourth internal data clock signal IWCK / 2_270.

[0105] Fig.10 is a block diagram illustrating a delay control circuit according to one or more example embodiments. Fig.10 The delay control circuit can be Figure 5 implemented in a memory device.

[0106] refer to Fig.10 , the delay control circuit 400 may include a first frequency divider 410, a second frequency divider 420, a first delay unit 430, a second delay unit 440, a first synchronization detector 450, and a delay selector 500. In an example embodiment. The first delay unit 430 and the second delay unit 440 may not be included in the delay control circuit 400. In addition, the delay control circuit 400 may receive the first divided-by-two clock signal to the fourth divided-by-two clock signal WCK / 2_0, WCK / 2_90, WCK / 2_180, and WCK / 2_270 from the clock synchronization circuit 300. In this case, the first frequency divider 410 may not be included in the delay control circuit 400.

[0107] The first frequency divider 410 can divide the data clock signal WCK / WCKB to generate a first divided-by-two clock signal to a fourth divided-by-two clock signal WCK / 2_0, WCK / 2_90, WCK / 2_180 and WCK / 2_270, and can provide the first divided-by-two clock signal WCK / 2_0 and the third divided-by-two clock signal WCK / 2_180 to the second frequency divider 420, and can provide the second divided-by-two clock signal WCK / 2_90 and the fourth divided-by-two clock signal WCK / 2_270 to the first delay unit 430.

[0108] The second frequency divider 420 can divide the first divided-by-two clock signal WCK / 2_0 and the third divided-by-two clock signal WCK / 2_180 (the first two) to generate a first divided-by-four clock signal to a fourth divided-by-four clock signal WCK / 4_0_T, WCK / 4_0_C, WCK / 4_180_T and WCK / 4_180_C, and can provide the first divided-by-four clock signal to the fourth divided-by-four clock signal WCK / 4_0_T, WCK / 4_0_C, WCK / 4_180_T and WCK / 4_180_C to the second delay unit 440.

[0109] The first delay unit 430 may delay the second divided-by-two clock signal WCK / 2_90 and the fourth divided-by-two clock signal WCK / 2_270, and may provide the second delayed divided-by-two clock signal WCK / 2_90D and the fourth delayed divided-by-two clock signal WCK / 2_270D to the first synchronous detector 450. The second delay unit 440 may delay the first to fourth divided-by-four clock signals WCK / 4_0_T, WCK / 4_0_C, WCK / 4_180_T, and WCK / 4_180_C, and may provide the first delayed divided-by-four clock signal to the fourth delayed divided-by-four clock signals WCK / 4_0_TD, WCK / 4_0_CD, WCK / 4_180_TD, and WCK / 4_180_CD to the delay selector 500.

[0110] The first synchronization detector 450 detects the phases of the second delayed divided-by-two clock signal WCK / 2_90D and the fourth delayed divided-by-two clock signal WCK / 2_270D (the second two) based on the clock synchronization signal ISYNC, and provides the divided-by-two alignment signals ALG and MISALG to the delay selector 500, which indicate whether the second delayed divided-by-two clock signal WCK / 2_90D and the fourth delayed divided-by-two clock signal WCK / 2_270D are synchronized with the data clock signal WCK. If the second delayed divided-by-two clock signal WCK / 2_90D is synchronized with the data clock signal WCK, the first synchronization detector 450 outputs the first divided-by-two alignment signal ALG having a high level based on the activation of the clock synchronization signal ISYNC (or activates the first divided-by-two alignment signal ALG). If the fourth delayed divided-by-2 clock signal WCK / 2_270D is synchronized with the data clock signal WCK, the first synchronization detector 450 outputs the second divided-by-2 alignment signal MISALG having a high level (or activates the second divided-by-2 alignment signal MISALG) based on the activation of the clock synchronization signal ISYNC.

[0111] The delay selector 500 receives the first delayed four-divided-frequency clock signal to the fourth delayed four-divided-frequency clock signal WCK / 4_0_TD, WCK / 4_0_CD, WCK / 4_180_TD and WCK / 4_180_CD, detects the phase of the first delayed four-divided-frequency clock signal to the fourth delayed four-divided-frequency clock signal WCK / 4_0_TD, WCK / 4_0_CD, WCK / 4_180_TD and WCK / 4_180_CD, and generates the first four-divided-frequency alignment signal to the fourth four-divided-frequency alignment signal. The first to fourth divided-by-four alignment signals are used to adjust the delay LTC of the main clock signal CK based on one of the first to fourth delayed divided-by-four clock signals WCK / 4_0_TD, WCK / 4_0_CD, WCK / 4_180_TD, and WCK / 4_180_CD that corresponds to the synchronized one of the first to fourth divided-by-four alignment signals, and provide the adjusted delay as the delay information LTI of the internal data clock signal IWCK for the data I / O circuit 195. Each of the first to fourth divided-by-four alignment signals may indicate whether a corresponding one of the first to fourth delayed divided-by-four clock signals WCK / 4_0_TD, WCK / 4_0_CD, WCK / 4_180_TD, and WCK / 4_180_CD is synchronized with the data clock signal WCK.

[0112] In an example embodiment, the delay selector 500 can generate the first four-division alignment signal to the fourth four-division alignment signal by detecting the phases of the first four-division clock signal to the fourth four-division clock signal WCK / 4_0_T, WCK / 4_0_C, WCK / 4_180_T and WCK / 4_180_C instead of detecting the phases of the first delayed four-division clock signal to the fourth delayed four-division clock signal WCK / 4_0_TD, WCK / 4_0_CD, WCK / 4_180_TD and WCK / 4_180_CD.

[0113] Fig.11 is a block diagram illustrating a delay selector according to one or more example embodiments. Fig.11 The delay selector shown in Fig.10 The delay control circuit is implemented in the

[0114] refer to Fig.11 , the delay selector 500 may include a second synchronous detector 510 , a third synchronous detector 520 , and a selection circuit 530 .

[0115] The second synchronization detector 510 detects the phases of the first and second four-divided clock signals WCK / 4_0_T and WCK / 4_0_C based on the first divide-by-two alignment signal ALG, and provides the first and second four-divided frequency alignment signals ALG_T and ALG_C indicating whether the first and second four-divided frequency clock signals WCK / 4_0_T and WCK / 4_0_C are synchronized with the data clock signal WCK to the selection circuit 530. The third synchronization detector 520 detects the phases of the third and fourth four-divided frequency clock signals WCK / 4_180_T and WCK / 4_180_C based on the second divide-by-two alignment signal MISALG, and provides the third and fourth four-divided frequency alignment signals MISALG_T and MISALG_C indicating whether the third and fourth four-divided frequency clock signals WCK / 4_180_T and WCK / 4_180_C are synchronized with the data clock signal WCK to the selection circuit 530.

[0116] The selection circuit 530 receives the first to fourth quarter-divided clock signals WCK / 4_0_T, WCK / 4_0_C, WCK / 4_180_T and WCK / 4_180_C, adjusts the delay of a quarter-divided clock signal among the first to fourth quarter-divided clock signals WCK / 4_0_T, WCK / 4_0_C, WCK / 4_180_T and WCK / 4_180_C corresponding to an activated quarter-divided clock signal among the first to fourth quarter-divided clock signals ALG_T, ALG_C, MISALG_T and MISALG_C based on the main clock signal CK, and provides the delay information LTI associated with the data clock signal WCK to the data I / O circuit 195.

[0117] Fig.12 A second synchronous detector according to one or more example embodiments is shown. For example, Fig.12 The second synchronous detector shown in FIG. Fig.11 The delay selector shown in FIG.

[0118] refer to Fig.12 , the second synchronous detector 510 may include a trigger 511 and a trigger 513 and an inverter 512 and an inverter 514. The trigger 511 and the trigger 513 may be D triggers. The inverter 512 inverts the first divided-by-four clock signal WCK / 4_0_T. The trigger 511 latches the output of the inverter 512 based on the rising edge of the first divided-by-two alignment signal ALG to output the first divided-by-four alignment signal ALG_T. The inverter 514 inverts the second divided-by-four clock signal WCK / 4_0_C. The trigger 513 latches the output of the inverter 514 based on the rising edge of the first divided-by-two alignment signal ALG to output the second divided-by-four alignment signal ALG_C.

[0119] Fig.13 An example of a third synchronous detector according to one or more example embodiments is shown. For example, Fig.13 The third synchronous detector shown in FIG. Fig.11 The delay selector shown in FIG.

[0120] refer to Fig.13, the third synchronous detector 520 may include a trigger 521 and a trigger 523 and an inverter 522 and an inverter 524. The trigger 521 and the trigger 523 may be D triggers. The inverter 522 inverts the third four-division clock signal WCK / 4_180_T. The trigger 521 latches the output of the inverter 522 based on the rising edge of the second two-division alignment signal MISALG to output the third four-division alignment signal MISALG_T. The inverter 524 inverts the fourth four-division clock signal WCK / 4_180_C. The trigger 523 latches the output of the inverter 524 based on the rising edge of the second two-division alignment signal MISALG to output the fourth four-division alignment signal MISALG_C.

[0121] Fig.14 is a block diagram showing an example of a selection circuit according to one or more embodiments. Fig.14 The selection circuit shown in Fig.11 The delay selector shown in FIG.

[0122] refer to Fig.14 , the selection circuit 530 a may include first to fourth delay adjustment circuits (LACs) 540 , 560 , 570 , and 580 and an OR gate 590 . Each of the first to fourth delay adjustment circuits 540, 560, 570 and 580 can receive the delay LTC associated with the main clock signal CK, can receive a corresponding one of the first to fourth quarter-frequency alignment signals ALG_T, ALG_C, MISALG_T and MISALG_C, can be enabled based on an activated corresponding one of the first to fourth quarter-frequency alignment signals ALG_T, ALG_C, MISALG_T and MISALG_C, can adjust the delay LTC associated with the main clock signal CK based on a corresponding one of the first to fourth quarter-frequency alignment signals WCK / 4_0_T, WCK / 4_0_C, WCK / 4_180_T and WCK / 4_180_C, and can provide a corresponding one of the adjusted delays to the OR gate 590 as a corresponding one of the sub-delay information STL11, STLI2, STLI3 and STLI4. The OR gate 590 performs an OR operation on the sub-delay information STL11 , STLI2 , STLI3 , and STLI4 to provide delay information LTI to the data I / O circuit 195 .

[0123] Fig.15 is a circuit diagram illustrating a first delay adjustment circuit according to one or more example embodiments. For example, Fig.15 The first delay adjustment circuit shown in FIG. Fig.14 is implemented in the selection circuit shown in .

[0124] The configuration of each of the second to fourth delay adjustment circuits 560 , 570 , and 580 may be substantially the same as that of the first delay adjustment circuit 540 .

[0125] refer to Fig.15 The first delay adjustment circuit 540 includes flip-flops 541-545, a NAND gate 546, multiplexers (MUX) 547-549 and clock control logic (CCTL) 551-555. The flip-flops 541-545 may be D flip-flops.

[0126] The flip-flops 541-545, the NAND gates 546, the multiplexers 547-549 and the clock control logic 551-555 can be as follows: Fig.15 Connections shown.

[0127] The flip-flop 541 latches the level of the delayed LTC associated with the main clock signal CK based on the rising edge of the first delayed four-frequency clock signal WCK / 4_0_TD provided from the clock control logic 551 and outputs the latched level. The NAND gate 546 performs a "NAND" operation on the selection signal FS1 and the output of the flip-flop 541. The flip-flop 542 latches the output of the NAND gate 546 based on the rising edge of the delayed four-frequency clock signal WCK / 4_0_TD3 provided from the clock control logic 552. Each of the multiplexers 547 to 549 outputs one of the first input and the second input based on a corresponding one of the selection signals FS2, FS3, and FS4. The first input of each of the multiplexers 547 to 549 can be the output of the flip-flop 541, and the second input of each of the multiplexers 547 to 549 can be the output of the corresponding one of the flip-flops 542 to 544. The clock control logic 551-555 can provide the first delayed four-frequency clock signal WCK / 4_0_TD, the delayed four-frequency clock signal WCK / 4_0_TD3, WCK / 4_0_TD2, WCK / 4_0_TD1 and the first four-frequency clock signal WCK / 4_0_T to the first input of the flip-flops 541-545 respectively based on the first four-frequency adjustment signal ALG_T. The delay LTC associated with the main clock signal CK is adjusted by the selection signals FS1-FS4, and the adjusted delay is provided as the first sub-delay information STLI1 at the output of the flip-flop 545. The selection signals FS1-FS4 can be provided from the outside of the delay selector 500.

[0128] Fig.16 is a block diagram showing a selection circuit according to one or more embodiments. For example, Fig.16 The selection circuit shown in Fig.11 The delay selector shown in FIG.

[0129] refer to Fig.16 , the selection circuit 530b may include first to fourth delay adjustment circuits 540a, 560a, 570a, and 580a and a multiplexer (e.g., delay multiplexer) 595. Each of the first to fourth delay adjustment circuits 540a, 560a, 570a, and 580a may receive a delay LTC associated with the main clock signal CK, may adjust the delay LTC associated with the main clock signal CK based on a corresponding one of the first to fourth divided-by-four clock signals WCK / 4_0_T, WCK / 4_0_C, WCK / 4_180_T, and WCK / 4_180_C, and may provide a corresponding one of the adjusted delays to the multiplexer 595 as a corresponding one of the sub-delay information STL11, STLI2, STLI3, and STLI4. The multiplexer 595 can select one of the sub-delay information STL11, STLI2, STLI3 and STLI4 based on an activated one of the first to fourth quarter-frequency alignment signals ALG_T, ALG_C, MISALG_T and MISALG_C to provide delay information LTI to the data I / O circuit 195.

[0130] Fig.17A , Fig. 17B , Fig. 17C and Fig.17D A timing control diagram of a delay control circuit according to one or more example embodiments is shown. For example, the timing control diagram may correspond to Fig.10 Delay control circuit.

[0131] exist Fig.17A , Fig. 17B , Fig. 17C and Fig.17D In the process, the data clock signal WCK is received normally.

[0132] refer to Fig.17A As shown by reference numerals 611 and 613, the second divided-by-two clock signal WCK / 2_90 and the first divided-by-four clock signal WCK / 4_0_T are synchronized with the data clock signal WCK, and the first divided-by-two alignment signal ALG and the first divided-by-four alignment signal ALG_T are transformed into a high level from time point T21.

[0133] refer to Fig. 17B As shown by reference numerals 611 and 615, the second divided-by-two clock signal WCK / 2_90 and the second divided-by-four clock signal WCK / 4_0_C are synchronized with the data clock signal WCK, and the first divided-by-two alignment signal ALG and the second divided-by-four alignment signal ALG_C are changed to a high level from time point T21.

[0134] refer to Fig. 17C As shown by reference numerals 621 and 623, the fourth two-division clock signal WCK / 2_270 and the third four-division clock signal WCK / 4_180_T are synchronized with the data clock signal WCK, and the second two-division alignment signal MISALG and the third four-division alignment signal MISALG_T are transformed into a high level from time point T31.

[0135] refer to Fig.17D As shown by reference numerals 621 and 625, the fourth divided-by-two clock signal WCK / 2_270 and the fourth divided-by-four clock signal WCK / 4_180_C are synchronized with the data clock signal WCK, and the second divided-by-two alignment signal MISALG and the fourth divided-by-four alignment signal MISALG_C are transformed into a high level from time point T31.

[0136] Fig.18A , Fig.18B , Fig. 18C and Fig.18D A timing control diagram of a delay control circuit according to one or more example embodiments is shown. For example, the timing control diagram may correspond to Fig.10 Delay control circuit.

[0137] exist Fig.18A , Fig.18B , Fig. 18C and Fig.18D In the embodiment, before the clock synchronization signal ISYNC changes to a high level, as shown by reference numeral 630, the data clock signal WCK is abnormally received.

[0138] refer to Fig.18A , as shown in reference numerals 631 and 633, the second divided-by-two clock signal WCK / 2_90 and the first divided-by-four clock signal WCK / 4_0_T are synchronized with the data clock signal WCK, and the first divided-by-two alignment signal ALG and the first divided-by-four alignment signal ALG_T are transformed into a high level from time point T41.

[0139] refer to Fig.18B As shown by reference numerals 631 and 635, the second divided-by-two clock signal WCK / 2_90 and the second divided-by-four clock signal WCK / 4_0_C are synchronized with the data clock signal WCK, and the first divided-by-two alignment signal ALG and the second divided-by-four alignment signal ALG_C are changed to a high level from time point T41.

[0140] refer to Fig. 18CAs shown in reference numerals 641 and 643, the fourth two-division clock signal WCK / 2_270 and the third four-division clock signal WCK / 4_180_T are synchronized with the data clock signal WCK, and the second two-division alignment signal MISALG and the third four-division alignment signal MISALG_T are transformed into a high level from time point T51.

[0141] refer to Fig.18D As shown in reference numerals 641 and 645, the fourth two-division clock signal WCK / 2_270 and the fourth four-division clock signal WCK / 4_180_C are synchronized with the data clock signal WCK, and the second two-division alignment signal MISALG and the fourth four-division alignment signal MISALG_C are transformed into a high level from time point T51.

[0142] exist Figures 10 to 16 , Fig.17A , Fig. 17B , Fig. 17C , Fig.17D , Fig.18A , Fig.18B , Fig. 18C and Fig.18D In the embodiment, the second frequency divider 420 may use the second divided-by-two clock signal WCK / 2_90 and the fourth divided-by-two clock signal WCK / 2_270 instead of the first divided-by-two clock signal WCK / 2_0 and the third divided-by-two clock signal WCK / 2_180.

[0143] Fig.19 is a flowchart illustrating a method of operating a memory device according to example embodiments.

[0144] refer to Figures 5 to 16 , Fig.17A , Fig. 17B , Fig. 17C , Fig.17D , Fig.18A , Fig.18B , Fig. 18C , Fig.18D and Fig.19In the method of operating the memory device 100, in operation S510, the delay control circuit 400 generates a plurality of divided-by-two clock signals WCK / 2_0, WCK / 2_90, WCK / 2_180, and WCK / 2_270 based on the data clock signal WCK. In operation S520, the delay control circuit 400 divides the first two divided-by-two clock signals WCK / 2_0 and the divided-by-two clock signal WCK / 2_180 to generate a first divided-by-four clock signal to a fourth divided-by-four clock signal WCK / 4_0_T, WCK / 4_0_C, WCK / 4_180_T, and WCK / 4_180_C. In operation S530, the delay control circuit 400 detects the phases of the second two divided-by-two clock signals WCK / 2_90 and the divided-by-two clock signal WCK / 2_270 to generate a divided-by-two alignment signal ALG and a divided-by-two alignment signal MISALG indicating whether the divided-by-two clock signals WCK / 2_90 and the divided-by-two clock signal WCK / 2_270 are synchronized with the data clock signal WCK. In operation S540, the delay control circuit 400 detects the phases of the divided-by-four clock signals WCK / 4_0_T, WCK / 4_0_C, WCK / 4_180_T, and WCK / 4_180_C, and adjusts the delay LTC associated with the main clock signal CK to output the adjusted delay as the delay information LTI. In operation S550, the data I / O circuit 195 receives / transmits data according to the delay corresponding to the delay information LTI.

[0145] Fig. 20 is a block diagram illustrating a memory device according to one or more example embodiments.

[0146] refer to Fig. 20 , the memory device 700 as a stacked memory device may include a first group of wafers 710 and a second group of wafers 720 .

[0147] The first group of wafers 710 may include at least one buffer wafer 711. The second group of wafers 720 may include a plurality of memory wafers 720-1 to 720-p which are stacked on the first group of wafers 710 and transmit data through a plurality of through silicon via (TSV) lines.

[0148] At least one of the memory dies 720-1 to 720-p may include a memory cell array (MCA) 722 for storing data. The memory cell array 722 includes a plurality of dynamic memory cells.

[0149] The buffer chip 711 may include an ECC engine 712, and when a transmission error is detected from the transmission data received through the TSV line, the ECC engine 712 corrects the transmission error using the transmission parity bit and generates error-corrected data. The ECC engine 712 may be referred to as a "pass ECC engine". The buffer chip 711 may also include a clock control circuit 714 and a data I / O circuit 716. The clock control circuit 714 may be the above-mentioned clock synchronization circuit and delay control circuit, and may receive the data clock signal WCK to provide the internal data clock signal IWCK and delay information LTI to the data I / O circuit 716. The data I / O circuit 716 may receive / send data DQ by using the internal data clock signal IWCK according to the delay corresponding to the delay information LTI in a write operation and a read operation.

[0150] The memory device 700 may be a stacked chip type memory device or a stacked memory device, which transmits data and control signals through TSV lines. The TSV lines may also be referred to as "via electrodes."

[0151] Through the above description, the data TSV line group 732 formed at one memory die 720 - p may include TSV lines L1 to Ls, and the parity TSV line group 734 may include TSV lines L10 to Lt. Here, s and t are integers greater than 1.

[0152] The TSV lines L1 to Ls in the data TSV line group 732 and the parity TSV lines L10 to Lt in the parity TSV line group 734 may be connected to micro bumps MCBs which are correspondingly formed between the memory wafers 720 - 1 to 720 - p .

[0153] The memory device 700 may have a three-dimensional (3D) chip structure or a two-and-a-half-dimensional (2.5D) chip structure to communicate with the host through a data bus B10. The buffer chip 711 may be connected to the memory controller through the data bus B10.

[0154] The ECC engine 712, referred to as a pass ECC engine, may determine whether a transmission error has occurred in the transmission data received through the data TSV line group 732 based on the transmission parity bits received through the parity TSV line group 734. When a transmission error is detected, the ECC engine 712 may correct the transmission data using the transmission parity bits. When the transmission error is uncorrectable, the ECC engine 712 may output information indicating that an uncorrectable data error has occurred.

[0155] Fig.21 is a cross-sectional view of a 3D chip structure according to one or more example embodiments. For example, Fig.21 The 3D chip structure shown in Fig. 20 semiconductor memory devices.

[0156] Fig.21 A 3D chip structure 800 is shown in which a host and a high bandwidth memory (HBM) are directly connected without an interposer layer.

[0157] refer to Fig.21 , a host wafer 810 such as a system on chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU) may be disposed on a printed circuit board (PCB) 820 using flip chip bumps FB. Memory wafers D11 to D14 may be stacked on the host wafer 810 to implement a system such as Fig. 20 The HBM structure of the memory chip 720 in FIG. Fig.21 In, omitted Fig. 20 The buffer wafer 711 or logic wafer in the host wafer 810. However, the buffer wafer 711 or logic wafer may be disposed between the memory wafer D11 and the host wafer 810. In order to realize an HBM structure such as the memory wafer 720, TSV lines may be formed at the memory wafer D11 and the memory wafer D14. The TSV lines may be electrically connected to the microbumps MCB placed between the memory wafers.

[0158] Fig. 22 is a configuration diagram illustrating a semiconductor package including a memory device according to one or more example embodiments.

[0159] refer to Fig. 22 , the semiconductor package 900 may include one or more memory devices 910 and a memory controller (CONT) 920. For example, the memory devices 910 may be stacked.

[0160] The stacked memory device 910 and the memory controller 920 may be mounted on an interposer 930, and the interposer 930 on which the stacked memory device 910 and the memory controller 920 are mounted may be mounted on a package substrate 940. The memory controller 920 may correspond to a semiconductor device that may perform a memory control function, for example, the memory controller 920 may be implemented as an application processor (AP).

[0161] The stacked memory device 910 may be implemented in various forms, and the stacked memory device 910 may be a high bandwidth memory (HBM) in which a plurality of layers are stacked.

[0162] Thus, the stacked memory device 910 may include a buffer die and a plurality of memory dies. Additionally, the buffer die may include a clock control circuit.

[0163] A plurality of stacked memory devices 910 may be mounted on an interposer 930, and a memory controller 920 may communicate with the plurality of stacked memory devices 910. Here, the interposer 930 may include a TSV form, a non-TSV embedded multi-die interconnect bridge (EMIB), or a printed circuit board (PCB) form.

[0164] Aspects of the present disclosure may be applied to various memory devices using a data clock signal and a master clock signal.

[0165] The foregoing is an illustration of example embodiments and should not be construed as limiting the present disclosure. Although some example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made to the example embodiments without substantially departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims.

Claims

1. A memory device, comprising: a clock buffer configured to receive a master clock signal and provide an internal master clock signal to a core circuit; A data clock buffer, configured to receive a data clock signal; and a delay control circuit configured to generate delay information based on the data clock signal and provide the delay information to a data input / output circuit, Wherein, the delay control circuit comprises: A first frequency divider configured to generate a plurality of divided-by-two clock signals based on the data clock signal, wherein the plurality of divided-by-two clock signals include a first group of divided-by-two clock signals and a second group of divided-by-two clock signals; a second frequency divider configured to generate a plurality of divided-by-four clock signals based on the first set of divided-by-two clock signals; a first synchronization detector configured to output a plurality of divide-by-two alignment signals indicating whether the second group of divided-by-two clock signals are synchronized with the data clock signal, wherein the plurality of divide-by-two alignment signals are generated based on a phase of the second group of divided-by-two clock signals based on a clock synchronization signal; and A delay selector is configured to automatically detect phases of the plurality of divided-by-four clock signals based on the plurality of divided-by-two alignment signals, and adjust a delay of the master clock signal based on the phases of the plurality of divided-by-four clock signals.

2. The memory device according to claim 1, wherein: The delay selector is also configured to generate a plurality of divided-by-four alignment signals indicating whether the plurality of divided-by-four clock signals are synchronized with the data clock signal, and adjust the delay of the master clock signal based on at least one of the plurality of divided-by-four alignment signals and a corresponding one of the plurality of divided-by-four clock signals.

3. The memory device of claim 1 , wherein: The plurality of divided-by-two clock signals include a first divided-by-two clock signal, a second divided-by-two clock signal, a third divided-by-two clock signal, and a fourth divided-by-two clock signal; The first group of divided-by-two clock signals includes the second divided-by-two clock signal and the fourth divided-by-two clock signal. The second divided-by-two clock signal and the fourth divided-by-two clock signal have a phase difference of 180 degrees relative to each other; The second group of divided-by-two clock signals includes the first divided-by-two clock signal and the third divided-by-two clock signal. The first divided-by-two clock signal and the third divided-by-two clock signal have a phase difference of 180 degrees relative to each other; and The first divided-by-two clock signal and the second divided-by-two clock signal have a phase difference of 90 degrees with respect to each other.

4. The memory device according to claim 3, wherein: The first synchronization detector is further configured to activate a first divide-by-two alignment signal of the plurality of divide-by-two alignment signals based on a falling edge of the second divide-by-two clock signal.

5. The memory device according to claim 3, wherein: The first synchronous detector is further configured to activate a second divide-by-two alignment signal among the plurality of divide-by-two alignment signals based on a falling edge of the fourth divide-by-two clock signal.

6. The memory device according to claim 1, wherein: The delay selector comprises: a second synchronization detector configured to output a first divided-by-four alignment signal and a second divided-by-four alignment signal based on a first divided-by-two alignment signal among the plurality of divided-by-two alignment signals, the first divided-by-four alignment signal and the second divided-by-four alignment signal respectively indicating whether a first divided-by-four clock signal and a second divided-by-four clock signal among the plurality of divided-by-four clock signals are synchronized with the data clock signal; a third synchronization detector configured to output a third divide-by-four alignment signal and a fourth divide-by-four alignment signal based on a second divide-by-two alignment signal among the plurality of divide-by-two alignment signals, the third divide-by-four alignment signal and the fourth divide-by-four alignment signal respectively indicating whether a third divide-by-four clock signal and a fourth divide-by-four clock signal among the plurality of divide-by-four clock signals are synchronized with the data clock signal; and A selection circuit is configured to: receive the multiple divided-by-four clock signals, adjust multiple delays associated with the multiple divided-by-four clock signals based on the first divided-by-four clock signal, the second divided-by-four clock signal, the third divided-by-four clock signal, and the fourth divided-by-four clock signal, respectively, and select one of the adjusted multiple delays as the delay information.

7. The memory device according to claim 6, wherein: The selection circuit is configured to select an adjusted delay corresponding to activation of one of the first divide-by-four alignment signal, the second divide-by-four alignment signal, the third divide-by-four alignment signal, and the fourth divide-by-four alignment signal as the delay information.

8. The memory device according to claim 6, wherein: The second synchronous detector is further configured to: activating the first divide-by-four alignment signal based on the first divide-by-four clock signal having a low level at an edge of the first divide-by-two alignment signal; and The second divide-by-four alignment signal is activated based on the second divide-by-four clock signal having a low level at the edge of the first divide-by-two alignment signal.

9. The memory device according to claim 6, wherein: The third synchronous detector is configured as: activating the third divide-by-four alignment signal based on the third divide-by-four clock signal having a low level at an edge of the second divide-by-two alignment signal; and The fourth divide-by-four alignment signal is activated based on the fourth divided-by-four clock signal having a low level at the edge of the second divide-by-two alignment signal.

10. The memory device according to claim 6, wherein: The second synchronous detector comprises: A first inverter configured to invert the first divided-by-four clock signal; a first flip-flop configured to latch the output of the first inverter based on a first edge of the first divide-by-two alignment signal to generate the first divide-by-four alignment signal; a second inverter configured to invert the second divided-by-four clock signal; and A second flip-flop is configured to latch the output of the second inverter based on the first edge of the first divide-by-two alignment signal to generate the second divide-by-four alignment signal.

11. The memory device according to claim 10, wherein: The second synchronous detector further comprises: a third inverter configured to invert the third divided-by-four clock signal; a third flip-flop configured to latch the output of the third inverter based on a second edge of the second divided-by-two alignment signal to generate the third divided-by-four alignment signal; a fourth inverter configured to invert the fourth divided-by-four clock signal; and a fourth flip-flop configured to latch the output of the fourth inverter based on the second edge of the second divide-by-two alignment signal to generate the fourth divide-by-four alignment signal.

12. The memory device according to claim 6, wherein: The selection circuit comprises: a first delay adjustment circuit configured to: receive the delay, adjust the delay based on the first divided-by-four clock signal, and output a first adjusted delay as first sub-delay information based on the first divided-by-four alignment signal being activated; a second delay adjustment circuit configured to: receive the delay, adjust the delay based on the second divided-by-four clock signal, and output a second adjusted delay as second sub-delay information based on the second divided-by-four alignment signal being activated; a third delay adjustment circuit configured to: receive the delay, adjust the delay based on the third divided-by-four clock signal, and output a third adjusted delay as third sub-delay information based on the third divided-by-four alignment signal being activated; a fourth delay adjustment circuit configured to: receive the delay, adjust the delay based on the fourth divided-by-four clock signal, and output a fourth adjusted delay as fourth sub-delay information based on the fourth divided-by-four alignment signal being activated; and An OR gate is configured to generate the delay information by performing an OR operation on the first sub-delay information, the second sub-delay information, the third sub-delay information, and the fourth sub-delay information.

13. The memory device of claim 12, wherein: One of the first, second, third and fourth delay adjustment circuits is enabled based on the first, second, third and fourth divide-by-four alignment signals.

14. The memory device according to claim 6, wherein: The selection circuit comprises: a first delay adjustment circuit configured to: receive the delay, adjust the delay based on the first divided-by-four clock signal, and output first sub-delay information; a second delay adjustment circuit configured to: receive the delay, adjust the delay based on the second divided-by-four clock signal, and output second sub-delay information; a third delay adjustment circuit configured to: receive the delay, adjust the delay based on the third divided-by-four clock signal, and output third sub-delay information; a fourth delay adjustment circuit configured to: receive the delay, adjust the delay based on the fourth divided-by-four clock signal, and output fourth sub-delay information; and A multiplexer is configured to select one of the first sub-delay information, the second sub-delay information, the third sub-delay information and the fourth sub-delay information as the delay information for output based on the first four-division frequency alignment signal, the second four-division frequency alignment signal, the third four-division frequency alignment signal and the fourth four-division frequency alignment signal.

15. A memory device comprising: A memory cell array comprising a plurality of memory bank arrays; a command decoder configured to output a clock synchronization signal based on a clock synchronization command synchronized with the master clock signal; a bank control logic configured to generate a plurality of bank control signals based on the bank addresses in the address signal to control the plurality of bank arrays; a clock synchronization circuit configured to: generate a plurality of divided-by-two clock signals based on a data clock signal, and output one of the plurality of divided-by-two clock signals as an internal data clock signal; a delay control circuit configured to: generate a plurality of divided-by-four clock signals based on a first group of the plurality of divided-by-two clock signals, generate a plurality of divided-by-two alignment signals indicating whether the plurality of divided-by-two clock signals are synchronized with the data clock signal based on the clock synchronization signal, identify phases of the plurality of divided-by-four clock signals based on the plurality of divided-by-two alignment signals, and adjust a delay associated with the master clock signal based on the phases of the plurality of divided-by-four clock signals to output delay information associated with the internal data clock signal; and a data input / output circuit configured to transmit and receive data based on the internal data clock signal and the delay information, Each of the plurality of memory bank arrays includes a plurality of dynamic memory cells coupled to a plurality of word lines and a plurality of bit lines.

16. The memory device of claim 15, wherein: The delay control circuit comprises: a frequency divider configured to generate the plurality of divided-by-four clock signals based on a first set of divided-by-two clock signals among the plurality of divided-by-two clock signals; a first synchronization detector configured to output the plurality of divide-by-two alignment signals based on the clock synchronization signal, the plurality of divide-by-two alignment signals indicating whether a second group of divide-by-two clock signals among the plurality of divide-by-two clock signals is synchronized with the data clock signal; and A delay selector is configured to identify phases of the plurality of divided-by-four clock signals based on the plurality of divided-by-two alignment signals, and adjust a delay of the master clock signal based on the phases of the plurality of divided-by-four clock signals.

17. The memory device of claim 16, wherein: The delay selector is also configured to generate a plurality of four-division alignment signals respectively indicating whether each of the plurality of four-division clock signals is synchronized with the data clock signal, and adjust the delay based on at least one of the plurality of four-division alignment signals and a corresponding one of the plurality of four-division clock signals.

18. The memory device of claim 15, further comprising: An error correction code engine is configured to perform error correction code encoding and error correction code decoding on the data.

19. The memory device of claim 15, further comprising: A data clock buffer is configured to receive the data clock signal and provide the data clock signal to the clock synchronization circuit and the delay control circuit.

20. A memory device comprising: at least one buffer wafer; and a plurality of memory chips stacked on the at least one buffer chip and configured to transmit and receive data through a plurality of through silicon via lines, wherein at least one of the plurality of memory chips comprises a memory cell array, and Wherein, the at least one buffer chip comprises: a clock synchronization circuit configured to generate a plurality of divided-by-two clock signals based on the data clock signal, and output one of the plurality of divided-by-two clock signals as an internal data clock signal; a delay control circuit configured to: generate a plurality of divided-by-four clock signals based on a first group of the plurality of divided-by-two clock signals, generate a plurality of divided-by-two alignment signals indicating whether the plurality of divided-by-two clock signals are synchronized with the data clock signal based on a clock synchronization signal, identify phases of the plurality of divided-by-four clock signals based on the plurality of divided-by-two alignment signals, adjust a delay of a master clock signal based on the phases of the plurality of divided-by-four clock signals, and output delay information associated with the internal data clock signal; and A data input / output circuit is configured to transmit and receive the data based on the internal data clock signal and the delay information.

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