A hermetic sealing device and hermetic sealing method

Abstract

The present invention discloses an airtight package device and an airtight package method, wherein the airtight package device comprises: a lower package structure comprises a first ceramic substrate, the first ceramic substrate is provided with a first through hole, and the metal in the first through hole is recorded as a first metal column; a first chip is arranged on the first ceramic substrate, and the pad of the first chip is connected to the first metal column; an intermediate package structure is arranged on the lower package structure, and comprises a second ceramic substrate, the second ceramic substrate is provided with a second through hole, and the metal in the second through hole is recorded as a second metal column; a second chip is arranged on the second ceramic substrate, and the pad of the second chip is connected to the second metal column, and the second metal column connected to the second chip is connected to the first chip or the first metal column through a conductive structure; an upper package structure is arranged on the intermediate package structure. The present invention forms two vertical package cavities, and sensitive components are stored separately, avoiding secondary packaging and improving integration.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to an airtight packaging device and an airtight packaging method. Background Art

[0002] From cellular communication networks with a frequency of several hundred megahertz, to the current 4G communication and the soon-to-be-popular 5G communication with a frequency of tens of gigahertz, to the THz field, the operating frequency bands of RF microwave circuits are getting higher and higher. Although the corresponding chip packaging has been upgraded for many times, there are still many shortcomings.

[0003] As the functional integration of chips increases and the size of devices decreases, the integrated design of chips, chip adapters and housings becomes increasingly critical. Currently, in order to meet the different usage requirements of chips during chip packaging, it is often necessary to package sensitive chips independently, and then connect the independently packaged chips to the chips in the hermetic packaging device, which reduces the integration of the hermetic packaging device. Summary of the invention

[0004] The embodiments of the present invention provide a hermetic packaging device and a hermetic packaging method, aiming to solve the problem of low integration of the current hermetic packaging device.

[0005] A first aspect of an embodiment of the present invention provides a hermetic packaging device, comprising:

[0006] The lower packaging structure adopts a first ceramic substrate as a mounting base plate, the first ceramic substrate is provided with a first through hole penetrating the upper surface and the lower surface of the first ceramic substrate, the first through hole is filled with metal, and the metal in the first through hole is recorded as a first metal column;

[0007] A first chip is disposed on the first ceramic substrate, wherein a pad of the first chip is connected to a first metal column through a first bonding wire;

[0008] an intermediate packaging structure, arranged on the lower packaging structure, wherein the intermediate packaging structure uses a second ceramic substrate as an intermediate mounting plate, the second ceramic substrate is provided with a second through hole penetrating the upper surface and the lower surface of the second ceramic substrate, the second through hole is filled with metal, the metal in the second through hole is recorded as a second metal column, and the lower packaging structure and the intermediate packaging structure form a first packaging cavity for accommodating a first chip;

[0009] A second chip is disposed on the second ceramic substrate, a pad of the second chip is connected to a second metal column via a second bonding wire, and the second metal column connected to the second chip is connected to the first chip or the first metal column via a conductive structure;

[0010] The upper packaging structure is arranged on the middle packaging structure, and the middle packaging structure and the upper packaging structure form a second packaging cavity for accommodating the second chip.

[0011] In an embodiment of the present application, the conductive structure is a spring column, a first end of the spring column is connected to a first chip or a first metal column, and a second end of the spring column is connected to a second metal column connected to a second chip.

[0012] In an embodiment of the present application, the lower packaging structure includes:

[0013] a first ceramic substrate;

[0014] A first metal surrounding frame is arranged on the first ceramic substrate at a position for setting the first metal surrounding frame;

[0015] The intermediate packaging structure comprises:

[0016] a second ceramic substrate;

[0017] A front metal surrounding frame is arranged on the front of the second ceramic substrate at a position for setting the front metal surrounding frame;

[0018] A back metal enclosure frame is arranged on the back of the second ceramic substrate at a position for setting the back metal enclosure frame, and the lower surface of the back metal enclosure frame is connected to the upper surface of the first metal enclosure frame;

[0019] The upper packaging structure comprises:

[0020] Cover plate;

[0021] The second metal enclosure is arranged under the cover plate at a position for arranging the second metal enclosure, and the lower surface of the second metal enclosure is connected to the upper surface of the front metal enclosure.

[0022] In an embodiment of the present application, an isolation layer is provided on the lower surface of the second ceramic substrate.

[0023] In an embodiment of the present application, the hermetic packaging device further includes:

[0024] The copper heat-conducting pillars are arranged on the back side of the first ceramic substrate, wherein at least a preset number of the copper heat-conducting pillars are connected to the first metal pillars as input and output pins of the hermetic package device.

[0025] In an embodiment of the present application, the first metal pillar connected to the pad connected to the first chip is recorded as a conductive pillar, and a signal shielding structure formed by a circle of first metal pillars is further provided around the conductive pillar.

[0026] A second aspect of an embodiment of the present invention provides a hermetic packaging method, comprising:

[0027] Mounting a first chip on the prepared lower package structure;

[0028] Mounting a second chip on the prepared intermediate package structure;

[0029] Welding the middle packaging structure above the lower packaging structure, and connecting the second metal column connected to the second chip to the first chip through the conductive structure to form a first packaging cavity for accommodating the first chip;

[0030] The prepared upper packaging structure is welded on top of the middle packaging structure to form a second packaging cavity for accommodating the second chip.

[0031] In an embodiment of the present application, a specific method for preparing the lower packaging structure includes:

[0032] Preparing a first through hole on the first ceramic substrate, wherein the first through hole penetrates the upper surface and the lower surface of the first ceramic substrate;

[0033] Filling metal in the first through hole to form a first metal column penetrating the upper surface and the lower surface of the first ceramic substrate;

[0034] Making a first metal frame at a location reserved for making a first metal frame on the first ceramic substrate;

[0035] Accordingly, the first chip is mounted on the prepared lower package structure as follows:

[0036] A first chip is mounted inside a first metal frame on the first ceramic substrate, and a pad of the first chip is connected to a first metal column through a first bonding wire.

[0037] In an embodiment of the present application, a specific method for preparing the intermediate packaging structure includes:

[0038] preparing a second through hole on the second ceramic substrate, wherein the second through hole penetrates the upper surface and the lower surface of the second ceramic substrate;

[0039] Filling metal in the second through hole to form a second metal column penetrating the upper surface and the lower surface of the second ceramic substrate;

[0040] Prepare a front metal surrounding frame at a position reserved for setting the front metal surrounding frame on the front side of the second ceramic substrate;

[0041] Prepare a back metal surrounding frame at a position reserved for setting a back metal surrounding frame on the back side of the second ceramic substrate;

[0042] Accordingly, the second chip is mounted on the prepared intermediate package structure as follows:

[0043] Mounting a second chip inside the front metal frame on the second ceramic substrate, and connecting the pad of the second chip to the second metal column through a second bonding wire;

[0044] Accordingly, the middle packaging structure is welded on top of the lower packaging structure, and the second metal column connected to the second chip is connected to the first chip through the conductive structure to form a first packaging cavity accommodating the first chip:

[0045] The back metal enclosure is welded on the top of the first metal enclosure, and the second metal column connected to the second chip is connected to the first chip or the first metal column through a conductive structure to form a first packaging cavity for accommodating the first chip.

[0046] In an embodiment of the present application, before preparing the front metal frame at a position reserved for setting the front metal frame on the front of the second ceramic substrate, the method further includes:

[0047] An isolation layer is prepared on the back side of the second ceramic substrate.

[0048] The present invention forms a first packaging cavity for accommodating the first chip through the lower packaging structure and the middle packaging structure, and forms a second packaging cavity for accommodating the second chip through the middle packaging structure and the upper packaging structure, so that the airtight packaging device forms two independent packaging cavities distributed vertically, and the sensitive chips can be placed in the first packaging cavity and the second packaging cavity respectively. There is no need to package the sensitive components separately and then connect them to the airtight packaging device, thus avoiding secondary packaging and improving the integration of the airtight packaging device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0050] Figure 1 A schematic diagram of the structure of a hermetic packaging device provided by one embodiment of the present invention;

[0051] Figure 2 A schematic flow chart of a hermetic packaging method provided by one embodiment of the present invention;

[0052] Figure 3 A schematic cross-sectional structure diagram of a first through hole provided on a first ceramic substrate according to an embodiment of the present invention;

[0053] Figure 4 A schematic top view of a structure in which a first through hole is provided on a first ceramic substrate according to an embodiment of the present invention;

[0054] Figure 5 A schematic diagram of a cross-sectional structure after depositing a first front seed layer and a first back seed layer provided in one embodiment of the present invention;

[0055] Figure 6 A schematic diagram of a cross-sectional structure after manufacturing a first photoresist layer provided by an embodiment of the present invention;

[0056] Figure 7 A schematic diagram of a cross-sectional structure after manufacturing a first front conductor layer and a first back conductor layer provided by an embodiment of the present invention;

[0057] Figure 8 A schematic diagram of a cross-sectional structure of a copper heat-conducting column provided in an embodiment of the present invention Figure 1 ;

[0058] Fig. 9 A schematic diagram of a cross-sectional structure of a copper heat-conducting column provided in an embodiment of the present invention Figure 2 ;

[0059] Fig.10 A schematic diagram of a cross-sectional structure of a copper heat-conducting column provided in an embodiment of the present invention Figure 3 ;

[0060] Fig.11 A schematic diagram of a cross-sectional structure for manufacturing a first metal frame and a solder resist layer provided in one embodiment of the present invention;

[0061] Fig.12 A schematic cross-sectional structure diagram of installing a first chip provided by an embodiment of the present invention;

[0062] Fig.13 A schematic diagram of a cross-sectional structure of manufacturing a second front seed layer and a second back seed layer on a second ceramic substrate provided in one embodiment of the present invention;

[0063] Fig.14 A schematic diagram of a cross-sectional structure of manufacturing a second front conductor layer and a second back conductor layer provided in one embodiment of the present invention;

[0064] Fig.15 A schematic cross-sectional structure diagram of removing the second front conductor layer and the second back conductor layer provided by an embodiment of the present invention;

[0065] Fig.16 A schematic cross-sectional structure diagram of manufacturing a front metal surrounding frame, a back metal surrounding frame and a first coupling structure provided by an embodiment of the present invention;

[0066] Fig.17 A schematic structural diagram of an upper packaging structure provided by an embodiment of the present invention.

[0067] Wherein: 1. first ceramic substrate; 2. first through hole; 3. first front seed layer; 4. first photoresist layer; 5. first metal column; 6. first front conductor layer; 7. first back conductor layer; 8. fifth photoresist layer; 9. copper thermal conductive column; 10. first metal frame; 11. first chip; 12. second ceramic substrate; 13. solder resist layer; 14. first isolation wall; 15. conductive structure; 16. second through hole; 17. second front seed layer; 18. second back seed layer; 19. second front conductor layer; 20. second back conductor layer; 21. first coupling structure; 22. front metal frame; 23. back metal frame; 24. cover plate; 25. third front seed layer; 26. third back conductor layer; 27. third front conductor layer; 28. second metal frame; DETAILED DESCRIPTION

[0068] In order to enable people in the technical field to better understand the present solution, the technical solution in the embodiment of the present solution will be clearly described below in conjunction with the drawings in the embodiment of the present solution. Obviously, the described embodiment is an embodiment of a part of the present solution, not all of the embodiments. Based on the embodiments in the present solution, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present solution.

[0069] The term "including" and any other variations in the specification and claims of this solution and the above drawings mean "including but not limited to", and are intended to cover non-exclusive inclusions. In addition, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order.

[0070] The implementation of the present invention is described in detail below with reference to the accompanying drawings:

[0071] like Figure 1 As shown, an airtight package device provided by an embodiment of the present invention includes:

[0072] The lower packaging structure adopts a first ceramic substrate 1 as a mounting base, the first ceramic substrate 1 is provided with a first through hole 2 penetrating the upper surface and the lower surface of the first ceramic substrate 1, the first through hole 2 is filled with metal, and the metal in the first through hole 2 is recorded as a first metal column 5;

[0073] A first chip 11 is disposed on the first ceramic substrate 1, and a pad of the first chip 11 is connected to the first metal column 5 through a first bonding wire;

[0074] an intermediate packaging structure, arranged on the lower packaging structure, wherein the intermediate packaging structure adopts a second ceramic substrate 12 as an intermediate mounting plate, the second ceramic substrate 12 is provided with a second through hole 16 penetrating the upper surface and the lower surface of the second ceramic substrate 12, the second through hole 16 is filled with metal, the metal in the second through hole 16 is recorded as a second metal column, and the lower packaging structure and the intermediate packaging structure constitute a first packaging cavity accommodating the first chip 11;

[0075] A second chip is disposed on the second ceramic substrate 12, wherein the pad of the second chip is connected to the second metal column via a second bonding wire, and the second metal column connected to the second chip is connected to the first chip 11 or the first metal column 5 via a conductive structure 15;

[0076] The upper packaging structure is arranged on the middle packaging structure, and the middle packaging structure and the upper packaging structure form a second packaging cavity for accommodating the second chip.

[0077] In this embodiment, the present invention is not limited to two packaging cavities, and more than two packaging cavities can be vertically arranged. The metal slurry is a copper electroplating solution. The first chip 11 and the second chip can both be radio frequency chips. The first metal column 5 connected to the pad of the first chip 11 is recorded as a conductive column, and a signal shielding structure formed by a circle of the first metal column 5 is also provided around the conductive column. A signal shielding structure formed by a circle of the second metal column is provided around the second metal column. The signal shielding structure can be a coaxial signal shielding structure.

[0078] Since the conductive column needs to transmit signals, a signal shielding structure needs to be provided for the conductive column. The signal shielding structure in the present application can be provided as follows: when preparing the first through hole 2 corresponding to the conductive column, a circle of first through holes 2 is prepared around the first through hole 2, and metal is also injected into the circle of first through holes 2 to form a first metal column 5, and the first metal column 5 surrounding the conductive column can form a signal shielding structure.

[0079] In this embodiment, the first ceramic substrate 1 and the second ceramic substrate 12 are pre-sintered, for example, they can be alumina ceramics, aluminum nitride ceramics and quartz. The selection of the diameter of the first through hole 2 can refer to the following constraints: the ratio of the thickness of the first ceramic substrate 1 to the diameter of the first through hole 2 is between 3:1 and 4:1. According to the thickness of the first ceramic substrate 1 during actual packaging, the diameter of the first through hole 2 can be set between 70-125 microns. The selection of the diameter of the second through hole 16 can refer to the following constraints: the ratio of the thickness of the second ceramic substrate 12 to the diameter of the second through hole 16 is between 3:1 and 4:1. According to the thickness of the second ceramic substrate 12 during actual packaging, the diameter of the second through hole 16 can be set between 70-125 microns.

[0080] In the embodiment of the present invention, the lower packaging structure and the middle packaging structure form a first packaging cavity for accommodating the first chip 11, and the middle packaging structure and the upper packaging structure form a second packaging cavity for accommodating the second chip, so that the airtight packaging device forms two independent packaging cavities distributed vertically, and the sensitive chip can be placed in the first packaging cavity and the second packaging cavity respectively, and there is no need to package the sensitive element separately and then connect it to the airtight packaging device, thus avoiding secondary packaging and improving the integration of the airtight packaging device. The present invention sets two independent packaging cavities, independently packages the sensitive chip, avoids secondary packaging of the sensitive element, and can directly use the bare chip.

[0081] like Figure 1 As shown, in an embodiment of the present invention, the conductive structure 15 is a spring column, a first end of the spring column is connected to the first chip 11 or the first metal column 5, and a second end of the spring column is connected to the lower surface of the second metal column connected to the second chip.

[0082] In this embodiment, the spring column can be prepared or purchased from the market, and the spring column is made of metal. The setting of the spring column can not only transmit signals, but also buffer the slight deformation caused by heating and eliminate expansion stress.

[0083] like Figure 1 As shown, in an embodiment of the present invention, the hermetic packaging device further includes:

[0084] The copper heat-conducting pillars 9 are arranged on the back side of the first ceramic substrate 1 , wherein at least a preset number of the copper heat-conducting pillars 9 are connected to the first metal pillars 5 as input and output pins of the hermetic package device.

[0085] In this embodiment, the copper heat-conducting pillars 9 on the back side of the first ceramic substrate 1 meet the following constraints: the height of the copper heat-conducting pillars 9 is 200-1000 microns, and the accuracy of the copper heat-conducting pillars 9 is within ±5 microns.

[0086] In the embodiment of the present invention, a portion of the copper heat-conducting columns 9 can be directly connected to the first ceramic substrate 1. The copper heat-conducting columns 9 connected to the first ceramic substrate 1 can dissipate the heat on the first ceramic substrate 1 on the one hand, and can support the overall package shell on the other hand, so that the package shell is more stable when connected to other structures. The copper heat-conducting columns 9 connected to the first metal column 5 serve as package I / O lead-out terminals, can serve as heat dissipation channels, help packaged devices dissipate heat, and can also buffer the thermal stress between the airtight package device and the PCB mounting motherboard during installation, avoiding cracking due to thermal mismatch when the airtight package device is connected to the PCB mounting motherboard.

[0087] like Figure 1As shown, in an embodiment of the present invention, the lower packaging structure includes:

[0088] A first ceramic substrate 1;

[0089] A first metal enclosure 10, disposed on the first ceramic substrate 1 at a position for disposing the first metal enclosure 10;

[0090] The intermediate packaging structure comprises:

[0091] A second ceramic substrate 12;

[0092] A front metal frame 22 is disposed on the front of the second ceramic substrate 12 and is used to set the front metal frame 22;

[0093] A back metal enclosure 23 is arranged on the back of the second ceramic substrate 12 at a position for setting the back metal enclosure 23 , and the lower surface of the back metal enclosure 23 is connected to the upper surface of the first metal enclosure 10 ;

[0094] The upper packaging structure comprises:

[0095] Cover plate 24;

[0096] The second metal enclosure 28 is disposed under the cover plate 24 at a position for disposing the second metal enclosure 28 , and the lower surface of the second metal enclosure 28 is connected to the upper surface of the front metal enclosure 22 .

[0097] In this embodiment, the bottom of the second chip can also be connected to the front metal frame 22 through a second connecting structure. The connecting structure plays a role in transferring heat. The second connecting structure transfers the heat of the second chip to the front metal frame 22, and then transfers it downward to the second metal frame 28 through the front metal frame 22, and then transfers it out.

[0098] In this embodiment, the upper surface of the first metal enclosure 10 is provided with a first bite convex point, the upper surface of the front metal enclosure 22 is provided with a front bite convex point, and the lower surface of the back metal enclosure 23 is provided with a back bite convex point that matches the front bite convex point; the lower surface of the second metal enclosure 28 is provided with a second bite convex point that matches the front bite convex point. During manufacturing, the first metal enclosure 10 and the back metal enclosure 23 are connected by laser side welding technology. The front metal enclosure 22 and the second metal enclosure 28 are connected by laser side welding technology.

[0099] like Figure 1 As shown, in an embodiment of the present invention, the hermetic packaging device further includes:

[0100] A first front seed layer 3, located on the upper surface of the first ceramic substrate 1 and the inner side wall of the first through hole 2, and the metal is connected to the first through hole 2 through the first front seed layer 3;

[0101] The first front conductor layer 6 is located above the first front seed layer 3, and the first area of ​​the upper surface of the first front conductor layer 6 is used to set the first metal frame 10, the second area of ​​the upper surface of the second front conductor layer 19 is used to thicken the first metal column 5, and the third area of ​​the first front conductor layer 6 is used to install the first chip 11.

[0102] A first back seed layer, located on the lower surface of the first ceramic substrate 1;

[0103] The first back conductor layer 7 is located below the second back seed layer 18 , and the first area of ​​the lower surface of the first back conductor layer 7 is used to thicken the first metal column 5 , and the second area of ​​the lower surface of the first back conductor layer 7 is used to prepare the copper thermal conductive column 9 .

[0104] The first front conductor layer is arranged above the first ceramic substrate and the first metal column, and the first back conductor layer is arranged below the first ceramic substrate and the first metal column. A complete coating structure is formed between the first ceramic substrate and the first metal column to ensure air tightness.

[0105] like Figure 1 As shown, in an embodiment of the present invention, the hermetic packaging device further includes:

[0106] A second front seed layer 17 is located on the upper surface of the second ceramic substrate 12 and the inner side wall of the second through hole 16, and the metal is connected to the second through hole 16 through the second front seed layer 17;

[0107] The second front conductor layer 19 is located above the second front seed layer 17, the first area of ​​the upper surface of the second front conductor layer 19 is used to set the front metal frame 22, the second area of ​​the upper surface of the second front conductor layer 19 is used to thicken the second metal column, and the third area of ​​the upper surface of the second front conductor layer 19 is used to install the second chip.

[0108] A second back seed layer 18 , located on the lower surface of the second ceramic substrate 12 ;

[0109] The second back conductor layer 20 is located below the second back seed layer 18 . The first area of ​​the lower surface of the second back conductor layer 20 is used to make the back metal frame 23 , and the second area of ​​the lower surface of the second back conductor layer 20 is used to thicken the second metal column.

[0110] In this embodiment, the second front seed layer 17 and the second front conductor layer 19 can be used as a second connection structure to realize the interconnection between the second chip and the front metal frame 22. The second front conductor layer is arranged above the second ceramic substrate and the second metal column, and the second back conductor layer is arranged below the second ceramic substrate and the second metal column, and a complete coating structure is formed between the second ceramic substrate and the second metal column to ensure airtightness.

[0111] like Figure 1 As shown, in an embodiment of the present invention, the hermetic packaging device further includes:

[0112] A third back seed layer, disposed on the lower surface of the cover plate 24;

[0113] The third back conductive layer 26 is disposed below the third back seed layer. The first area of ​​the lower surface of the third back conductive layer 26 is used to manufacture the second metal frame 28 .

[0114] In this embodiment, the materials of the first front seed layer 3, the first back seed layer, the second front seed layer 17, the second back seed layer 18 and the third back seed layer can all be Ti or copper, and the thickness can all be 50nm-5000nm, and other thicknesses can also be selected according to specific needs.

[0115] In this embodiment, the thickness of the first front conductor layer 6, the first back conductor layer 7, the second front conductor layer 19, the second back conductor layer 20 and the third back conductor layer 26 can all be between 15-20 μm to achieve airtightness, and the material can all be copper.

[0116] In an embodiment of the present invention, a shielding layer is further provided on the back of the cover plate 24. The shielding layer can be provided on the back of the entire cover plate 24 or only on the second chip. The function of the shielding layer is to reduce the interference of external signals on the second chip. If a third back seed layer is provided on the back of the cover plate 24, the shielding layer is provided on the lower surface of the third back seed layer in an area for providing the shielding layer. If a third back seed layer and a third back conductor layer 26 are provided on the back of the cover plate 24, the shielding layer is provided on the lower surface of the third back conductor layer 26 in an area for providing the shielding layer.

[0117] like Figure 1 As shown, in the embodiment of the present invention, a third through hole may be provided on the cover plate 24, and metal is filled in the third through hole, and the metal in the third through hole is recorded as a third metal column. The third through hole is provided on the cover plate 24. On the one hand, the manufacturing method can be the same as that of the first ceramic substrate 1 and the second ceramic substrate 12, making the manufacturing more convenient and simple, and on the other hand, it is convenient to continue to raise the height of the cover plate 24 to make another packaging cavity.

[0118] In the embodiment of the present invention, an isolation layer is disposed on the lower surface of the second ceramic substrate 12 .

[0119] In this embodiment, the isolation layer can be a metal material, such as a metal copper material. The isolation layer is arranged on the lower surface of the second ceramic substrate 12, and can cover the entire back side of the second ceramic substrate 12, or the isolation layer can be arranged only on the lower surface position of the second ceramic substrate 12 corresponding to the first chip 11. The function of the isolation layer is to reduce the mutual influence of the radiation of the second chip and the first chip 11.

[0120] In actual applications, if a second back side seed layer 18 is provided on the back side of the second ceramic substrate 12, the isolation layer is provided in an area on the second back side seed layer 18 for preparing the isolation layer; if a second back side seed layer 18 and a second back side conductor layer 20 are provided on the back side of the second ceramic substrate 12, the isolation layer is provided in an area on the second back side conductor layer 20 for preparing the isolation layer.

[0121] like Figure 1 As shown, in an embodiment of the present invention, the hermetic packaging device further includes:

[0122] The first coupling structure 21 is disposed on the lower surface of the second ceramic substrate 12 and above the first chip 11 .

[0123] The second coupling structure is disposed on the lower surface of the cover plate 24 and above the second chip.

[0124] In this embodiment, the first coupling structure 21 and the second coupling structure can both be planar structures or stepped structures. The first coupling structure 21 can be set when the first chip 11 needs to be coupled to increase the coupling property of the first chip 11. The second coupling structure can be set when the second chip needs to be coupled to increase the coupling property of the second chip.

[0125] like Figure 1 As shown, in an embodiment of the present invention, when there are at least two first chips 11 and the first chips 11 need to be isolated, the airtight packaging device also includes: a first isolation wall 14, which is arranged on the first ceramic substrate, and the multiple first chips 11 that need to be isolated are located in different airtight spaces, and the airtight spaces are isolated by the first isolation wall 14.

[0126] When there are at least two second chips and the second chips need to be isolated, the airtight packaging device also includes: a second isolation wall, which is arranged on the second ceramic substrate, and the multiple second chips that need to be isolated are located in different airtight spaces, and the airtight spaces are isolated by the second isolation wall.

[0127] In this embodiment, the first isolation wall 14 is used to separate the first chips 11 so that the first chips 11 do not interfere with each other. The thickness of the first isolation wall 14 may be between 150 and 200 μm. The first isolation wall 14 may be made of metal material.

[0128] like Figure 1 As shown, in an embodiment of the present invention, the hermetic packaging device further includes:

[0129] The solder resist layer 13 is disposed on the back surface of the first ceramic substrate 1 and is located in other regions except the region of the first metal pillar 5 .

[0130] In this embodiment, a solder resist layer 13 is provided on the outer mounting surface on the back side of the first ceramic substrate 1 to improve the reliability and assembly convenience of the hermetic packaged device.

[0131] If a copper heat-conducting column 9 is disposed on the back side of the first ceramic substrate 1 , the solder resist layer 13 is located in other areas except the area of ​​the copper heat-conducting column 9 .

[0132] In an embodiment of the present invention, the front of the cover plate 24 may also be provided with heat dissipation fins, the bottom of the first chip 11 is connected to the first metal frame 10 through a first connecting structure, and the second chip is connected to the front metal frame 22 through a second connecting structure. The first connecting structure may be a first front seed layer 3 and a first front conductor layer 6.

[0133] In this embodiment, the heat dissipation fins are directly formed on the cover plate 24, which is beneficial to the heat dissipation of the first chip 11 and the second chip.

[0134] In the embodiment of the present invention, a planar antenna may be further provided on the front of the cover plate 24, the lower surface of the planar antenna is in contact with the upper surface of the cover plate 24, a cover plate 24 through hole is provided on the cover plate 24, metal is filled in the cover plate 24 through hole, and the metal in the cover plate 24 through hole is recorded as a cover plate 24 metal column. The planar antenna is connected to a cover plate 24 metal column in a cover plate 24 through hole. The lower end of the cover plate 24 metal column is connected to the first end of a spring column, the second end of the spring column is connected to the second chip, and can also be connected to the first chip 11 through the spring column and the second metal column.

[0135] In this embodiment, the planar antenna is directly made on the cover plate 24 , and the lower surface of the planar antenna is in contact with the upper surface of the cover plate 24 .

[0136] like Figure 2 As shown, an airtight packaging method provided by an embodiment of the present invention includes:

[0137] S101 , mounting a first chip 11 on the prepared lower package structure.

[0138] In this embodiment, the first chip 11 needs to be packaged on the lower package structure, and the first chip 11 can be mounted on the first ceramic substrate 1 of the lower package structure by surface mounting, and the first chip 11 also needs to be connected to the metal in the first through hole 2 of the first ceramic substrate 1 by bonding wires inside the first metal frame 10. For ease of description, the metal slurry in the first through hole 2 of the first ceramic substrate 1 can be recorded as the first metal column 5.

[0139] S102, mounting a second chip on the prepared intermediate package structure.

[0140] In this embodiment, the second chip needs to be packaged on the middle packaging structure, and the second chip can be mounted on the second ceramic substrate 12 of the lower packaging structure by surface mounting, and the second chip also needs to be connected to the metal in the second through hole 16 of the second ceramic substrate 12 by bonding wires inside the front metal frame 22. For ease of description, the metal in the second through hole 16 of the second ceramic substrate 12 can be recorded as a second metal column.

[0141] S103 , welding the middle packaging structure onto the lower packaging structure, and connecting the second metal column connected to the second chip to the first chip 11 through the conductive structure 15 , to form a first packaging cavity for accommodating the first chip 11 .

[0142] In this embodiment, the back metal surrounding frame 23 of the middle packaging structure is welded to the first metal surrounding frame 10 of the lower packaging structure. In order to ensure the airtightness of the packaging shell, laser welding can be used.

[0143] In order to ensure that the first chip 11 is grounded or the first chip 11 is connected to the second chip, a conductive structure 15 is used to achieve mutual communication, wherein the conductive structure 15 is a spring column. The spring column can be purchased from the market or prepared in advance.

[0144] S104, welding the prepared upper packaging structure onto the middle packaging structure to form a second packaging cavity for accommodating the second chip.

[0145] In this embodiment, the second metal surrounding frame 28 of the upper packaging structure is welded to the back metal surrounding frame 23 of the middle packaging structure. To ensure the airtightness of the packaging shell, laser welding may be used.

[0146] Figures 3 to 17 It is a structural schematic diagram corresponding to each step in another process flow for preparing a packaged device provided in an embodiment of the present application.

[0147] First, a first through hole 2 is prepared on the first ceramic substrate 1 on the lower packaging structure, wherein the first through hole 2 passes through the upper surface and the lower surface of the first ceramic substrate 1. The cross-sectional view of the first ceramic substrate 11 after the first through hole 2 is prepared can be seen in Figure 3 The top view of the first ceramic substrate 1 after the first through hole 2 is prepared can be referred to Figure 4 , the details are the same as step S101.

[0148] In this embodiment, the lower package structure is prepared in advance, and the first ceramic substrate 1 in the lower package structure is pre-sintered. When preparing the first through hole 2 on the first ceramic substrate 1, picosecond cold laser processing and drilling can be used, and the processed first through hole 2 passes through the upper surface and the lower surface of the first ceramic substrate 1. The hole wall of the first through hole 2 prepared in this way is smooth, the verticality is high, and the aperture difference between the front and back of the first ceramic substrate 1 is less than 5%. The first through hole 2 will be injected with metal slurry as a signal transmission line later, and the first through hole 2 prepared in this way can reduce transmission loss after the metal slurry is injected.

[0149] Second, metal is deposited on the upper surface of the first ceramic substrate 1 and the inner side wall of the first through hole 2 to form a first front seed layer 3, a position of a first metal frame 10 is reserved on the upper surface of the first ceramic substrate 1, and the first metal frame 10 is prepared on the first front seed layer 3 by electrochemical deposition. For details, please refer to Figure 5 shown.

[0150] In this embodiment, the first ceramic substrate 1 and the first through hole 2 are cleaned before depositing the first front seed layer 3. Physical vapor deposition or chemical vapor deposition is used to deposit the first front seed layer 3 on the front of the first ceramic substrate 1. Of course, the thickness of the first front seed layer 3 can be set as needed, and the first front seed layer 3 can be set in other ways.

[0151] In this embodiment, a position for arranging the first chip 11 may be reserved on the first front seed layer 3. The first chip 11 may be arranged at the position reserved for arranging the first chip 11.

[0152] Third, metal is injected into the first through hole 2 of the first ceramic substrate 1 provided with the first front seed layer 3 to form a first metal column 5 penetrating the upper surface and the lower surface of the first ceramic substrate 1 .

[0153] In practical applications, while injecting metal into the first through hole 2, a first front conductor layer 6 can also be prepared on the first front seed layer 3. Figure 6-10 shown.

[0154] A first front conductor layer 6 is prepared on the first front seed layer 3 by electrochemical deposition, wherein a first area of ​​the first front conductor layer 6 is used to prepare a first metal frame 10, a second area of ​​the first front conductor layer 6 is used to surface mount a first chip 11 to be packaged, and a third area of ​​the first front conductor layer 6 is used to thicken the conductive column and a signal shielding structure around the conductive column.

[0155] If it is necessary to prepare the first front conductor layer 6, accordingly, the position of the first metal frame 10 is reserved on the upper surface of the first ceramic substrate 1, and the first metal frame 10 is prepared on the first front seed layer 3 by electrochemical deposition method, including:

[0156] A position for a first metal frame 10 is reserved on the upper surface of the first ceramic substrate 1 , and the first metal frame 10 is prepared on the first region of the first front conductor layer 6 by electrochemical deposition.

[0157] In the embodiment of the present application, the specific method for preparing the first front conductor layer 6 and the first metal column 5 is as follows: the first photoresist layer 4 is coated on the first front seed layer 3 by spin coating or lamination hot pressing on the upper surface of the first front seed layer 3, and then the position where the first front conductor layer 6 is to be prepared on the first photoresist layer 4 is subjected to standard photolithography processes such as exposure and development to obtain the conductor layer through hole for preparing the first front conductor layer 6, and finally the position of the conductor layer through hole on the first photoresist layer 4 and the first through hole 2 of the first ceramic substrate 1 deposited with the first front seed layer 3 are deposited by electrochemical deposition. The metal in the first through hole 2 is higher than the first through hole 2, and the metal filled in the first through hole 2 is recorded as the first metal column 5, and finally the first photoresist layer 4 is removed to obtain the first front conductor layer 6 on the first front seed layer 3 and above the first metal column 5. The metal slurry filling when preparing the first front conductor layer 6 and the first metal column 5 is electroplating, and the combination of pulse plating and direct current plating is used during electroplating, which can ensure that the copper deposition in the first through hole 2 has no voids and can also improve the efficiency.

[0158] The material of the first photoresist layer 4 can be selected from high-viscosity photoresist or high-resolution photosensitive dry film. The first photoresist layer 4 meets the constraints: the thickness is greater than 15 microns, the line resolution is less than 10 microns, and the inner side wall of the conductor layer through hole obtained after the first photoresist layer 4 is exposed is steep.

[0159] After preparing the first front conductor layer 6, in order to obtain a first front conductor layer 6 of a preset thickness and also to obtain a first front conductor layer 6 with higher precision and lower surface roughness, the first front conductor layer 6 may be thinned and surface treated.

[0160] Specifically, during the manufacturing process, the first front conductor layer 6 can be thinned. During the grinding process, some scratches may be left, and the first front conductor layer 6 needs to be polished to reduce the surface roughness of the first front conductor layer 6. In order to facilitate the manufacturing of the metal frame, when the first photoresist layer 4 needs to be preserved, the surface of the first photoresist layer 4 is also ground and polished to reduce the surface roughness. Through the grinding and polishing process, the transmission loss of the packaged device can be reduced when it is used.

[0161] Fourth, a copper heat-conducting column 9 is prepared at a position reserved for the copper heat-conducting column 9 on the back of the first ceramic substrate 1, wherein the position reserved for the copper heat-conducting column 9 includes: a position corresponding to the first metal column 5 on the back of the first ceramic substrate 1, such as Figure 8-10 shown.

[0162] The specific preparation method of the copper thermal conductive column 9 is: coating a fifth photoresist layer 8 on the back of the first ceramic substrate 1, photoetching a copper thermal conductive column 9 pattern on the fifth photoresist layer 8, filling metal in the copper thermal conductive column 9 pattern, and finally peeling off the fifth photoresist layer 8 to obtain the copper thermal conductive column 9.

[0163] Specifically, during the manufacturing process, the copper heat-conducting column 9 can be thinned. During the grinding process, some scratches may be left, and the copper heat-conducting column 9 needs to be polished to reduce the roughness of the copper heat-conducting column 9. After the grinding and polishing process, the Z-phase height of the copper heat-conducting column 9 is controlled within the range of ±5 μm.

[0164] Fifth, the first front seed layer 3 other than the position corresponding to the first front conductor layer 6 on the first ceramic substrate 1 is removed.

[0165] In this embodiment, the first front seed layer 3 may be removed by chemical etching. If the first front seed layer 3 is made of copper, it may be removed by acid etching solution; if the first front seed layer 3 is made of titanium, it may be removed by oxide etching solution.

[0166] Of course, in practical applications, if the first front conductive layer 6 is not made, the first front seed layer 3 in other areas except the area for preparing the first metal frame 10, the area for surface-mounting the first chip 11 to be packaged, and the area for thickening the conductive column and the signal shielding structure around the conductive column can be removed. Fig.11 shown.

[0167] Sixth, a position of the first metal enclosure 10 is reserved on the upper surface of the first ceramic substrate 1 and the first metal enclosure is welded to the first front conductor layer 6, as shown in Figure 11. The upper surface of the first metal enclosure 10 may also be provided with a first bite bump.

[0168] If the first front side conductor layer 6 is provided, the first metal surrounding frame 10 is welded to the first front side conductor layer 6 .

[0169] In this embodiment, the first metal enclosure 10 is used as the side wall of the packaged device. When preparing the first metal enclosure 10, the pre-prepared first metal enclosure 10 can be reinforced on the first ceramic substrate 1, or by a semiconductor process: for example, the photoresist of the position reserved for the first metal enclosure 10 on the first ceramic substrate 1 is removed by photolithography, and the photoresist is left in other areas of the first ceramic substrate 1; the first metal enclosure 10 can also be prepared by electroplating at the position reserved for the first metal enclosure 10 on the surface of the first ceramic substrate 1. Of course, in practical applications, there are other ways to prepare the first metal enclosure 10, for example, the first metal enclosure 10 can also be prepared by electrochemical deposition. The first metal enclosure 10 is directly grown on the first ceramic substrate 1, and the height of the first metal enclosure 10 is controllable. The height of the first metal enclosure 10 is precisely matched with the frequency of the first chip 11, and the spatial coupling degree is controllable, thereby improving the radio frequency characteristics of the first chip 11.

[0170] In this embodiment, during the actual preparation, the upper surface of the first metal enclosure 10 may be thinned. During the grinding process, some scratches may be left, and the upper surface of the first metal enclosure 10 needs to be polished to reduce the surface roughness. In this embodiment, the height of the first metal enclosure 10 can be precisely controlled by the electroplating thickening and CMP thinning processes to reduce the spatial coupling of the hermetic packaged device.

[0171] Seventh, after the copper heat-conducting column 9 is prepared at the position reserved for the copper heat-conducting column 9 on the back of the first ceramic substrate 1, in order to improve the environmental tolerance of the airtight packaged device, a solder resist layer 13 is prepared on the back of the first ceramic substrate 1 and on other areas other than the position reserved for the copper heat-conducting column 9 by chemical nickel-gold plating, referring to Fig.11 shown.

[0172] Eighth, the first chip 11 to be packaged is mounted inside the first metal frame 10 on the first ceramic substrate 1, and the pads of the first chip 11 to be packaged are connected to the first metal pillars 5 on the first ceramic substrate 1 through bonding wires, referring to Fig.12 shown.

[0173] In this embodiment, the first metal pillar 5 connected to the pad of the first chip 11 is recorded as a conducting pillar, and a signal shielding structure formed by a circle of first metal pillars 5 is further provided around the periphery of the conducting pillar.

[0174] Since the conductive column needs to transmit signals, a signal shielding structure needs to be set for the conductive column. The signal shielding structure in the present application can be set as follows: when preparing the first through hole 2 corresponding to the first conductive column, a circle of first through holes 2 is prepared around the first through hole 2, and metal is also injected into the circle of first through holes 2 to form a first metal column 5, and the first metal column 5 surrounding the conductive column can form a signal shielding structure.

[0175] By adopting the above method, there is no need to prepare the signal shielding structure additionally, and the signal shielding structure can be prepared together with the conducting column, thus saving process costs.

[0176] In the embodiment of the present application, when there are at least two first chips 11 to be packaged and the first chips 11 to be packaged need to be isolated, a first isolation wall 14 is further provided in the first metal enclosure 10, and the multiple first chips 11 to be isolated are located in different airtight spaces, and the airtight spaces are isolated by the first isolation wall 14. The first isolation wall 14 is used to separate the first chips 11 so that the first chips 11 do not interfere with each other.

[0177] Ninth, the preparation method of the intermediate packaging structure is:

[0178] A second through hole 16 is prepared on the second ceramic substrate 12 on the middle packaging structure, wherein the second through hole 16 passes through the upper surface and the lower surface of the second ceramic substrate 12. For the specific preparation method, refer to the preparation method of the first through hole 2 in the first.

[0179] Metal is deposited on the upper surface of the second ceramic substrate 12 and the inner sidewall of the second hole to form a second front seed layer 17, and metal is deposited on the lower surface of the second ceramic substrate 12 to form a second back seed layer 18. For a specific preparation method, refer to the preparation method of the first front seed layer 3 in the second. Fig.13 shown.

[0180] Metal is injected into the second through hole 16 of the second ceramic substrate 12 provided with the second front seed layer 17 to form a second metal column penetrating the upper surface and the lower surface of the second ceramic substrate 12. For details, refer to the preparation method of the first metal column 5 in the third. When preparing the second metal column, a second front conductor layer 19 and a second back conductor layer 20 can also be prepared together. An isolation layer can also be prepared on the lower surface of the second ceramic substrate 12 or the second back conductor layer 20. The specific preparation method of the isolation layer is to deposit a second photoresist layer on the back of the second ceramic substrate 12, etch an isolation layer pattern on the second photoresist layer, deposit metal in the isolation layer pattern, and finally peel off the second photoresist layer to obtain the isolation layer, such as Fig.14 shown.

[0181] A front metal enclosure 22 is prepared on the second front conductor layer 19, and a back metal enclosure 23 is prepared on the second back conductor layer 20. The specific preparation method refers to the preparation method of the first metal enclosure 10 in the sixth. The upper surface of the front metal enclosure 22 is provided with a front bite convex point, and the lower surface of the back metal enclosure 23 is provided with a back bite convex point that matches the front bite convex point, such as Fig.16 shown.

[0182] The second front seed layer 17 is removed except for the position corresponding to the second front conductor layer 19 on the second ceramic substrate 12. The second back seed layer 18 is removed except for the position corresponding to the second back conductor layer 20 under the second ceramic substrate 12. For details, please refer to the fifth method for removing the first front seed layer 3, such as Fig.15 shown.

[0183] The second chip to be packaged is mounted inside the front metal enclosure 22 on the second ceramic substrate 12, and the pads of the second chip to be packaged are connected to the second metal pillars on the second ceramic substrate 12 through bonding wires. In the embodiment of the present application, when there are at least two second chips to be packaged and the second chips to be packaged need to be isolated, a first isolation wall is further provided in the second metal enclosure 28, and the multiple second chips to be isolated are located in different airtight spaces, and the airtight spaces are isolated by the second isolation wall. The second isolation wall is used to separate the second chips so that the second chips do not interfere with each other.

[0184] Tenth, a method for preparing the upper packaging structure, such as Fig.17 As shown:

[0185] A third back seed layer is deposited on the lower surface of the cover plate 24 in the upper packaging structure, and is disposed below the third back seed layer to prepare a third back conductor layer 26. The first area of ​​the lower surface of the third back conductor layer 26 is used to make a second metal enclosure 28. The lower surface of the second metal enclosure 28 is provided with a second bite bump that matches the front bite bump.

[0186] For details, please refer to the preparation method of the first front seed layer 3 and the first front conductor layer 6, which will not be described in detail here.

[0187] A second metal enclosure 28 is prepared under the third back conductive layer 26 . The specific preparation method is referred to the preparation method of the first metal enclosure 10 in the sixth section, which will not be described in detail here.

[0188] In practical applications, a shielding layer may also be made on the back of the cover plate 24. The specific method for making the shielding layer is the same as the method for making the ninth isolation layer, which will not be described in detail here.

[0189] In order to make the manufacturing process of the cover plate 24 the same as that of the first ceramic substrate 1, a through hole of the cover plate 24 can be provided on the cover plate 24, and metal is filled in the through hole of the cover plate 24 to form a third metal column. The process can be simplified, and the cover plate 24 can be manufactured at the same time as the first ceramic substrate 1.

[0190] Eleventh, the middle packaging structure is welded on top of the lower packaging structure, and the second metal column connected to the second chip is connected to the first chip 11 through the conductive structure 15 to form a first packaging cavity for accommodating the first chip 11.

[0191] like Figure 1 As shown, please refer to S103 for details.

[0192] Twelfth, welding the prepared upper packaging structure on top of the middle packaging structure to form a second packaging cavity for accommodating the second chip.

[0193] like Figure 1 As shown, please refer to S104 for details.

[0194] Of course, in practical applications, before the upper packaging structure and the middle packaging structure are sealed, heat dissipation fins may be made on the front side of the cover plate 24 .

[0195] Specifically, the method for making the heat sink fins is to make a third photoresist layer on the front side of the cover plate 24 by spin coating or lamination hot pressing, and etch through holes for making the heat sink fins on the third photoresist layer. Finally, metal is deposited at the position where the through holes for making the heat sink fins are etched on the third photoresist layer, and the heat sink fins can be obtained by removing the third photoresist layer.

[0196] In a specific application, when heat sink fins are manufactured, the bottom of the first chip 11 is connected to the first metal enclosure 10, and the bottom of the second chip is connected to the front metal enclosure 22. If the first chip 11 is manufactured on the first front seed layer 3, the first front seed layer 3 under the first chip 11 is connected to the first metal enclosure 10, and the heat is transferred to the metal enclosure through the first front seed layer 3, and the heat is transferred upward to the heat sink fins through the metal enclosure. If the first chip 11 is manufactured on the first front conductor layer 6, it can be connected to the metal enclosure through the first front conductor layer 6 under the first chip 11 and the first front seed layer 3, or the first front seed layer 3 is connected to the metal enclosure. The second chip is the same.

[0197] In the embodiment of the present invention, before the cover plate 24 is sealed on the upper surface of the metal frame, an antenna may be manufactured on the front surface of the cover plate 24 .

[0198] Specifically, the method for making the antenna is to make a fourth photoresist layer on the front side of the cover plate 24 by spin coating or lamination hot pressing, and etch a pattern for making the antenna on the fourth photoresist layer, and finally deposit metal at the position where the pattern for making the antenna is etched on the fourth photoresist layer, and the antenna can be obtained by removing the fourth photoresist layer.

[0199] In a specific application, when making an antenna, picosecond cold laser processing can be used to drill holes on the cover plate 24 to form a through hole in the cover plate 24, and metal is deposited in the through hole of the cover plate 24. The metal in the through hole of the cover plate 24 is recorded as a metal column of the cover plate 24, and the antenna is connected to a metal column of the cover plate 24 in a through hole of the cover plate 24.

[0200] Correspondingly, a spring column is also installed in the first packaging cavity and the second packaging cavity. One end of the spring column in the first packaging cavity is connected to the first chip 11 by welding, or connected to the first front seed layer 3 or the first front conductor layer 6 under the first chip 11; the other end of the spring column is connected to the second metal column. One end of the spring column in the second packaging cavity is connected to the second chip by welding, or connected to the second front seed layer 17 or the second front conductor layer 19 under the second chip; the other end of the spring column is connected to the metal column of the cover plate 24.

[0201] In practical applications, a first coupling structure 21 may be provided on the lower surface of the second ceramic substrate 12 above the first chip 11, and the first coupling structure 21 may be a planar structure or a stepped structure. A second coupling structure may be provided on the lower surface of the cover plate 24 above the second chip, and the second coupling structure may be a planar structure or a stepped structure.

[0202] In practical applications, the airtightness of the airtight packaging structure can be further verified to determine whether the airtight packaging structure is qualified.

[0203] Specifically, the airtight package structure is placed in a leak detection container, and helium is filled in the container and a pressure of 0.5Mpa is applied. After 4 hours, the airtight package structure is taken out and a leak detection liquid immersion method is used for a rough inspection. If no bubbles are generated on the surface of the leak detection liquid, it is qualified, otherwise it is unqualified. Finally, the qualified airtight package structure is carefully inspected by a helium mass spectrometer. If the leak detector shows that the helium flow rate is lower than 1*10-9pa.cm3 / s, it is qualified, otherwise it is unqualified.

[0204] The first to eleventh steps above can be deleted or recombined according to actual needs.

[0205] It should be noted that, in the above-mentioned embodiment, the first front seed layer 3 and the first front conductor layer 6 are both arranged on the first ceramic substrate 1. In actual applications, a first back seed layer can also be arranged on the back side of the first ceramic substrate 1, and the copper thermal conductive column 9 is prepared at the position reserved for setting the copper thermal conductive column 9 under the first back seed layer. The specific steps are the same as the steps of preparing the first front seed layer 3.

[0206] A first back conductor layer 7 may also be provided under the first back seed layer. The first back conductor layer 7 may be obtained by depositing a first lower photoresist layer under the first back seed layer, and then subjecting the first lower photoresist layer to photolithography, deposition, etc. The specific steps are the same as the steps for preparing the first front conductor layer 6. A copper heat-conducting column 9 is prepared at a position reserved for the copper heat-conducting column 9 under the first back conductor layer 7.

[0207] A third front seed layer 25 and a third front conductor layer 27 may also be formed on the upper surface of the cover plate 24 .

[0208] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hermetic package device, characterized in that: include: The lower packaging structure adopts a first ceramic substrate as a mounting base plate, the first ceramic substrate is provided with a first through hole penetrating the upper surface and the lower surface of the first ceramic substrate, the first through hole is filled with metal, and the metal in the first through hole is recorded as a first metal column; A first chip is disposed on the first ceramic substrate, wherein a pad of the first chip is connected to a first metal column through a first bonding wire; an intermediate packaging structure, arranged on the lower packaging structure, wherein the intermediate packaging structure uses a second ceramic substrate as an intermediate mounting plate, the second ceramic substrate is provided with a second through hole penetrating the upper surface and the lower surface of the second ceramic substrate, the second through hole is filled with metal, the metal in the second through hole is recorded as a second metal column, and the lower packaging structure and the intermediate packaging structure form a first packaging cavity for accommodating a first chip; A second chip is disposed on the second ceramic substrate, a pad of the second chip is connected to a second metal column via a second bonding wire, and the second metal column connected to the second chip is connected to the first chip or the first metal column via a conductive structure; An upper packaging structure, disposed on the middle packaging structure, wherein the middle packaging structure and the upper packaging structure form a second packaging cavity for accommodating the second chip; Wherein, the lower packaging structure comprises: a first ceramic substrate; A first metal surrounding frame is arranged on the first ceramic substrate at a position for setting the first metal surrounding frame; The intermediate packaging structure comprises: a second ceramic substrate; A front metal surrounding frame is arranged on the front of the second ceramic substrate at a position for setting the front metal surrounding frame; A back metal enclosure frame is arranged on the back of the second ceramic substrate at a position for setting the back metal enclosure frame, wherein the lower surface of the back metal enclosure frame is connected to the upper surface of the first metal enclosure frame to form a first packaging cavity; The upper packaging structure comprises: Cover plate; The second metal enclosure is arranged under the cover plate at a position for arranging the second metal enclosure, and the lower surface of the second metal enclosure is connected to the upper surface of the front metal enclosure to form a second packaging cavity.

2. The hermetic package device according to claim 1, characterized in that: The conductive structure is a spring column, a first end of the spring column is connected to the first chip or the first metal column, and a second end of the spring column is connected to the second metal column connected to the second chip.

3. The hermetic package device according to claim 1, characterized in that: An isolation layer is provided on the lower surface of the second ceramic substrate.

4. The hermetic package device according to claim 1, characterized in that: The hermetic packaging device also includes: The copper heat-conducting pillars are arranged on the back side of the first ceramic substrate, wherein at least a preset number of the copper heat-conducting pillars are connected to the first metal pillars as input and output pins of the hermetic package device.

5. The hermetic package device according to claim 1, characterized in that: The first metal column connected to the pad connected to the first chip is recorded as a conductive column, and a signal shielding structure formed by a circle of first metal columns is also provided around the conductive column.

6. A hermetic packaging method, characterized in that: include: Mounting a first chip on the prepared lower package structure; Mounting a second chip on the prepared intermediate package structure; Welding the middle packaging structure above the lower packaging structure, and connecting the second metal column connected to the second chip to the first chip through the conductive structure to form a first packaging cavity for accommodating the first chip; Welding the prepared upper packaging structure onto the middle packaging structure to form a second packaging cavity for accommodating the second chip; Wherein, the lower packaging structure comprises: a first ceramic substrate; A first metal surrounding frame is arranged on the first ceramic substrate at a position for setting the first metal surrounding frame; The intermediate packaging structure comprises: a second ceramic substrate; A front metal surrounding frame is arranged on the front of the second ceramic substrate at a position for setting the front metal surrounding frame; A back metal enclosure frame is arranged on the back of the second ceramic substrate at a position for setting the back metal enclosure frame, wherein the lower surface of the back metal enclosure frame is connected to the upper surface of the first metal enclosure frame to form a first packaging cavity; The upper packaging structure comprises: Cover plate; The second metal enclosure is arranged under the cover plate at a position for arranging the second metal enclosure, and the lower surface of the second metal enclosure is connected to the upper surface of the front metal enclosure to form a second packaging cavity.

7. The hermetic packaging method according to claim 6, characterized in that: The specific preparation method of the lower packaging structure includes: Preparing a first through hole on the first ceramic substrate, wherein the first through hole penetrates the upper surface and the lower surface of the first ceramic substrate; Filling metal in the first through hole to form a first metal column penetrating the upper surface and the lower surface of the first ceramic substrate; Making a first metal frame at a location reserved for making a first metal frame on the first ceramic substrate; Accordingly, the first chip is mounted on the prepared lower package structure as follows: A first chip is mounted inside a first metal frame on the first ceramic substrate, and a pad of the first chip is connected to a first metal column through a first bonding wire.

8. The hermetic packaging method according to claim 7, characterized in that: The specific preparation method of the intermediate packaging structure includes: preparing a second through hole on the second ceramic substrate, wherein the second through hole penetrates the upper surface and the lower surface of the second ceramic substrate; Filling metal in the second through hole to form a second metal column penetrating the upper surface and the lower surface of the second ceramic substrate; Prepare a front metal surrounding frame at a position reserved for setting the front metal surrounding frame on the front side of the second ceramic substrate; Prepare a back metal surrounding frame at a position reserved for setting a back metal surrounding frame on the back side of the second ceramic substrate; Accordingly, the second chip is mounted on the prepared intermediate package structure as follows: Mounting a second chip inside the front metal frame on the second ceramic substrate, and connecting the pad of the second chip to the second metal column through a second bonding wire; Accordingly, the middle packaging structure is welded on top of the lower packaging structure, and the second metal column connected to the second chip is connected to the first chip through the conductive structure to form a first packaging cavity accommodating the first chip: The back metal enclosure is welded on the top of the first metal enclosure, and the second metal column connected to the second chip is connected to the first chip or the first metal column through a conductive structure to form a first packaging cavity for accommodating the first chip.

9. The hermetic packaging method according to claim 8, characterized in that: Before preparing the front metal surrounding frame at the position reserved for setting the front metal surrounding frame on the front side of the second ceramic substrate, the method further includes: An isolation layer is prepared on the back side of the second ceramic substrate.

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