Implementing a multi-layer neural network using a crossbar matrix

Abstract

The present disclosure discloses a system and method for implementing a multi-layer neural network using a crossbar switch matrix. In some implementation methods, the device includes: a plurality of first devices, a plurality of second devices, and a plurality of first flow controllers connecting the plurality of first devices and the plurality of second devices. Each of the plurality of first flow controllers is independent of the other plurality of first flow controllers. In some implementation methods, the device also includes: a plurality of third devices; a plurality of second flow controllers connecting the plurality of second devices and the plurality of third devices; and a first common ground line separating the plurality of first flow controllers and the plurality of second flow controllers. Each of the plurality of second flow controllers is independent of each of the plurality of first flow controllers.

Description

Technical Field

[0001] The present disclosure relates to crossbar switch matrix circuits, and more particularly, to implementing a multi-layer neural network using one or more crossbar switch matrices. Background Art

[0002] High-performance neural networks typically include deep and wide neural layers, and their implementation involves performing a large number of large-scale matrix multiplications in sequence. A crossbar matrix may include rows and columns of metal wires (or electrodes) that cross each other, forming crosspoint devices at the intersections. However, a single crossbar matrix can perform a single vector-matrix multiplication.

[0003] Therefore, implementing multi-layer neural networks involving large-scale matrix multiplications remains a technical challenge. Summary of the invention

[0004] A device includes: a plurality of first devices; a plurality of second devices; and a plurality of first flow controllers connecting the plurality of first devices and the plurality of second devices, wherein each of the plurality of first flow controllers is independent of the other plurality of first flow controllers.

[0005] In some implementations, one of the plurality of first devices and / or one of the plurality of second devices includes: a memristor, a memristor system, a floating gate device, a phase change random access memory (PCRAM) device, a resistive random access memory (RRAM or ReRAM), a magnetoresistive random access memory (MRAM), a dynamic random access memory (DRAM), a static random access memory (static RAM or SRAM), or other devices with adjustable resistance.

[0006] In some implementation methods, the device also includes: a plurality of third devices; a plurality of second flow controllers connecting the plurality of second devices and the plurality of third devices; and a first common ground line separating the plurality of first flow controllers and the plurality of second flow controllers, wherein each of the plurality of second flow controllers is independent of each of the plurality of first flow controllers.

[0007] In some implementation methods, the device also includes: a plurality of fourth devices; a plurality of third flow controllers connecting the plurality of third devices and the plurality of fourth devices; and a second common ground line separating the plurality of second flow controllers and the plurality of third flow controllers, wherein each of the plurality of third flow controllers is independent of each of the plurality of second flow controllers.

[0008] In some implementation methods, the device also includes: multiple first metal layers; multiple second metal layers; and a signal source connected to the multiple first metal layers and the multiple second metal layers, wherein the multiple first metal layers and the multiple second metal layers are formed at both ends of the multiple second flow controllers.

[0009] A method includes: preparing an input signal for a device, the configuration including a plurality of first devices, a plurality of second devices, a plurality of third devices, a plurality of fourth devices, a plurality of first flow controllers connecting the plurality of first devices and the plurality of second devices, a plurality of second flow controllers connecting the plurality of second devices and the plurality of third devices, a plurality of third flow controllers connecting the plurality of third devices and the plurality of fourth devices; selecting one of the plurality of second flow controllers as a selected second flow controller; changing one of the plurality of second devices and one of the plurality of third devices located at both ends of the selected second flow controller to a conductive state; programming the selected second flow controller, wherein the plurality of second devices and the plurality of third devices are row devices.

[0010] A method includes: preparing an input signal for a device, the configuration including a plurality of first devices, a plurality of second devices, a plurality of third devices, a plurality of fourth devices, a plurality of first flow controllers connecting the plurality of first devices and the plurality of second devices, a plurality of second flow controllers connecting the plurality of second devices and the plurality of third devices, and a plurality of third flow controllers connecting the plurality of third devices and the plurality of fourth devices; selecting one of the plurality of second flow controllers as a selected second flow controller; changing one of the plurality of second devices and one of the plurality of third devices located at both ends of the selected second flow controller to an on state; changing other devices of the plurality of second devices located on the same column as one of the plurality of second devices to an off state; changing other devices of the plurality of third devices located on the same column as one of the plurality of third devices to an off state; programming the selected second flow controller, wherein the plurality of second devices and the plurality of third devices are column devices.

[0011] A device comprises: a plurality of first devices; a plurality of second devices; a plurality of third devices; a plurality of fourth devices; a plurality of first flow controllers connecting the plurality of first devices and the plurality of second devices; a plurality of second flow controllers connecting the plurality of second devices and the plurality of third devices; a plurality of third flow controllers connecting the plurality of third devices and the plurality of fourth devices; and a plurality of fourth flow controllers connecting the plurality of fourth devices and the plurality of first devices, wherein each of the plurality of first flow controllers, the plurality of second flow controllers, the plurality of third flow controllers and the plurality of fourth flow controllers is independent of the other flow controllers.

[0012] In some implementation methods, the device also includes: a first common ground line; a second common ground line, wherein the first common ground line separates the plurality of second flow controllers and the plurality of third flow controllers, and / or the plurality of third flow controllers and the plurality of fourth flow controllers.

[0013] In some implementations, a second common ground line separates the plurality of second flow controllers from the plurality of third flow controllers, and / or the plurality of first flow controllers from the plurality of fourth flow controllers. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram illustrating an exemplary neural network.

[0015] Figure 2 is a block diagram showing an exemplary transformation from 4D convolution to 2D dense matrix multiplication.

[0016] Figure 3A is a block diagram illustrating an exemplary multi-layer neural network implemented using a crossbar switch matrix circuit, according to some implementation methods.

[0017] Figure 3B and 3C is a block diagram illustrating two exemplary flow controllers according to some implementation methods.

[0018] Figure 4 is a block diagram illustrating an exemplary dual-tile crossbar switch matrix, according to some implementations.

[0019] Figure 5 is a block diagram illustrating an exemplary three-tile crossbar switch matrix, according to some implementations.

[0020] Figure 6 is a block diagram illustrating an exemplary four-tile crossbar switch matrix with row access transistors, according to some implementations.

[0021] Figure 7 is a block diagram illustrating an exemplary four-tile crossbar switch matrix with column-based access transistors, according to some implementations.

[0022] Fig. 8A is a block diagram illustrating an exemplary twelve-tile crossbar switch matrix, according to some implementations.

[0023] Figure 8B is a block diagram illustrating an exemplary twelve-tile crossbar switch matrix, according to some implementations.

[0024] Fig. 9is a block diagram illustrating an exemplary five-layer neural network, according to some implementation methods.

[0025] Fig.10 is a block diagram showing the Fig. 9 Example simulation results produced by a five-layer neural network are shown.

[0026] Fig.11 is a block diagram illustrating an exemplary five-layer neural network, according to some implementation methods.

[0027] Fig.12 is a flow chart illustrating an exemplary method for implementing a multi-layer neural network using a crossbar switch matrix, according to some implementation methods.

[0028] Fig.13 is a block diagram illustrating an exemplary computing system for implementing a multi-layer neural network using a crossbar switch matrix, according to some implementation methods.

[0029] The embodiments disclosed in the present disclosure are illustrated in the accompanying drawings by way of example and not limitation. Reference numerals refer to corresponding parts in the drawings. DETAILED DESCRIPTION

[0030] Systems and methods can use one or more crossbar switch matrices to implement high-performance and high-efficiency multi-layer neural networks. The technology described in the present disclosure can bring the following technical advantages. First, the programming signal for controlling the flow controller within the crossbar switch matrix and the programming signal for controlling the crosspoint device can have different signal thresholds, thereby reducing the disturbance and interference between the flow controller and the crosspoint device. Second, the programming signals for the flow controller can be programmed separately and independently of each other, which enables multiple crossbar switch matrices to be connected more compactly and can significantly improve power efficiency and circuit speed. Third, the crossbar switch matrix can be used to implement neural networks that require shortcut paths, such as residual networks (ResNet).

[0031] Figure 1 is a block diagram illustrating an exemplary neural network 100. A neural network typically comprises multiple layers, e.g. Figure 1 Neural network 100 is shown. In some implementations, data flows in from the leftmost layer (e.g., input layer) and results flow out from the rightmost layer (e.g., output layer), where each layer may involve calculations similar to the following:

[0032] Y n+l =F n (G n (W n5 Y n ))

[0033] Here, Y n represents the output matrix of the nth layer, Wn represents the weight matrix of the nth layer, W i,j G represents the weight between the i-th output of the n-th layer and the j-th input of the (n+1)-th layer. n Indicates description Y n How to use the nth layer W n Functions that perform calculations: In the fully connected layer, G n Can be the matrix product Y n W n ; In the convolutional layer, G n It can be a convolution operation Y n *W n . F n Describes how to process G at layer n n The computational complexity of the neural network can be determined by G, because G involves large-scale matrix multiplication (convolution can also be converted into matrix multiplication).

[0034] F n It can be a linear function (such as F n -a*G n +b), nonlinear functions (such as Softmax function), rectified linear unit (ReLU) function, pooling function or batch normalization function. n It can also be a combination of linear functions and nonlinear functions. The present disclosure provides a linear F n Function and nonlinearity F n One or more functions implementing different or the same F can be connected in series or in parallel. n Function circuit units to form more complex F n function.

[0035] Figure 2 2 is a block diagram showing an exemplary conversion 200 from 4D convolution to 2D dense matrix multiplication. 4D convolution is a common type of convolution used by neural networks to process images. n Probably convolution.

[0036] The exemplary conversion 200 can be implemented using a crossbar matrix. Each 2D convolution kernel is expanded into a vector and mapped to the columns of the crossbar matrix, so as long as there are a sufficient number of columns in the crossbar matrix, a crossbar matrix can implement multiple 2D convolution kernels. For the input signal, only the data in the convolution window is converted to the row input of the crossbar matrix. For multiple channel data, the 2D convolution kernels of different channels are stacked in the same column because the inputs from different channels may be provided to different rows and weighted summed. The input shift register stores the input data in the convolution in the current iteration and updates the stored data when the convolution window moves through the entire data space. The convolution results of the data in the convolution window are collected at the column output of the crossbar matrix. In this way, a single memristor-based convolution kernel needs to perform j*k iterations on input data of size (j, k, p), where j, k, and p represent data height, width, and channel, respectively.

[0037] Figure 3A is a block diagram illustrating an exemplary multi-layer neural network 200 implemented using a crossbar switch matrix circuit, according to some implementations.

[0038] like Figure 3A As shown, the crossbar switch matrix circuit 10 includes a tile crossbar switch matrix 20, a first flow controller array 30 and a second flow controller array 40. The tile crossbar switch matrix 20 includes a row line 21, a column line 23 and a crosspoint device 25 connecting the row line 21 and the column line 23. The first flow controller array 30 includes a first flow controller 31; the second flow controller array 40 includes a second flow controller 41.

[0039] The on / off states of the flow controllers (eg, the first flow controller 31 and the second flow controller 41 ) within the flow controller arrays 30 and 40 may be switched to generate a control signal flow within the tile crossbar switch matrix 2 .

[0040] Figure 3B and Figure 3C is a block diagram showing two exemplary flow controllers 32 and 33 according to some implementation methods. In some implementation methods, the flow controller can be a floating gate (e.g. Figure 3B flow controller 32 shown) or a memristor (e.g. Figure 3C In other implementations, the flow controller may be a neuron, or other two-terminal programmable device / circuit with desired linear or nonlinear characteristics, similar to G n .

[0041] In some implementations, the cross-point device may be one of the following devices: a memristor, a memristor system, a floating gate device, a phase change device, a resistive random access memory (RRAM or ReRAM), a magnetoresistive random access memory (MRAM), a dynamic random access memory (DRAM), a static random access memory (static RAM or SRAM), or other devices with adjustable resistance. In some implementations, the cross-point device may be a 1-transistor-1-resistor (1T1R), 1-selector-1-resistor (1S1R), or 2-resistor (2R) structure. The conductance of the cross-point device may be tuned by applying a sufficiently large voltage / current signal to the cross-point device. In some implementations, the row lines, column lines, or both are metal lines.

[0042] In an implementation including a 1T1R structure, the RRAM may be a two-terminal non-volatile memory based on a resistive switching effect. Exemplary devices may include RRAM, STT-MRAM, PCRAM, or any cross-point device with adjustable resistance. In certain embodiments, the transistor may be a semiconductor device configured to amplify or switch electronic signals and power. The transistor may be provided with at least three terminals for connecting to an external circuit. The transistors in the disclosed embodiments include bipolar junction transistors (BJTs), field effect transistors (FETs), high electron mobility transistors (HEMTs), TaOx devices, TiOx devices, HfOx devices, FeOx devices, and any devices with different switching materials.

[0043] Dual-Tile Crossbar Switch Matrix

[0044] Figure 4 is a block diagram illustrating an exemplary dual-tile crossbar switch matrix 400 , according to some implementations.

[0045] like Figure 4 As shown, the dual-tile crossbar switch matrix 400 includes a first tile crossbar switch matrix 101, a second tile crossbar switch matrix 103, and a flow controller array 102 connecting the first tile crossbar switch matrix 101 and the second tile crossbar switch matrix 103. The first tile crossbar switch matrix 101 includes row lines 111, column lines 131, and a crosspoint device 151 connecting the row lines 111 and the column lines 131.

[0046] In order to reduce the interference between the cross-point device (eg, the cross-point device 151 ) and the flow controller (eg, the flow controller 1021 ) within the dual-tile crossbar switch matrix 100 , the following two technical solutions may be implemented.

[0047] First, the flow controller is threshold programmed. In one exemplary implementation, a suddenly switched voltage or current is applied to the flow controller; as a result, the analog tuned crosspoint device is not accidentally programmed by such programming signals applied to the flow controller. In one exemplary implementation, the programming signals applied to the flow controller are significantly higher than those applied to the crosspoint device, thereby reducing potential interference with the crosspoint device.

[0048] Second, the programming signal for each flow controller is independent, so each flow controller can be programmed individually, and the programming signal path should pass through and only through the intended flow controller.

[0049] Three-tile crossbar switch matrix

[0050] Figure 5 is a block diagram illustrating an exemplary three-tile crossbar switch matrix 500 , according to some implementations.

[0051] Figure 5 A three-tile crossbar switch matrix 500 is shown. The three-tile crossbar switch matrix 500 includes a first tile crossbar switch matrix 201, a second tile crossbar switch matrix 203, a third tile crossbar switch matrix 205, a first flow controller array 202, a second flow controller array 204, and a common ground line 2031, the common ground line 2031 separating the first flow controller array 202 from the second flow controller array 204. In some implementations, the common ground line 2031 is specifically designed to electrically isolate the first flow controller array 202 from the second flow controller array 204 and achieve the advantages of two different groups of flow controller arrays that are programmed separately.

[0052] Before discussing the four-tile row cross-switch matrix and the four-tile column cross-switch matrix, attention should first be paid to the more common case of the cross-switch matrix. If there are no access transistors in the cross-point devices of the cross-switch matrix, there is no difference between the row and column embodiments. The column solution is applicable to cross-point devices without access transistors, and the cross-point devices on the same column need to be pre-programmed. If the four-tile cross-switch matrix is ​​a 1T1R structure with access transistors that can better control each cross-point device, the row and column solutions are different depending on whether the access transistor control lines are shared by rows or columns. According to the present disclosure, the following are embodiments of the four-tile row cross-switch matrix and the four-tile column cross-switch matrix.

[0053] Four-tile row crossbar switch matrix

[0054] Figure 6 is a block diagram illustrating an exemplary four-tile row crossbar switch matrix 600 , according to some implementations.

[0055] like Figure 6 As shown, the four-tile crossbar switch matrix 600 includes a first tile crossbar switch matrix 301, a second tile crossbar switch matrix 303, a third tile crossbar switch matrix 305, a fourth tile crossbar switch matrix 307, a first flow controller array 302, a second flow controller array 304, a third flow controller array 306, a first common ground line 3031 and a second common ground line 3051, wherein the first common ground line 3031 separates the first flow controller array 302 from the second flow controller array 304; and the second common ground line 3051 separates the second flow controller array 304 from the third flow controller array 306. In some implementation methods, the first common ground line 3031 and the second common ground line 3051 are specially designed to electrically isolate different flow controller arrays and realize the advantages of individually programmed flow controller arrays.

[0056] In an exemplary four-tile row-type embodiment, the second tile crossbar switch matrix 303 includes a first crosspoint device 3531 and a plurality of second crosspoint devices 3532 on the first column line 313; the third tile crossbar switch matrix 305 includes a third crosspoint device 3551 and a plurality of fourth crosspoint devices 3552 on the second column line 315. Since this is a row-type embodiment, the first crosspoint device 3531, the plurality of second crosspoint devices 3532, the third crosspoint device 3551, and the plurality of fourth crosspoint devices 3552 are row-type. Note that row-type means that when the access transistor is in the on state, current may only pass through the crosspoint device in the row direction. Therefore, in order to program the flow controller array individually in the four-tile row-type embodiment, the crosspoint devices 3531 and 3551 at both ends of the flow controller 3041 can be pre-programmed to the on state, so as to find the programming path of the flow controller, and then program the state of the flow controller 3041. Thanks to the shared ground lines 3031 and 3051, other flow controller arrays (eg, 302 and 306) will not be affected.

[0057] Four-tile column crossbar switch matrix

[0058] Figure 7 is a block diagram illustrating an exemplary four-tile column-based crossbar switch matrix 700 , according to some implementations.

[0059] like Figure 7As shown, the four-tile crossbar switch matrix 700 includes a first tile crossbar switch matrix 301, a second tile crossbar switch matrix 303, a third tile crossbar switch matrix 305, a fourth tile crossbar switch matrix 307, a first flow controller array 302, a second flow controller array 304, a third flow controller array 306, a first common ground line 3031 and a second common ground line 3051, wherein the first common ground line 3031 separates the first flow controller array 302 from the second flow controller array 304; and the second common ground line 3051 separates the second flow controller array 304 from the third flow controller array 306. In some implementation methods, the first common ground line 3031 and the second common ground line 3051 are specially designed to electrically isolate different flow controller arrays and realize the advantages of individually programmed flow controller arrays.

[0060] In an exemplary four-tile column-type embodiment, the second tile crossbar switch matrix 303 includes a first crosspoint device 353 and a plurality of second crosspoint devices 3532 on a first column line 313; the third tile crossbar switch matrix 305 includes a third crosspoint device 3551 and a plurality of fourth crosspoint devices 3552 on a second column line 315. Since this is a column-type embodiment, the first crosspoint device 3531, the plurality of second crosspoint devices 3532, the third crosspoint device 3551, and the plurality of fourth crosspoint devices 3552 are column-type. Note that column-type means that when the access transistor is in the on state, the current may only pass through the crosspoint device in the column direction. Therefore, in order to program the flow controller array individually in the four-tile column-type embodiment, in addition to pre-programming the crosspoint devices 3531 and 3551 at both ends of the flow controller 3041 to the on state, we also need to program the other crosspoint devices 3532 and 3552 on the same column to the off state, and then program the state of the flow controller 3041. Thanks to the common ground lines 3031 and 3051, other flow controller arrays (such as 302 and 306) will not be affected. In addition, since the cross point devices 3532 and 3552 are in the off state, other flow controllers in the flow controller array 304 will not be affected except for the flow controller 3041.

[0061] Twelve-tile crossbar switch matrix

[0062] Fig. 8A is a block diagram illustrating an exemplary twelve-tile crossbar switch matrix 800, according to some implementations. Fig. 8AIn the embodiment, the cross-point devices at both ends of the target flow controller are pre-programmed to the on state, and the cross-point devices at both ends of the other flow controllers on the same column are pre-programmed to the off state, so that all flow controllers can find the programming path by using a common ground line.

[0063] 3D structure of the crossbar switch matrix

[0064] like Fig. 8A As shown, by utilizing the location of a common ground line (e.g., 802a, 802b, 802c, 802d, 802e, 802f, 802g, and 802h), the flow controllers can be individually programmed and thus independent of each other.

[0065] However, in some crossbar switch matrix circuit designs, the flow controllers in the crossbar switch matrix 850 cannot be controlled individually using only the common ground line. Figure 8B As shown, if there is no programming path for programming the flow controller 404 alone without affecting other flow controllers, different metal layers (e.g., the first metal layer 401 and the second metal layer 402) can be connected to the two ends of the flow controller, thereby connecting to the input or output signal source. This is another 3D structure design when arranging a more complex crossbar switch matrix circuit. When applying the above crossbar switch matrix circuit embodiment in a neural network, please at least refer to Figure 9-11 Let's discuss an example of the convolution operation.

[0066] Fig. 9 is a block diagram showing an exemplary five-layer neural network 900 according to some implementation methods. The five-layer neural network in the crossbar switch matrix circuit 900 includes a first tile crossbar switch matrix 501, a second tile crossbar switch matrix 503, a third tile crossbar switch matrix 505, a fourth tile crossbar switch matrix 507, a first flow controller array 502, a second flow controller array 504, a third flow controller array 506, a fourth flow controller array 508, a first common ground line 5031, and a second common ground line 5051. The first common ground line 5031 separates the second flow controller array 504 from the third flow controller array 506, and / or separates the third flow controller array 506 from the fourth flow controller array 508. The second common ground line 5051 separates the third flow controller array 506 from the fourth flow controller 508, and / or separates the first flow controller array 502 from the fourth flow controller array 508. Therefore, all flow controllers of the five-layer neural network in the crossbar switch matrix are independent of each other. Thereby realizing individual programming function.

[0067] Before inserting the input data of the first matrix n1 into the first tile cross-switch matrix 501, the first flow controller array 502 is pre-programmed to the off state, the second weight matrix n2 is pre-programmed in the second flow controller array 504, the third weight matrix n3 is pre-programmed in the third flow controller array 506, and the fourth weight matrix n4 is pre-programmed in the fourth flow controller array 508. Therefore, when it outputs the data of the fifth matrix n5, the n1->n2->^n3->n4->n5 neural network is realized. In these implementations, it is assumed that the tile cross-switch matrix is ​​large enough to handle the size of the matrix. If it is not large enough, partitioning technology can be used.

[0068] Fig.10 is a block diagram showing the Fig. 9 Exemplary simulation results 1000 produced by a five-layer neural network are shown.

[0069] Simulation result 1000 shows the controlled current of four 16x16 tiles in a 32x32 crossbar switch matrix, in which a five-layer neural network is implemented. In some implementations, the resistance of devices and lines at different crosspoints may be different, thus affecting the current; the resistance difference can be compensated by compensating the corresponding input signal of the simulation result to reduce interference caused by different resistance levels in different devices. Fig.10 The solid arrows in the figure represent the current in the row direction; the dotted arrows represent the current in the column direction.

[0070] Fig.11 is a block diagram illustrating an exemplary five-layer neural network 1100 with shortcut functionality, according to some implementations.

[0071] Five-layer neural network 1100 and Fig. 9 The neural network 900 shown in FIG. 1 is similar to the neural network 900 shown in FIG. 1 , but has an additional shortcut path function. Some neural networks require shortcut paths to exist therein, such as residual networks (ResNet). Such networks require shortcut paths so that the output results from a certain layer can be passed not only to adjacent layers, but also to non-adjacent layers. For example, as shown in FIG. Fig.11 As shown, when the last flow controller 5021 in the first flow controller array 502 is switched to the on state, the output result from the first layer (n1) can be directly passed to the fifth layer (n5).

[0072] Fig.12 1 is a flowchart illustrating an exemplary method 1200 for implementing a multi-layer neural network using a crossbar matrix according to some implementation methods. The computer-implemented method 1200 can be used to construct at least the crossbar matrix shown in Figures 3-9. The computer system 1300 can execute the method 1200 when appropriately programmed.

[0073] In some implementations, the method 1200 includes preparing (1202) an input signal for a device. The device (1204) includes: a plurality of first devices, a plurality of second devices, a plurality of third devices, a plurality of fourth devices, a plurality of first flow controllers connected to the plurality of first devices and the plurality of second devices, a plurality of second flow controllers connected to the plurality of second devices and the plurality of third devices, and a plurality of third flow controllers connected to the plurality of third devices and the plurality of fourth devices.

[0074] In some implementations, the method 1200 further includes: selecting (1206) one of the plurality of second flow controllers as a selected second flow controller; turning (1208) one of the plurality of second devices and one of the plurality of third devices located at both ends of the selected second flow controller into a conductive state; and programming (1210) the selected second flow controller. The plurality of second devices and the plurality of third devices are row devices.

[0075] Fig.13 1 is a block diagram illustrating an exemplary computing system 1300 for implementing a multi-layer neural network using a crossbar switch matrix according to some implementation methods. The computer system 1300 may be used at least Figure 1 and 11 The crossbar or crossbar matrix shown. In some implementations, the computer system 1300 includes one or more processing units CPU 1302 (also referred to as processors), one or more network interfaces, an optional user interface, a memory 1306, and one or more communication buses 1310 for interconnecting these components. The communication bus 1310 may optionally include circuits (sometimes referred to as chipsets) that interconnect and control communication between system components. The memory 1306 typically includes a high-speed random access memory, such as DRAM, SRAM, DDR RAM, or other random access solid-state memory; and may optionally include non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. The memory 1306 may optionally include one or more storage devices away from the CPU 100. The memory 1306 or the non-volatile memory within the memory 1306 includes a non-transitory computer-readable storage medium. In some implementations, the memory 1306 or the non-transitory computer-readable storage medium is used to store the following programs, modules, data structures, or subsets thereof:

[0076] ■ an operating system 1310 (e.g., an embedded Linux operating system), including programs for handling various basic system services and for performing hardware-related tasks;

[0077] ■ Network communication module 1312, used to connect the computer system and production equipment through one or more network interfaces (wired or wireless);

[0078] ■Computing module 1314, for executing programming instructions;

[0079] ■ a controller 1316 for controlling the production equipment according to the executed programming instructions; and

[0080] ■User interaction module 13113 , used to enable a user to interact with the computer system 1300 .

[0081] One or more of the above-mentioned determined elements may be stored in one or more of the aforementioned memories and correspond to a set of instructions for performing the above-mentioned functions. The above-mentioned determined modules or programs (e.g., instruction sets) do not need to be implemented as separate software programs, programs or modules, and therefore, various subsets of these modules may be combined or rearranged in various implementations. In some implementation methods, the memory 1306 may selectively store a subset of the above-mentioned determined modules and data structures. In addition, the memory 1306 may also store other modules and data structures not described above.

[0082] Multiple instances may be provided for components, operations, or structures described as single instances in this disclosure. Finally, the boundaries between various components, operations, and data stores are somewhat arbitrary, and specific operations are described in the context of a specific illustrative configuration. Other functional allocations are foreseeable and may fall within the scope of implementation. Generally, structures and functions presented as separate components in the exemplary configuration may be implemented as a combined structure or component. Similarly, structures and functions presented as single components may also be implemented as separate components. These and other changes, modifications, additions, and improvements fall within the scope of implementation.

[0083] It should also be understood that although the present disclosure uses the terms "first," "second," etc. to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first column can be called the second column, and likewise, the second column can be called the first column without changing the meaning of the description, as long as all occurrences of "first column" are renamed consistently, and all occurrences of "second column" are also renamed consistently. The first column and the second column are still the original two columns, but each column is different from the original column.

[0084] The terms used in this disclosure are only used to describe specific implementations and are not intended to limit the claims. As used in the description of the various described embodiments and in the appended claims, the singular forms "a" and "the" also cover the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in this disclosure includes any and all combinations of one or more related listed items. In addition, it should be further understood that the terms "including" and / or "comprising" used in this disclosure specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or sets.

[0085] As used in this disclosure, the term "if" may be interpreted as "when" or "once" or "in response to determining" or "according to determining" or "in response to detecting" that the stated antecedent is true, depending on the context. Similarly, the phrase "if it is determined that (the stated antecedent is true)" or "if (the stated antecedent is true)" or "when (the stated antecedent is true)" may be interpreted as "once determined" or "in response to determining" or "according to determining" or "once detected" or "in response to detecting" that the stated antecedent is true, depending on the context.

[0086] The above description includes exemplary systems, methods, techniques, instruction sequences, and computer programs that embody the illustrative embodiments of the present disclosure. For illustrative purposes, numerous specific details are described in order to provide an understanding of various embodiments of the subject matter of the present invention. However, it is obvious to those skilled in the art that the subject matter of the present invention can be practiced without these specific details. Typically, well-known instruction instances, protocols, structures, and techniques are not necessarily shown in detail.

[0087] For illustrative purposes, the above description has been described with reference to specific embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. In view of the above teachings, many modifications and variations are possible. The embodiments selected and described are intended to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the embodiments and various modifications suitable for the specific use contemplated.

Claims

1. A device comprising: multiple first cross-point devices; a plurality of second cross point devices; as well as a plurality of first flow controllers connecting the plurality of first cross-point devices and the plurality of second cross-point devices, wherein Each of the plurality of first flow controllers is independent of the other plurality of first flow controllers, and the plurality of first flow controllers are used to control the current flowing through the plurality of first cross-point devices and the plurality of second cross-point devices.

2. The device according to claim 1, wherein the plurality of first cross-point devices and / or the plurality of second cross-point devices include a device with an adjustable resistance, wherein the device with an adjustable resistance includes at least one of a memristor, a memristor system, a floating gate device, a phase change random access memory (PCRAM) device, a resistive random access memory (RRAM or ReRAM), a magnetoresistive random access memory (MRAM), a dynamic random access memory (DRAM), and a static random access memory (static RAM or SRAM).

3. The device according to claim 1, further comprising: multiple third cross-point devices; a plurality of second flow controllers connected to the plurality of second cross-point devices and the plurality of third cross-point devices, wherein the plurality of second flow controllers are used to control current flowing through the plurality of second cross-point devices and the plurality of third cross-point devices; and a first common ground line separating the plurality of first flow controllers and the plurality of second flow controllers, wherein Each of the plurality of second flow controllers is independent of each of the plurality of first flow controllers.

4. The device according to claim 3, further comprising: multiple fourth cross point devices; a plurality of third flow controllers connected to the plurality of third cross-point devices and the plurality of fourth cross-point devices, wherein the plurality of third flow controllers are used to control current flowing through the plurality of third cross-point devices and the plurality of fourth cross-point devices; and A second common ground line separates the plurality of second flow controllers from the plurality of third flow controllers, wherein each of the plurality of third flow controllers is independent of each of the plurality of second flow controllers.

5. The device according to claim 4, further comprising: multiple first metal layers; multiple second metal layers; as well as A signal source connected to a plurality of first metal layers and a plurality of second metal layers, wherein A plurality of first metal layers and a plurality of second metal layers are formed at both ends of the plurality of second flow controllers.

6. A method comprising: An input signal is prepared for an apparatus, the apparatus comprising: a plurality of first cross-point devices, a plurality of second cross-point devices, a plurality of third cross-point devices, a plurality of fourth cross-point devices, a plurality of first flow controllers connecting the plurality of first cross-point devices and the plurality of second cross-point devices, a plurality of second flow controllers connected to the plurality of second cross-point devices and the plurality of third cross-point devices, and connecting a plurality of third flow controllers to the plurality of third cross-point devices and the plurality of fourth cross-point devices; selecting one of the plurality of second flow controllers as the selected second flow controller; Forming a programming path for programming the selected second flow controller includes: respectively turning on one of the plurality of second cross-point devices and one of the plurality of third cross-point devices connected to both ends of the selected second flow controller; and The selected second flow controller is programmed, wherein the second plurality of cross-point devices and the third plurality of cross-point devices are row devices.

7. The method according to claim 6, wherein the plurality of first cross-point devices and / or the plurality of second cross-point devices include a device with an adjustable resistance, and the device with an adjustable resistance includes at least one of a memristor, a memristor system, a floating gate device, a phase change random access memory (PCRAM) device, a resistive random access memory (RRAM or ReRAM), a magnetoresistive random access memory (MRAM), a dynamic random access memory (DRAM), and a static random access memory (static RAM or SRAM).

8. An apparatus comprising: multiple first cross-point devices; a plurality of second cross point devices; multiple third cross-point devices; multiple fourth cross point devices; a plurality of first flow controllers connected to the plurality of first cross-point devices and the plurality of second cross-point devices, wherein the plurality of first flow controllers are used to control current flowing through the plurality of first cross-point devices and the plurality of second cross-point devices; a plurality of second flow controllers connected to the plurality of second cross-point devices and the plurality of third cross-point devices, wherein the plurality of second flow controllers are used to control current flowing through the plurality of second cross-point devices and the plurality of third cross-point devices; a plurality of third flow controllers connected to the plurality of third cross-point devices and the plurality of fourth cross-point devices, wherein the plurality of third flow controllers are used to control current flowing through the plurality of third cross-point devices and the plurality of fourth cross-point devices; as well as a plurality of fourth flow controllers connected to the plurality of fourth cross-point devices and the plurality of first cross-point devices, wherein the plurality of fourth flow controllers are used to control current flowing through the plurality of first cross-point devices and the plurality of fourth cross-point devices, wherein Each of the plurality of first flow controllers, the plurality of second flow controllers, the plurality of third flow controllers, and the plurality of fourth flow controllers is independent of the other flow controllers.

9. The device according to claim 8, further comprising: The first common ground wire; as well as The second common ground wire, where The first common ground line separates the plurality of second flow controllers from the plurality of third flow controllers, and / or the plurality of third flow controllers from the plurality of fourth flow controllers.

10. The device according to claim 9, wherein the second common ground line separates the plurality of second flow controllers from the plurality of third flow controllers, and / or the plurality of first flow controllers from the plurality of fourth flow controllers.

Images