FPGA Control Board, Multi-Motor Topological Cascade Device Based on FPGA, and Cooperative Control System

Abstract

The present invention provides an FPGA control board, comprising an FPGA control board body. The FPGA control board body includes a board body and a plurality of signal interfaces, and the plurality of signal interfaces are fixedly installed at the edge of the board body. At least one power interface is included in the plurality of signal interfaces; the signal interface includes a first interface and a second interface; the first interface and the second interface are respectively arranged on two end faces of the board body, and the first interface and the second interface are respectively connected to the signal interfaces of adjacent and different FPGA control board bodies. The present invention also relates to a topology cascading device and a cooperative control system for multiple motors based on FPGA. By corresponding the first interface of one board body to connect the second interface of another board body, the FPGA control board body does not require other connection tools when performing topology connection, and can realize a three-dimensional network architecture by itself. Moreover, the topology cascading structure enables a plurality of motor components to be simultaneously controlled through a parallel processing method, improving the precision of synchronous control of multiple motor components.

Description

Technical Field

[0001] The present invention relates to the field of synchronous control of multi-motor components, and particularly to an FPGA control board and a multi-motor topology cascade device based on FPGA. Background Art

[0002] With the continuous maturity of the development and application of current computer information technology and microelectronics technology, the application scope of stepper motor components is increasingly wide and the maturity is constantly improving. As an execution part of automatic control, stepper motor components are applied in various fields and industries. Of course, when applying stepper motor components in many fields, it is necessary to coordinate and accurately control multiple stepper motor components. For example, medical microscopes, 3D printing, etc.

[0003] Of course, in recent years, with the rapid development of embedded technology and integration technology, it has become possible to realize a synchronous control system for multi-channel motor components. At present, a synchronous control scheme is mostly based on an ARM processor. Although its cost is relatively low, it is far inferior to FPGA technology in high-precision parallel processing. Moreover, the performance of its parallel program depends on the serialized part in the program, and the program performance will not continuously improve with the increase in the number of parallel threads. And too many threads will cause resource contention among threads for the processor, resulting in a decline in parallel performance. The resulting system response delay and blockage are unacceptable for some application scenarios that require both complex calculations and high time accuracy requirements, and may lead to irreversible catastrophic consequences.

[0004] FPGA (Field Programmable Gate Array) field programmable gate array is a further developed product based on programmable devices such as PAL and GAL. It appears as a semi-custom circuit in the field of application-specific integrated circuits (ASIC). It not only solves the deficiencies of custom circuits but also overcomes the shortcomings of limited gate circuits in the original programmable devices. FPGA is a chip composed of many logic gates to be configured. Different from specific application integrated circuit chips (ASIC) whose functions are determined by manufacturers, FPGA can be repeatedly configured according to the needs of different applications. Since FPGA can implement custom algorithms on hardware, and can also provide precise timing and synchronization, fast decision-making, and simultaneous execution of parallel tasks. Therefore, it is applied in various devices such as instruments, consumer electronics, automobiles, airplanes, copiers, and special application computer hardware.

[0005] For a long time, the work of programming FPGAs could only be carried out by engineers with in-depth knowledge of VHDL or other low-level design tools. However, mastering these tools requires a long time of learning and accumulation, which has restricted the development and application of FPGAs to a certain extent. Especially for small and medium-sized enterprises, the application cost is very high, and they are often reluctant to develop their own FPGA-based systems. After the emergence of the LabVIEW graphical tool, its additional LabVIEW FPGA module can redefine the logical functions of FPGAs without the need for knowledge of other design tools, and the logical functions of FPGAs on devices can be configured. This enables measurement and control engineers to focus on the testing and control applications they are good at without having to consider how to implement logical functions on each unit of the chip. This greatly facilitates user development and also promotes the application development of FPGAs. In addition, the parallelism of LabVIEW graphical programming is very suitable for the parallel architecture design of FPGAs, and parallel tasks in synchronous or asynchronous modes can be achieved.

[0006] However, conventional FPGA boards are mostly connected in a planar manner or use other connection tools for three-dimensional connection; the accuracy of synchronous operation of multiple motor components cannot be effectively controlled, and the efficiency is low. Summary of the Invention

[0007] In order to overcome the deficiencies of the prior art, the present invention provides an FPGA control board.

[0008] The present invention solves the above problems through an FPGA control board body including a number of first interfaces and second interfaces.

[0009] The present invention provides a multi-motor topology cascade device based on FPGA, including an FPGA control board body. The FPGA control board body includes a board body and a number of signal interfaces. A number of the signal interfaces are fixedly installed at the edge of the board body. At least one power interface is included in the number of signal interfaces, and the power interface is used to supply power to the FPGA control board body;

[0010] The signal interfaces include first interfaces and second interfaces; the first interfaces and the second interfaces are respectively arranged on two end faces of the board body, and the first interfaces and the second interfaces are respectively connected to the signal interfaces of adjacent and different FPGA control board bodies.

[0011] Preferably, the first interfaces and the second interfaces are installed staggeredly.

[0012] Preferably, the board body is a polygonal structure, and each side of the board body includes at least one of the first interfaces and the second interfaces.

[0013] Preferably, the first interface of one of the plate bodies is correspondingly connected to the second interface of the other plate body.

[0014] The present invention also provides a multi-motor topology cascading device based on FPGA, which includes several of the FPGA control board bodies and several execution units. Among the several FPGA control board bodies, there is a main control board and several FPGA control sub-boards. The main control board sends instructions to the several FPGA control sub-boards. The main control board and the FPGA control sub-boards form a topology cascading structure through the signal interface, and the sub-level of the topology cascading structure is connected to several execution units.

[0015] Preferably, the execution unit includes a motor assembly, and the motor assembly is connected to the last level of the topology cascading structure; the mother level of the FPGA control sub-board is at least connected to the main control board, and the sub-level of the FPGA control sub-board is at least connected to several of the motor assemblies.

[0016] Preferably, several of the FPGA control sub-boards are connected through signal interfaces to form a three-dimensional network structure, and the first interface of one FPGA control sub-board is connected to the second interface of another FPGA control sub-board.

[0017] The present invention also provides a cooperative control system for multi-motors based on FPGA, which includes the above-mentioned multi-motor topology cascading device based on FPGA and a control device. The control device includes the topology cascading structure to receive instructions from the main control board. The topology cascading structure creates multiple operation paths within the same clock cycle so that several of the motor assemblies can respond to the instructions of the main control board simultaneously.

[0018] Preferably, the signal interface is a USB Type-C interface.

[0019] Preferably, the control device further includes a limit sensor. The limit sensor is installed on the motor assembly, and the limit sensor sends the detected signal to the main control board. The main control board sends a stop instruction to the motor assembly so that the motor assembly returns to the initial position.

[0020] Preferably, a voltage conversion module is included between the main control board and the power interface. The voltage conversion module is used to convert the voltage of the main control board into the voltage acceptable by the FPGA control sub-board.

[0021] Preferably, the control device further includes a serial port IP core. When the FPGA control sub-board performs data transmission, it calls the serial port IP core and creates a FIFO queue. The FIFO queue makes the data go first in first out during the transmission process.

[0022] Preferably, the motor assembly and the FPGA control sub-board respectively include a motor assembly number flag bit and an FPGA address bit, and the motor assembly and the FPGA control sub-board are identified and located through the motor assembly number flag bit and the FPGA address bit when transmitting instructions.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] The present invention discloses an FPGA control board, a multi-motor topology cascading device based on FPGA, and a cooperative control system. The FPGA control board body includes a board body and a plurality of signal interfaces. The first interface and the second interface are respectively fixedly installed on the upper surface and the lower surface of the board body. By correspondingly connecting the first interface of one board body to the second interface of another board body, the FPGA control board body can realize a three-dimensional network architecture without other connection tools when performing topology connection.

[0025] A plurality of FPGA control board bodies form a topology cascading structure through a plurality of signal interfaces. The topology cascading structure enables a plurality of motor assemblies to be controlled simultaneously through a parallel processing method, improving the accuracy of synchronous control of multiple motor assemblies. The FPGA main control board of the topology cascading structure distributes the total control signal layer by layer to the lower layer, and a plurality of motor assemblies simultaneously respond to the instructions sent by the main control board.

[0026] A plurality of FPGA control sub-boards perform signal processing in parallel, which can not only improve the signal processing efficiency and the accuracy of synchronous control of multiple motor assemblies, but also avoid affecting the operation of other FPGA control sub-boards when one FPGA control sub-board fails.

[0027] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly and implement it according to the content of the specification, the following takes the preferred embodiments of the present invention and combines the drawings to describe in detail as follows. The specific implementation manners of the present invention are given in detail by the following embodiments and their drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings described herein are used to provide a further understanding of the present invention and form a part of this application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0029] Figure 1 is a three-dimensional overall structure diagram of an FPGA control board of the present invention;

[0030] Figure 2 is a partial three-dimensional schematic diagram of a multi-motor topology cascading device based on FPGA of the present invention;

[0031] Figure 3For Figure 2 The enlarged view of part A of Figure 2 ;

[0032] Figure 4 Schematic diagram of the connection relationship between an FPGA control board and a motor assembly of a multi-motor topology cascading device based on FPGA according to the present invention;

[0033] Figure 5 Schematic diagram for explaining the motor communication instructions of a multi-motor topology cascading device based on FPGA according to the present invention;

[0034] Figure 6 Schematic diagram of the motor assembly of a multi-motor topology cascading device based on FPGA according to the present invention;

[0035] Figure 7 Schematic diagram of a cooperative control system for multi-motors based on FPGA according to the present invention;

[0036] Figure 8 The topology cascading structure formed by using the multi-motor topology cascading device of the present invention;

[0037] Reference numerals: 100, topology cascading structure; 10, FPGA control board body; 110, power interface; 120, first interface; 130, second interface; 140, board body; 20, motor assembly; 210, drive assembly; 220, display panel. Detailed implementation manners

[0038] Next, in combination with the accompanying drawings and specific implementation manners, the present invention will be further described. It should be noted that, on the premise of no conflict, any combination of the following-described embodiments or technical features can form a new embodiment.

[0039] The present invention provides an FPGA control board, as Figure 1As shown in the figure, it includes the FPGA control board body 10. The FPGA control board body 10 includes a board body 140 and a number of signal interfaces. The number of signal interfaces is fixedly installed at the edge of the board body 140. Among the number of signal interfaces, there is a power interface 110. The power interface 110 is used to supply power to the FPGA control board body 10. The signal interfaces include a first interface 120 and a second interface 130. The first interface 120 and the second interface 130 are respectively arranged on both end faces of the board body 140. The first interface 120 and the second interface 130 are respectively connected to the signal interfaces of adjacent and different FPGA control board bodies 10. In one embodiment, by fixedly installing a number of first interfaces 120 and second interfaces 130 on the upper and lower surfaces of the board body 140 respectively, and connecting the first interface 120 of one board body 140 to the second interface 130 of another board body 140, the FPGA control board body 10 can realize a three-dimensional network architecture without other connection tools when performing topological connection.

[0040] The first interface 120 and the second interface 130 are installed staggeredly, which can increase its stability during the connection process of a number of FPGA control board bodies 10. In addition, it can also make the installation process more convenient and fast.

[0041] The board body 140 is a polygonal structure, and each side of the board body 140 includes at least one first interface 120 and a second interface 130. Preferably, the board body is rectangular, and each side of the board body 140 includes at least one first interface 120 and a second interface 130. Each side of the board body 140 includes at least two signal interfaces, namely the first interface 120 and the second interface 130. One of the four sides also includes a power interface 110. Preferably, each side includes two signal interfaces, namely the first interface 120 and the second interface 130. The power interface 110 is installed on one of the four sides, that is, there are a total of nine signal interfaces. Topology is performed on the FPGA control board body 10 according to the number of required motor components. A number of FPGA control board bodies 10 are topologically connected through the first interface 120 and the second interface 130 to form a topological cascade structure 100.

[0042] Among the number of signal interfaces, there is a power interface 110. In this embodiment, the number of power interfaces 110 is preferably one. When the number of FPGA control board bodies 10 in the control system is small, one power interface 110 is connected to the main control board, and the main control board provides power for a number of FPGA control board bodies in the control system. When the data of the FPGA control board bodies 10 in the control system is relatively large and the main control board cannot provide power for a large number of FPGA control board bodies 10, the power interface of each FPGA control board body 10 can be connected to a dedicated power supply device. The setting of the power interface increases the flexibility of the control system.

[0043] The present invention provides a multi-motor topology cascading device based on FPGA, as Figure 2 shown. Figure 3 It includes a number of FPGA control board bodies and a number of execution units. Among the number of FPGA control board bodies, there is a main control board and a number of FPGA control sub-boards. The main control board sends instructions to the number of FPGA control sub-boards. The main control board and the FPGA control sub-boards form a topology cascading structure through signal interfaces, and the sub-levels of the topology cascading structure are connected to a number of execution units. In one embodiment, the connection between the FPGA control board body and external devices is all achieved using signal interfaces, preferably USB Type-C interfaces. For example, the connection between two adjacent FPGA control sub-boards, the connection between the FPGA control sub-board and the execution unit, the connection between the FPGA control sub-board and the main control board, etc. The FPGA control sub-board forms a topology cascading structure through signal interfaces, and a number of execution units are connected to the sub-level of the topology cascading structure. When more execution units are needed, the topology can continue on the last-level FPGA control sub-board.

[0044] Specifically, as Figure 6 shown, the embedded computer maps the input image pixels to a number of motor components 20. The motor components include a drive component 210 and a display panel 220. Each motor component 20 maps one pixel point in the image pixels, so that the input image drives the display panel 220 to move differently through a number of motor components 20 to obtain a three-dimensional display diagram. Each motor component 20 corresponds to one pixel point of the input image. The motor component 20 receives instructions from the main control board. The motor component 20 drives the display panel 220 to move according to the received instructions through the drive component 210. The instructions include the step size, the speed of movement, the direction of movement, etc.; the entire image includes a number of pixel points corresponding to a number of motor components 20. The embedded computer analyzes the gray value of the input image to send instructions to each motor component 20, so that each display panel 220 moves a certain step size according to the instructions, and finally a three-dimensional effect diagram is displayed on the cascade board. The three-dimensional effect diagram will present different effects according to different input images.

[0045] The topology cascading structure is that a number of FPGA control board bodies are connected to form a three-dimensional network structure. This network architecture is similar to the "brain-like" structure, that is, a structure formed by simulating the operation of the human brain. Each FPGA control sub-board can be regarded as an independent neuron, and its function can be customized. Any two FPGA control sub-boards can communicate. This network structure can form a huge and complex hardware neural network structure without additional fixation through its own connection.

[0046] The execution unit includes a motor assembly, and the motor assembly is connected to the last stage of the topological cascade structure; the mother level of the FPGA control daughter board is at least connected to the main control board, and the daughter level of the FPGA control daughter board is at least connected to several motor assemblies. In one embodiment, the execution unit is preferably a motor assembly, and the motor assembly is connected to the last stage of the topological cascade structure. The mother level of the FPGA control daughter board is connected to the upper-level FPGA control daughter board or the main control board, and is also connected to the FPGA control daughter board at the same level. Of course, it at least includes the main control board; the daughter level of the FPGA control daughter board is connected to the lower-level FPGA control daughter board or the motor assembly, and is also connected to the FPGA control daughter board at the same level. Of course, it at least includes the motor assembly. The FPGA control board determines its own position during configuration, that is, what its mother level, peer level, and lower level are respectively.

[0047] The present invention also provides a cooperative control system for multiple motors based on FPGA, as Figure 7 shown, including a multi-motor topological cascade device and a control device based on FPGA. The control device includes a topological cascade structure that receives instructions from the main control board. The topological cascade structure creates multiple operation paths within the same clock cycle so that several motor assemblies can respond to the instructions of the main control board simultaneously. In one embodiment, the main control board is an embedded computer. The embedded computer is a small and rugged industrial control and acquisition system that uses FPGA technology to achieve ultra-high performance and customizable functions. This embedded computer can be rapidly developed using the efficient LabVIEW graphical programming tool and the supporting FPGA module. Its working performance and optimization characteristics can be comparable to those of a specially customized hardware circuit. A voltage conversion module is included between the main control board and the power interface. The voltage conversion module is used to convert the voltage of the main control board into the voltage acceptable to the FPGA control daughter board. In this embodiment, the main control board is an embedded computer, and the 5V voltage of the embedded computer is converted into the 3.3V voltage required by the FPGA control daughter board through the conversion module, that is, the USB Type-C interfaces of all FPGA control daughter boards are 3.3V voltages.

[0048] The topological cascade structure creates a multi-way loop structure in the same clock cycle to make several motor components run synchronously. The LabVIEW FPGA development module is used to create multiple while loops in the FPGA program using the same clock cycle. DIR and CLK are set to F when each loop is initialized. The motor component is in an idle state at this time. When receiving a forward or reverse command, the program jumps to the corresponding step. At this time, the CLK pin will send high and low levels according to the set number of pulses. At the same time, the direction is set to T when forward and F when reverse. When a reset command is received, the FPGA will send continuous pulses to the motor component until the limit switch signal is detected to be high, and the pulse sending stops. In the whole process, data transmission will be realized by calling the dedicated serial port IP core of LabVIEW FPGA.

[0049] The control device also includes a serial IP core. The FPGA control subboard calls the serial IP core and creates a FIFO queue when transmitting data. The FIFO queue allows data to be first in first out during the transmission process. The communication interface is a USB Type-C interface. The USB Type-C interface uses the LabVIEW FPGA module to design a serial communication protocol, which includes serial port opening, writing, reading and closing operations. Each protocol is called in the FPGA compilation layer. After the protocol is encapsulated, the compilation system must be executed. After the compilation is successful, it is loaded into the FPGA chip for communication. The encapsulation in this embodiment solves the problems of high encapsulation requirements and difficult maintenance of the traditional Verilog language. The currently common peripherals and bus protocols, such as AD, DA, USB, Gigabit Ethernet, IIC, SPI, SSI, Camera, serial communication, SD card reading and writing, encoder acquisition, RTC, EEPROM, Flash, VGA, PID, FFT, etc., are all reconstructed using Verilog. In this way, the execution efficiency of the encapsulated IP core is higher than that of the communication IP core that comes with LabVIEW. The FIFO queue allows data to be first in first out, without causing data loss. Each data 25 motor components respond to operations simultaneously according to unified instructions.

[0050] Specifically, it also includes a handheld terminal, which is connected to the main control board, and the main control board receives the instructions sent by the handheld terminal. In one embodiment, the handheld terminal includes a motor component step setting module, a speed setting module, a direction control module, a step display module, and a handle control module, preferably a wired handle, which is connected to the embedded computer via USB, and the wired handle controls the system by sending instructions through buttons. The control process of the control system is achieved by customizing the buttons of the wired handle and parsing the instructions using the software protocol to implement the handle control software, which greatly improves the control feel and convenience of the device. The handle can also complete the control of the system through a wireless handle, and wireless connection is an existing technology, such as through Bluetooth.

[0051] The control device further includes a limit sensor which is installed on the motor assembly. The limit sensor sends the detected signal to the FPGA control sub-board, and the FPGA control sub-board sends a stop instruction to the motor assembly to make the motor assembly return to the initial position. When the FPGA control sub-board receives the detection signal sent by the limit sensor, that is, when the FPGA control sub-board receives the reset instruction, the FPGA control sub-board sends a stop instruction to the motor assembly and the motor assembly is reset. The motor assembly includes a driving block and a motor. The driving block is used to drive the motor to rotate. The driving block includes a driving chip and a power supply module. The driving chip is respectively connected to the signal pin of the FPGA control sub-board and the motor, and the power supply module is used to supply power to the driving chip. In one embodiment, as Figure 4 shown, the motor is preferably a stepper motor. The blue, black, red, and yellow wires of the stepper motor assembly are respectively connected to the driving wires A+, A-, B+, B- of the driving block. The 24V power supply pin on the driving chip is connected to the DC power supply. The DIR on the driving chip is connected to DIO0 of the GPIO pin on the FPGA control sub-board. The CLK on the driving chip is connected to DIO1 of the GPIO on the FPGA control board. The limit switch on the motor assembly is connected to DIO2 of the GPIO on the FPGA control sub-board. In this way, a total of three GPIO pins are required for one motor assembly. Generally, each USB Type-C interface of the FPGA processor has 24 GPIO pins, 4 of which are grounded and 4 are used for power supply, and there are still 16 pins left. So each USB Type-C can connect 5 motor assemblies. Preferably, each FPGA chip board can mount 5×5 = 25 motor assemblies. If more motor assemblies need to be synchronized, the FPGA control sub-board needs to be cascaded and expanded through the USB Type-C interface, which greatly improves the scalability of the system.

[0052] As Figure 5 shown, the motor assembly and the FPGA control sub-board respectively include a motor assembly number flag bit and an FPGA address bit. When the motor assembly and the FPGA control sub-board perform instruction transmission, they are identified and located through the motor assembly number flag bit and the FPGA address bit. In one embodiment, the communication instruction of a single motor assembly is transmitted to the lower computer through the serial port mode. Each instruction includes a frame header, a frame tail, an FPGA board address bit, a motor assembly number bit, a stop or start flag bit, a forward or reverse flag bit, a forward or reverse cycle bit, and a step size. When multiple FPGA control sub-boards are cascaded, the system performs instruction transmission by parsing the FPGA address bit. Similarly, different motor assembly instructions also complete data transmission by parsing the motor assembly number flag bit, which ensures that the instructions of the entire system are passed down level by level and effectively avoids the occurrence of instruction crosstalk.

[0053] Apply a multi-motor topology cascading device based on FPGA of the present invention to a topology cascading structure with 9,600 motor components, as Figure 8 shown below:

[0054] The 9,600 motor components adjust the stepping amount of each motor component's movement according to the image pixel values input by the embedded computer, and finally simulate a 120*80 pixel three-dimensional stereogram, which changes according to the change of the image input by the embedded computer.

[0055] The first level of the topology cascading structure is the main control board. The main control board at the first level, i.e., the one numbered 1 in the figure, is connected to four FPGA control sub-boards at the second level, i.e., 2-1, 2-2, 2-3, and 2-4 in the figure, through USB Type-C. Among them, the connection of the power supply interface is also included (not shown in the figure); each of the four FPGA control sub-boards at the second level topology-out four FPGA control sub-boards, that is, there are a total of sixteen FPGA control sub-boards at the third level, i.e., 3-1 to 3-16 in the figure; similarly, at the fourth level, there will be 16X4 = 64 FPGA control sub-boards, and only four of them, i.e., 4-1 to 4-4, are shown in the figure. Each of the sixteen FPGA control sub-boards at the third level will topology-out four FPGA control sub-boards, for a total of sixty-four. At the fifth level, there will be 64x6 = 384 FPGA control sub-boards, and only some of them are shown in the figure. In this way, a total of 1 + 4 + 16 + 64 + 384 = 469 FPGA control boards are used in this topology cascading structure. Among them, the fifth level, i.e., 5-1 to 5-6, is the last level of the entire topology cascading structure. The last level is connected to a number of motor components through USB Type-C. Some motors are shown in the figure. As described above, each USB Type-C interface can connect 5 motor components, i.e., motor 1, motor 2, motor 3, motor 4, and motor 5. Each FPGA control sub-board has 8 USB Type-C interfaces. Therefore, each FPGA control sub-board can connect 40 motors. However, each FPGA control sub-board also needs to be connected to the upper-level, lower-level, and peer FPGA control sub-boards through USB Type-C. Therefore, each FPGA control sub-board in this example is connected to 5 USB Type-C interfaces, and each USB Type-C interface can connect 5 motor components. Therefore, each FPGA control sub-board can connect 5x5 = 25 motor components. There are 384 FPGA control sub-boards at the last level, and 384*25 = 9,600 motor components can be connected.

[0056] It should be noted that in this embodiment, one FPGA control sub-board has 9 USB Type-C interfaces, including one power interface. In the second and third levels, not all 8 USB Type-C interfaces of each FPGA control sub-board are utilized, resulting in interface redundancy. This will be topologically arranged reasonably according to the number of motor components required by the topological cascade structure and specific requirements.

[0057] It should also be noted that during the configuration of several FPGA control boards, each FPGA control board is configured to clarify the position of the FPGA control board, that is, to clarify the superior, inferior, and peer of each FPGA control board.

[0058] The above is only a preferred embodiment of the present invention, and it is not intended to limit the present invention in any form; any ordinary technician in the industry can implement the present invention smoothly according to the instructions in the attached drawings and the above; however, any equivalent changes such as slight modifications, decorations, and evolutions made by those skilled in the art within the scope of the technical solution of the present invention using the technical content disclosed above are equivalent embodiments of the present invention; at the same time, any equivalent changes, modifications, and evolutions made to the above embodiments based on the substantial technology of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. An FPGA control board, characterized in that, it includes an FPGA control board body, and the FPGA control board body includes a board body and several signal interfaces. Several of the signal interfaces are fixedly installed at the edge of the board body. At least one power interface is included in several of the signal interfaces, and the power interface is used to supply power to the FPGA control board body; the signal interfaces include a first interface and a second interface; the first interface and the second interface are respectively arranged on both end faces of the board body. The first interface and the second interface are respectively connected to the signal interfaces of adjacent and different FPGA control board bodies, and the first interface and the second interface are installed staggeredly; the board body is a rectangular structure, and each side of the board body includes at least one of the first interface and the second interface; wherein, the first interface of one board body is correspondingly connected to the second interface of another board body.

2. A multi-motor topology cascading device based on FPGA, characterized in that, it includes several FPGA control boards as described in claim 1, and also includes several execution units. Among several FPGA control board bodies, there is a main control board and several FPGA control sub-boards. The main control board sends instructions to several FPGA control sub-boards. The main control board and the FPGA control sub-boards form a topology cascading structure through the signal interfaces, and the sub-level of the topology cascading structure is connected to several execution units; the execution unit includes a motor assembly, and the motor assembly is connected to the last level of the topology cascading structure; the mother level of the FPGA control sub-board is at least connected to the main control board, and the sub-level of the FPGA control sub-board is at least connected to several motor assemblies.

3. A multi-motor topology cascading device based on FPGA as described in claim 2, characterized in that, several of the FPGA control sub-boards are connected through the signal interfaces to form a three-dimensional network structure, and the first interface of one FPGA control sub-board is connected to the second interface of another FPGA control sub-board.

4. A cooperative control system for multi-motors based on FPGA, characterized in that, it includes a multi-motor topology cascading device based on FPGA as described in claim 2, and also includes a control device. The control device receives the instructions of the main control board through the topology cascading structure. The topology cascading structure creates multiple operation paths within the same clock cycle, so that several motor assemblies can respond to the instructions of the main control board simultaneously.

5. A cooperative control system for multi-motors based on FPGA as described in claim 4, characterized in that, the signal interface is a USB Type-C interface.

6. A cooperative control system for multi-motors based on FPGA as described in claim 4, characterized in that, the control device further includes a limit sensor. The limit sensor is installed on the motor assembly, and the limit sensor sends the detected signal to the main control board. The main control board sends a stop instruction to the motor assembly so that the motor assembly returns to the initial position.

7. A collaborative control system for multiple motors based on FPGA as claimed in claim 4, characterized in that, a voltage conversion module is included between the main control board and the power interface, and the voltage conversion module is used to convert the voltage of the main control board into the voltage acceptable to the FPGA control sub-board.

8. A collaborative control system for multiple motors based on FPGA as claimed in claim 4, characterized in that, the control device further includes a serial port IP core. When the FPGA control sub-board performs data transmission, it calls the serial port IP core and creates a FIFO queue, and the FIFO queue makes the data first-in first-out during the transmission process.

9. A collaborative control system for multiple motors based on FPGA as claimed in claim 4, characterized in that, the motor assembly and the FPGA control sub-board respectively include a motor assembly number flag bit and an FPGA address bit, and the motor assembly and the FPGA control sub-board are identified and located through the motor assembly number flag bit and the FPGA address bit when performing instruction transmission.

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