Semiconductor subassemblies and semiconductor power modules

Abstract

The present invention relates to a semiconductor subassembly and a semiconductor power module, which can have a reduced chip thickness and reduced thermal resistance. The semiconductor subassembly includes a single or multiple semiconductor chips, the semiconductor chip having a first electrode formed on its lower surface, a second electrode formed on its upper surface, and a plurality of chip-side signal electrode pads formed at one end of its upper surface. The semiconductor chip is embedded in an embedded structure, and a plurality of extended signal electrode pads are correspondingly connected to the chip-side signal electrode pads. When viewed on a plane, the extended signal electrode pad is formed on the embedded substrate with a size larger than the chip-side signal electrode pad.

Description

Technical Field

[0001] The present invention relates to a semiconductor sub-assembly and a semiconductor power module, and more particularly, to a semiconductor sub-assembly capable of minimizing and reducing thermal resistance and a semiconductor power module having the semiconductor sub-assembly. Background Art

[0002] The heat dissipation performance of semiconductor power modules is being improved, and in addition, the development trend is to reduce the installed semiconductor chips. For example, in a double-sided cooling package, equivalent cooling performance can be obtained using about half the size of a single-sided cooling package. In addition, in silicon carbide (SiC) power devices as an example of power semiconductors, it is expected that equivalent performance can be obtained using chips that are 1 / 5 the size of traditional chips. At the same time, in double-sided cooling packages, the connection structure with signal terminals becomes an obstacle to size reduction. As the chip size decreases, the signal electrode pads on the chip surface are also reduced, which makes it reasonable to make the wires used for connection smaller, but there are problems with mechanical strength and reliability.

[0003] A developed technology discloses an internal structure of a semiconductor power module capable of double-side cooling. Bonding wires are used to connect to signal terminals. Considering the wiring space, wire bonding connection requires ensuring an insulating space inside a semiconductor package.

[0004] However, the wire bonding connection has a large number of assembly operations. Instead of wire bonding, there is an example of manual connection using a ball grid array (BGA), but in the case of a double-sided cooling package, the position matching accuracy of the package and the chip is low. Therefore, it is preferred that such a semiconductor chip packaging structure can replace the wire bonding connection, correspond to a reduced size signal electrode pad, and reduce thermal resistance.

[0005] Figure 6 1 is a conventional example of a package of a power semiconductor 1 according to the prior art. Specifically, the power semiconductor 1 is an insulated gate bipolar transistor (IGBT). IGBT is called an insulated gate bipolar transistor and is used to operate a three-phase alternating current (AC) motor, etc. IGBT has three terminals: collector C, emitter E and gate G. Figure 1A The semiconductor chip 1a of the IGBT shown is shown in a plan view (top view), and the second electrode 3 (3b) of the emitter E is rectangular on its surface. The first electrode 3 (3a) of the collector C is on the lower surface of the back side. The semiconductor chip 1a of the IGBT has, for example, five chip-side signal electrode pads 2. This includes the control line of the gate G, the input / output line of the temperature sensor (e.g., diode) prepared therein, etc.

[0006] like Figure 6 As shown, the semiconductor power module 200 of the IGBT is packaged in a package 9 and has a semiconductor chip 1a of the IGBT, a direct copper bonding (DCB) substrate 4, 4', a plurality of external signal terminals 8, a spacer 7, a first external electrode terminal 22, and a second external electrode terminal 23. The semiconductor chip 1a of the IGBT is arranged at the center thereof, the conductive spacer 7 is welded on the semiconductor chip 1a, and the DCB substrate 4' is connected to the conductive spacer 7. The DCB substrate 4 is also connected to the lower side of the semiconductor chip 1a of the IGBT.

[0007] The DCB substrate has a three-layer structure in which a copper plate 4b is directly bonded to each of the upper and lower sides of a ceramic plate 4a. The upper and lower sides of the semiconductor chip 1a of the IGBT are bonded so that the semiconductor chip 1a is inserted between two DCB substrates 4, 4' (for example, a first direct copper bonding substrate and a second direct copper bonding substrate). The second external electrode terminal 23 is led out from the upper DCB substrate 4', and the first external electrode terminal 22 is led out from the lower DCB substrate 4. Figure 6 As can be seen on the right side of the semiconductor power module 200, the external signal terminal 8 is led out to the outside. The external signal terminal 8 is connected to the semiconductor chip 1a of the IGBT through the wire bonding connection 6. In such a conventional structure, the temperature may rise due to the thermal resistance of the spacer 7, and a space for the wire bonding connection is also required, so it is difficult for the semiconductor power module 200 to have a thin thickness.

[0008] The above information disclosed in this section is only for deepening the understanding of the background of the invention and therefore the information it may contain does not constitute the prior art that is already known in this country to those skilled in the art. Summary of the invention

[0009] The present invention provides a semiconductor subassembly and a semiconductor power module which can have a reduced chip thickness and reduced thermal resistance.

[0010] According to an exemplary embodiment of the present invention, a semiconductor sub-component may include: a single or multiple semiconductor chips 1a, an embedded substrate 12, and a plurality of extended signal electrode pads 11, wherein the single or multiple semiconductor chips 1a have a first electrode 3a formed on a lower surface thereof, a second electrode 3b formed on an upper surface thereof, and a plurality of chip-side signal electrode pads 2 formed at one end of the upper surface thereof; the embedded substrate 12 has the semiconductor chip 1a embedded therein; the plurality of extended signal electrode pads 11 are correspondingly connected to the chip-side signal electrode pads 2, and when viewed on a plane, the extended signal electrode pads 11 may be formed on the embedded substrate 12 with a size larger than the chip-side signal electrode pads 2.

[0011] In addition, in the semiconductor sub-assembly according to the exemplary embodiment of the present invention, an opening 19 for accommodating a semiconductor chip can be formed in the embedded substrate 12; the first electrode 3a can be electrically and thermally connected to the first electrode pad 13 installed on the entire lower surface of the embedded substrate 12; the second electrode 3b can be exposed to the upper surface of the semiconductor chip 1a; the chip-side signal electrode pad 2 can be connected to the extended signal electrode pad 11 through a connecting wiring installed on the upper surface of the embedded substrate 12; the first electrode pad 13 and the extended signal electrode pad 11 can be formed by metal electroplating; at least one pair of adjacent chip-side signal electrode pads 2 among the multiple chip-side signal electrode pads 2 of the semiconductor chip 1a can have a first side connected to a connecting wiring 17 included in a first wiring layer 15 formed on the embedded substrate 12, and a second side connected to a connecting wiring 18 included in a second wiring layer 16 formed on the first wiring layer 15, an insulating layer is interposed between the first wiring layer and the second wiring layer, and the connecting wiring 17 included in the first wiring layer 15 and the connecting wiring 18 included in the second wiring layer 16 are formed to have areas overlapping each other in the vertical direction.

[0012] In the semiconductor subassembly according to the exemplary embodiment of the present invention, when a plurality of semiconductor chips 1 a are connected in parallel, corresponding signal electrodes of chip-side signal electrode pads 2 of semiconductor chips 1 a may be connected to each other and to corresponding extended signal electrode pads 11 .

[0013] In addition, the semiconductor power module according to the exemplary embodiment of the present invention is a semiconductor power module in which the semiconductor sub-assembly 100 is utilized, the first electrode pad 13 of the semiconductor sub-assembly can be connected to the first electrode terminal 20 of the DCB substrate 4 mounted on the lower side of the first electrode pad 13; the first external electrode terminal 22 can be connected to the first electrode terminal 20; the second electrode 3b of the semiconductor chip 1a can be connected to the second electrode terminal 21 of the DCB substrate 4' mounted on the upper side of the second electrode 3b; the second external electrode terminal 23 can be connected to the second electrode terminal 21; and the plurality of extended signal electrode pads 11 connected to the chip-side signal electrode pad 2 of the semiconductor chip 1a can be connected to the plurality of external signal terminals 8. When viewed on a plane, the insulation distance can be ensured by insulating between the second electrode terminal 21 and the extended signal electrode pad 11 and between the second electrode terminal 21 and the external signal terminal 8.

[0014] In addition, in the semiconductor power module according to the exemplary embodiment of the present invention, the connection between the first electrode pad 13 and the first electrode terminal 20, the connection between the second electrode 3b and the second electrode terminal 21, and the connection between the extended signal electrode pad 11 and the external signal terminal 8 can be performed by welding.

[0015] The semiconductor subassembly according to the present invention:

[0016] (a) An extended signal electrode pad 11 having a larger size can be formed on an embedded substrate 12 in which a semiconductor chip 1a is embedded, and the extended signal electrode pad 11 and the chip-side signal electrode pad 2 of the semiconductor chip 1a are connected, thereby connecting the signal external terminal to the extended signal electrode pad 11 without relying on a wiring bonding connection.

[0017] (b) Wire bonding connections can be omitted, thereby making the chip thinner.

[0018] (c) In addition, the spacer can be omitted, thereby reducing the two welding processes to one.

[0019] (d) In addition, the spacer can be omitted, thereby improving the thermal resistance by about 20% through thinning.

[0020] (e) In addition, the spacer may be omitted so that the first external electrode terminal 22 and the second external electrode terminal 23 are close to each other to achieve low inductance.

[0021] In addition, a first electrode pad 13 of a metal plating layer may be prepared on the entire lower surface of the embedded substrate 12, so that the first electrode 3a of the semiconductor chip 1a is well bonded to the first side surface of the first electrode pad 13 by welding, and the first electrode terminal 20 of the DCB substrate 4 is bonded to the second side surface. The second electrode 3b of the semiconductor chip 1a may have a second electrode pad 14 of a metal plating layer inserted therein, so that it is well bonded to the first electrode terminal 20 of the DCB substrate 4' by welding.

[0022] The chip-side signal electrode pad 2 and the extended signal electrode pad 11 can be connected by two layers of connection wiring, and the first layer of connection wiring and the second layer of connection wiring can overlap each other in the vertical direction, thereby reducing inductance. In other words, the two lines corresponding to the gate / source wiring of the signal terminal can be parallel and overlap each other in the vertical direction, thereby reducing inductance.

[0023] Furthermore, in the case of parallel connection, for example, corresponding signal electrodes in the subassembly can be connected to each other, thereby operating two SiC-MOSFETs using one G terminal. The signal electrodes between semiconductor chips can be greatly shortened.

[0024] According to the semiconductor power module of the present invention, the insulation distance can be ensured by insulating between the second electrode terminal 21 and the extended signal electrode pad 11 and between the second electrode terminal 21 and the external signal terminal 8, thereby providing an insulation space for suppressing the influence of the signal terminal on the second electrode terminal 21. In addition, the space in the height direction such as wire bonding can be omitted, thereby reducing the thickness of the semiconductor power module.

[0025] Furthermore, the connection between the first electrode pad 13 and the first electrode terminal 20, the connection between the second electrode 3b and the second electrode terminal 21, and the connection between the extended signal electrode pad 11 and the external signal terminal 8 can be performed by welding, thereby improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of the present invention will now be described in detail with reference to exemplary embodiments of the illustrative drawings, which are given below for illustration purposes only and are therefore non-limiting to the present invention, wherein:

[0027] Figures 1A to 1D To illustrate a schematic diagram of a semiconductor power module according to an exemplary embodiment of the present invention, Figure 1D is the symbol of IGBT;

[0028] Figure 2A and Figure 2B is a schematic diagram showing a semiconductor subassembly according to an exemplary embodiment of the present invention;

[0029] Figure 3 A schematic diagram showing a semiconductor power module model for temperature analysis according to an exemplary embodiment of the present invention;

[0030] Figure 4A and Figure 4B A diagram showing a comparison of temperature distributions of a semiconductor power module according to an exemplary embodiment of the present invention and a conventional semiconductor power module;

[0031] Figure 5A and Figure 5B A schematic diagram showing an example of mounting a plurality of power semiconductors on a subassembly according to an exemplary embodiment of the present invention; and

[0032] Figure 6 FIG. 1 is a schematic diagram showing an example of a conventional power semiconductor package according to the prior art.

[0033] It should be understood that the drawings are not necessarily drawn to scale, but rather present simplified representations of various features to illustrate the basic principles of the invention. The specific design features of the invention disclosed herein (including, for example, specific dimensions, orientations, locations, and shapes) will be determined in part by the specific target application and the environment of use. In these figures, throughout the multiple figures of the drawings, the reference numerals represent the same or equivalent parts of the invention. DETAILED DESCRIPTION

[0034] It should be understood that the term "vehicle" or "vehicle-related" or other similar terms used herein generally include motor vehicles, such as passenger cars including sport utility vehicles (SUVs), buses, trucks, various commercial vehicles, ships including various boats, ships, aircraft, etc., and include hybrid vehicles, electric vehicles, plug-in hybrid electric vehicles, hydrogen-powered vehicles, and other alternative fuel vehicles (e.g., fuels derived from non-petroleum energy sources). As referred to herein, a hybrid vehicle is a vehicle having two or more power sources, such as both gasoline-powered and electric-powered vehicles.

[0035] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "one", "an" and "said" are intended to also include plural forms, unless the context clearly states otherwise. It will also be further understood that when the terms "include" and / or "include" are used in this specification, it is indicated that the features, numerical values, steps, operations, elements and / or components exist, but the presence or addition of one or more other features, numerical values, steps, operations, elements, components and / or their groups are not excluded. As used herein, the term "and / or" includes any and all combinations of one or more related enumerated items.

[0036] Unless otherwise stated or apparent from the context, the term "about" as used herein is understood to be within the normal tolerance range in the art, such as within 2 standard deviations of the mean. "About" may be understood to be within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, 0.5%, 0.1%, 0.05%, or 0.01% of a specified value. Unless otherwise apparent from the context, all numerical values ​​provided herein are modified by the term "about".

[0037] A semiconductor subassembly and a semiconductor power module according to the present invention will be described below with reference to the accompanying drawings.

[0038] Figures 1A to 1D Schematic diagram of a semiconductor power module 200 according to the present invention. Specifically, the power semiconductor 1 is a semiconductor chip 1a of an IGBT, and the symbol of the IGBT is as follows: Figure 1D shown. Figure 1A It is a plan view, the second electrode 3b can be formed on the upper surface of the semiconductor chip 1a, and the first electrode 3a can be formed on its back. Five chip-side signal electrode pads 2 can be formed on the right side of the semiconductor chip 1a. Specifically, there are control lines of the gate G or input / output lines of two prepared temperature sensor elements.

[0039] Figure 1B is a plan view of the semiconductor subassembly 100. Figure 1B As shown, an opening 19 for embedding the semiconductor chip 1a can be installed in the embedded substrate 12. After the semiconductor chip 1a is embedded therein, the first electrode pad 13 can be formed at the bottom of the embedded substrate 12 by metal plating. Therefore, the first electrode 3a on the back of the semiconductor chip 1a and the first electrode pad 13 can be electrically and thermally connected. Similarly, the five chip-side signal electrode pads 2 of the embedded substrate 12 can be formed by metal plating.

[0040] Figure 1C To show a schematic diagram of the internal structure of the semiconductor power module 200, after metal plating, the semiconductor subassembly 100 may be mounted to form the semiconductor power module 200. The first electrode pad 13 of the semiconductor subassembly 100 may be connected to the first electrode terminal 20 of the DCB substrate 4 mounted thereunder by welding. In addition, the first electrode terminal 20 has a first external electrode terminal 22 pre-connected at one end thereof.

[0041] The second electrode 3b of the semiconductor chip 1a, that is, the second electrode pad 14 formed on the second electrode 3b, can be connected to the second electrode terminal 21 of the DCB substrate 4' mounted on the upper portion thereof by welding 10. In addition, the second electrode terminal 21 may include a second external electrode terminal 23 pre-connected at one end thereof. As a result, the first electrode 3a on the lower surface of the semiconductor chip 1a is led out to the first external electrode terminal 22 of the semiconductor power module 200, and the second electrode 3b on the upper surface of the semiconductor chip 1a is led out to the second external electrode terminal 23 of the semiconductor power module 200.

[0042] The extended signal electrode pad 11 may be connected to the external signal terminal 8 by soldering 10. As a result, the five chip-side signal electrode pads 2 of the semiconductor chip 1a may be led out to the second external electrode terminal 23 of the semiconductor power module 200 by inserting the extended signal electrode pad 11. In addition, the insulation distance may be ensured by insulating between the second electrode terminal 21 and the extended signal electrode pad 11 and between the second electrode terminal 21 and the external signal terminal 8.

[0043] Figure 2A and Figure 2BFIG. 1 is a schematic diagram showing a semiconductor subassembly 100 according to the present invention. Figure 2A is a plan view of a semiconductor subassembly 100, Figure 2B For along Figure 2A The connection between the chip-side signal electrode pad 2 of the semiconductor chip 1a and the extended signal electrode pad 11 can be made in a wiring layer of two metal plating layers. The wiring layer can include a first wiring layer 15 and a second wiring layer 16.

[0044] like Figure 2A As shown, three right-side extended signal electrode pads 11 spaced apart from the semiconductor chip 1a may be formed on the first wiring layer 15 at the lower portion thereof, and two left-side extended signal electrode pads 11 adjacent to the semiconductor chip 1a may be formed on the second wiring layer 16 at the upper portion thereof. The connection between the chip-side signal electrode pad 2 and the three right-side extended signal electrode pads 11 may be performed through the connection wiring 17 of the first wiring layer 15 at the lower portion thereof. The connection between the chip-side signal electrode pad 2 and the two left-side extended signal electrode pads 11 may be performed through the connection wiring 18 of the second wiring layer 16 at the upper portion thereof. Here, the connection wiring 17 included in the first wiring layer 15 may be formed to have a wider width (e.g., about 1 mm) and have an area overlapping with the connection wiring 18 included in the second wiring layer 16 in the vertical direction. As a result, when the direction of the current is applied to two wirings in opposite directions, the inductance may be reduced.

[0045] like Figure 2B As shown, the first electrode 3a can be electrically and thermally connected to the first electrode pad 13 by a metal plating layer installed on the entire lower surface of the embedded substrate 12. The second electrode 3b of the semiconductor chip 1a can be exposed on the upper surface of the semiconductor chip 1a (having a thickness of about 250 microns), and the second electrode pad 14 of the metal plating layer can be thinly formed on the surface of the second electrode 3b. High thermal resistance high insulation resin 24 can be used for the embedded substrate 12 (having a thickness of about 150 microns).

[0046] Figure 3 Schematic diagram showing a model of a semiconductor power module 200 for temperature analysis according to the present invention. The semiconductor chip 1a can be embedded in the semiconductor subassembly 100 and can be composed of a structure inserted between ceramic DCB substrates 4 and 4' (e.g., first and second) in a vertical direction. L1 and L2 are power layers or signal layers.

[0047] Figure 4A and Figure 4BFIG. 2 is a diagram showing a comparison of temperature distributions of the semiconductor power module 200 according to the present invention and a conventional semiconductor power module. In addition, the size of the semiconductor chip is a square of about 12 mm×12 mm, and double-side cooling is performed.

[0048] exist Figure 4A and Figure 4B In the figure, the chip temperature Rth when 50W is applied is compared. Figure 4A As shown, in the traditional structure, Rth is calculated to be 0.1℃ / W, as Figure 4B As shown, in the present invention Figure 3 In the structure shown, Rth is calculated to be 0.08°C / W. These figures show that the thermal resistance can be improved by about 20%. When 50W is multiplied by Rth, it is 5°C in the conventional structure and 4°C in the structure of the present invention, so the temperature can be reduced by about 1°C.

[0049] Figure 5A and Figure 5B Schematic diagram showing an example of mounting multiple power semiconductors on one subassembly. SiC-MOSFET is currently about 5mm×5mm, and the same is true for SiC-SBD. Figure 5A and Figure 5B As shown, since SiC-MOSFET is small in size and high in speed compared to IGBT, and the current capacity of each chip is small, multiple chips can be arranged in a parallel circuit to increase the current capacity. In this parallel circuit, the diode and the transistor are connected in parallel so that the first electrode pad 13 and the second electrode pad 14 connected to the S terminal and the D terminal can be shared. In addition, the two G terminals can also connect the corresponding connection wirings 17 of the first wiring layer 15 to each other, thereby sharing an extended signal electrode pad 11.

[0050] The present invention is very suitable as a semiconductor sub-assembly which is compact and can reduce thermal resistance, and a semiconductor power module having the semiconductor sub-assembly mounted thereon.

Claims

1. A semiconductor subassembly comprising: a single or a plurality of semiconductor chips having a first electrode formed on a lower surface thereof, a second electrode formed on an upper surface thereof, and a plurality of chip-side signal electrode pads formed at one end portion of the upper surface thereof; an embedded substrate in which the semiconductor chip is embedded; as well as a plurality of extended signal electrode pads, the plurality of extended signal electrode pads being correspondingly connected to the chip-side signal electrode pads; Wherein, when viewed on a plane, the extended signal electrode pad is formed on the embedded substrate with a size larger than the chip-side signal electrode pad; An opening for accommodating a semiconductor chip is formed in the embedded substrate; The electrical connection between the chip-side signal electrode pad and the extended signal electrode pad of the semiconductor chip is formed in a two-layer metal-plated wiring layer, the wiring layer including a first wiring layer and a second wiring layer; The first electrode is electrically and thermally connected to a first electrode pad mounted on the entire lower surface of the embedded substrate, and the second electrode is exposed to the upper surface of the semiconductor chip; The chip-side signal electrode pad is connected to the extended signal electrode pad through a connection wiring mounted on the upper surface of the embedded substrate.

2. The semiconductor subassembly of claim 1, wherein: The first electrode pad and the extended signal electrode pad are formed by metal electroplating; At least one pair of adjacent chip side signal electrode pads among a plurality of chip side signal electrode pads of a semiconductor chip has a first side connected to a connection wiring included in a first wiring layer formed on an embedded substrate, and a second side connected to a connection wiring included in a second wiring layer formed on the first wiring layer, an insulating layer is interposed between the first wiring layer and the second wiring layer, and the connection wiring included in the first wiring layer and the connection wiring included in the second wiring layer are formed to have areas overlapping each other in a vertical direction.

3. The semiconductor subassembly of claim 1, wherein: When a plurality of semiconductor chips are connected in parallel, the first electrode and the second electrode are shared.

4. A semiconductor power module comprising the semiconductor subassembly according to claim 1, wherein: A first electrode pad of the semiconductor subassembly is connected to a first electrode terminal of a first direct copper bonding substrate mounted on a lower side of the first electrode pad; a first external electrode terminal connected to the first electrode terminal; The second electrode of the semiconductor chip is connected to a second electrode terminal of a second direct copper bonding substrate mounted on an upper side of the second electrode; a second external electrode terminal connected to the second electrode terminal; A plurality of extended signal electrode pads connected to the chip-side signal electrode pads of the semiconductor chip are connected to a plurality of external signal terminals; When viewed on a plane, an insulation distance is ensured by insulation between the second electrode terminal and the extended signal electrode pad and insulation between the second electrode terminal and the external signal terminal.

5. The semiconductor power module according to claim 4, wherein: The connection between the first electrode pad and the first electrode terminal, the connection between the second electrode and the second electrode terminal, and the connection between the extended signal electrode pad and the external signal terminal are all performed by welding.

6. A semiconductor power module comprising the semiconductor subassembly according to claim 2, wherein: A first electrode pad of the semiconductor subassembly is connected to a first electrode terminal of a first direct copper bonding substrate mounted on a lower side of the first electrode pad; a first external electrode terminal connected to the first electrode terminal; The second electrode of the semiconductor chip is connected to a second electrode terminal of a second direct copper bonding substrate mounted on an upper side of the second electrode; a second external electrode terminal connected to the second electrode terminal; A plurality of extended signal electrode pads connected to the chip-side signal electrode pads of the semiconductor chip are connected to a plurality of external signal terminals; When viewed on a plane, an insulation distance is ensured by insulation between the second electrode terminal and the extended signal electrode pad and insulation between the second electrode terminal and the external signal terminal.

7. The semiconductor power module according to claim 6, wherein: The connection between the first electrode pad and the first electrode terminal, the connection between the second electrode and the second electrode terminal, and the connection between the extended signal electrode pad and the external signal terminal are all performed by welding.

8. A semiconductor power module comprising the semiconductor subassembly according to claim 1, wherein: A first electrode pad of the semiconductor subassembly is connected to a first electrode terminal of a first direct copper bonding substrate mounted on a lower side of the first electrode pad; a first external electrode terminal connected to the first electrode terminal; The second electrode of the semiconductor chip is connected to a second electrode terminal of a second direct copper bonding substrate mounted on an upper side of the second electrode; a second external electrode terminal connected to the second electrode terminal; A plurality of extended signal electrode pads connected to the chip-side signal electrode pads of the semiconductor chip are connected to a plurality of external signal terminals; When viewed on a plane, an insulation distance is ensured by insulation between the second electrode terminal and the extended signal electrode pad and insulation between the second electrode terminal and the external signal terminal.

9. The semiconductor power module according to claim 8, wherein: The connection between the first electrode pad and the first electrode terminal, the connection between the second electrode and the second electrode terminal, and the connection between the extended signal electrode pad and the external signal terminal are all performed by welding.

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