Image sensor, image sensor module, and method of manufacturing image sensor

Abstract

An image sensor, an image sensor module, and a method for manufacturing the image sensor are provided. The image sensor includes: a photoelectric converter located in a pixel region of a substrate to generate photoelectrons in response to incident light incident on the pixel region; a signal generator located on a first surface of the substrate in the pixel region to generate an electrical signal corresponding to image information of an object according to the photoelectrons; and a pixel separation pattern penetrating the substrate from the first surface of the substrate to a second surface of the substrate opposite to the first surface of the substrate, the pixel separation pattern including an insulating pattern having a refractive index less than that of the substrate and a metal conductive pattern surrounded by the insulating pattern, and the pixel region is surrounded by the pixel separation pattern and isolated from adjacent pixel regions.

Description

[0001] Korean Patent Application No. 10-2018-0126241, filed on October 22, 2018 in the Korean Intellectual Property Office and entitled “IMAGE SENSOR, IMAGE SENSOR MODULE AND METHOD OF MANUFACTURING THE IMAGE SENSOR” is hereby incorporated by reference in its entirety. Technical Field

[0002] Example embodiments relate to an image sensor, an image sensor module having the same, and a method of manufacturing the same, and more particularly, to a CMOS image sensor, an image sensor module having the same, and a method of manufacturing the CMOS image sensor. Background Art

[0003] Recently, high-resolution image sensor modules have been widely used in various digital devices such as digital cameras and smart phones, and thus there has been a great demand for image sensors for converting optical signals (or image signals) into electrical signals. For example, charge coupled devices (CCDs) and complementary metal oxide semiconductor (CMOS) devices have been mainly used as image sensors.

[0004] Specifically, a CMOS image sensor (CIS) can be manufactured by a conventional semiconductor manufacturing process, and the image quality of the CIS can be simply and easily improved only by improving a signal processing algorithm. Therefore, the CIS has been more widely used in recent digital devices. Summary of the invention

[0005] According to an exemplary embodiment, an image sensor is provided, the image sensor including: a photoelectric converter located in a pixel region of a substrate and generating photoelectrons in response to incident light incident on the pixel region; a signal generator arranged on a first surface of the substrate in each pixel region and generating an electrical signal corresponding to image information of an object according to the photoelectrons; a pixel separation pattern penetrating the substrate from the first surface to the second surface so that the pixel region can be surrounded by the pixel separation pattern and can be isolated from an adjacent pixel region. The pixel separation pattern may include an insulating pattern having a refractive index less than that of the substrate and a metal conductive pattern surrounded by the insulating pattern.

[0006] According to an exemplary embodiment, there is provided an image sensor module, the image sensor module comprising: an image sensor having a plurality of unit pixels for generating an electrical signal corresponding to an image of an object according to incident light, such that the unit pixels can be separated and isolated from each other by a separation pattern penetrating a substrate; and an image signal processor (ISP) electrically connected to the image sensor and processing the electrical signal to thereby generate image data of the object. The separation pattern may include an insulating pattern and a metal conductive pattern surrounded by the insulating pattern.

[0007] According to an exemplary embodiment, a method for manufacturing the above-mentioned image sensor is provided. An ion implantation process may be performed on the first surface of a substrate having an illumination area, a black area, and a contact area, thereby forming a photoelectric converter layer in the illumination area and the black area of ​​the substrate. The photoelectric converter layer may generate photoelectrons according to the incident light. Then, a dummy separation pattern may be formed to extend from the first surface of the substrate to the inside of the substrate, thereby defining a pixel area having a photoelectric converter, a reference cell area having a photoelectric converter, and a contact margin area in the illumination area, the black area, and the contact area of ​​the substrate, respectively. The dummy separation pattern may include an insulating pattern having a refractive index less than that of the substrate and a dummy pattern surrounded by the insulating pattern. A signal generator and a wiring structure connected to the signal generator may be sequentially formed on the first surface of the substrate. The signal generator may generate an electrical signal corresponding to an image of an object according to photoelectrons. The rear portion of the substrate opposite to the first surface may be partially removed until the dummy separation pattern may be exposed through the second surface of the substrate. Then, a metal replacement process may be performed on the second surface of the substrate to thereby replace the dummy pattern with a metal conductive pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 shows a plan view of an image sensor according to example embodiments;

[0010] Figure 2 Shown along Figure 1 A cross-sectional view taken along line II';

[0011] Figure 3 Shows Figure 2 A cross-sectional view of a first modified example of the image sensor in;

[0012] Figure 4 Shows Figure 2 A cross-sectional view of a second modified example of the image sensor in;

[0013] Figure 5 Shows Figure 2A cross-sectional view of a third modified example of the image sensor in;

[0014] Fig. 6A Shows Figure 2 A cross-sectional view of a fourth modified example of the image sensor in;

[0015] Figure 6B Shows Figure 2 A cross-sectional view of a fifth modified example of the image sensor in FIG.

[0016] Figure 7 shows a block diagram of an image sensor module according to an example embodiment;

[0017] Figure 8 Shows Figure 7 A plan view of an image sensor of an image sensor module;

[0018] Fig. 9 Shown along Figure 8 A cross-sectional view taken along line II-II';

[0019] Fig.10 Shows Figure 8 A circuit diagram of a unit pixel of an image sensor in FIG.

[0020] FIG. 11A to FIG. 11O Shows the manufacturing Fig. 9 A cross-sectional view of a stage in a method of manufacturing an image sensor module;

[0021] FIG. 12A to FIG. 12E Shows the manufacturing Figure 3 A cross-sectional view of a stage in a method of providing an image sensor module in an image sensor; and

[0022] FIG. 13A to FIG. 13C Shows the manufacturing Figure 4 A cross-sectional view of a stage in a method of manufacturing an image sensor module of an image sensor. DETAILED DESCRIPTION

[0023] Reference will now be made to example embodiments illustrated in the drawings, wherein like reference numerals may refer to like components throughout.

[0024] Figure 1 is a plan view illustrating an image sensor according to example embodiments, Figure 2 is along Figure 1 Cross-sectional view along line II'.

[0025] Reference Figure 1 and Figure 2, an image sensor 90 according to an example embodiment may include a substrate 10 having a plurality of pixel regions A, a photoelectric converter 20 disposed in the substrate 10 at each pixel region A and generating photoelectrons in response to incident light R incident on the pixel region A, a signal generator 30 generating an electrical signal corresponding to the photoelectrons as an image signal, and a pixel separation pattern 40 penetrating the substrate 10 and surrounding the pixel region A in such a configuration that the pixel separation pattern 40 includes an insulating pattern 41 having a refractive index less than that of the substrate 10 and a metal conductive pattern 45 filled into the insulating pattern 41. Therefore, the photoelectric converter 20, the signal generator 30, and the pixel separation pattern 40 in the pixel region A may constitute a unit pixel UP of the image sensor 90.

[0026] For example, the substrate 10 may include a semiconductor substrate. In an example embodiment, the semiconductor substrate 10 may include a bulk silicon substrate to which a plurality of p-type impurities may be locally doped, so that some p-type wells may be arranged on the bulk silicon substrate. In addition, a p-type epitaxial layer may also be arranged on the p-type bulk silicon substrate, so that the substrate 10 may include a double-layer semiconductor substrate. In addition, the bulk silicon substrate may be removed from the double-layer semiconductor substrate, so that the substrate 10 may include a p-type single epitaxial layer. In addition, the substrate 10 may include an n-type bulk substrate, an n-type epitaxial layer, and a double-layer semiconductor of an n-type bulk substrate and an n-type epitaxial layer.

[0027] The substrate 10 may include a first surface 11 and a second surface 12 opposite to the first surface 11. The first surface 11 may correspond to the front surface of the silicon wafer, and the signal generator 30 and the wiring structure 50 may be arranged on the first surface 11 of the substrate 10, for example, the first surface 11 of the substrate 10 may face the wiring structure 50. The signal generator 30 may include at least one transistor that may be formed by a semiconductor manufacturing process. The second surface 12 may correspond to the rear surface of the silicon wafer, and the buffer layer 60 and the light-transmitting unit 70 may be arranged on the second surface 12 of the substrate 10, for example, the second surface 12 of the substrate 10 may face the buffer layer 60. Therefore, the image sensor 90 may be configured as a backside illumination structure in which light may be incident on the second surface 12 from the outside (i.e., incident on the back side of the substrate 10).

[0028] The substrate 10 may be separated into a plurality of pixel regions A by the deep trench hole DTH, for example, the pixel regions A may be arranged in a matrix pattern in the x direction and the y direction, and the pixel separation pattern 40 may be located in each of the deep trench holes DTH. Therefore, adjacent pixel regions A adjacent to each other may be separated from each other by the pixel separation pattern 40, for example, in the x direction and the y direction.

[0029] The photoelectric converter 20 and the signal generator 30 may be arranged in each pixel region A. The photoelectric converter 20 may be positioned in the substrate 10 and may generate photoelectrons in response to incident light R incident on the corresponding pixel region A. The signal generator 30 may be arranged on the first surface 11 of the substrate 10 and may generate an electrical signal corresponding to the photoelectrons. Figure 2 As shown in , the photoelectric converter 20 can be positioned within the substrate 10 between the second surface 12 of the substrate 10 and the signal generator 30. For example, as shown in Figure 2 As shown in FIG. 1 , the signal generator 30 may be positioned within the substrate 10 between the first surface 11 of the substrate 10 and the photoelectric converter 20. The electrical signal may provide image information of an object from which incident light may be reflected.

[0030] Specifically, one or more photoelectric converters 20 may be arranged in a single pixel region A, and a plurality of electron-hole pairs may be generated in response to incident light R, and may be collected in the photoelectric converter 20. The electron-hole pairs generated by the incident light R are known as photoelectrons. That is, the photoelectric converter 20 may be positioned deeply in the pixel region A, so the photoelectric converter 20 may be positioned away from the first surface 11 and near the second surface 12, for example, the photoelectric converter 20 may be positioned closer to the second surface 12 than the first surface 11. In addition, the photoelectric converter 20 may intersect (e.g., overlap) substantially the entire surface of the pixel region A to expand the light receiving area as much as possible, thereby improving the light receiving efficiency of the photoelectric converter 20.

[0031] For example, the photoelectric converter 20 may include a first doping layer and a second doping layer, which may be vertically stacked in a p-type semiconductor substrate 10 to which a plurality of p-type impurities may be doped. In this example embodiment, the first doping layer may include an n-type impurity, and the second doping layer may include a p-type impurity. Therefore, the substrate 10, the first doping layer, and the second doping layer may be configured as a PNP junction structure in the substrate 10, and the photoelectric converter 20 may be used as a photodiode PD. That is, the photodiode PD may be provided as the photoelectric converter 20.

[0032] Although the present exemplary embodiment discloses a photodiode PD as the photoelectric converter 20, any other photoelectric structure may be used as the photoelectric converter 20. For example, a phototransistor, a photogate, and a pinned photodiode (PPD) may also be used as the photoelectric converter 20.

[0033] In addition, the present exemplary embodiment discloses that a single photoelectric converter 20 may be arranged in a single pixel region A, but the embodiment is not limited thereto. For example, two or more photoelectric converters 20 may also be arranged in a single pixel region A depending on the configuration of the image sensor 90 .

[0034] For example, the signal generator 30 may be arranged at a surface portion of the first surface 11 of the substrate 10 at each pixel region A, and may generate an electrical signal corresponding to photoelectrons as image information of the object. The well region W may be provided between the first surface 11 and the photoelectric converter 20. The well region W may be doped with impurities of a semiconductor type different from the semiconductor type of the photoelectric converter 20. The well region W may be separated into a plurality of active regions and a field region defining the active regions. A device isolation layer may be formed on the field region, and adjacent active regions may be electrically isolated from each other by the device isolation layer.

[0035] A plurality of transistors may be arranged on the active region of the first surface 11. For example, a transfer transistor 31, a floating diffusion node 32, and at least one signal transistor 33 may be arranged on the active region of the first surface 11. The transfer transistor 31 may transfer photoelectrons from the photoelectric converter 20 to the floating diffusion node 32, and thus, the photoelectrons may be accumulated in the floating diffusion node 32. The signal transistor 33 may be connected to the floating diffusion node 32, and may generate an electrical signal corresponding to a potential difference or voltage of the photoelectrons in the floating diffusion node 32.

[0036] The transfer transistor 31 may extend vertically from the first surface 11 toward the photoelectric converter 20 into the substrate 10 until the lower end of the transfer transistor 31 may be positioned near the photoelectric converter 20. For example, the transfer transistor 31 may include a conductive portion that may be arranged on the first surface 11 and a transfer gate extending from the conductive portion toward the photoelectric converter 20 into the substrate 10. A gate signal may be applied to the conductive portion of the transfer transistor 31, and the photoelectrons of the photoelectric converter 20 may be transferred to the floating diffusion node 32 in response to the gate signal. Since the transmission efficiency of the photoelectrons may be determined by the length of the effective channel of the transfer gate, various shapes and configurations may be permissible for the transfer gate as long as the length of the effective channel may be maximized. For example, the transfer gate may be shaped as a cup or a column.

[0037] The photoelectrons of the photoelectric converter 20 may be transferred to the floating diffusion node 32 and accumulated in the floating diffusion node 32, and thus the accumulated photoelectrons may be changed by the incident light that may be incident on the corresponding pixel region A. Therefore, the potential difference or voltage (hereinafter, referred to as the node voltage) of the photoelectrons of the floating diffusion node 32 may be changed by the pixel region A. The floating diffusion node 32 may be positioned on the first surface 11 between the transfer gate and the device isolation layer 39. The floating diffusion node 32 may be doped with an impurity whose semiconductor type may be different from that of the well region W.

[0038] The signal transistor 33 may generate an electric signal corresponding to the accumulated photoelectrons of the floating diffusion node 32. The electric signal may give image information of the object.

[0039] For example, the signal transistor 33 may include a reset transistor, a drive transistor (sometimes referred to as a source follower), and a select transistor. The reset transistor may remove photoelectrons from the floating diffusion node 32 and may reset the charge state of the floating diffusion node 32. The drive transistor or source follower may amplify the node voltage to facilitate detection of the node voltage. The select transistor may detect the amplified node voltage in response to a selection signal. The floating diffusion node 32 may be connected to the source electrode of the reset transistor and simultaneously connected to the gate electrode of the drive transistor. The drive transistor may be connected to the select transistor.

[0040] Although the present exemplary embodiment discloses that the signal transistor 33 is configured as a 3-transistor structure having three transistors, the signal transistor 33 may be configured as another transistor structure. For example, the signal transistor 33 may be configured as a 1-transistor structure, a 2-transistor structure, a 4-transistor structure, or a 5-transistor structure according to the characteristics and use of the image sensor 90. In addition, the reset transistor, the drive transistor, and the selection transistor may be arranged on the photoelectric converter 20 or may be separated from the photoelectric converter 20.

[0041] For example, the pixel separating pattern 40 may be configured as a penetration structure penetrating the substrate 10 between the first surface 11 and the second surface 12 , and may surround the pixel region A. Thus, a plurality of pixel regions A may be defined by the pixel separating pattern 40 and separated from one another.

[0042] The pixel separation pattern 40 may include an insulating pattern 41 and a conductive pattern 45. The insulating pattern 41 may penetrate the substrate 10 from the first surface 11 to the second surface 12, for example, along the z direction, and may include an insulating material having a refractive index smaller than that of the substrate 10. Figure 2 As shown in , the insulating pattern 41 may have a top surface and a bottom surface that are coplanar with the second surface 12 and the first surface 11 of the substrate 10, respectively. Figure 2 As shown in , the insulating pattern 41 may extend along the sidewall of the pixel region A (e.g., define the sidewall of the pixel region A). The conductive pattern 45 may be filled in the insulating pattern 41 and may be surrounded by the insulating pattern 41, for example, the conductive pattern 45 may be filled in the region between two facing insulating patterns 41 of two corresponding adjacent pixel regions A.

[0043] In detail, the insulating pattern 41 may be provided as a sidewall liner arranged on the inner surface or inner sidewall of the deep trench hole DTH, for example, the insulating pattern 41 may cover the entire inner sidewall of each deep trench hole DTH. The conductive pattern 45 may fill the remaining portion of the deep trench hole DTH between the facing portions of the insulating pattern 41, for example, the insulating pattern 41 may be between the conductive pattern 45 and the corresponding pixel region A.

[0044] For example, when the substrate 10 is a silicon wafer having a refractive index of about 3.5, the insulating pattern 41 may include silicon oxide (SiO 2 ). Therefore, even when the incident light R is incident on the pixel area A obliquely to the second surface 12 of the substrate 10, the oblique light can be reflected from the insulating pattern 41 into the pixel area A, thereby improving the efficiency of the photoelectric converter 20. In addition, since each unit pixel UP can be covered by its own color filter 71, the incident light R passing through the color filter 71 does not need to be fully separated from the adjacent incident light R passing through the adjacent color filter 71, because the incident light R passing through the color filter 71 is fully prevented from leaking into the adjacent unit pixel UP due to the separation pattern 40, thereby preventing optical interference between the unit pixels UP of the image sensor 90.

[0045] The conductive pattern 45 may include a low resistance metal and may be provided as a single conductive line that may be individually connected to each unit pixel UP. An external power source may be connected to the single conductive line.

[0046] When photoelectrons are generated in the photoelectric converter 20, some of the photoelectrons may be trapped on the boundary surface between the photoelectric converter 20 and the insulating pattern 41. Therefore, dark current is generated on the boundary surface of the insulating pattern 41. Although the floating diffusion node 32 is reset, the dark current does not disappear. That is, an electrical signal is detected from the floating diffusion node 32 after the charge of the floating diffusion node 32 is reset, which may cause a noise defect in the image sensor 90.

[0047] When a negative bias is applied to the conductive pattern 45, trapped charges can be sufficiently removed from the boundary surface between the insulating pattern 41 and the photoelectric converter 20, thereby removing dark current from the insulating pattern 41 and minimizing noise defects. Specifically, white spot defects of an image can be effectively prevented by removing dark current.

[0048] For example, the conductive pattern 45 may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and copper (Cu). Specifically, the conductive pattern 45 may be formed by a metal replacement process to be described in detail below, and the resistance of the conductive pattern 45 may be sufficiently reduced. Therefore, a negative bias may be applied to the conductive pattern 45 more effectively.

[0049] In a modified example embodiment, the conductive pattern 45 may include a transparent conductive oxide (TCO) having good total reflection characteristics. For example, the TCO may include indium tin oxide (ITO). The TCO may have a refractive index similar to that of silicon, so although the incident light R may be transmitted through the insulating pattern 41, the incident light R may be totally reflected from the TCO into the unit pixel UP, thereby improving the efficiency of the photoelectric converter 20 and minimizing optical interference between adjacent unit pixels UP.

[0050] According to the comparative image sensor, the deep trench may be filled with polysilicon, which serves as an electrode to which a negative bias is applied. However, as recent image sensors have been gradually reduced in size and the aspect ratio of the deep trench has increased, the resistance of polysilicon has increased. In contrast, according to example embodiments, the relatively high-resistance polysilicon may be replaced with a low-resistance metal conductive pattern 45, to which a negative bias may be easily and effectively applied, thereby substantially minimizing dark current in the image sensor 90.

[0051] In the present exemplary embodiment, the pixel separation pattern 40 may be shaped as a trapezoid, and the width of the trapezoid, for example, along the x direction, may decrease in a direction oriented from the first surface 11 to the second surface 12. The trapezoidal pixel separation pattern 40 may include a first width W1, for example, along the x direction, close to the first surface 11 and a second width W2, for example, along the x direction, close to the second surface 12. Therefore, the pixel separation pattern 40 may be narrowed from the signal generator 30 toward the microlens 73, that is, narrowed so that the first width W1 is greater than the second width W2. As a result, the pixel area A measured along the second surface 12, for example, the area of ​​the surface of the photodiode PD of the photoelectric converter 20 facing the microlens 73 ( Figure 1 and Figure 2 ), thereby maximizing the receiving area of ​​the incident light R on the second surface 12 of the substrate 10. In this way, the efficiency and photosensitivity of the photoelectric converter 20 can be improved.

[0052] Specifically, the second width W2 of the pixel separation pattern 40 may be about 60% to about 80% of the first width W1. When the second width W2 is greater than about 90% of the first width W1, the receiving area of ​​the second surface 12 to which the incident light R is irradiated may be substantially the same as the area of ​​the first surface 11 in the unit pixel UP, so that although the pixel separation pattern 40 is trapezoidal, the increase in the incident light R may be insignificant. In addition, when the second width W2 of the pixel separation pattern 40 is less than about 60% of the first width W1, adjacent unit pixels UP adjacent to each other may be difficult to be separated from each other by the pixel separation pattern 40, thereby generating light interference between adjacent unit pixels UP. For these reasons, the second width W2 of the pixel separation pattern 40 may be about 60% to about 80% of the first width W1. For example, the first width W1 may be in the range of about 80nm to about 100nm, and the second width W2 may be in the range of about 50nm to about 90nm.

[0053] In the present example embodiment, the thickness of the insulating pattern 41, for example, along the x-direction may be uniform between the first surface 11 and the second surface 12, while the thickness of the conductive pattern 45, for example, along the x-direction may decrease from the first surface 11 to the second surface 12. The insulating pattern 41 may be provided as a sidewall liner covering the inner surface or sidewall of the deep trench hole DTH, and the conductive pattern 45 may fill up the inside of the deep trench hole DTH that may be defined by the insulating pattern 41. Therefore, the insulating pattern 41 may have a uniform thickness, while the conductive pattern 45 may have a non-uniform thickness.

[0054] If you will refer to Figures 3 to 6B As described, the pixel separation pattern 40 may be variously modified according to the characteristics and requirements of the image sensor 90 .

[0055] Figure 3 It is shown Figure 2 A cross-sectional view of a first modified example of an image sensor in FIG. Figure 3 In addition to the pixel separation pattern, the image sensor may have Figure 2 The image sensor in the Figure 3 In the drawings, the same reference numerals denote Figure 2 The same elements are described herein and any further detailed description of the same elements will be omitted hereinafter.

[0056] Reference Figure 3, the additional separation pattern 39a may also be disposed at a first end portion of the deep trench hole DTH near the first surface 11, for example, the additional separation pattern 39a may be located in the widest portion of the deep trench hole DTH between the first surface 11 and the conductive pattern of the separation pattern. The device isolation layer 39 may be surrounded by the additional separation pattern 39a (for example, along its periphery), and the first modified pixel separation pattern 40a may include an insulating pattern 41 and a first modified conductive pattern 45a filling the deep trench hole DTH above the additional separation pattern 39a.

[0057] The additional separation pattern 39a may include an insulating material for sufficiently isolating a unit pixel from its surroundings. Therefore, the additional separation pattern may separate adjacent unit pixels UP from each other together with the device isolation layer 39 and the insulating pattern 41.

[0058] For example, the additional separation pattern 39a may include a boundary surface BS that may be coplanar with the first surface 11 and may be positioned at a boundary region of the substrate 10, and an inner surface IS that may be positioned in the deep trench hole DTH opposite to the boundary surface BS, for example, the inner surface IS may contact the first modified conductive pattern 45a. Therefore, the additional separation pattern 39a may have a thickness (or height) corresponding to a gap distance between the boundary surface BS and the inner surface IS in the deep trench hole DTH.

[0059] Specifically, the additional separation pattern 39a may be surrounded by the insulating pattern 41 in the deep trench hole DTH in such a configuration that the unit pixel UP may be surrounded by the additional separation pattern 39a. Therefore, the signal generator 30 may be surrounded by the insulating pattern 41 and the additional separation pattern 39a as well as the device isolation layer 39, and thus adjacent signal generators 30 adjacent to each other may be sufficiently insulated from each other.

[0060] The height of the first modified conductive pattern 45a may be controlled by simply changing the thickness of the additional separation pattern 39a with reference to the device isolation layer 39. In the present exemplary embodiment, the additional separation pattern 39a may have a thickness (or height) greater than that of the device isolation layer 39. In this case, the first modified conductive pattern 45a may fill up the hole space defined by the additional separation pattern 39a and the insulating pattern 41, and may extend from the inner surface IS to the second end of the deep trench hole near the second surface 12. Therefore, the thickness (or height) of the first modified conductive pattern 45a may be less than Figure 2 The thickness (or height) of the conductive pattern 45 in .

[0061] Although the present example embodiment discloses that the thickness of the additional separation pattern 39a may be greater than the thickness of the device isolation layer 39, the thickness of the additional separation pattern 39a may be less than or equal to the thickness of the device isolation layer 39. That is, the thickness (or height) of the first modified conductive pattern 45a may be controlled according to the characteristics and requirements of the image sensor 90.

[0062] In the present example embodiment, the additional separation pattern 39a may include an oxide having good insulation and gap-filling properties. However, the additional separation pattern 39a may include any other materials as well as the oxide as long as the materials have sufficient insulation and gap-filling properties.

[0063] Signal interference between adjacent signal generators 30 can be substantially minimized by the additional separation pattern 39a. In addition, since the height of the first modified conductive pattern 45a can be reduced, the layer uniformity of the first modified conductive pattern 45a can be substantially improved, thereby reducing the aspect ratio of the first modified conductive pattern 45a within the deep trench hole DTH, for example, the height of the first modified conductive pattern 45a in the z direction can be reduced within the same deep trench hole DTH due to the additional separation pattern 39a within the deep trench hole DTH relative to the same width in the x direction.

[0064] Figure 4 It is shown Figure 2 A cross-sectional view of a second modified example of the image sensor in FIG. Figure 4 In addition to the pixel separation pattern, the image sensor may have Figure 2 The image sensor in the Figure 4 In the drawings, the same reference numerals denote Figure 2 The same elements are described herein and any further detailed description of the same elements will be omitted hereinafter.

[0065] Reference Figure 4 , the second modified pixel separation pattern 40b may include an insulating pattern 41, a protection pattern 43, and a second modified conductive pattern 45b. The protection pattern 43 may be arranged on the insulating pattern 41 and may have a bottom surface coplanar with the first surface 11 of the substrate 10. Therefore, the protection pattern 43 may be shaped into an inner surface profile of the deep trench hole DTH and may have a uniform thickness between the first surface 11 and the second surface. Specifically, when the insulating pattern 41 may have a uniform thickness between the first surface 11 and the second surface 12, the thicknesses of the insulating pattern 41 and the protection pattern 43 may also be uniform in the deep trench hole DTH. The second modified conductive pattern 45b may be filled in the space of the deep trench hole DTH that may be defined by the protection pattern 43, and thus the size of the second conductive pattern 45b may be smaller than Figure 2As a result, the protection pattern 43 may be interposed between the second modified conductive pattern 45 b and the insulating pattern 41 .

[0066] The protection pattern 43 can protect the second surface 12 of the substrate 10 in the metal replacement process for forming the second modified conductive pattern 45b. Therefore, the protection pattern 43 can include any material that can protect the substrate in the metal replacement process. For example, the protection pattern 43 can include any one of silicon oxide, silicon nitride, and silicon oxynitride.

[0067] Specifically, when the refractive index of the protective pattern 43 can be smaller than the refractive index of the substrate 10, although the incident light R inclined relative to the second surface 12 (hereinafter, referred to as inclined light) can pass through the insulating pattern 41 and the refractive index of the second modified conductive pattern 45b can be greater than the substrate 10, the inclined light can also be reflected into the corresponding photoelectric converter 20.

[0068] Figure 5 It is shown Figure 2 A cross-sectional view of a third modified example of the image sensor in FIG. Figure 5 In addition to the pixel separation pattern, the image sensor may have Figure 2 The image sensor in the Figure 5 In the drawings, the same reference numerals denote Figure 2 The same elements are described herein and any further detailed description of the same elements will be omitted hereinafter.

[0069] Reference Figure 5 , the third modified pixel separating pattern 40c may include the first modified protection pattern 43a contacting the additional separating pattern 39a, the insulating pattern 41, and the third modified conductive pattern 45c.

[0070] For example, the first modified protection pattern 43a may contact the insulating pattern 41 in the vertical direction, and contact the additional separation pattern 39a in the horizontal direction along the surface profile of the hole space defined by the additional separation pattern 39a and the insulating pattern 41. That is, the hole space may be further reduced by the first modified protection pattern 43a and the additional separation pattern 39a, and the insulating pattern 41 may be covered by the first modified protection pattern 43a. The third modified conductive pattern 45c may be filled in the hole space defined by the first modified protection pattern 43a. Therefore, the deep trench hole DTH may be filled with the insulating pattern 41, the additional separation pattern 39a, the first modified protection pattern 43a, and the third modified conductive pattern 45c.

[0071] Apart from Figure 5 The additional separation pattern 39a may have an inner surface IS that contacts the first modified protection pattern 43a. Figure 3 The additional separation pattern 39a shown in FIG. 3 may be surrounded by the insulating pattern 41 in the deep trench hole DTH in such a configuration that the unit pixel UP may be surrounded by the additional separation pattern 39a. The first modified protection pattern 43a may be interposed between the third modified conductive pattern 45c and the insulating pattern 41 and between the third modified conductive pattern 45c and the additional separation pattern 39a.

[0072] Therefore, the signal generator 30 may be surrounded by the device isolation layer 39 , the insulation pattern 41 , the first modified protection pattern 43 a , and the additional separation pattern 39 a , so that neighboring signal generators 30 adjacent to each other may be more adequately insulated from each other.

[0073] The first modified protection pattern 43a may have substantially the same structure as the protection pattern 43, except that the height of the first modified protection pattern 43a may be less than the height of the first protection pattern 43 according to the height of the additional separation pattern 39a, that is, the height difference between the first modified protection pattern 43a and the protection pattern 43 may be equal to the height of the additional separation pattern 39a. In the same manner, the third modified conductive pattern 45c may have substantially the same structure as the protection pattern 43, except that the height of the first modified protection pattern 43a may be less than the height of the first protection pattern 43 according to the height of the additional separation pattern 39a. Figure 4 The second modified conductive pattern 45b in FIG. 4 may have substantially the same structure as the third modified conductive pattern 45c, that is, a height difference between the third modified conductive pattern 45c and the second modified conductive pattern 45b may be equal to a height of the additional separation pattern 39a.

[0074] The substrate 10 may be protected by the first modified protection pattern 43a from the metal replacement process for forming the third modified conductive pattern 45c. In addition, the signal generator 30 may be surrounded by the insulating pattern 41 and the additional separation pattern 39a and the device isolation layer 39. Therefore, adjacent signal generators 30 adjacent to each other may be sufficiently insulated from each other, thereby sufficiently minimizing signal interference between adjacent unit pixels UP.

[0075] In addition, since the aspect ratio of the hole space can be reduced by the additional separation pattern 39a and the insulation pattern 41, the first modified protection pattern 43a and the third modified conductive pattern 45c can have a reduced aspect ratio, for example, the height of the first modified protection pattern 43a and the third modified conductive pattern 45c can be reduced within the deep trench hole DTH. As a result, the uniformity of the layer characteristics of the third modified conductive pattern 45c and the first modified protection pattern 43a can be greatly improved.

[0076] In other modified example embodiments, air holes may also be provided in the deep trench hole DTH to more improve the insulation characteristics of the unit pixel UP.

[0077] Fig. 6A It is shown Figure 2 A cross-sectional view of a fourth modified example of the image sensor in FIG. Fig. 6A In addition to the pixel separation pattern, the image sensor may have Figure 2 The image sensor in the Fig. 6A In the drawings, the same reference numerals denote Figure 2 The same elements are described herein and any further detailed description of the same elements will be omitted hereinafter.

[0078] Reference Fig. 6A , the fourth modified pixel separation pattern 40d may include an insulating pattern 41 and a conductive pattern 45 in which an air gap AG may be disposed. In addition to the air gap AG being disposed in the conductive pattern 45, the insulating pattern 41 and the conductive pattern 45 may have the same Figure 2 The air gap may include at least one hole in the conductive pattern 45 that may be filled with air. Therefore, any detailed description of the insulating pattern 41 and the conductive pattern 45 will be omitted hereinafter.

[0079] Due to the high aspect ratio of the deep trench hole DTH, at least one hole may be generated during the formation of the conductive pattern 45, and air may be filled in the hole, thereby forming an air gap AG in the conductive pattern 45. Therefore, the insulation property of the fourth modified pixel separation pattern 40d may be improved by, for example, the insulation degree of the air, and the unit pixels UP may be more fully separated from each other in the image sensor 90. That is, the crosstalk defect between adjacent unit pixels UP may be minimized due to the air gap AG in the conductive pattern 45.

[0080] For example, for forming the conductive pattern 45 (or Fig.11I The process conditions of the conductive layer 450a in the deep trench hole DTH may be controlled in such a manner that at least one void may be generated in the conductive pattern 45 in the deep trench hole DTH. The size of the void may be determined by the process conditions and the aspect ratio of the deep trench hole DTH and may be formed as a bubble.

[0081] Figure 6B It is shown Fig. 6A A cross-sectional view of a fifth modified example of the image sensor in FIG. Figure 6B In addition to the pixel separation pattern, the image sensor may have Fig. 6A The image sensor in the Figure 6B In the drawings, the same reference numerals denote Fig. 6A The same elements are described herein and any further detailed description of the same elements will be omitted hereinafter.

[0082] Reference Figure 6B , the fifth modified pixel separation pattern 40e may include an insulating pattern 41 and a conductive pad 45d covering the insulating pattern 41, so the remaining portion of the hole space defined by the conductive pad 45d (i.e., the remaining portion of the deep trench hole DTH) may be set as the trench gap TG. That is, the hole may extend in a linear shape along the deep trench hole DTH, and the linear hole may be filled with air. That is, the linear hole filled with air may be set as the trench gap TG in the deep trench hole DTH.

[0083] For example, the conductive material may be deposited (e.g., conformally deposited) on the insulating pattern 41 to a predetermined thickness by a precise thickness controllable deposition process (e.g., an atomic layer deposition (ALP) process). Therefore, a thin conductive layer may be formed on the insulating pattern 41 along the surface profile of the deep trench hole DTH, just like a liner covering the insulating pattern 41, thereby forming a conductive liner 45d. Therefore, the hole space of the deep trench hole DTH defined by the conductive liner 45d may be set as a trench gap TG. In the present example embodiment, the insulating pattern 41 and the conductive liner 45d may have substantially the same thickness.

[0084] In the present example embodiment, the conductive pad 45d may be formed in the deep trench hole DTH in such a configuration that a first end near the first surface 11 may be closed by the conductive pad 45d and a second end near the second surface 12 may be open. Figure 11K The process conditions of the buffer layer 600 shown in FIG. 1 are used to close the open second end of the deep trench hole DTH. Therefore, the trench gap TG can be formed as a closed space filled with air. The unit pixel UP can be formed by the trench gap TG having a ratio of Fig. 6A The air gap AG in the fifth modified pixel separation pattern 40e is surrounded by air of a much larger size, and adjacent unit pixels UP can be sufficiently insulated from each other by the air in the trench gap TG. Therefore, due to the improved insulation characteristics of the fifth modified pixel separation pattern 40e, various noises caused by dark current and crosstalk defects can be sufficiently prevented.

[0085] Refer again Figure 2 , the wiring structure 50 may be arranged on the first surface 11 of the substrate 10. The wiring structure 50 may include a plug structure 53 and a metal wiring 51 that may be connected to the signal generator 30, and at least one insulating interlayer 52. A plurality of insulating interlayers 52 may be stacked on the first surface 11 of the substrate 10, and a plurality of metal wirings 51 may be arranged on each insulating interlayer 52.

[0086] The metal wiring 51 may include a low-resistance conductive metal. Examples of low-resistance conductive metals may include copper (Cu), tungsten (W), titanium (Ti), aluminum (Al), etc. These may be used alone or in combination. For example, the wiring structure 50 may be formed by a wiring process (e.g., a back-end of line (BEOL) process) for a semiconductor device.

[0087] The buffer layer 60 may be disposed on the second surface 12 of the substrate 10. The buffer layer 60 may include a single layer or a multi-layer structure. In the present example embodiment, the buffer layer 60 may include a metal oxide layer 61, an anti-reflection layer 62, and a passivation layer 63.

[0088] The metal oxide layer 61 can eliminate surface defects of the second surface 12 that may be generated in a substrate process for forming the second surface 12, thereby minimizing noise caused by the surface defects of the second surface 12. The anti-reflection layer 62 can prevent the incident light R transmitted through the light-transmitting unit 70 from being reflected outward from the unit pixel UP, thereby improving the efficiency of the photoelectric converter 20. The passivation layer 63 may include, for example, silicon oxide.

[0089] Since the pixel separation pattern 40 may penetrate the substrate 10, the pixel separation pattern 40 may contact the buffer layer 60. Although the present example embodiment discloses that the pixel separation pattern 40 may contact (e.g., directly contact) the metal oxide layer 61, when the buffer layer 60 does not include the metal oxide layer 61, the pixel separation pattern 40 may also contact the anti-reflection layer 62.

[0090] The light transmitting unit 70 may be disposed on the buffer layer 60, and the incident light R may reach the photoelectric converter 20 through the light transmitting unit 70. For example, the light transmitting unit 70 may include a color filter 71 and a micro lens 73.

[0091] The color filter 71 may be arranged on the buffer layer 60 according to the unit pixel UP, and may filter the incident light according to the wavelength so that only the specific wavelength of the light corresponding to the color filter can be transmitted through the color filter 71 and reach the photoelectric converter 20. That is, the light of a specific color can be transmitted through the corresponding color filter 71, and the color information of the object can be realized in each corresponding unit pixel UP. The incident light R can be focused to the unit pixel UP through the microlens 73.

[0092] The color filter 71 may be arranged on the buffer layer 60 according to the unit pixel UP, and therefore, the color filter 71 and the unit pixel UP may correspond one to one. Therefore, a plurality of color filters 71 may be arranged as a color filter array in a matrix shape corresponding to the pixel matrix. For example, the color filter array may include a Bayer pattern having a red filter, a green filter, and a blue filter.

[0093] The microlenses 73 may be arranged on the color filter 71 per unit pixel UP. The microlenses 73 may change the path of the incident light R in such a manner that the incident light R may be focused on the photoelectric converter 20 in each unit pixel UP. A plurality of microlenses 73 may be provided as a microlens array in a matrix shape corresponding to a pixel matrix.

[0094] According to the above-described exemplary embodiment of the image sensor 90, a conductive pattern 45 including a low-resistance metal may be provided in the pixel separation pattern 40, and a negative bias may be applied to the conductive pattern 45. Therefore, a dark current on a boundary surface between the photoelectric converter 20 and the pixel separation pattern 40 may be effectively removed in the unit pixel UP. In a conventional image sensor, since the conductive pattern may include polysilicon having a relatively high resistance, a negative bias may not be stably applied to the conductive pattern of the pixel separation pattern, which generally results in a noise defect caused by a dark current in the image sensor. In contrast, in an exemplary embodiment, by replacing the polysilicon of a conventional conductive pattern with the low-resistance metal of the present conductive pattern 45 in the image sensor 90, a noise defect caused by a dark current may be substantially reduced or prevented.

[0095] Specifically, the conductive pattern 45 may include a material having a refractive index less than that of the substrate, and thus oblique light (i.e., oblique light incident at an oblique angle) may be reflected into the corresponding photoelectric converter 20. In addition, the conductive pattern 45 may include a transparent conductive oxide (TCO) having good total reflection characteristics, and thus although some incident light R may be transmitted through the insulating pattern 41, the incident light R may be totally reflected from the TCO into the unit pixel UP, thereby improving the efficiency of the photoelectric converter 20 and minimizing optical interference between adjacent unit pixels UP.

[0096] In addition, the pixel separation pattern 40 may be shaped as a trapezoid in which the width may decrease from the first surface 11 on which the wiring structure 50 is disposed toward the second surface 12 on which the buffer layer 60 is disposed. Since the second surface 12 may correspond to the back side or rear surface of the substrate 10 and the incident light R may be incident on the second surface 12, the image sensor 90 may be configured as a backside illumination (BSI) structure, and the trapezoidal pixel separation pattern 40 may expand the receiving area of ​​the incident light R, thereby improving the efficiency of the image sensor 90.

[0097] In the following, reference will be made to Figures 7 to 10 The image sensor module having the image sensor 90 is described in detail.

[0098] Figure 7 is a block diagram of an image sensor module 1000 according to an example embodiment, Figure 8 is a plan view showing the image sensor 910 of the image sensor module 1000 . Fig. 9 is along Figure 8 A cross-sectional view along line II-II' in FIG. Fig.10 is a circuit diagram of a unit pixel of the image sensor 910 .

[0099] Reference Figures 7 to 9 According to an example embodiment, the image sensor module 1000 may include an image sensor 910 that generates image information of an object in response to incident light, and an image signal processor (ISP) 950 that generates image data of the object from the image information generated from the image sensor 910.

[0100] For example, the image sensor 910 may include a pixel unit Px, a reference pixel unit RPx, and a connector unit P, and the pixel unit Px, the reference pixel unit RPx, and the connector unit P may be arranged on the illumination area IA, the black area BA, and the contact area CA of the substrate 100, respectively. The pixel unit Px may include a reference pixel unit RPx. Figures 1 to 6B The image sensor 90 described in detail with such a configuration that a plurality of unit pixels UP may be arranged on the illumination area 1A of the substrate 100. The pixel unit Px may be arranged at the central portion of the substrate 100 and may generate a plurality of photoelectrons in response to incident light. The reference pixel unit RPx may be arranged on the black area BA at the peripheral area of ​​the substrate 100, and the connector unit P may be arranged on the contact area CA at the pad area of ​​the substrate 100.

[0101] The substrate 100 may include a semiconductor substrate having at least one layer. The front surface of the substrate 100 may be provided as a first surface 101 of the substrate 100 , and the rear surface or rear side surface of the substrate 100 may be provided as a second surface 102 of the substrate 100 .

[0102] The substrate 100 may be divided into a plurality of uniform unit areas UA by the deep trench hole DTH. The unit area UA in the illumination area IA may be set as a pixel area A for generating photoelectrons in response to incident light, and the unit area UA of the black area BA may be set as a reference unit area B for generating reference charges for comparison with the photoelectrons in the illumination area IA. The unit area UA of the contact area CA may be set as a contact margin area C in which the connector unit P may be sufficiently positioned. The deep trench hole DTH may be filled with a pixel separation pattern 400 described in detail below, and thus, each unit area UA may be surrounded by the pixel separation pattern 400 and may be insulated from adjacent unit areas UA by the pixel separation pattern 400. Each unit area UA of the pixel area A and the reference unit area B may include a photoelectric converter 200 and a signal generator 300, the photoelectric converter 200 being used to generate photoelectrons in response to incident light, and the signal generator 300 being used to generate an electrical signal according to the photoelectrons. Therefore, each unit area UA of the pixel area A and the reference unit area B may be set as a unit pixel UP of the image sensor 910. A plurality of unit pixels UP may be arranged in a matrix shape on a central region and a peripheral region of the substrate.

[0103] At least one photoelectric converter 200 may be arranged in the unit pixel UP and may generate photoelectrons in response to incident light. For example, the photoelectric converter 200 may include a photodiode, a phototransistor and a photogate, a pinned photodiode (PPD), etc. For example, the photoelectric converter 200 may be deeply positioned in the unit pixel UP in such a configuration that the photoelectric converter 200 may be positioned near the second surface 102 on which light may be incident. In addition, since the pixel separation pattern 400 may be shaped as a trapezoid, the unit pixel UP may be shaped as an inverted trapezoid, so that the light receiving area of ​​the photoelectric converter 200 may be enlarged in the image sensor 910.

[0104] The signal generator 300 may be arranged at a surface portion of the first surface 101 of the substrate 100 at each unit pixel UP, and may generate an electrical signal based on photoelectrons in the photoelectric converter 200. The electrical signal may include image information about the object. The well region W may be placed between the photoelectric converter 200 and the first surface 101 of the substrate 100, and impurities having a semiconductor type different from that of the photoelectric converter 200 may be implanted into the surface portion of the well region W, thereby forming an active region on the first surface 101 of the substrate 100. The active region on the well region W may be defined by a device isolation layer, and the signal generator 300 may be arranged on the active region in the well region W.

[0105] The signal generator 300 may include a transfer transistor 310, a floating diffusion node 320, and at least one signal transistor 330. The transfer transistor 310 may transfer photoelectrons from the photoelectric converter 200 to the floating diffusion node 320, and may accumulate a plurality of photoelectrons at the floating diffusion node 320. The signal transistor 330 may be connected to the floating diffusion node 320, and may generate an electrical signal corresponding to a potential difference or voltage of the photoelectrons accumulated in the floating diffusion node 320.

[0106] Reference Fig.10 In the present example embodiment, the signal transistor 330 may include a reset transistor Rx for discharging photoelectrons from the floating diffusion node 320, a source follower transistor SF for amplifying the voltage of the floating diffusion node 320, and a selection transistor Sx for detecting the amplified voltage of the floating diffusion node 320 in response to a selection signal. The floating diffusion node 320 (i.e., Fig.10 The floating diffusion node FD in the reset transistor Rx can be connected to the source of the reset transistor Rx and simultaneously connected to the gate electrode of the source follower transistor SF. The source follower transistor SF can be connected to the selection transistor Sx.

[0107] The photoelectric converter 200 and the signal generator 300 may have Figure 1 and Figure 2 The photoelectric converter 20 and the signal generator 30 of the image sensor 90 in FIG. 1 have substantially the same structure. Therefore, any detailed description of the photoelectric converter 200 and the signal generator 300 is omitted.

[0108] The contact margin region C may be provided as a process margin region for a process of forming the connector unit P. Therefore, the photoelectric converter 200 and the signal generator 300 may not be arranged in the contact margin region C.

[0109] The pixel separation pattern 400 defining the unit area UA may penetrate the substrate 100 and may be provided as a penetration structure in contact with both the first surface 101 and the second surface 102. In the present example embodiment, the pixel separation pattern 400 may include an insulating pattern 410 having a refractive index less than that of the substrate 100 and a metal conductive pattern 450 filled in the insulating pattern 410.

[0110] The pixel separation pattern 400 may be used as a pixel separation pattern for individually separating the unit pixels UP in the illumination area IA and the black area BA of the substrate 100, and may be used as a size factor for determining the size of the contact margin area C in the contact area CA of the substrate 100. That is, each unit area UA of the substrate 100 may be separated and isolated from each other by the pixel separation pattern 400.

[0111] In the present example embodiment, the insulating pattern 410 may be provided as a sidewall liner covering the sidewall or inner side surface of the deep trench hole DTH, and the conductive pattern 450 may fill up the deep trench hole DTH together with the insulating pattern 410. Therefore, the conductive pattern 450 may be surrounded by the insulating pattern 410 in the deep trench hole DTH.

[0112] The insulating pattern 410 may include an oxide having a refractive index lower than that of the substrate 100, for example, silicon oxide (SiO 2 ), and the conductive pattern 450 may include a low resistance metal, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu), etc. These may be used alone or in combination. Therefore, the conductive pattern 450 may be used as an effective electrode for a negative bias.

[0113] Specifically, the conductive pattern 450 may be formed on the second surface 102 by a metal replacement process as will be described in detail below. Therefore, the signal generator 300 that may be disposed on a surface portion of the first surface 101 may be sufficiently protected from the metal replacement process, and damage to the signal generator 300 may be sufficiently prevented or minimized in a process for forming the conductive pattern 450. In addition, since a negative bias voltage may be stably applied to the conductive pattern 450, dark current may be sufficiently reduced or removed from a boundary surface between the insulating pattern 410 and the photoelectric converter 200.

[0114] In a modified example embodiment, the conductive pattern 450 may include a transparent conductive oxide (TCO) having good total reflection characteristics. Therefore, although the incident light R may be transmitted through the insulating pattern 410, the incident light R may be totally reflected from the TCO into the unit pixel UP, thereby improving the efficiency of the photoelectric converter 200 and minimizing optical interference between adjacent unit pixels UP.

[0115] In the present exemplary embodiment, the pixel separation pattern 400 may be shaped as a trapezoid whose width may decrease from the first surface 101 to the second surface 102. Therefore, the surface area of ​​the unit area UA may increase from the first surface 101 to the second surface 102, and the pixel separation pattern 400 may be shaped as a hollow truncated pyramid surrounding the unit area UA of the substrate 100. Specifically, the increase in the surface area of ​​the unit pixel UP at the illumination area IA and the black area BA may result in an increase in the light receiving area. Therefore, the photosensitivity and efficiency of the photoelectric converter 200 may be substantially improved by the inverted trapezoidal shape of the unit pixel UP.

[0116] The pixel separating pattern 400 may further include a protection pattern for covering the insulating pattern 410. In this case, the insulating pattern 410, the protection pattern, and the conductive pattern 450 may have uniform or non-uniform thicknesses.

[0117] The pixel separation pattern 400 may have substantially the same structure as the pixel separation pattern 40, and refer to Figures 1 to 5 The first, second and third modified pixel separating patterns 40a to 40c are described in detail. Therefore, further detailed description of the pixel separating pattern 400 is omitted.

[0118] The wiring structure 500 may be disposed on the first surface 101 of the substrate 100 , and the buffer layer 600 may be disposed on the second surface of the substrate 100 .

[0119] The wiring structure 500 may include a conductive line connected to the signal generator 300, at least one plug, at least one metal wiring, and an interlayer insulating layer covering and insulating the conductive line. The buffer layer 600 may include a metal oxide layer, an anti-reflection layer, and a passivation layer. Since the pixel separation pattern 400 may penetrate the substrate 100, the pixel separation pattern 400 may contact the buffer layer 600. The wiring structure 500 and the buffer layer 600 may have the same structure as described in reference. Figure 1 and Figure 2 The wiring structure 500 and the buffer layer 60 described in detail have substantially the same structure, and thus any further detailed description of the wiring structure 500 and the buffer layer 600 is omitted.

[0120] The low resistance capping layer 650 may be disposed on the buffer layer 600. The capping layer 650 may include a conductive material having low resistance.

[0121] The cover layer 650 in the illumination area IA may be disposed on the buffer layer 600 corresponding to the pixel separation pattern 400, and the pixel area A may be surrounded by the cover layer 650. That is, the cover layer 650 in the illumination area IA may serve as a grid pattern 651 for reflecting oblique light that may be obliquely irradiated to the peripheral portion of the unit pixel UP to the photoelectric converter 200 in the unit pixel UP. Fig. 9 As shown in FIG. 1 , the grid pattern 651 in the illumination area IA may have a grid shape in a top view, which is positioned on the pixel separation pattern 400 to overlap the top surface of the conductive pattern 450 , for example, and exposes the photoelectric converter 200 and the insulating pattern 410 .

[0122] The covering layer 650 in the black area BA can be arranged on the buffer layer 600 across the entire black area BA, for example, continuously covering the entire buffer layer 600 in the black area BA, so that the light that can be irradiated onto the reference pixel cell RPx can be fully blocked in such a way that the minimum light can reach the reference pixel cell RPx. Therefore, the covering layer 650 in the black area BA can be used as an optical blocking pattern 653. The photoelectrons generated from the reference pixel cell RPx in response to the minimum light can be set as a reference charge or reference voltage of the photoelectrons generated from the pixel cell Px. When the pixel cell Px generates photoelectrons greater than the reference charge, the pixel cell Px can be classified as a valid pixel, and when the pixel cell Px generates photoelectrons less than the reference charge, the pixel cell Px can be classified as an invalid pixel in the illumination area IA of the substrate 100.

[0123] The capping layer 650 in the contact area CA may function as a contact pad 655 of the contact structure 800. The contact hole CH may penetrate the contact pad 655, the buffer layer 600, the substrate 100, and the wiring structure 500, and the contact structure 800 may fill the contact hole CH.

[0124] The contact structure 800 may include a contact extension 810 that is arranged on the inner surface and the bottom of the contact hole CH and may be connected to the contact pad 655 on the buffer layer 600. The contact structure 800 may also include an insulating column 890 that fills up the contact hole CH on the contact extension 810, for example, the insulating column 890 may be surrounded by the contact extension 810. Therefore, a first end portion of the contact extension 810 located near the first surface 101 may contact the wiring structure 500 and the ISP 950, and a second end portion of the contact extension 810 located near the second surface 102 may contact the contact pad 655. In the present example embodiment, the contact extension 810 may be formed simultaneously with the cover layer 650, so that the contact extension 810 and the contact pad 655 may be formed integrally with each other in one body (for example, continuously formed as a single layer).

[0125] Specifically, the contact structure 800 may be positioned at the contact margin region C defined by the pixel separation pattern 400 in the contact region CA of the substrate 100. Therefore, the formation process for forming the contact structure 800 may be performed with a sufficient process margin, thereby improving the reliability of the contact structure 800. In addition, the contact structure 800 may be separated from another contact structure by the pixel separation pattern 400, thereby preventing electrical interference between the contact structure 800 and an adjacent contact structure.

[0126] Although the present example embodiment discloses that the contact hole CH may be filled with the insulating pillar 890 and the contact extension 810, the insulating pillar may not be provided to the contact hole CH, and a hole surrounded by the contact extension 810 may be provided in the central portion of the contact hole CH. In this case, the contact extensions 810 facing each other in the contact hole CH may be insulated from each other by the air filling the hole.

[0127] The light-transmitting unit 700 may be disposed on the buffer layer 600 in the pixel region A. The light-transmitting unit 700 may include a color filter 710 that covers the buffer layer 600 defined by the grid pattern 651 at each unit pixel UP, and a microlens 730 that is disposed on the color filter 710 and focuses incident light onto the unit pixel UP. The color filter 710 may filter incident light by wavelength, and the microlens 730 may change the path of the incident light toward the photoelectric converter 200.

[0128] The light-transmitting unit 700 may have the same Figure 1 and Figure 2 The light transmission unit 70 of the image sensor 90 described in detail has substantially the same structure. Therefore, any detailed description of the light transmission unit 700 is omitted.

[0129] An electric signal corresponding to an image of a subject (sometimes referred to as an image signal) may be generated from the unit pixel UP through the following mechanism.

[0130] Reference Figure 7 and Fig.10 , first, the image sensor 910 may be set to a black state in which light may be blocked from reaching the unit pixel UP and each unit pixel UP may not be exposed to light. Then, when the reset transistor Rx ( Figure 8 The drain electrode of the element 330 in the embodiment of the present invention and the source follower transistor SF ( Figure 8 When the power supply voltage Vdd is applied to the drain electrode of the element 330 in the embodiment, the reset transistor Rx can be turned on in the standby state. Figure 8 Most of the charges in the element 320 in the floating diffusion node FD can be removed, and the floating diffusion node FD can be completely discharged in each unit pixel UP.

[0131] When the floating diffusion node FD is fully discharged, the reset transistor Rx may be turned off. In this case, photoelectrons may be generated in the photoelectric converter 200 in response to incident light, and the photoelectrons may be transmitted to the floating diffusion node FD. When incident light reflected from an object may be incident on the photoelectric converter 200 having a PN junction photodiode, electron-hole pairs may be generated in the photoelectric converter 200. That is, photoelectrons as holes and electrons may be generated in the photoelectric converter 200. Holes may accumulate in the P-type region of the photodiode, and electrons may accumulate in the N-type region of the photodiode. The electrons in the N-type region of the photodiode may be transferred to the photoelectric converter 200 by the transfer transistor Tx ( Figure 8 The element 310 in FIG. 1 is transmitted to the floating diffusion node FD, so the electrons or photoelectrons can be accumulated in the floating diffusion node FD.

[0132] The gate bias of the source follower transistor SF can be changed according to the amount of photoelectrons in the floating diffusion node FD, and the potential of the source electrode of the source follower transistor SF can be changed. In this case, the selection transistor Sx ( Figure 8 A portion of the element 330 in FIG. 1 may be turned on, and the potential or voltage of the floating diffusion node FD may be detected as an electrical signal Vout via a column line.

[0133] Specifically, since the pixel region A in which the photodiode may be arranged may be surrounded by the pixel separation pattern 400, electrons may be trapped on the boundary surface between the pixel separation pattern 400 and the photodiode. However, since the conductive pattern 450 of the pixel separation pattern 400 may include a low-resistance metal, a negative bias may be well stably applied to the conductive pattern 450, and as a result, charge capture at the boundary surface of the separation pattern may be sufficiently prevented in each unit pixel UP. Therefore, dark current may be sufficiently minimized in each unit pixel UP.

[0134] The electrical signal generated from the image sensor 910 may be transmitted to the ISP 950 to generate image data of the object. The ISP 950 may include an operation driver 951 for applying an operation signal to the image sensor 910, a signal detector 953 for detecting an electrical signal (image signal) from the image sensor 910 as a detection signal, and a timing generator 955 for selectively controlling the operation signal and the detection signal. A signal buffer 957 for temporarily storing the detection signal may also be provided with the image sensor module 1000.

[0135] Each unit pixel UP of the image sensor 910 can be activated by an operation signal such as a pixel selection signal, a reset signal, and a charge transfer signal. The image signal of each unit pixel UP can be detected as an analog signal by a column decoder 953a and a correlated double sampler (CDS) 953b of the signal detector 953.

[0136] The operation driver 951 may include a row decoder 951a for selecting a driving row of unit pixels UP that may be arranged in a matrix shape (pixel matrix) and a row driver 951b for transmitting an operation signal to the driving row. Therefore, the operation signal may be transmitted simultaneously to a plurality of unit pixels UP on the same row of the pixel matrix.

[0137] The signal detector 953 may detect an electrical signal from each unit pixel UP of the image sensor 910. For example, the signal detector 953 may include a column decoder 953a for selecting a read column of a pixel matrix, a CDS 953b, and an analog-to-digital converter 953c for converting an analog signal into a digital signal.

[0138] The CDS 953b can detect a cell voltage indicating the potential of the photoelectrons in the pixel cell Px and a reference voltage indicating the power part of the photoelectrons in the reference pixel cell RPx, and can perform a correlated double sampling process. The CDS 953b can extract a valid signal of the pixel cell Px through a correlated double sampling process, and can select the valid signal as an analog sampling signal corresponding to the valid pixel cell Px. The CDS 953b may include a plurality of CDS circuits, each of which may be connected to each read column of the pixel matrix and may detect an analog sampling signal through the read column. Then, the analog sampling signal may be converted into a digital signal through the ADC 953c.

[0139] The timing generator 955 may provide a timing signal to the row decoder 951 a and the column decoder 953 a , and may control a driving row to which an operation signal may be applied and a reading column from which an electrical signal may be detected.

[0140] The signal buffer 957 may temporarily store the digital image (electrical) signal detected by the signal detector 953 , and may sequentially transfer the digital image signal to the video signal processor in a decoding order of the column decoder 953 a .

[0141] In the present example embodiment, the image sensor 910 may be disposed on the substrate 100, and the ISP 950 may be disposed on another substrate different from the substrate 100. Therefore, the image sensor 910 and the ISP 950 may be connected to each other through the contact structure 800.

[0142] For example, the image sensor 910 may be used as Fig.11F The single image sensor chip ISC is disposed on the substrate 100 and the ISP 950 can be used as Fig.11F The logic chip LC in the embodiment is disposed on the additional substrate 958. The logic chip LC and the image sensor chip ISC may be electrically connected to each other through the contact structure 800. Fig.11F As described, the image sensor chip ISC and the logic chip LC may be combined with each other through a chip scaling process, and the wiring structure 500 of the image sensor chip ISC may be connected to the additional wiring structure 959 of the logic chip LC through the contact structure 800. For example, the contact structure 800 may include a through silicon via (TSV) structure.

[0143] For example, the operation driver 951, the signal detector 953, the timing generator 955, and the signal buffer 957 may be arranged on an additional substrate 958 ( Fig.11F ) and may be electrically connected to each other through an additional wiring structure 959. In this case, the contact structure 800 may be arranged in a contact margin region C, and the contact margin region C may have a sufficient size to prevent electrical interference between adjacent contact structures 800.

[0144] Specifically, since the pixel separation pattern 400 may be formed in a trapezoidal shape, the surface area of ​​the contact margin region C at the second surface 102 may be greater than the surface area at the first surface 101. Since the etching process for forming the contact hole CH may be performed on the second surface 102 of the substrate 100, a process margin for the etching process may be sufficiently provided due to the inverted trapezoidal shape of the contact margin region C.

[0145] Although the present exemplary embodiment discloses that the image sensor 910 and the ISP 950 may be disposed on different substrates, respectively, the image sensor 910 and the ISP 950 may be disposed on the same substrate. In this case, the contact structure 800 may not be required in the image sensor module 1000.

[0146] According to the present example embodiment of the image sensor module 1000, the conductive pattern 450 of the pixel separation pattern 400 may include a low resistance metal, and thus a negative bias voltage may be stably applied to the conductive pattern 450. Therefore, unstable application of a negative bias voltage due to a relatively high resistance of polysilicon may be minimized, and as a result, dark current in the image sensor module 1000 may be effectively removed.

[0147] In addition, the pixel separation pattern 400 may be shaped as a trapezoid in which the width may decrease from the first surface 101 on which the wiring structure 500 may be disposed to the second surface 102 on which the buffer layer 600 may be disposed. Since the second surface 102 may correspond to the back side or rear surface of the substrate 100 and incident light may be irradiated onto the second surface 102, the image sensor 910 may be configured as a backside illumination (BSI) structure, and the trapezoidal pixel separation pattern 400 may expand the receiving area of ​​the incident light, thereby improving the efficiency of the image sensor module 1000.

[0148] In the following, reference will be made to FIG. 11A to FIG. 13C A method of manufacturing the image sensor 910 is described in detail.

[0149] FIG. 11A to FIG. 11O It shows the manufacturing Figures 7 to 10 A cross-sectional view of a stage in a method of manufacturing an image sensor module 1000 .

[0150] Reference Fig.11A , an ion implantation process may be performed on the substrate 100 having the illumination area IA, the black area BA, and the contact area CA, thereby forming a well area W and a photoelectric converter layer 200 a in the illumination area IA and the black area BA of the substrate 100 .

[0151] The substrate 100 may include a first surface 101 on which an ion implantation process may be performed and a second surface 102 opposite to the first surface 101. For example, the substrate 100 may include a bulk silicon substrate having a p-type well doped with p-type impurities and a semiconductor substrate having a p-type bulk silicon substrate and a p-type epitaxial layer on the p-type bulk silicon substrate.

[0152] A plurality of unit areas UA may be arranged on the substrate 100. For example, a plurality of pixel areas A may be arranged in a matrix shape on the illumination area IA of the substrate 100. The matrix of the pixel areas A is referred to as a pixel matrix. A plurality of reference pixel areas B may be arranged on the black area BA of the substrate 100 along each row or column of the pixel matrix. Considering the process margin for forming the contact structure 800, at least one contact margin area C may be arranged on the contact area CA of the substrate 100. Therefore, the unit area UA may include the pixel area A, the reference pixel area B, and the contact margin area C.

[0153] Incident light may be irradiated on the illumination area IA, and photoelectrons may be generated as pixel charges in response to the incident light. Incident light may be blocked in the black area BA, and minimum light may be irradiated to the black area BA. Therefore, photoelectrons may be generated as reference charges in response to the minimum light. The reference charge may be set as a reference value of the pixel charge. The contact structure 800 may be formed on the contact area CA of the substrate 100.

[0154] The mask pattern may be formed on the substrate 100 in such a manner that the illumination area IA and the black area BA may be exposed by the mask pattern and the contact area CA may be covered by the mask pattern. Thereafter, an ion implantation process may be performed on the substrate 100 using the mask pattern as an ion implantation mask.

[0155] For example, since a p-type well region W may be formed at a surface portion of the first surface of the substrate 100, a plurality of n-type impurities may be doped into the substrate below the well region W, thereby forming an n-type dopant layer below the well region W in the illumination area IA and the black area BA of the substrate 100. Therefore, the n-type dopant layer and the p-type well region W may be formed as a PN junction diode, and the photoelectric converter layer 200a may be formed in the illumination area IA and the black area BA of the substrate 100.

[0156] Although the present example embodiment discloses that the photoelectric converter layer 200 a is formed before the pixel separating pattern 400 , the pixel separating pattern 400 may be formed before the photoelectric converter layer 200 a .

[0157] Then, a device isolation layer 390 may be formed in the well region W of the substrate 100, and some portions of the well region W defined by the device isolation layer 390 may be provided as active regions. For example, the device isolation layer 390 may be formed by a shallow trench isolation (STI) process.

[0158] Reference Fig. 11B The deep trench DT may be formed from the first surface 101 in such a manner that the unit area UA may be surrounded by the deep trench DT. Specifically, the deep trench DT may be shaped into an inverted trapezoidal shape in such a configuration that the width of the deep trench DT may be reduced from the first surface 101 and the deep trench DT may be narrowed downward into the substrate 100.

[0159] The mask pattern may be formed on the first surface 101 in such a manner that the unit area UA may be covered by the mask pattern and the peripheral portion of the unit area UA may be exposed by the mask pattern. Then, the substrate 100 may be partially removed by an etching process using the mask pattern as an etching mask, thereby forming a deep trench DT surrounding the unit area UA.

[0160] The substrate 100 may be subjected to a dry etching or wet etching process until the substrate 100 may be recessed to a predetermined depth near the unit area UA. Thus, the well region W and the photoelectric converter layer 200a may be partially removed from the substrate 100. The bottom surface TBS of the deep trench DT may be disposed near the second surface of the substrate 100. In this case, the side surface TSS of the deep trench DT may be inclined in such a manner that the deep trench DT may be narrowed downward from the first surface 101 to the second surface 102.

[0161] Reference Fig. 11C , a dummy separation layer 470a may be formed on the first surface 101 to a sufficient thickness to fill the deep trench DT. An insulating layer 410a may be formed on the bottom surface TBS and the side surface TSS of the deep trench DT and on the first surface 101 along the surface profile of the deep trench DT. Then, a dummy layer 420a may be formed on the insulating layer 410a to a sufficient thickness to fill the deep trench DT.

[0162] The insulating layer 410a can eliminate damage to the substrate caused by the etching process for forming the deep trench DT, and can reflect light toward the pixel region A and the reference pixel region B. For example, the insulating layer 410a may include silicon oxide and may be formed by an atomic layer deposition (ALD) process or a thermal oxidation process. Specifically, the insulating layer 410a may be formed as a liner extending on the first surface 101 of the substrate 100 along the surface profile of the deep trench DT. Therefore, although the size of the deep trench DT is reduced, a good Fig.11D The dummy pattern 420 has a sufficient width, and as a result, Fig.11J The metal conductive pattern 450 in FIG. 4 may be formed to be thick enough as much as possible.

[0163] In addition, the insulating layer 410a may include an insulating material with a refractive index lower than that of the substrate 100, thereby Fig.11D The oblique light of the insulating pattern 410 in FIG. 4 is refracted to the pixel region A and the reference pixel region B. In the present example embodiment, the insulating layer 410 a may have a refractive index of about 1.5.

[0164] Although the present example embodiment discloses that the insulating layer 410a may include silicon oxide, any other material may be used for the insulating layer 410a as long as the material may have a sufficiently small refractive index and damage to the substrate 100 caused by the etching process for forming the deep trench DT may be sufficiently eliminated due to the material. For example, the insulating pattern 410 may include silicon nitride or silicon oxynitride.

[0165] Thereafter, a dummy layer 420a may be formed on the insulating layer 410a to a sufficient thickness to fill the deep trench DT by a deposition process. Specifically, the dummy layer 420a may include a dummy material having a sufficient etching selectivity with respect to the substrate 100 and the insulating layer 410a. Examples of the dummy material may include silicon germanium (SiGe), silicon oxide (SiO 2 ), silicon nitride (SiN), borosilicate glass (BSG), polysilicon, etc. These may be used alone or in combination thereof.

[0166] Reference Fig.11DThe dummy separation layer 470a may be partially removed from the substrate 100 by a planarization process until the first surface 101 is exposed, thereby forming a dummy separation pattern 470 in the deep trench DT. Therefore, the unit area UA may be defined by the dummy separation pattern 470.

[0167] For example, the dummy separation layer 470a may be subjected to a chemical mechanical polishing process until the first surface 101 is exposed. Therefore, the dummy separation layer 470a may remain only in the deep trench DT, thereby forming a dummy separation pattern 470 having the insulating pattern 410 and the dummy pattern 420.

[0168] Specifically, the insulating layer 410a may remain only on the side surface TSS and the bottom surface TBS of the deep trench DT, thereby forming the insulating pattern 410 on the side surface TSS and the bottom surface TBS of the deep trench DT. In addition, the dummy layer 420a may remain only in the deep trench DT defined by the insulating pattern 410, thereby forming the dummy pattern 420 filling the deep trench DT and surrounded by the insulating pattern 410. The insulating pattern 410 may have a uniform thickness on the side surface TSS and the bottom surface TBS of the deep trench DT, and the dummy pattern 420 may be formed in an inverted trapezoidal shape.

[0169] The photoelectric converter layer 200a may be separated by pixel region A and reference pixel region B, thereby forming the photoelectric converter 200 in each pixel region A and in each reference pixel region B. In the present example embodiment, the photoelectric converter 200 may be formed as a PN junction photodiode.

[0170] Reference Fig.11E , a signal generator 300 and a wiring structure 500 may be sequentially formed on a substrate 100. The signal generator 300 may generate an electrical signal corresponding to an image of an object, and the wiring structure 500 may be connected to the signal generator 300.

[0171] For example, the active region of the well region W may be subjected to a front end of line (FEOL) process of a semiconductor manufacturing process to form a transfer transistor 310, a floating diffusion node 320, and a signal transistor 330 as the signal generator 300 on the active region. In the present example embodiment, the signal generator 300 may be formed at a surface portion of the active region in the well region W. However, the arrangement of the transfer transistor 310, the floating diffusion node 320, and the signal transistor 330 may be changed according to the characteristics and requirements of the image sensor 910. Therefore, some of the transfer transistor 310, the floating diffusion node 320, and the signal transistor 330 may be arranged in the active region, while others may be arranged on the active region.

[0172] The transfer transistor 310 may extend downward from the first surface 101 in the well region W, and an end of the transfer transistor 310 may be positioned near the photoelectric converter 200. That is, the transfer transistor 310 may be provided as a vertical transfer transistor. Therefore, photoelectrons may be efficiently transferred from the photoelectric converter 200 to the floating diffusion node 320.

[0173] The floating diffusion node 320 may be positioned near the transfer transistor 310, and photoelectrons may be transferred from the photoelectric converter 200 and accumulated in the floating diffusion node 320. The floating diffusion node 320 may be formed at a surface portion of the first surface 101 between the transfer transistor 310 and the device isolation layer 390 by an ion implantation process. The floating diffusion node 320 may have a semiconductor type different from that of the well region W. Therefore, in the present example embodiment, the floating diffusion node 320 may be formed by implanting an n-type dopant onto an active region of the well region W.

[0174] The signal transistor 330 may generate an electrical signal based on the photoelectrons accumulated at the floating diffusion node 320. The electrical signal may indicate image information of an object from which incident light may be reflected. Therefore, if necessary, the electrical signal may be referred to as an image signal. The electrical signal may be transmitted to the ISP 950, and the ISP 950 may process the image signal to generate image data of the object.

[0175] At least one signal transistor 330 may be formed on an active region of the well region W. Portions of the active region on which the transfer transistor 310, the floating diffusion node 320, and the signal transistor 330 are formed may be different from each other, and adjacent active regions may be isolated from each other by a device isolation layer 390. For example, the signal transistor 330 may include a reset transistor for discharging photoelectrons from the floating diffusion node 320, a source follower transistor for amplifying the voltage of the floating diffusion node 320, and a selection transistor for detecting the amplified voltage of the floating diffusion node 320 in response to a selection signal. The floating diffusion node 320 may be connected to the source electrode of the reset transistor and simultaneously to the gate electrode of the source follower transistor SF. The source follower transistor SF may be connected to the selection transistor.

[0176] Depending on the construction and requirements of the image sensor module 1000, all of the reset transistor, source follower transistor and select transistor can be formed on the pixel area A, or some of the reset transistor, source follower transistor and select transistor can be formed on an additional transistor area adjacent to the pixel area A.

[0177] Each pixel region A may include a photoelectric converter 200 and a signal generator 300, and may be separated from an adjacent pixel region A by a dummy separation pattern 470. Therefore, each pixel region A may be formed as a unit pixel UP of an image sensor. A plurality of unit pixels UP may be arranged in a matrix form, and a pixel unit Px may be formed in an illumination region IA of a substrate 100. Since a unit pixel UP may be formed at each pixel region A, a plurality of unit pixels UP may be arranged in a pixel matrix.

[0178] Each reference pixel region B may include a photoelectric converter 200 and a signal generator 300, and may be separated from an adjacent reference pixel region B by a dummy separation pattern 470. Thus, each reference pixel region B may be formed as a reference unit pixel RPx of an image sensor. The reference unit pixel RPx may generate a reference charge in response to minimum light. At least one reference unit pixel RPx may be arranged along a column or row of a pixel matrix, and the reference unit pixel RPx may be formed in a black area BA of the substrate 100.

[0179] The contact area CA may be protected from the FEOL process for forming the signal generator 300 by the mask pattern. Therefore, the unit area UA of the contact area CA may include bulk silicon defined by the dummy separation pattern 470 and may be provided as the contact margin area C.

[0180] When the formation of the signal generator 300 is completed, a semiconductor chip wiring process such as a BEOL process may be performed on the first surface 101 of the substrate 100 , thereby forming a wiring structure 500 that may be connected to the signal generator 300 .

[0181] For example, the first insulating interlayer 521 may be formed on the first surface 101 to such a thickness that the signal generator 300 may be covered by the first insulating interlayer 521, and the first plug P1 may be formed through the first insulating interlayer 521 in such a manner that the first plug P1 may be connected to the signal generator 300. Then, the lower metal wiring M0 may be formed on the first insulating interlayer 521 in such a manner that the lower metal wiring M0 may contact the first plug P1. Then, the second insulating interlayer 522 for covering the lower metal wiring M0 may be formed on the first insulating interlayer 521, and the second plug P2 may be formed through the second insulating interlayer 522 to contact the lower metal wiring M0. The first metal wiring M1 may be formed on the second insulating interlayer 522 in such a manner that the first metal wiring M1 may contact the second plug P2. The third insulating interlayer 523 may be formed on the second insulating interlayer 522, and the first metal wiring M1 may be insulated from the surrounding environment by the third insulating interlayer 523.

[0182] Thus, the lower metal wiring M0, the first metal wiring M1, the first plug P1, and the second plug P2 may constitute the conductive line 510. The first to third insulating interlayers 521, 522, and 523 may constitute the insulating layer 520, thereby forming the wiring structure 500.

[0183] Thus, the unit pixel UP and the reference unit pixel RPx may be formed in the substrate 100, and the signal generator 300 may be formed at a surface portion of the substrate in the illumination area IA and the black area BA of the substrate 100. Then, the wiring structure 500 may be formed across the illumination area IA, the black area BA, and the contact area CA of the substrate 100, thereby forming the image sensor 910.

[0184] Specifically, the image sensor 910 may be formed as a single image sensor chip ISC, and the image signal processor 950 may be formed as a single logic chip LC. Then, as described in detail below, the pixel chip and the logic chip may be combined with each other through a semiconductor packaging process, thereby forming the image sensor module 1000.

[0185] Reference Fig.11F ISP 950 may be manufactured as a separate logic chip LC by using an additional substrate 958, and ISP 950 may be combined with an image sensor chip ISC. For example, an operation device OD of ISP 950, such as an operation driver 951, a signal detector 953, a timing generator 955, and a signal buffer 957, may be formed on the additional substrate 958 by a conventional semiconductor manufacturing process. The operation driver 951, the signal detector 953, the timing generator 955, and the signal buffer 957 may have the same structure as the reference chip LC. Figures 7 to 10 The structures described in detail are substantially the same structures, and thus any further detailed description of the same operating device OD elements is omitted.

[0186] Then, an additional wiring structure 959 may be formed on the additional substrate 958 through a wiring process such as a BEOL process. The additional wiring structure 959 may be covered by an insulating layer and may be connected to the operating device OD of the ISP 950. That is, the ISP 950 may be provided as a separate logic chip LC.

[0187] In the present example embodiment, the image sensor 910 may be provided as an image sensor chip ISC, and the ISP 950 may be provided as a logic chip LC. Therefore, the image sensor structure 910 and the ISP may be combined with each other through a chip bonding process, thereby forming a package structure 990. For example, the logic chip LP and the image sensor chip ISC may be combined into a chip-scale package through a chip-scale packaging process.

[0188] Reference Fig.11G The package structure 990 may be turned upside down in such a manner that the second surface 102 may face upward and the logic chip LC may face downward. Then, the substrate 100 may be subjected to a thinning process until the dummy separation pattern 470 and the photoelectric converter 200 may be exposed.

[0189] For example, the second surface 102 of the substrate 100 may be subjected to a grinding process, and the overall thickness of the substrate 100 may be reduced. Thus, the second surface 102 may become closer to the first surface 101, and the photoelectric converter 200 and the dummy separation pattern 470 may be exposed. In the present example embodiment, the second surface 102 may correspond to the top surface of the photoelectric converter 200 and the top surface of the pixel separation pattern 400 after the thinning process.

[0190] Reference Fig.11H , the dummy pattern 420 may be removed from the substrate 100 by an etching process to thereby form a deep trench hole DTH defined by the insulating pattern 410 and closed by the first insulating interlayer 521 of the wiring structure 500 .

[0191] For example, the dummy pattern 420 may be subjected to a wet etching process by using an etchant having an etching selectivity with respect to the substrate 100 and the insulating pattern 410. The dummy pattern 420 may be removed from the substrate 100 without substantially damaging the insulating pattern 410 and the wiring structure 500.

[0192] When the dummy pattern 420 may include silicon germanium (SiGe), the etchant used in the wet etching process may include an aqueous solution of ammonium peroxide known as a standard clean-1 (SC-1) solution. Otherwise, when the dummy pattern 420 may include silicon oxide, the etchant used in the wet etching process may include an aqueous solution of hydrofluoric acid (HF). In addition, when the dummy pattern 420 may include silicon nitride, borosilicate glass (BSG), or polysilicon, the etchant used in the wet etching process may include an aqueous solution of phosphoric acid, an aqueous solution of hydrofluoric acid, an aqueous solution of hydrofluoric acid (HF), and an aqueous solution of ammonium, respectively.

[0193] In the present example embodiment, the dummy pattern 420 may include silicon germanium (SiGe) having a maximum etching selectivity with respect to the substrate 100 , and an aqueous ammonium peroxide solution or a standard clean-1 (SC-1) solution may be used as an etchant for selectively etching the dummy pattern 420 .

[0194] Reference Fig.11I , the conductive layer 450a may be formed on the second surface 102 of the substrate 100 to a thickness sufficient to fill the deep trench hole DTH. The conductive layer 450a may include a low-resistance metallic conductive material.

[0195] For example, when the low-resistance metal conductive material includes metal nitrides such as titanium nitride (TiN) and / or tantalum nitride (TaN), the conductive layer 450a can be formed by an atomic layer deposition (ALD) process. On the contrary, when the low-resistance metal conductive material includes a single metal such as tungsten (W) and copper (Cu), the conductive layer 450a can be formed by a chemical vapor deposition (CVD) process. Specifically, when copper (Cu) is used as the low-resistance metal conductive material, the conductive layer 450a can be grown from the first insulating interlayer 521 by an electroplating process until the deep trench hole DTH is fully filled with the conductive layer 450a.

[0196] In a modified example embodiment, the conductive layer 450a may include a transparent conductive oxide (TCO) having a refractive index sufficiently smaller than that of the substrate 100. For example, an indium tin oxide (ITO) layer may be formed to such a thickness as to fill up the deep trench hole DTH on the first insulating interlayer 521 and the photoelectric converter 200. In this case, although incident light may be obliquely irradiated onto the unit pixel UP and may be transmitted through the insulating pattern 410, the oblique light may be reflected again into the photoelectric converter 200, thereby improving light receiving efficiency.

[0197] Specifically, since the high temperature metal process for forming the conductive layer 450a can be performed at the side of the substrate opposite to the first surface 101, thermal damage to the signal generator 300 and the wiring structure 500 can be sufficiently prevented in the metal process. Therefore, the conductive layer 450a can be formed on the photoelectric converter 200 and the first insulating interlayer 521 without causing substantial thermal damage to the signal generator 300 and the wiring structure 500.

[0198] In addition, since the low resistance metal conductive material may have a much better gap filling property than polysilicon, the conductive layer 450a may be more uniform in the deep trench hole DTH even when the aspect ratio of the deep trench hole DTH becomes higher. When a negative bias voltage may be applied to the conductive pattern 450, the uniformity of the conductive layer 450a may be improved. Fig.11J The resistance of the conductive pattern 450 is reduced.

[0199] Reference Fig.11J The conductive layer 450a may be partially removed from the substrate 100 by a planarization process until the second surface 102 of the substrate may be exposed, thereby forming a conductive pattern 450 in the deep trench hole DTH. The insulating pattern 410 and the conductive pattern 450 in the deep trench hole DTH may be formed as a pixel separation pattern 400.

[0200] For example, the conductive layer 450a may be subjected to a chemical mechanical polishing (CMP) process until the second surface 102 may be exposed. Therefore, the conductive layer 450a may remain only in the deep trench hole DTH and be separated by the deep trench hole DTH, thereby forming a conductive pattern 450 in the deep trench hole DTH. Therefore, the dummy pattern 420 may be replaced with the conductive pattern 450, and the dummy separation pattern 470 having the insulating pattern 410 and the dummy pattern 420 may be replaced with the pixel separation pattern 400 having the insulating pattern 410 and the conductive pattern 450.

[0201] The conductive pattern 450 may be used as an electrode to which a negative bias may be applied. Since the conductive pattern 450 may include a low resistance conductive material, a negative bias may be stably applied to the conductive pattern 450, thereby effectively preventing dark current from being generated on the boundary surface between the photoelectric converter 200 and the insulating pattern 410.

[0202] According to the conventional image sensor, the separation pattern surrounding the unit pixel may include relatively high-resistance polysilicon, so the negative bias voltage may be unstably applied to the polysilicon pattern of the separation pattern. Therefore, the dark current may not be sufficiently removed from the surface of the separation pattern, which causes noise defects and deteriorates the image quality of the conventional image sensor.

[0203] In contrast, according to example embodiments, since polysilicon is replaced with the low resistance metal conductive pattern 450 without substantially thermally damaging the signal generator 300 and the wiring structure 500, a negative bias may be sufficiently applied to the pixel separating pattern 400. Therefore, dark current in the image sensor module 1000 may be sufficiently reduced.

[0204] Reference Figure 11K , a buffer layer 600 may be formed on the pixel separation pattern 400 and the photoelectric converter 200. For example, a metal oxide layer 610 may be formed on the pixel separation pattern 400 and the photoelectric converter 200, and an anti-reflection layer 620 may be formed on the metal oxide layer 610. The metal oxide layer 610 and the anti-reflection layer 620 may be formed by a CMP process.

[0205] In the present exemplary embodiment, the metal oxide layer 610 may include an aluminum oxide layer having a plurality of fixed charges. Since the fixed charges of the aluminum oxide may have a high negative potential, the photoelectrons of the photoelectric converter 200 may be prevented from being trapped on the boundary surface between the photoelectric converter 200 and the metal oxide layer 610. The anti-reflection layer 620 may prevent incident light from being reflected outward from the unit pixel UP, thereby improving the light receiving efficiency of the photoelectric converter 200.

[0206] A passivation layer 630 may be further formed on the anti-reflection layer 620. The passivation layer 630 may include silicon oxide.

[0207] Reference Fig.11L , the buffer layer 600 , the bulk silicon substrate, and the wiring structure 500 may be sequentially and partially removed from the contact area CA of the substrate 100 , thereby forming a contact hole CH through which the ISP 950 may be exposed.

[0208] For example, a mask pattern may be formed on the buffer layer 600 in such a configuration that the illumination area IA and the black area BA may be covered by the mask pattern and the contact area CA may be exposed by the mask pattern. Then, a dry etching process such as a plasma etching process may be performed on the package structure 990 in such a manner that the buffer layer 600 corresponding to the contact area CA, the substrate 100 of the contact margin area C, and the wiring structure 500 on the contact margin area C of the substrate 100 may be partially removed until the operating device OD may be exposed, thereby forming a contact hole CH through which the operating device OD of the ISP 950 may be exposed.

[0209] Reference Fig.11M , a conductive capping layer 650 may be disposed on the buffer layer 600 and on the sidewall and bottom of the contact hole CH. Therefore, the capping layer 650 may contact the wiring structure 500 and the ISP 950 in the contact hole CH.

[0210] For example, a low resistance conductive material may be deposited on the sidewalls and bottom of the buffer layer 600 and the contact hole CH by an ALD process, thereby forming a capping layer 650 on the sidewalls and bottom of the buffer layer 600 and the contact hole CH. The capping layer 650 may include a conductive material having a low resistance such as tungsten (W), titanium (Ti), tantalum (Ta) and nitrides thereof.

[0211] Reference Fig.11N , an insulating column 890 can be formed in the contact hole CH in the contact area CA of the substrate, and the cover layer 650 can be formed into a grid pattern 651, an optical blocking pattern 653 and a contact pad 655 in the illumination area IA, the black area BA and the contact area CA of the substrate 100, respectively.

[0212] For example, a supplementary insulating layer may be formed on the cover layer 650 to a thickness sufficient to fill the contact hole CH, and then the supplementary insulating layer may be planarized until the cover layer may be exposed. Therefore, the supplementary insulating layer may remain only in the contact hole CH as an insulating column 890. Therefore, the insulating column 890 may be surrounded by the cover layer 650 in the contact hole CH, and the upper surface of the insulating column 890 may be coplanar with the upper surface of the cover layer 650. The supplementary insulating layer may include an insulating material such as silicon oxide. Specifically, the cover layer 650 on the sidewall and bottom of the contact hole CH may be used as a vertical contact line for contacting both the wiring structure 500 and the ISP950, thereby forming a contact extension 810 in the contact hole CH. The contact extension 810 may surround the insulating column 890 in the contact hole CH, and the contact hole CH may be filled with the contact extension 810 and the insulating column 890. The contact extension 810 and the insulating column 890 may constitute the contact structure 800.

[0213] In addition, the cover layer 650 on the buffer layer 600 in the contact area CA of the substrate 100 may be integrally provided with the contact extension 810 as one body, and may be used as a contact pad 655 for expanding the contact area of ​​the contact extension 810. That is, the cover layer 650 in the contact area CA may be divided into the contact extension 810 in the contact hole CH and the contact pad 655, and the contact pad 655 may be arranged on the buffer layer 600 and may be connected to the contact extension 810.

[0214] The capping layer 650 in the black area BA may function as an optical blocking pattern 653 for blocking light transmission into the reference pixel unit RPx. Therefore, the photoelectric converter 200 in the reference pixel area B may generate photoelectrons in response to the minimum light, and the photoelectrons of the reference pixel unit RPx may be set as reference charges of the image sensor module 1000.

[0215] The cover layer 650 in the illumination area IA may be partially removed from the buffer layer 600 in such a manner that the buffer layer 600 on the photoelectric converter 200 may be exposed and the cover layer 650 on the separation pattern may remain, thereby forming the filter hole FH and the grid pattern 651 defining the filter hole FH. Oblique light that may be obliquely incident on the unit pixel UP may be reflected from the grid pattern 651 into the photoelectric converter 200, thereby improving the light receiving efficiency of the photoelectric converter 200.

[0216] Reference Fig.11O , another mask pattern may be formed on the optical blocking pattern 653 , the contact pad 655 , and the contact structure 800 , and then the color filter 710 may be formed in the filter hole FH.

[0217] For example, a color filter layer may be formed on the buffer layer 600 in the illumination area IA by a dyeing process, a pigment dispersion process, and a printing process. Then, the color filter layer may be partially removed from the encapsulation structure 990 by a photolithography process and a planarization process until the grid pattern 651 may be exposed, thereby forming a color filter 710 in the filter hole FH.

[0218] Thereafter, a microlens 730 may be formed on the color filter 710 per unit pixel UP, and may be arranged on each photoelectric converter 200. For example, the microlens may have a convex shape that may diverge toward an incident direction of light.

[0219] Thereafter, the mask pattern may be removed from the encapsulation structure 990, and the optical blocking pattern 653, the contact pad 655, and the contact structure 800 may be exposed, thereby forming Figures 7 to 10 Image sensor module in.

[0220] FIG. 12A to FIG. 12E According to another exemplary embodiment, Figure 3 A cross-sectional view of a stage in a method of manufacturing an image sensor module.

[0221] Reference Fig. 12A , can be referenced FIG. 11A to FIG. 11C After forming the dummy layer 420 a on the substrate 100 , the dummy layer 420 a may be subjected to an etch-back process by using the insulating layer 410 a as an etch stop layer, thereby separating the dummy layer 420 a through the deep trench DT.

[0222] Therefore, the insulating layer 410a may be exposed to the surrounding environment, and the dummy layer 420a may be formed in the deep trench DT as the reduction dummy pattern 440. The top surface of the reduction dummy pattern 440 may be lower than the top surface of the insulating layer 410a, and the recess R may be provided at the upper portion of the deep trench DT in such a configuration that the recess R may be defined by the reduction dummy pattern 440 and the insulating layer 410a.

[0223] Reference Fig. 12B , the additional separation layer 394a may be formed on the insulating layer 410a and the reduction dummy pattern 440 to a thickness sufficient to fill the recess R. For example, an oxide having a good gap-filling property may be deposited on the insulating layer 410a and the reduction dummy pattern 440 by a CVD process, thereby forming the additional separation layer 394a on the insulating layer 410a and the reduction dummy pattern 440.

[0224] Reference Fig. 12C , the additional separation layer 394 a and the insulating layer 410 a may be planarized until the first surface 101 and the device isolation layer 390 may be exposed, thereby forming an additional separation pattern 394 in the recess R.

[0225] For example, the CMP process may be performed on the additional separation layer 394 a and the insulating layer 410 a , and the additional separation layer 394 a may remain only in the recess R and may be separated by the recess R. In addition, the insulating layer 410 a may also be separated by the deep trench DT.

[0226] Thus, the deep trench DT may be filled with the reduced dummy pattern 440 , the additional separation pattern 394 , and the insulating pattern 410 , thereby forming a modified dummy pattern 480 in the deep trench DT. Top surfaces of the additional separation pattern 394 and the insulating pattern 410 may be coplanar with the first surface 101 and the top surface of the device isolation layer 390 .

[0227] Reference Fig.12D , can be obtained by referring to Figures 11E to 11G The same process as described in detail forms the wiring structure 500 and the ISP 950 on the first surface 101 of the substrate 100, thereby forming a package structure 992. In this case, the ISP 950 may be provided as an additional logic chip LC. Thereafter, the package structure 992 may be turned upside down in such a manner that the second surface 102 may face upward and the logic chip LC may face downward. Thereafter, the second surface 102 of the substrate 100 may be thinned until the dummy separation pattern 480 and the photoelectric converter 200 may be exposed. Thus, the second surface 102 may become closer to the first surface 101, and the photoelectric converter 200 and the modified dummy pattern 480 may be exposed.

[0228] Reference Fig.12E , can be obtained by referring to FIG. 11H to FIG. 11I The same process as described in detail replaces the reduced dummy pattern 440 with a conductive layer 450 a , thereby forming a first modified pixel separating pattern 400 a in the deep trench hole DTH.

[0229] The conductive layer 450a may extend from the surface of the additional separation pattern 394 to the second surface 102 of the substrate 100, so that the height of the conductive layer 450a may be greater than Fig. 9 The height of the conductive pattern 450 in the embodiment is smaller than the thickness of the additional separation pattern 394. Therefore, the aspect ratio of the conductive layer 450a can be reduced by the thickness of the additional separation pattern 394, thereby reducing gap filling defects of the conductive layer 450a and increasing the uniformity of the conductive layer 450a. The uniformity of the conductive layer 450a can reduce the resistance of the conductive layer 450a, and thus a negative bias can be applied to the conductive layer 450a more stably.

[0230] Thereafter, the package structure 992 having the first modified pixel separation pattern 400a may be subjected to the same Figures 11J to 11O The same process as described in detail, thereby manufacturing Figure 3 An image sensor module of an image sensor in the image sensor.

[0231] FIG. 13A to FIG. 13C It is shown that manufacturing has Figure 4 A cross-sectional view of a stage in a method of manufacturing an image sensor module of an image sensor.

[0232] Reference Fig.13A , can be referenced by FIG. 11A to FIG. 11H After forming the deep trench hole DTH in the package structure 990 , a protection layer 430 a may be formed on the insulation pattern 410 , the photoelectric converter, and the first surface 101 of the substrate 100 along the surface profile of the deep trench hole DTH.

[0233] The protective layer 430a can protect the second surface 102 and the photoelectric converter 200 from the subsequent CMP process for forming the conductive pattern 450. Therefore, the silicon substrate can be protected from the high temperature metal replacement process. For example, the protective layer 430a can include any one of silicon oxide, silicon nitride and silicon oxynitride.

[0234] Specifically, the protective layer 430 a may include a material having a refractive index smaller than that of the substrate 100 , which may improve light receiving efficiency of the unit pixel UP.

[0235] Reference Fig. 13B , can be obtained by referring to Fig.11I The same process as described in detail, the conductive layer 450a is formed on the second surface 102 of the substrate 100 to a thickness sufficient to fill the deep trench hole DTH. The conductive layer 450a may include a low resistance metal conductive material.

[0236] Reference Fig. 13C , the conductive layer 450a and the protective layer 430a can be partially removed from the substrate 100 by a planarization process until the second substrate 102 of the substrate can be exposed, thereby Fig.11J The same process as described in detail forms the conductive pattern 450 and the protective pattern 430 in the deep trench hole DTH. The insulating pattern 410, the protective pattern 430, and the conductive pattern 450 in the deep trench hole DTH may be formed as a second modified pixel separating pattern 400b.

[0237] Thereafter, the package structure 990 having the second modified pixel separation pattern 400b may be compared with the reference Figures 11K to 11O The same process as described in detail, thereby manufacturing Figure 4 An image sensor module of an image sensor in the image sensor.

[0238] Therefore, the second surface 102 of the substrate 100 may be sufficiently protected from the high temperature metal replacement process by the protection layer 430 a , thereby preventing or minimizing noise defects caused by surface defects of the second surface 102 .

[0239] By way of summary and review, a CIS may include a plurality of pixels in a 2×2 matrix shape, and at least one photoelectric converter such as a photodiode is arranged at each pixel. Incident light is converted into an electrical signal by the photoelectric converter.

[0240] A pair of adjacent pixels adjacent to each other can be separated by a pixel separation pattern, and thus the electrical signals generated individually from each adjacent pixel can be electrically separated by the pixel separation pattern. The pixel separation pattern may include an insulating material having a refractive index different from that of the substrate, and thus the incident light entering each pixel is prevented from being refracted into the adjacent pixel by the pixel separation pattern. Therefore, signal interference between adjacent pixels, which is known as a crosstalk defect, can be fully prevented by the pixel separation pattern.

[0241] Polysilicon can be filled in the pixel separation pattern, and the pixel separation pattern can be used as an electrode for applying a negative bias voltage that minimizes the dark current of the CSI. However, when the aspect ratio of the deep trench for the separation pattern increases (increases as the cell size of the image sensor decreases), it is difficult to fill the polysilicon into the deep trench of the pixel separation pattern. In addition, the resistance of the polysilicon will increase significantly due to the gap filling defects of the polysilicon in the deep trench, and therefore it will not be sufficient to minimize the dark current in the image sensor. In addition, the difficulty of filling polysilicon into the deep trench makes the filling process more complicated, which significantly reduces the manufacturing efficiency of the image sensor.

[0242] In contrast, example embodiments provide an image sensor having a pixel separation pattern into which a low resistance metal pattern is filled. Other example embodiments provide an image sensor module having the above image sensor, and a method of manufacturing the above image sensor.

[0243] That is, according to the example embodiment, the conductive pattern of the separation pattern in the deep trench hole may include a low-resistance metal replacing the polysilicon. Therefore, a negative bias voltage may be stably applied to the separation pattern, and dark current in the image sensor may be effectively removed. In addition, since the polysilicon may be replaced with a low-resistance metal by a metal replacement process performed on the second surface of the substrate without causing any thermal damage to the signal generator and the wiring structure, a negative bias voltage may be stably applied to the pixel separation pattern, and the image quality of the image sensor may be significantly improved without causing any damage to the signal generator and the wiring structure.

[0244] In addition, the separation pattern may be shaped as a trapezoid in which the width may decrease from the first surface on which the wiring structure is arranged to the second surface on which the buffer layer is arranged. Since the second surface may correspond to the back side or rear surface of the substrate and incident light may be irradiated onto the second surface, the image sensor may be configured as a back side illumination (BSI) structure, and the trapezoidal pixel separation pattern may expand the receiving area of ​​the incident light, thereby improving the efficiency of the image sensor.

[0245] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, unless otherwise specifically indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by one of ordinary skill in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims below.

Claims

1. An image sensor, comprising: a substrate comprising a first surface and a second surface opposite to the first surface; a photoelectric converter located in the pixel region of the substrate to generate photoelectrons in response to incident light incident on the pixel region; a signal generator located on the first surface of the substrate in the pixel region to generate an electrical signal corresponding to image information of the object based on the photoelectrons; a pixel separation pattern, comprising an insulating pattern having a refractive index less than that of the substrate and a metal conductive pattern surrounded by the insulating pattern, wherein the pixel region is surrounded by the pixel separation pattern and isolated from adjacent pixel regions; as well as an additional separation pattern, adjacent to the first surface of the substrate, in contact with the insulating pattern and separating adjacent pixel regions, the additional separation pattern comprising a boundary surface coplanar with the first surface of the substrate and an inner surface in contact with the lower surface of the metal conductive pattern in the substrate, wherein the pixel separation pattern and the additional separation pattern are vertically stacked to penetrate the entire thickness of the substrate, The upper surface of the metal conductive pattern is coplanar with the second surface of the substrate, and The insulating pattern is coplanar with each of the first surface and the second surface of the substrate.

2. The image sensor according to claim 1, wherein: The pixel separation pattern has a trapezoidal shape whose width decreases from the first surface to the second surface of the substrate.

3. The image sensor according to claim 2, wherein: The insulating pattern has a uniform thickness between the first surface and the second surface, and the metal conductive pattern has a non-uniform thickness that decreases from the first surface to the second surface.

4. The image sensor according to claim 2, wherein: The pixel separating pattern includes a protection pattern between the insulating pattern and the metal conductive pattern.

5. The image sensor according to claim 4, wherein: The insulating pattern and the protection pattern have uniform thicknesses between the first surface and the second surface, respectively, and the metal conductive pattern has non-uniform thicknesses between the first surface and the second surface.

6. The image sensor according to claim 4, wherein: The protection pattern extends between an inner surface of the additional separation pattern and a lower surface of the metal conductive pattern.

7. The image sensor according to claim 1, wherein: The pixel separation pattern includes air gaps in the metal conductive pattern, the air gaps including holes filled with air.

8. The image sensor according to claim 1, further comprising: a wiring structure located on the first surface of the substrate and connected to the signal generator; a buffer layer, located on the second surface of the substrate; as well as The light-transmitting unit is located on the buffer layer, and the incident light is incident on the photoelectric converter through the light-transmitting unit.

9. The image sensor according to claim 1, wherein: The metal conductive pattern includes at least one of titanium nitride, tantalum nitride, tungsten, copper, transparent conductive oxide, and combinations thereof.

10. An image sensor module, comprising: An image sensor, comprising a substrate and a plurality of unit pixels, wherein the substrate comprises a first surface and a second surface opposite to the first surface; the plurality of unit pixels generate electrical signals corresponding to an image of an object according to incident light, the plurality of unit pixels are located on the substrate and are separated from each other by a pixel separation pattern and an additional separation pattern penetrating the substrate; the pixel separation pattern has an insulating pattern and a metal conductive pattern surrounded by the insulating pattern; the additional separation pattern is adjacent to the first surface of the substrate and contacts the insulating pattern and comprises a boundary surface coplanar with the first surface of the substrate and an inner surface in the substrate that contacts the lower surface of the metal conductive pattern; and an image signal processor (ISP), which is electrically connected to the image sensor and processes the electrical signal to generate image data of the object, wherein the pixel separation pattern and the additional separation pattern are vertically stacked to penetrate the entire thickness of the substrate, The upper surface of the metal conductive pattern is coplanar with the second surface of the substrate, and The insulating pattern is coplanar with each of the first surface and the second surface of the substrate.

11. The image sensor module according to claim 10, wherein: The pixel separation pattern of the image sensor has a trapezoidal shape whose width decreases from a first surface of the substrate to a second surface of the substrate opposite to the first surface.

12. The image sensor module according to claim 11, wherein: The pixel separation pattern of the image sensor includes a protection pattern between an insulation pattern and a metal conductive pattern.

13. The image sensor module of claim 12, wherein: The protection pattern extends between an inner surface of the additional separation pattern and a lower surface of the metal conductive pattern.

14. The image sensor module of claim 10, wherein: The substrate includes an illumination area, a black area and a contact area, incident light is incident on the illumination area, the incident light is blocked on the black area, and the contact structure penetrates the substrate through the contact area. At least one photoelectric converter that generates photoelectrons in response to incident light is arranged in unit pixels of the illumination area and the black area, and The at least one photoelectric converter and the contact structure are respectively surrounded by a pixel separation pattern in each of an illumination area, a black area, and a contact area of ​​the substrate.

15. The image sensor module of claim 14, wherein: Image sensors include: a signal generator disposed on the first surface of the substrate in each unit pixel to generate an electrical signal according to the photoelectrons; a wiring structure located on the first surface of the substrate and connected to the signal generator; a buffer layer disposed on a second surface opposite to the first surface of the substrate; and The light-transmitting unit is located on the buffer layer in the illumination area, and the incident light is focused on the photoelectric converter through the light-transmitting unit.

16. The image sensor module of claim 15, wherein: Image sensors include: A grid pattern is located on the buffer layer corresponding to the pixel separation pattern in the illumination area of ​​the substrate, and oblique light obliquely incident on the unit pixel is reflected from the grid pattern to the photoelectric converter; an optical blocking pattern covering the buffer layer in a black region of the substrate, the optical blocking pattern blocking incident light from entering the photoelectric converter in the black region; and A contact pad covers the buffer layer and contacts the contact structure in a contact region of the substrate.

17. The image sensor module of claim 16, wherein: The contact structure includes: a conductive contact extension that contacts the contact pad and penetrates the substrate to contact the wiring structure and the ISP; and An insulating post extends through the substrate and is surrounded by the conductive contact extension.

18. The image sensor module of claim 14, wherein: The image sensor includes an image sensor chip on a substrate, and the ISP includes a logic chip on an additional substrate different from the substrate, the image sensor chip and the logic chip being electrically connected to each other through a contact structure.

19. A method for manufacturing an image sensor, the method comprising the following steps: Performing an ion implantation process on a first surface of the substrate having an illumination region, a black region, and a contact region, so that a photoelectric converter layer is formed in the illumination region and the black region of the substrate; forming a deep groove extending from the first surface of the substrate to the inside of the substrate so that a pixel area, a reference pixel area, and a contact margin area are defined in the illumination area, the black area, and the contact area of ​​the substrate, respectively, and forming a photoelectric converter in the pixel area and the reference pixel area; forming an insulating layer on the bottom surface and side surfaces of the deep trench and on the first surface of the substrate along the surface profile of the deep trench and forming a dummy layer having a sufficient thickness to fill the deep trench on the insulating layer; performing an etch-back process on the dummy layer by using the insulating layer as an etch stop layer to form reduced dummy patterns located in the deep trench and separated from each other, the top surface of the reduced dummy patterns being lower than the top surface of the insulating layer to form a recess; forming an additional separation layer having a sufficient thickness to fill the recess on the insulating layer and the reduced dummy pattern; planarizing the additional separation layer and the insulating layer to form an additional separation pattern; sequentially forming a signal generator and a wiring structure connected to the signal generator on a first surface of the substrate, the signal generator generating an electrical signal corresponding to an image of the object based on photoelectrons generated by the photoelectric converter; thinning a second surface of the substrate opposite to the first surface to form dummy separation patterns, each of the dummy separation patterns including an insulating pattern formed of an insulating layer and having a refractive index less than that of the substrate and a reduced dummy pattern surrounded by the insulating pattern; as well as replacing the reduced dummy pattern with a metal conductive pattern through a metal replacement process to form a pixel separation pattern formed of the metal conductive pattern and the insulating pattern, wherein the pixel separation pattern and the additional separation pattern are vertically stacked to penetrate the entire thickness of the substrate, The upper surface of the metal conductive pattern is coplanar with the second surface of the substrate, and The insulating pattern is coplanar with each of the first surface and the second surface of the substrate.

20. The method of claim 19, wherein: The steps to perform the metal replacement process include: removing the reduced dummy pattern from the substrate to form a deep trench hole, the insulation pattern and the wiring structure being exposed through the deep trench hole; forming a metal conductive layer on the second surface of the substrate to a thickness sufficient to fill the deep trench hole; and The metal conductive layer is planarized until the second surface is exposed, so that the metal conductive layer is formed to be coplanar with the second surface and fill the deep trench hole.

21. The method of claim 20, further comprising: Before forming the metal conductive layer, a protection layer is formed on the insulating layer, the additional separation pattern and the second surface of the substrate along the surface profile of the deep trench hole.

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