Multi-output gate driver system and method of operating the same

Abstract

A multi-output gate driver system and an operation method thereof are disclosed. The multi-output gate driver system includes: a power device having a gate node; a first driver having an input terminal and an output terminal coupled to the gate node; a second driver having an input terminal and an output terminal coupled to the gate node; a first comparator having a first input terminal coupled to the output terminal of the second driver, a second input terminal coupled to a first reference voltage, and an output terminal; a second comparator having a first input terminal coupled to the output terminal of the second driver, a second input terminal coupled to a second reference voltage, and an output terminal; and a logic circuit having an input terminal for receiving a control signal, a first output terminal coupled to the input terminal of the first driver, and a second output terminal coupled to the input terminal of the second driver.

Description

Technical Field

[0001] The present invention generally relates to systems and methods for static gate clamping in a multiple output gate driver system. Background Art

[0002] The gate driver is a power amplifier and may also include additional circuits such as a level shifter. The gate driver accepts a low-power input signal from an associated controller IC and generates a high-current drive input signal for the gate of a high-power transistor such as an insulated gate bipolar transistor (IGBT) or a power metal oxide semiconductor field effect transistor (MOSFET). Typically, a single output of the gate driver is used to drive a single gate node of a power transistor. Two outputs can sometimes be used to drive a high-side power transistor and a low-side power transistor. The gate driver may have one or more dedicated outputs for providing a clamping function. Summary of the invention

[0003] A multi-output gate driver system includes: a power device having a gate node; a first driver having an input terminal and an output terminal coupled to the gate node; a second driver having an input terminal and an output terminal coupled to the gate node; a first comparator having a first input terminal coupled to the output terminal of the second driver, a second input terminal coupled to a first reference voltage, and an output terminal; a second comparator having a first input terminal coupled to the output terminal of the second driver, a second input terminal coupled to a second reference voltage, and an output terminal; and a logic circuit having an input terminal for receiving a control signal, a first output terminal coupled to the input terminal of the first driver, and a second output terminal coupled to the input terminal of the second driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] For a more complete understanding of the present invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0005] Figure 1A is a schematic diagram of an embodiment of a multiple output gate driver system including a voltage comparator associated with an on-state operating condition and an off-state operating condition, and a schematic diagram of an alternative configuration of a gate resistor used in the gate driver system;

[0006] Figure 1B is with Figure 1A Logic tables associated with a multiple output gate driver system;

[0007] Figure 2A is a schematic diagram of another embodiment of a multi-output gate driver system, wherein the second output terminal is used only for clamping;

[0008] Figure 2B is with Figure 2A Logic tables associated with a multiple output gate driver system;

[0009] Figure 3A is a schematic diagram of another embodiment of a multi-output gate driver system, wherein the second output terminal is used for sourcing and clamping during an off state;

[0010] Figure 3B is with Figure 3A Logic tables associated with a multiple output gate driver system;

[0011] Figure 4 is with Figure 1A to the timing diagram associated with the multi-output gate driver system shown in FIG3 ;

[0012] Figure 5 is a graph of the variation of collector voltage over time ("dV / dt") of a power device as a function of collector current for an on operating condition and an off operating condition for a specified value of gate resistance of the power device;

[0013] Figure 6 is a schematic diagram of an embodiment of a multi-output gate driver system including a multi-output gate driver integrated circuit ("IC") having two output terminals, wherein the two output terminals can sink and source current, respectively;

[0014] Figure 7 is similar to Figure 6 An embodiment of a multi-output gate driver system as shown in a schematic diagram of a multi-output gate driver system, but including a series diode for causing deactivation of the second output terminal under an off condition;

[0015] Figure 8 is a diagram of a control scheme for driving a power device at a specified dv / dt target value for use with a multi-output gate driver IC according to an embodiment;

[0016] Fig. 9 is with Figure 6 Logic tables associated with a multiple output gate driver system;

[0017] Fig.10 is with Fig. 9 The timing diagram corresponding to the table shown;

[0018] Fig.11 is a schematic diagram of a multiple output gate driver system, wherein a second output of a gate driver IC can be switched with a predetermined or programmable delay or simultaneously with a first output depending on logic conditions applied at an input;

[0019] Fig.12is a schematic diagram of a multi-output gate driver system, wherein a second output terminal of a gate driver IC may be operated using a comparator to detect a voltage level at a gate of a power device;

[0020] Fig.13 is a schematic diagram showing a multi-output gate driver system of more than two drivers, wherein each driver has a single output terminal; and

[0021] Fig.14 is a schematic diagram showing a multi-output gate driver system of more than two drivers, wherein each driver has separate sinking and sourcing outputs. DETAILED DESCRIPTION

[0022] According to an embodiment, the gate driver may have two or more independently controllable outputs or related controllable outputs, each of which applies a gate voltage to a driven power transistor in an operating mode. Each of the outputs may have a gate resistor that is independently used for switching on and off. Each output may be activated according to a dedicated load condition or a temperature condition or other operating condition. The more outputs are activated (switched in parallel), the faster the driven power transistor (sometimes referred to as a "switch" or "device") can be switched. Therefore, the switching speed of the corresponding converter or inverter including the gate driver and the switch can also be improved. A better trade-off between switching losses and EMI or a safe operating area can also be achieved.

[0023] In a dual-output gate driver, when only one of the two outputs is operated, the other output can be kept in a high-impedance state. However, for power transistors, high-impedance operation of the second output has two disadvantages:

[0024] 1. Power transistors are sensitive to parasitic turn-on during dv / dt events in the off state.

[0025] 2. The high-side clamping strength in the on state is relatively weak.

[0026] Thus, according to an embodiment of the multi-output gate driver system, the second output supports both an off-state clamping to a negative gate voltage and an on-state clamping to a positive gate voltage. Clamping refers to the activation of an associated driver stage, circuit, or output FET. Clamping high refers to the activation of a sourcing stage of an associated driver. Clamping low refers to the activation of a sinking stage of an associated driver.

[0027] Once the gate voltage of the first output terminal reaches a certain level (at which the switching transients of the current and voltage of the driven transistor have passed), the multi-output gate driver system copies the state of the first output terminal to the second output terminal. This function can be implemented, for example, by a voltage comparator described in further detail below, which monitors the instantaneous gate voltage. If the gate voltage of the power transistor is lower than the gate emitter or gate source threshold of the power transistor, the gate can be clamped to a negative gate voltage. Similarly, if the gate voltage is close to the positive rail, the gate can be clamped to the positive rail voltage. However, during each change of the gate voltage, the second output terminal is inactive.

[0028] Figure 1A 1 shows a schematic diagram of a multi-output gate driver system 100, including: a power device 108 having a gate node; a first driver 104 having an input terminal and an output terminal OUT1 coupled to the gate node; a second driver 102 having an input terminal and an output terminal OUT2 coupled to the gate node; a first comparator CP1 having a positive input terminal coupled to the output terminal of the second driver 102 and coupled to a first reference voltage V on A second comparator CP2 having a negative input terminal coupled to the output terminal of the second driver 102, a negative input terminal coupled to the second reference voltage V OFF A positive input terminal and an output terminal of the first comparator CP1; and a logic circuit 106 having a first input terminal for receiving a control signal for turning on and off the power device, a second input terminal coupled to the output terminal of the first comparator CP1 and the output terminal of the second comparator CP2, a first output terminal 112 coupled to the input terminal of the first driver 104, and a second output terminal 110 coupled to the input terminal of the second driver 102. Figure 1A In the embodiment, the logic circuit 106 can be implemented as hardware or software. At least two input signals are received by the logic circuit 106: an on / off signal for changing the state of the power device 108, and a signal associated with the output of the comparators CP1 and CP2. Depending on the logic function used by the logic circuit 106, an input bus with an "n" bit width can be implemented, the "n" bit width depending on, for example, the number of outputs used. For example, in Figure 1A In an embodiment, a two-bit wide input bus corresponding to two different input signals may be used. The operation of the logic circuit 106 and the entire multi-output gate driver system 100 will be described in further detail below.

[0029] The gate driver circuit 116 including the gate drivers 102 and 104, the comparators CP1 and CP2, and the logic circuit 106 can be implemented as a single integrated circuit including other circuits such as a microprocessor and other circuits in the implementation. In other implementations, discrete components or multiple integrated circuits or a combination of discrete components and multiple integrated circuits can also be used.

[0030] exist Figure 1A , two gate resistors Rg1 and Rg2 are used. Gate resistor Rg1 is coupled between the output of driver 104 and the gate node of power device 108. Gate resistor Rg2 is coupled between the output of driver 102 and the gate node of power device 108. Single resistor elements with the same value or different values ​​can be used for gate resistors Rg1 and Rg2. However, an alternative parallel resistor circuit 114 can also be used to accommodate various operating modes. Parallel resistor circuit 114 shows a first resistor Rg1 in series combination with a diode D. OFF The first resistor and the diode and the second resistor Rg ON In an embodiment, the first resistor and the second resistor in the parallel resistor circuit 114 may have different values. In this case, the parallel resistor circuit 114 will have different values ​​when sinking or sourcing current from the gate of the power device 108. If a separate terminal for sourcing current (connected to the resistor Rg) is used, ON ) and a separate terminal for sinking current (connected to resistor Rg OFF ) implementation, the diode D can be omitted. Fig.14 Such an embodiment is shown in .

[0031] The filters at the input and / or output of each comparator CP1 and CP2 are optional. Fig.13 and Fig.14 A suitable filter arrangement is shown in FIG and described in further detail below.

[0032] In operation, depending on the control settings, the second output terminal OUT2 is used as a sensing input for the gate voltage. This is possible during a suitable time interval after the transition of OUT1 where OUT2 remains deactivated (in high impedance). In case of a turn-off transient, once the gate voltage is below the comparator threshold (V OFF ) , OUT2 is activated. In the case of the on-threshold, once the gate voltage is higher than the threshold of CP1 (V ON), OUT2 is activated. If the control is changed to switch both outputs (OUT1 and OUT2) together in order to obtain an overall lower gate resistance, in principle no monitoring comparator is required in the case of two driver stages. An alternative embodiment without the two comparators CP1 and CP2 will be explained in further detail below. In this embodiment, the second output OUT2 can still be sensed. If more than two driver stages are used in parallel, the last output should be sensed to compare with the other outputs ( Figure 1A Alternatively, a separate sense pin may also be used.

[0033] Figure 1A The resistance and voltage ranges of the multiple output gate driver system 100 shown in FIG. 1 may be varied to suit a particular application.

[0034] Figure 1B yes Figure 1A The corresponding logic table of the circuit implementation method includes twelve logic states, wherein each IN, INF, OUT1 and OUT2 logic state is specified. In addition, it is also shown Figure 1A The output impedance and operating state of the circuit implementation.

[0035] about Figure 1B , Figure 2B and Figure 3B , the asterisks in the logic table indicate optional logic states, and the output terminal OUT2 can alternatively be kept in HiZ (high impedance state).

[0036] Regarding the clamping function, the OUT2 output will not reach the on-state or off-state until the OUT2 voltage reaches a level close to the OUT1 voltage.

[0037] Figure 2A 2 is a schematic diagram of another embodiment of a multi-output gate driver system 200, which uses only the second output terminal OUT2 as a gate clamp. In the gate driver system 200, the second output terminal OUT2 is activated only when the first output terminal OUT1 has reached its stable state, that is, the on state or the off state. Therefore, the second gate resistor is not required in the gate driver system 200. In addition, as described above, Figure 2A All numbered parts shown in .

[0038] Figure 2B yes Figure 2A The corresponding logic table of the circuit implementation method includes twelve logic states, wherein each IN, INF, OUT1 and OUT2 logic state is specified. In addition, it is also shown Figure 2A The output impedance and operating state of the circuit implementation.

[0039] Figure 3A 3 is a schematic diagram of another embodiment of a multi-output gate driver system 300, wherein the second output terminal OUT2 is capable of sourcing gate current in parallel with OUT1 through a resistor Rg2. In addition, during the off state, the second output terminal OUT2 can be used as an active Miller clamp pin. Of course, the active Miller clamp performance can be reduced by an optional diode in parallel with Rg2. In the gate driver system 300, a diode in parallel with the resistor Rg2 is shown. In addition, as previously described Figure 3A All numbered parts shown in .

[0040] Figure 3B yes Figure 3A The corresponding logic table of the circuit implementation method includes twelve logic states, wherein each IN, INF, OUT1 and OUT2 logic state is specified. In addition, it is also shown Figure 3A The output impedance and operating state (and associated control settings) of a circuit implementation.

[0041] Figures 1A to 3A The implementation of using two comparators to monitor the gate voltage may result in Figure 4 The possible timing diagram 400 is shown, wherein the overall timing diagram 404 and the enlarged timing diagrams 402 and 406 show further operating details of the comparators and optional safety time delays. The gate voltage reaches the corresponding threshold voltage (which may require a time period t TDON or TDOFF ), before sending the decision of any comparator to the logic circuit, wait for the safety delay t dclampH or dclampL Expiration, wherein the logic circuit is used to determine the activation of the second output terminal OUT2.

[0042] The timing diagram 404 shows an overall switching sequence where both outputs (OUT1 and OUT2) are in the off state, only the first output OUT1 is in the on state, both outputs (OUT1 and OUT2) are in the on state, only the first output OUT1 is in the off state, and then both outputs (OUT1 and OUT2) are in the off state again. The example timing diagram 404 assumes that the control setting determines the sequence. The control setting determines which transition of OUT1 and OUT2 must work based on the decision of the comparator or independently of the decision of the comparator.

[0043] Timing diagram 406 shows further details of the turn-on sequence, including the OUT1 and OUT2 waveforms, and the output signal from comparator CP1 (OUT_CP1 and optional delay OUT_CP1_DEL).ON represents the difference between the final gate voltage during the on-state and the trigger threshold of comparator CP1.

[0044] Timing diagram 402 shows further details of the shutdown sequence, including the OUT1 and OUT2 waveforms, and the output signal from comparator CP1 (OUT_CP1 and optional delay OUT_CP1_DEL). OFF represents the difference between the final gate voltage during the off state and the trigger threshold of comparator CP2. Alternatively, it may represent the difference between ground (zero volts) and the trigger threshold of comparator CP2.

[0045] Depending on system-related conditions, the second output OUT2 can be switched according to OUT1 depending on the comparator and depending on an optional additional delay, or can be switched simultaneously with OUT1, resulting in a Figure 4 The example timing diagram 400 shown in FIG.

[0046] In conclusion, Figures 1A to 3B The illustrated multi-output gate driver system embodiment provides improved off-state clamping and on-state clamping of the power device gate voltage. This in turn supports tighter gate control and less sensitivity to parasitic effects. Thus, all inactive outputs (one output in a dual output embodiment or more outputs in a multi-output embodiment) can be used for gate clamping to the positive rail (on state) or the negative rail (off state).

[0047] For a given resistor Rg driving the gate, the rate of change of the drain / collector voltage of a power transistor, especially an IGBT, depends on whether the power transistor is turned on or off and exhibits opposite behavior for increasing collector current. Figure 5 As shown and described in further detail below, during turn-on, the drain / collector dv / dt decreases with higher collector current, while during turn-off, the drain / collector dv / dt increases with higher collector current. For example, graph 500 shows the dv / dt of the collector voltage during turn-on mode 502, and the dv / dt of the collector voltage during turn-off mode 504. Note that in both operating modes, the dv / dt exhibits a region of a high dv / dt operating mode and a region of a low dv / dt operating mode.

[0048] In applications, especially in drive systems where the maximum allowed drain / collector dv / dt is specified, this switching behavior can lead to excessively high drain / collector dv / dt values. Figure 6As shown and will be described in further detail below, such a gate drive circuit is used: it has two independent output terminals, and the two output terminals operate in parallel at high collector current, while only one driver output terminal is used under light load, and the other driver output terminal is held in a tri-state.

[0049] To achieve a more constant drain / collector dv / dt, a reduced gate resistance Rg is selectively used to increase the drain / collector dv / dt at turn-on for higher load currents, while a reduced Rg is selectively used to increase the drain / collector dv / dt at turn-off for reduced load currents.

[0050] Figure 6 A schematic diagram of a multi-output gate driver system 600 is shown, including: a power device 108 having a gate node; a first driver 104 having an input terminal and an output terminal OUT1 coupled to the gate node; a second driver 102 having an input terminal and an output terminal OUT2 coupled to the gate node; and a logic circuit 106 having an input terminal for receiving a control signal (on-off), a first output terminal 112 coupled to the input terminal of the first driver 104, and a second output terminal 110 coupled to the input terminal of the second driver 102.

[0051] By setting the gate resistance Rgf* < Rf at high drain / collector current, where Rgf* = Rg || Rgf, the drain / collector dv / dt can be set to a value very close to the value obtained using the gate resistance Rg at low drain / collector current, thereby maintaining low switching losses over the entire load range while maintaining the dv / dt level for EMI reasons.

[0052] This can be achieved by activating the second gate drive channel, so that the effective gate resistance is Rgf* = Rg || Rgf, as implemented by the gate driver system 600 as shown. However, setting a lower effective gate resistance for both the turn-on and turn-off of the power transistor 108 can only be achieved by enabling the output terminal OUT2 for high drain / collector current. In particular, at turn-off, activating the second gate drive channel OUT2 at high collector current will result in an even higher and thus undesirable drain / collector dv / dt. At high load currents, a lower gate resistance is beneficial for increasing only the maximum value of the dv / dt at the drain / collector during the turn-on of the power transistor 108. Figure 6 Therefore, a control strategy cannot be effectively used in which the second output terminal OUT2 is activated during high collector current operation for both the turn-on and turn-off phases.

[0053]

[0054] To obtain a limited drain / collector d​V / dt, according to an embodiment, the turn-on and turn-off phases are decoupled and processed inversely, with a lower gate resistance for turn-on and a higher gate resistance for turn-off. For example, referring to Figure 8 The low dv / dt operation mode and the high dv / dt operation mode are further described and explained in detail.

[0055] Figure 7 Schematic diagram 700 shows an alternative embodiment of a multi-output gate driver system in which a diode D is connected in series with the second gate resistor Rgf. Figure 6 The same as shown in. Figure 6 Identified and described Figure 7 All other parts shown in .

[0056] Therefore, if Figure 7 As shown, deactivation of the OUT2 sinking capability of the second output terminal during high drain / collector current operation can be achieved by adding a series diode D to the gate resistor Rgf. Including the diode D inhibits current flow into the terminal OUT2 during the off period, but still allows current flow during the on period.

[0057] In further embodiments, each driver 102 and 104 may be independently controlled. However, completely independent control may result in a more complex overall system solution.

[0058] According to an embodiment, the control scheme for the outputs OUT1 and OUT2 in the gate driver IC itself is based on the input control signal. The control scheme for maintaining a constant dv / dt follows Figure 8 During the first on-mode 802, only a single gate resistor and driver are required. During the second on-mode 804, two gate resistors and drivers are required. Conversely, during the first off-mode 806, two gate resistors and drivers are required. During the second off-mode 808, only a single gate resistor and driver are required.

[0059] The technical implementation of the logic circuit 106 is a simple logic which activates the output terminals OUT1 and / or OUT2 based on two control signals (IN and INF). The logic circuit 106 can be implemented using hardware logic gates or in software as required. Fig. 9 An example logic table showing the relationship between the input and output terminals of the logic circuit 106 is shown in Table 900 of FIG. Figure 6 The output impedance and operating state of the circuit implementation.

[0060] During the first logic state, both the IN input and the INF input are low, and the outputs OUT1 and OUT2 are also low. Note that the asterisk indicates an optional logic state for OUT2, which can be left in HiZ (high impedance state) if desired. This optional logic state for OUT2 belongs to the logic states 1, 3, 4, 6, 7, 8, 10, and 11 shown in Table 900. The output impedance of OUT1 and OUT2 is OFF.

[0061] During the second logic state, the IN input transitions from low to high, INF is low, OUT1 transitions from low to high, and the OUT2 output transitions from low to HiZ. The output impedance of OUT1 is Rg, and the output impedance of OUT2 is HiZ.

[0062] During the third logic state, the IN input is low, the INF input transitions from low to high, and the outputs OUT1 and OUT2 return to a logic low state. The output impedance of OUT1 and OUT2 is OFF.

[0063] During the fourth logic state, the IN input is high and the INF input is low. Outputs OUT1 and OUT2 are both high, although OUT2 may remain in a high impedance state as described above. The output impedance of OUT1 and OUT2 is ON.

[0064] During the fifth logic state, the IN input transitions from logic high to logic low, and INF is low. Both outputs OUT1 and OUT2 transition from logic high to logic low. The output impedance of OUT1 and OUT2 is the parallel combination of Rg and Rgf.

[0065] During the sixth logic state, the IN input is high and the INF input transitions from logic low to logic high. The output terminals OUT1 and OUT2 are both high. The output impedance of OUT1 and OUT2 is ON.

[0066] During the seventh logic state, the IN input is low and the INF input is high. The OUT1 output is low and the OUT2 output is low or in a high impedance state. The output impedance of OUT1 and OUT2 is OFF.

[0067] During the eighth logic state, the IN input is low and the INF input transitions from logic high to logic low. The OUT1 output is low and the OUT2 output is low or in a high impedance state. The output impedance of OUT1 and OUT2 is OFF.

[0068] During the ninth logic state, the IN input transitions from logic low to logic high and the INF input is high. Both outputs OUT1 and OUT2 transition from logic low to logic high. The output impedance of OUT1 and OUT2 is the combination of Rg and Rgf.

[0069] During the tenth logic state, all inputs and outputs are at logic high. Alternatively, the OUT2 output may be maintained in a high impedance state. The output impedance of OUT1 and OUT2 is ON.

[0070] During the eleventh logic state, the IN input is high and the INF input transitions from logic high to logic low. Outputs OUT1 and OUT2 are both at logic high. Alternatively, the OUT2 output may remain in a high impedance state. The output impedance of OUT1 and OUT2 is ON.

[0071] During the twelfth logic state, the IN input transitions from logic high to logic low, and the INF input is at logic high. The OUT1 output transitions from logic high to logic low, and the OUT2 output transitions from logic high to high impedance state. The output impedance of OUT1 is OFF, and the output impedance of OUT2 is in high impedance state.

[0072] Fig.10 is corresponding to Fig. 9 1000 of table 900 shown in FIG. 1000 shows the respective signal waveforms corresponding to the IN, INF, OUT1, and OUT2 nodes. The rising edge of the IN waveform occurs at time 1002, and the rising edge of the OUT2 waveform is fully switched at time 1004. The falling edge of the IN waveform occurs at time 1006, and the falling edge of the OUT2 waveform is fully switched at time 1008. In the time interval t DTON and t DTOFF During this time, output OUT2 remains in tri-state (HiZ or high impedance state). During these time intervals, the voltage at OUT2 follows the voltage at the gate of the power switch driven by output OUT1. When OUT2 switches according to OUT1, the rising or falling edges become faster. This switching behavior results in Fig.10 The “tilt” feature of the OUT2 waveform shown in .

[0073] Time delay t DTON ,t DTOFF can be predetermined or programmed in the logic, e.g. Fig.11 As shown, or may depend on a specific voltage level reached at the gate of the power switch, which may be detected by a threshold comparator, such as Figures 1A to 3B or Fig.12 shown.

[0074] For example, in Fig.11 , a schematic diagram 1100 of an alternative embodiment of a multi-output gate driver system includes a delay / time circuit 118 having a first input terminal and a second input terminal coupled to the logic circuit 106, and an output terminal coupled to the second driver 102. In addition, Fig.11 The schematic diagram shown in Figure 6 The schematic diagram shown in and previously described is essentially the same.

[0075] As another example, in Fig.12 1, a schematic diagram 1200 of an alternative embodiment of a multi-output gate driver system includes a first comparator CP1 and a second comparator CP2, each of which includes an input filter and / or an output filter. The positive input terminal of the comparator CP1 is coupled to the output terminal of the first driver 104, and the negative input terminal of the comparator CP1 is connected to the output terminal of the first driver 104 through the threshold voltage V ON The negative input terminal of the comparator CP2 is coupled to the output terminal of the first driver 104, and the positive input terminal of the comparator CP2 is coupled to the output terminal of the second driver 102. The output terminal of the comparator CP1 is coupled to the input terminal of the logic circuit 106. OFF is coupled to the output terminal of the second driver 102, and the output terminal of the comparator CP2 is coupled to the input terminal of the logic circuit 106. In addition, Fig.12 The schematic diagram shown in Figure 6 The schematic diagram shown in and previously described is essentially the same.

[0076] Fig.13 1 shows an embodiment multi-output gate driver system 1300, in which more than two drivers are explicitly shown. For example, drivers 1304, 1302A, 1302B, and 1302C are connected through output terminals OUT1, OUT2, OUT n-1 and OUT n Coupled to gate resistors Rg1, Rg2, Rg n-1 and Rg n The gate resistor is in turn coupled to the gate node of the power device 1308. The selection circuit 1312 selects one of the driver outputs to couple to the inputs of the comparators CP1 and CP2 under the control of the logic circuit 1306. The outputs of the comparators CP1 and CP2 are coupled to the inputs of the logic circuit 1306 through the low pass filter 1305. The logic circuit 1306 receives the "n" bit on-off signal. The operation of the multi-output gate driver system 1300 is similar to that of the reference system 1300 except for the operation of the selection circuit and the explicit presence of more than two drivers. Figures 1A to 3B Description of the embodiment.

[0077] Fig.14Another embodiment multi-output gate driver system 1400 is shown in which more than two drivers are explicitly shown. For example, drivers 1404, 1402A, 1402B, and 1402C are respectively provided through output terminals OUT_ON1, OUT_OFF1, OUT_ON2, OUT_OFF2, OUT_ON n-1 , OUT_OFF n-1 ,OUT_ON n and OUT_OFF n 1, Rgoff1, Rgon2, Rgoff2, Rgon_n-1, Rgoff_n-1, Rgon_n, and Rgoff_n. The gate resistors are in turn coupled to the gate nodes of the power devices 1408. The selection circuit 1412 selects one of the driver outputs to be coupled to the inputs of the comparators CP1 and CP2 under the control of the logic circuit 1406. The outputs of the comparators CP1 and CP2 are coupled to the inputs of the logic circuit 1406 through the low pass filter 1405. The logic circuit 1406 receives the “n” bit on-off signal. The operation of the multi-output gate driver system 1400 is similar to that of the reference system 1400, except for the operation of the selection circuit 1412 and the explicit presence of more than two drivers. Figures 1A to 3B Description of the embodiment.

[0078] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted as limiting. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art upon reference to this specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A multi-output gate driver system, comprising: A power device having a gate node; a first driver having an input terminal and an output terminal coupled to the gate node, for actively turning on and off the power device, wherein a first gate resistor is coupled between the output terminal of the first driver and the gate node of the power device; a second driver having an input terminal and an output terminal coupled to the gate node, wherein a second gate resistor is coupled between the output terminal of the second driver and the gate node of the power device; a first comparator having a first input terminal coupled to the output terminal of the second driver, a second input terminal coupled to a first reference voltage, and an output terminal; a second comparator having a first input terminal coupled to the output terminal of the second driver, a second input terminal coupled to a second reference voltage, and an output terminal; and a logic circuit having a first input terminal for receiving a control signal for turning on and off the power device, a second input terminal coupled to an output terminal of the first comparator and an output terminal of the second comparator, a first output terminal coupled to an input terminal of the first driver, and a second output terminal coupled to an input terminal of the second driver, The signal on the second input terminal of the logic circuit indicates whether the output of the second driver reaches or exceeds the first reference voltage or whether the output of the second driver reaches or falls below the second reference voltage, and the output terminal of the second driver is configured to be clamped to a positive voltage rail or a negative voltage rail accordingly in response to the signal on the second output terminal of the logic circuit.

2. The multi-output gate driver system according to claim 1, wherein: The second driver is configured to be clamped during both an on mode of operation and an off mode of operation.

3. The multi-output gate driver system according to claim 1, wherein: The second driver is configured to be clamped during an on mode of operation and configured to actively switch during an off mode of operation.

4. The multi-output gate driver system according to claim 1, wherein: The second driver is configured to be clamped during an off mode of operation and configured to actively switch during an on mode of operation.

5. The multi-output gate driver system according to claim 1, wherein: The second driver is configured to be clamped or actively switched in response to an additional control signal received by the logic circuit.

6. The multi-output gate driver system according to claim 1, wherein: The first comparator and the second comparator include at least one of an input filter or an output filter.

7. A multi-output gate driver system comprising: A power device having a gate node; a first driver having an input terminal and an output terminal coupled to the gate node, configured to actively turn on and off the power device, wherein the output terminal of the first driver is coupled to the gate node through a first gate resistor; a second driver having an input terminal and an output terminal coupled to the gate node, wherein the output terminal of the second driver is coupled to the gate node through a second gate resistor; and A logic circuit having an input terminal for receiving a control signal, a first output terminal coupled to the input terminal of the first driver, and a second output terminal coupled to the input terminal of the second driver, wherein the logic circuit is configured to excite only the first driver in an initial on-operation mode and is configured to excite the first driver and the second driver in an initial off-operation mode.

8. The multi-output gate driver system according to claim 7, wherein: The first gate resistor and the second gate resistor have different resistance values.

9. The multi-output gate driver system according to claim 7, wherein: The logic circuit is configured to activate one of the first driver and the second driver in a first on-operation mode and to activate both the first driver and the second driver in a second on-operation mode.

10. The multi-output gate driver system according to claim 7, wherein: The logic circuit is configured to activate both the first driver and the second driver in a first shutdown mode of operation and to activate one of the first driver and the second driver in a second shutdown mode of operation.

11. The multi-output gate driver system of claim 7, further comprising a timer circuit coupled between the logic circuit and the second driver. 12 . The multi-output gate driver system of claim 7 , further comprising a first comparator and a second comparator coupled between the output terminals of the first driver and the second driver and the logic circuit.

13. The multi-output gate driver system according to claim 7, wherein: The second driver is configured to be clamped or actively switched in response to an additional control signal received by the logic circuit.

14. A method for operating a multi-output gate driver system, the multi-output gate driver system comprising a first gate driver and a second gate driver, the first gate driver and the second gate driver respectively comprising a first gate driver output and a second gate driver output coupled to a power device, the method comprising: In a first operation mode, turning on the power device using the first gate driver output, sensing a voltage output by the second gate driver to determine whether the voltage output by the second gate driver is greater than a first reference voltage, and clamping the voltage output by the second gate driver to a first clamping voltage; as well as in a second operating mode, turning off the power device using the first gate driver output, sensing a voltage output by the second gate driver to determine whether the voltage output by the second gate driver is less than a second reference voltage, and clamping the voltage output by the second gate driver to a second clamping voltage, The multi-output gate driver system further includes at least one of a first gate resistor coupled between the first gate driver and the power device and a second gate resistor coupled between the second gate driver and the power device.

15. The method according to claim 14, wherein: In the first operating mode, the second gate driver is delayed relative to the first gate driver.

16. The method according to claim 14, wherein: In the second operating mode, the second gate driver is delayed relative to the first gate driver.

17. The method according to claim 14, further comprising: In the first operating mode, the second gate driver output is sensed using a first comparator and a second comparator.

18. The method according to claim 14, further comprising: In the second operating mode, the second gate driver output is sensed using a first comparator and a second comparator.

19. A method for operating a multi-output gate driver system, the multi-output gate driver system comprising a first driver and a second driver, the first driver and the second driver each comprising an output coupled to a power device, the method comprising: energizing only the first driver in an initial switch-on mode of operation; as well as energizing the first driver and the second driver in an initial shutdown mode of operation, The multi-output gate driver system further includes at least one of a first gate resistor coupled between the first driver and the power device and a second gate resistor coupled between the second driver and the power device.

20. The method of claim 19, further comprising energizing one of the first driver and the second driver in a first on mode of operation and energizing both the first driver and the second driver in a second on mode of operation.

21. The method of claim 19, further comprising energizing both the first driver and the second driver in a first off mode of operation and energizing one of the first driver and the second driver in a second off mode of operation.

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