Clock gating systems and devices

Abstract

A clock gating system and device are provided. According to one general aspect, a device may include: a latch circuit configured to transmit a clock signal as an output signal based in part on a state or at least one enable signal. The latch circuit may include: an input stage controlled by a clock signal and one or more enable signals. The latch circuit may include: an output stage configured to generate an output signal. The input stage and the output stage may share a common transistor controlled by the clock signal.

Description

[0001] This application claims priority to provisional patent application serial number 62 / 818,094, entitled “LOW POWER INTEGRATED CLOCK GATED SYSTEM AND METHOD,” filed on March 13, 2019. The subject matter of that earlier filed application is incorporated herein by reference. Technical Field

[0002] The present description relates to clock management and, more particularly, to low power integrated clock gating systems and methods. Background Art

[0003] Clock gating is a popular technique used in many synchronous circuits to reduce dynamic power consumption. Clock gating saves power by adding more logic to the circuit to prune the clock tree. Pruning the clock disables parts of the circuit so that the flip-flops in them do not have to switch states. Switching states consumes power. When no switching is taking place, the switching power consumption becomes zero and only leakage current is incurred.

[0004] In electronics, a flip-flop is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. This circuit can be caused to change state by a signal applied to one or more control inputs, and has one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are the basic building blocks of digital electronic systems used in computers, communications, and many other types of systems. Summary of the invention

[0005] According to one general aspect, a device may include a latch circuit configured to transmit a clock signal as an output signal based in part on a state of at least one enable signal. The latch circuit may include an input stage controlled by the clock signal and one or more enable signals. The latch circuit may include an output stage configured to generate an output signal. The input stage and the output stage may share a common transistor controlled by the clock signal.

[0006] According to another general aspect, an apparatus may include a latch circuit configured to transmit a clock signal as an output signal based in part on a state of at least one enable signal. The latch circuit may include a feedback circuit configured to hold the output signal. The feedback circuit may include an inverter powered by the output signal.

[0007] According to another general aspect, a system may include a clock generator circuit configured to generate a first clock signal. The system may include a clock gater circuit configured to receive the first clock signal and at least one enable signal as inputs and generate a second clock signal. The system may include a logic circuit configured to perform a synchronized logic function at least in part through the second clock signal. The clock gater circuit may include an input stage controlled by the first clock signal and one or more enable signals. The clock gater circuit may include an output stage configured to generate the second clock signal. The input stage and the output stage may share a common transistor controlled by the first clock signal.

[0008] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

[0009] There is provided a system and / or method for clock management, and more particularly a low power integrated clock gating system and method, substantially as shown in at least one of the accompanying drawings and / or substantially as described in conjunction with at least one of the accompanying drawings, as more fully set forth in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of an example embodiment of a system in accordance with the disclosed subject matter.

[0011] Figure 2A , Figure 2B and Figure 2C is a circuit diagram of an example embodiment of a system in accordance with the disclosed subject matter.

[0012] Figure 3 is a circuit diagram of an example embodiment of a system in accordance with the disclosed subject matter.

[0013] Figure 4A , Figure 4B , Figure 4C and Figure 4D is a circuit diagram of an example embodiment of a system in accordance with the disclosed subject matter.

[0014] Figure 5 is a schematic block diagram of an information processing system that may include devices formed according to the principles of the disclosed subject matter.

[0015] Like reference symbols in the various drawings indicate like elements. DETAILED DESCRIPTION

[0016] Hereinafter, various example embodiments will be described more fully with reference to the accompanying drawings showing some example embodiments. However, the subject matter of the present disclosure can be implemented in many different forms and should not be construed as being limited to the example embodiments set forth herein. On the contrary, these example embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the subject matter of the present disclosure to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0017] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intermediate elements or intermediate layers. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, there are no intermediate elements or intermediate layers. The same reference numerals always represent the same element. As used herein, the term "and / or" includes any one of the relevant listed items or any and all combinations of one or more items.

[0018] It will be understood that, although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teaching of the subject matter of the present disclosure, the first element, first component, first region, first layer or first part discussed below may be referred to as the second element, second component, second region, second layer or second part.

[0019] For ease of description, spatially relative terms such as "under," "below," "below," "above," "on," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as "under" or "below" other elements or features will subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "under" may include both above and below orientations. The device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0020] Likewise, for ease of description, electrical terms such as "high," "low," "pull up," "pull down," "1," "0," etc. may be used herein to describe voltage levels or currents relative to other voltage levels or relative to additional elements or features as shown in the accompanying drawings. It will be understood that the electrical relative terms are intended to encompass different reference voltages of the device in use or operation in addition to the voltages or currents depicted in the accompanying drawings. For example, if the device or signal in the accompanying drawings is inverted or uses other reference voltages, currents, or charges, an element described as "high" or "pull up" will subsequently be "low" or "pull down" compared to the new reference voltage or current. Thus, the exemplary term "high" may encompass both relatively low or relatively high voltages or currents. The device may additionally be based on a different reference electrical framework, and the electrical relative descriptors used herein may be interpreted accordingly.

[0021] The terms used herein are only for the purpose of describing specific example embodiments and are not intended to limit the subject matter of the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will also be understood that the terms "comprise" and / or "comprising" when used in this specification indicate the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0022] Example embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized example embodiments (and intermediate structures). As such, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are expected. Therefore, the example embodiments should not be construed as limited to the specific shapes of the regions shown herein, but will include deviations in shape resulting from, for example, manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and / or a gradient of implant concentration at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface where the implantation occurs. Therefore, the regions shown in the drawings are schematic in nature, their shapes are not intended to illustrate the actual shape of a region of the device, and are not intended to limit the scope of the subject matter of the present disclosure.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the subject matter of the present disclosure belongs. It will also be understood that, unless expressly so defined herein, terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0024] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

[0025] Figure 1 is a block diagram of an example embodiment of a system 100 in accordance with the disclosed subject matter. In various embodiments, the system 100 may include a computing device such as a processor, a system on a chip (SoC), a laptop computer, a desktop computer, a workstation, a personal digital assistant, a smart phone, a tablet computer, and other suitable computers or virtual machines or virtual computing devices thereof.

[0026] In the illustrated embodiment, system 100 may include a clock generator circuit 102 configured to generate a clock signal. The clock signal may then be distributed throughout system 100. In various embodiments, this may involve a grid or tree structure.

[0027] In the illustrated embodiment, system 100 may include a plurality of integrated clock gaters (ICGs) (or latch circuits) or clock gater circuits (e.g., circuits 104A, 104B, and 104C). In various embodiments, these ICGs may be configured to stop or block clock signals based on one or more enable signals (not shown).

[0028] In the illustrated embodiment, the system 100 may include one or more logic circuits (e.g., circuits 106A, 106B, and 106C) configured to perform tasks. In various embodiments, these logic circuits may include execution units (e.g., load / store units, arithmetic logic units, floating point units, etc.), function unit blocks (FUBs), combinatorial logic blocks (CLBs), or sub-portions thereof. According to an example embodiment, the logic circuits may perform synchronous logic functions based at least in part on a clock signal output by an integrated clock gater.

[0029] As described above, in various embodiments, the ICGs may be configured to shut down clocks to logic circuits (and thus switches and power consumption). In various embodiments, these ICGs may be integrated into, or may be part of, various integrated circuits.

[0030] In various embodiments, the ICG may also be configured to shape the clock signal and gate the clock signal. Traditionally, the ICG structure uses additional gates in the critical timing path to achieve the desired timing adjustment. As shown in the later figures, in the illustrated embodiment, the ICG does not include additional gates in the critical timing path.

[0031] Figure 2A , Figure 2B and Figure 2C2 is a circuit diagram of an example embodiment of a circuit or system 200 according to the disclosed subject matter. Because a single diagram of different aspects of system 200 may appear too cluttered, Figure 2A , Figure 2B and Figure 2C These aspects are highlighted.In various embodiments, as described above, system 200 may include an integrated clock gater (ICG).

[0032] In various embodiments, the system 200 may be configured to transmit the clock signal CLK 297 as the enable clock signal ECK or the inverted enable clock signal ECKN 295 based on the (inverted) enable signal EN 296. In such an embodiment, when the enable signal EN 296 is active (e.g., low), the CLK signal 297 may be freely transmitted (in inverted form) as ECKN 295. Conversely, when the enable signal EN 296 is inactive (e.g., high), the enable clock ECKN 295 may remain at a stable value (e.g., high). As described above, this may have the effect of powering down any logic circuits that rely on the enable clock ECKN 295 for synchronization.

[0033] In the illustrated embodiment, system 200 may be powered by power rails VDD 299 and VSS 298. In various embodiments, system 200 may utilize complementary metal oxide semiconductor (CMOS) technology, which uses two power supplies: a high voltage (VDD 299) and a low voltage or ground (VSS 298).

[0034] In the illustrated embodiment, circuit 200 may include P-type metal oxide semiconductor (PMOS) transistors 210, 211, 214, 216, 219, 220. Circuit 200 may include N-type metal oxide semiconductor (NMOS) transistors 212, 213, 215, 217, 218, and 221. In various embodiments, MOS transistors may include a source terminal, a drain terminal, and a gate terminal.

[0035] In the illustrated embodiment, transistors 210, 211, 212, and 213 may include input stage 202 (in Figure 2B 298). These transistors may be connected in series between VDD 299 and VSS 298. Transistor 210 may be controlled by its gate terminal or connected to CLK signal 297 via its gate terminal. Transistors 211 and 212 may be controlled by enable signal EN 296. Transistor 213 may be controlled by the output signal or the inverted enable clock 295.

[0036] In the illustrated embodiment, transistors 210, 219, 216, 217, and 218 may comprise output stage 204 (in Figure 2B 299 and VSS 298. Transistors 210 and 219 may be controlled by their gate terminals or connected to CLK signal 297 via their gate terminals. Transistors 216 and 217 may be controlled by feedback node or signal 294. Transistors 219, 217, and 218 may at least partially generate an output signal or an inverted enable clock 295.

[0037] In the illustrated embodiment, transistors 214, 215, 218, 220, and 221 may include feedback circuit 206 (at Figure 2C ). Transistors 214, 215, and 218 may be connected in series between VDD 299 and VSS 298. Similarly, transistors 220 and 221 may be connected in series between the inverted enable clock 295 and VSS 298.

[0038] Transistors 220 and 221 may form an inverter connected between an output signal or inverted enable clock 295 and VSS 298. They may be controlled by a feedback node or signal 294. They may output an inverted feedback signal FBN 294N.

[0039] Transistors 216, 210, 219, 217, and 218 may form a NAND gate connected between VDD 299 and VSS 298. Transistors 216 and 217 may be controlled by feedback node or signal 294. Transistors 210, 219, and 218 may be controlled by CLK signal 297.

[0040] Transistors 216 and 217 may be connected between VDD 299 and transistor 218 controlled by CLK 297. Transistor 214 may be controlled by an output signal or an inverted enable clock 295. Transistor 215 may be controlled by an inverted feedback signal FBN 294N. Transistors 214 and 215 may at least partially generate feedback signal 294.

[0041] In the illustrated embodiment, when the input clock signal CLK 297 is low and the input (inverted) enable signal EN 296 is low, the feedback node 294 is pulled high by PMOS transistors 211 and 210. In addition, whenever CLK 297 is low, PMOS transistors 210 and 219 precharge the ECKN signal 295 high.

[0042] In such an embodiment, when CLK 297 transitions from low to high, NMOS transistors 217 and 218 pull ECKN 295 low if (inverted) enable signal EN 296 was active or low when CLK 297 was high. Transistor 214 holds feedback node FB 294 high, thereby ensuring (via transistors 217 and 218) that ECKN 295 remains low.

[0043] On the contrary, in the illustrated embodiment, if the input enable signal EN 296 is invalid or high, the NMOS transistors 212 and 213 pull the feedback node 294 low. When the clock CLK 297 changes from low to high, since FB 294 is low, the output ECKN 295 is kept high by the PMOS transistor 216. At the same time, transistors 220 and 221 form an inverter using ECKN 295 as a power supply or a high voltage power supply. The output of the inverter is an inverted feedback signal FBN 294N, and when the feedback node FB 294 is low, the inverted feedback signal FBN 294N is high. If the input enable signal EN 296 changes to valid or low when CLK 297 is high, transistors 215 and 218 keep the feedback node FB 294 low and keep ECKN 295 high or invalid.

[0044] In such an embodiment, ECKN 295 is prevented from switching or gated when input enable signal EN 296 is inactive. Conversely, when input enable signal EN 296 is active, ECKN 295 follows CLK 297 (and inverts CLK 297), or CLK 297 (in inverted form) is passed to ECKN 295.

[0045] In such an embodiment, transistor 210 may be shared between input stage 202 and output stage 204. Furthermore, in various embodiments, transistors 210 and 219 may be configured to serve the dual purpose of reducing leakage current in output stage 204 and balancing the rise and fall delays to enable output clock ECKN 295. In various embodiments, PMOS stacks 210 and 219 may be nearly identical to NMOS stacks of 217 and 218.

[0046] In various embodiments, as described above, the inverter formed by transistors 220 and 221 utilizes a voltage supply from ECKN 295. In such embodiments, it is ensured that there are no unnecessary transitions or switches. Since CMOS technology requires a voltage difference to operate, the inverter may not be allowed to switch or may be substantially powered off when ECKN 295 is low (or substantially the same as VSS 298). In such embodiments, the system 200 is configured to not have a complete transition from a high (VDD 299) power rail to a low (VSS 298) power rail when the enable signal EN 296 indicates that the enable clock signal ECKN 295 should be disabled.

[0047] In the illustrated embodiment, the output of the inverter (inverted feedback signal FBN 294N) needs to be high only when EN 296 is active and CLK 297 is high. This means that ECKN 295 will be high and needs to be maintained high. Through FBN 294N and high CLK 297, NMOS transistors 215 and 218 help maintain FB 294 low, which in turn ensures that ECKN 295 is high. This means that power is reduced in both ON mode and OFF mode (EN 296 active and inactive).

[0048] In the illustrated embodiment, the free running or ungated clock CLK 297 may be connected to only three transistors: transistors 210, 219, and 218. In such an embodiment, if the enable signal EN 296 is inactive for an extended period of time, the loading of the CLK 297 network is reduced (compared to conventional designs), which means that the OFF or unenabled power consumption is relatively low. In addition, as described above, when the enable signal EN 296 is inactive for multiple clock CLK 297 transitions, the circuit 200 does not have an internal full rail transition.

[0049] In the illustrated embodiment, note that system 200 employs only a single clock signal CLK 297 as an input. Furthermore, this clock signal CLK 297 has no internal delays. Furthermore, clock signal CLK 297 is directly connected to the gate terminals of transistors 210, 218, and 219. This is in contrast to conventional ICG designs, in which multiple free-running clock signals are accepted as inputs, or the clock signals are internally delayed / inverted to generate control signals for transmission gates or other transistors. As described above, this minimal or reduced use of clock signal CLK 297 represents less capacitance on the clock network, and therefore less power consumption. It is understood that the above are merely some illustrative examples, and the disclosed subject matter is not limited thereto.

[0050] Figure 3is a circuit diagram of an example embodiment of a circuit or system 300 in accordance with the disclosed subject matter. In various embodiments, as described above, system 300 can include an integrated clock gater (ICG).

[0051] Similar to reference Figure 2A As described above, system 300 may be configured to transfer clock signal CLK 297 to enable clock signal ECK 294 based on enable signals E 396 and SE 395 .

[0052] In the illustrated embodiment, system 300 may be powered by power rails VDD 299 and VSS 298. In various embodiments, system 300 may utilize complementary metal oxide semiconductor (CMOS) technology, which uses two power supplies: a high voltage (VDD 299) and a low voltage or ground (VSS 298).

[0053] In the illustrated embodiment, circuit 300 may include P-type metal oxide semiconductor (PMOS) transistors 210, 211, 214, 216, 219, 220. Circuit 300 may include N-type metal oxide semiconductor (NMOS) transistors 212, 213, 215, 217, 218, and 221. In various embodiments, MOS transistors may include a source terminal, a drain terminal, and a gate terminal.

[0054] In the illustrated embodiment, the system 300 may include an output inverter 304. The inverter 304 may be configured to invert the inverted enable clock ECKN 295 into a non-inverted enable clock ECK 294.

[0055] In the illustrated embodiment, the system 300 may be configured to input multiple enable signals. In such an embodiment, if any of the enable signals are valid (or high), the system 300 may pass the free running clock CLK 297 as the enable clock signal 294. In the illustrated embodiment, the system 300 may include an enable circuit 302 that performs an OR or NOR Boolean operation on the enable signals (to produce EN 296). In another embodiment, other logical combinations of multiple enable signals may produce various states or various modes of operation. It is understood that the above is only an illustrative example and the disclosed subject matter is not limited thereto.

[0056] In the illustrated embodiment, the plurality of enable signals may include a first enable signal E 396 configured to turn on / off the clock 297 as part of a power mode or other normal operating mode. In the illustrated embodiment, the plurality of enable signals may include a second enable signal SE 395 configured to turn on / off the clock 297 when the circuit 300 is in a test mode, such as a scan mode. It is understood that the above are merely some illustrative examples and the disclosed subject matter is not limited thereto.

[0057] In various embodiments, system 300 may include one or both of inverter 304 and enabling circuit 302. In addition, it should be understood that one skilled in the art will recognize that the order, grouping, and even number of transistors may be changed to produce similar effects. It should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0058] Figure 4A is a circuit diagram of an example embodiment of a system 400 according to the disclosed subject matter. In various embodiments, the system 400 may include an integrated clock gater (ICG) as described above. Figure 3 As described above, system 400 may be configured to transfer clock signal CLK 297 to enable clock signal ECK 294 based on enable signals E 396 and SE 395 .

[0059] In the illustrated embodiment, the system 400 may be powered by power rails VDD 299 and VSS 298. In the illustrated embodiment, the circuit 400 may include P-type metal oxide semiconductor (PMOS) transistors 210, 211, 214, 216, 219, 220. The circuit 400 may include N-type metal oxide semiconductor (NMOS) transistors 212, 213, 215, 217, 218, and 221. In various embodiments, the MOS transistors may include a source terminal, a drain terminal, and a gate terminal.

[0060] In the illustrated embodiment, transistor 215 may be connected at a drain terminal to a drain terminal of transistor 212. In the illustrated embodiment, transistor 212 may be connected between ground 298 and transistor 213. However, transistor 213 may be connected between transistor 212 and transistor 211.

[0061] As described above, in various embodiments, the location, order, grouping, and even number of transistors may be changed to produce similar effects. It is understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0062] Figure 4Bis a circuit diagram of an example embodiment of a system 401 according to the disclosed subject matter. In various embodiments, the system 401 may include an integrated clock gater (ICG) as described above. Figure 3 As described above, system 401 may be configured to transfer clock signal CLK 297 to enable clock signal ECK 294 based on enable signal EN 496B.

[0063] In the illustrated embodiment, system 401 may be powered by power rails VDD 299 and VSS 298. In the illustrated embodiment, circuit 401 may include P-type metal oxide semiconductor (PMOS) transistors 210, 211, 214, 216, 219, 220. Circuit 401 may include N-type metal oxide semiconductor (NMOS) transistors 212, 213, 215, 217, 218, and 221. In various embodiments, MOS transistors may include source terminals, drain terminals, and gate terminals.

[0064] In the illustrated embodiment, the enable signal 496B may be generated by an enable generator circuit 499. In various embodiments, the enable generator circuit 499 may include a NOR gate as previously shown or similar, and combine multiple enable inputs into a single signal 496B. In another embodiment, other forms of logic (possibly more complex) may be used to generate the enable signal 496B. In another embodiment, the enable signal 496B may be a direct input without the enable generator circuit 499. In some embodiments, no other enable signals other than the enable signal 496B may be used at all.

[0065] In the illustrated embodiment, transistor 210 may not be shared between the input and output stages of system 401. Instead, transistor 219 may be connected to VDD 299 instead of transistor 210. It is understood that the above is merely an illustrative example and the disclosed subject matter is not limited in this regard.

[0066] As described above, in various embodiments, the location, order, grouping, and even number of transistors may be changed to produce similar effects. It is understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0067] Figure 4C is a circuit diagram of an example embodiment of a system 402 according to the disclosed subject matter. In various embodiments, the system 402 may include an integrated clock gater (ICG) as described above. Figure 3 As depicted, system 402 may be configured to transfer clock signal CLK 297 to enable clock signal ECK 294 based on enable signals E 396 and SE 395 .

[0068] In the illustrated embodiment, system 402 may be powered by power rails VDD 299 and VSS 298. In the illustrated embodiment, circuit 402 may include P-type metal oxide semiconductor (PMOS) transistors 210, 211, 214, 216, 219, and 417C. Circuit 402 may include N-type metal oxide semiconductor (NMOS) transistors 212, 213, 215, 218, 221, and 420C. In various embodiments, MOS transistors may include a source terminal, a drain terminal, and a gate terminal.

[0069] In the illustrated embodiment, transistor 420C may be connected between transistors 219 and 221. In such an embodiment, transistor 420C may be controlled using feedback node FB 294 (via a gate terminal).

[0070] In the illustrated embodiment, transistor 417C may be connected between transistors 216 and 218. In such an embodiment, transistor 417C may be controlled using feedback node FB 294 (via a gate terminal).

[0071] In the illustrated embodiment, transistor 210 may not be shared between the input and output stages of system 402. Instead, transistor 219 may be connected to VDD 299 instead of transistor 210. It is understood that the above is merely an illustrative example and the disclosed subject matter is not limited in this regard.

[0072] As described above, in various embodiments, the location, order, grouping, and even number of transistors may be changed to produce similar effects. It is understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0073] Figure 4D is a circuit diagram of an example embodiment of a system 403 according to the disclosed subject matter. In various embodiments, the system 403 may include an integrated clock gater (ICG) as described above. Figure 3 As described above, system 403 may be configured to transfer clock signal CLK 297 to enable clock signal ECK 294 based on enable signals E 396 and SE 395 .

[0074] In the illustrated embodiment, system 403 may be powered by power rails VDD 299 and VSS 298. In the illustrated embodiment, circuit 403 may include P-type metal oxide semiconductor (PMOS) transistors 210, 211, 214, 216, 219, and 420D. Circuit 403 may include N-type metal oxide semiconductor (NMOS) transistors 212, 213, 215, 218, 415D, and 417D. In various embodiments, MOS transistors may include source terminals, drain terminals, and gate terminals.

[0075] In the illustrated embodiment, transistor 420D may be connected to transistors 219 and 215. In such an embodiment, the drain terminal of transistor 420D may be connected to the gate terminal of transistor 215. In such an embodiment, transistor 420D may be controlled using feedback node FB 294 (via the gate terminal).

[0076] In the illustrated embodiment, transistor 415D may be connected between transistors 214 and 215. In such an embodiment, transistor 417D may be controlled by clock signal 297 (via a gate terminal).

[0077] In the illustrated embodiment, transistor 210 may not be shared between the input and output stages of system 403. Instead, transistor 219 may be connected to VDD 299 instead of transistor 210. It is understood that the above is merely an illustrative example and the disclosed subject matter is not limited in this regard.

[0078] As described above, in various embodiments, the location, order, grouping, and even number of transistors may be changed to produce similar effects. It is understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0079] Figure 5 is a schematic block diagram of an information processing system 500 that may include a semiconductor device formed according to the principles of the disclosed subject matter.

[0080] Reference Figure 5 , information processing system 500 may include one or more devices constructed according to the principles of the disclosed subject matter. In another embodiment, information processing system 500 may employ or perform one or more techniques according to the principles of the disclosed subject matter.

[0081] In various embodiments, information handling system 500 may include a computing device (such as a laptop computer, desktop computer, workstation, server, blade server, personal digital assistant, smart phone, tablet computer, and other suitable computers or their virtual machines or virtual computing devices). In various embodiments, information handling system 500 may be used by a user (not shown).

[0082] The information processing system 500 according to the disclosed subject matter may also include a central processing unit (CPU), a logic or processor 510. In some embodiments, the processor 510 may include one or more functional unit blocks (FUBs) or combinatorial logic blocks (CLBs) 515. In such embodiments, the combinatorial logic blocks may include various Boolean logic operations (e.g., NAND, NOR, NOT, XOR), stable logic devices (e.g., flip-flops, latches), other logic devices, or combinations thereof. These combinatorial logic operations may be configured in a simple or complex manner to process input signals to obtain desired results. It is understood that although some illustrative examples of synchronous combinatorial logic operations are described, the disclosed subject matter is not so limited and may include asynchronous operations or a mixture thereof. In one embodiment, the combinatorial logic operation may include a plurality of complementary metal oxide semiconductor (CMOS) transistors. In various embodiments, these CMOS transistors may be arranged in gates that perform logic operations; however, it is understood that other technologies may be used within the scope of the disclosed subject matter and within the scope of the disclosed subject matter.

[0083] The information handling system 500 according to the disclosed subject matter may also include volatile memory 520 (e.g., random access memory (RAM)). The information handling system 500 according to the disclosed subject matter may also include non-volatile memory 530 (e.g., hard drive, optical storage, NAND or flash memory). In some embodiments, the volatile memory 520, the non-volatile memory 530, or a combination or portions thereof may be referred to as a "storage medium". In various embodiments, the volatile memory 520 and / or the non-volatile memory 530 may be configured to store data in a semi-permanent or substantially permanent form.

[0084] In various embodiments, the information handling system 500 may include one or more network interfaces 540, which are configured to allow the information handling system 500 to become part of a communication network and communicate via the communication network. Examples of Wi-Fi protocols may include, but are not limited to, Institute of Electrical and Electronics Engineers (IEEE) 802.11g, IEEE802.11n. Examples of cellular protocols may include, but are not limited to: IEEE 802.16m (also known as Wireless-MAN (Metropolitan Area Network) Advanced), Long Term Evolution (LTE) Advanced, Enhanced Data Rates for GSM (Global System for Mobile Communications) Evolution (EDGE), Evolved High Speed ​​Packet Access (HSPA+). Examples of wired protocols may include, but are not limited to, IEEE 802.3 (also known as Ethernet), Fiber Channel, Power Line Communications (e.g., HomePlug, IEEE 1901). It is understood that the above are only some illustrative examples and the disclosed subject matter is not limited thereto.

[0085] The information processing system 500 according to the disclosed subject matter may also include a user interface unit 550 (e.g., a display adapter, a tactile interface, a human-machine interface device). In various embodiments, the user interface unit 550 may be configured to receive input from a user and / or provide output to a user. Other types of devices may also be used to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and the input from the user may be received in any form (including sound, voice, or tactile input).

[0086] In various embodiments, information handling system 500 may include one or more other devices or hardware components 560 (eg, display or monitor, keyboard, mouse, camera, fingerprint reader, video processor). It is understood that the above are merely some illustrative examples and the disclosed subject matter is not limited thereto.

[0087] The information processing system 500 according to the disclosed subject matter may also include one or more system buses 505. In such an embodiment, the system bus 505 may be configured to communicatively connect the processor 510, the volatile memory 520, the nonvolatile memory 530, the network interface 540, the user interface unit 550, and one or more hardware components 560. Data processed by the processor 510 or data input from the outside of the nonvolatile memory 530 may be stored in the nonvolatile memory 530 or the volatile memory 520.

[0088] In various embodiments, the information handling system 500 may include or execute one or more software components 570. In some embodiments, the software component 570 may include an operating system (OS) and / or an application. In some embodiments, the OS may be configured to provide one or more services to the application, and manage or serve as an intermediary between the application of the information handling system 500 and various hardware components (e.g., processor 510, network interface 540). In such an embodiment, the information handling system 500 may include one or more native applications, one or more native applications may be locally installed (e.g., locally installed in non-volatile memory 530), and configured to be directly executed by the processor 510 and directly interact with the OS. In such an embodiment, the native application may include precompiled machine executable code. In some embodiments, the native application may include a script interpreter (e.g., C shell (csh), AppleScript, AutoHotkey) or a virtual execution machine (VM) (e.g., Java virtual machine, Microsoft common language runtime) configured to convert source code or object code into executable code that is subsequently executed by the processor 510.

[0089] Various packaging technologies can be used to package the semiconductor devices described above. For example, any of the following can be used to package semiconductor devices constructed according to the principles of the disclosed subject matter: package on package (PoP) technology, ball grid array (BGA) technology, chip scale package (CSP) technology, plastic chip carrier with leads (PLCC) technology, plastic dual in-line package (PDIP) technology, waffle die packaging technology, die in wafer form technology, chip on board (COB) technology, ceramic dual in-line package (CERDIP) technology, plastic metric quad flat package (PMQFP) technology, plastic quad flat package (PQFP) technology, small outline package (SOIC) technology, shrink small outline package (SSOP) technology, thin small outline package (TSOP) technology, thin quad flat package (TQFP) technology, system-in-package (SIP) technology, multi-chip package (MCP) technology, wafer-level manufacturing package (WFP) technology, wafer-level processing stacked package (WSP) technology, and other technologies as will be understood by those skilled in the art.

[0090] The method steps may be performed by one or more programmable processors executing a computer program to perform functions by operating on input data and generating output. The method steps may also be performed by, and the apparatus may be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0091] In various embodiments, the computer-readable medium may include instructions that, when executed, cause the device to perform at least a portion of the method steps. In some embodiments, the computer-readable medium may be included in magnetic media, optical media, other media, or a combination thereof (e.g., a CD-ROM, a hard drive, a read-only memory, a flash drive). In such embodiments, the computer-readable medium may be a tangible and non-transitory article of manufacture.

[0092] Although the principles of the disclosed subject matter have been described with reference to example embodiments, it will be clear to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of these disclosed concepts. Therefore, it should be understood that the above embodiments are not restrictive, but merely illustrative. Therefore, the scope of the disclosed concepts will be determined by the broadest permissible interpretation of the claims and their equivalents, and should not be constrained or limited by the foregoing description. Therefore, it should be understood that the appended claims are intended to cover all such modifications and changes that fall within the scope of the embodiments.

Claims

1. A clock gating device, comprising: A latch circuit configured to transmit a clock signal as an output signal based in part on a state of at least one enable signal, wherein the latch circuit comprises: an input stage controlled by a clock signal and the at least one enable signal, and output stage, configured to generate an output signal, and In which the input stage and the output stage share common transistors controlled by a clock signal, The output stage includes a common transistor and a second transistor, both of which are controlled by a clock signal and connected in series to reduce leakage current from the output stage.

2. The clock gating device according to claim 1, wherein: The latch circuit also includes a feedback circuit having an inverter, wherein the inverter is powered by the output signal.

3. The clock gating device according to claim 2, wherein: The output of the inverter is configured to have a high voltage only when the clock signal is at a high voltage and the at least one enable signal is valid.

4. The clock gating device according to claim 2, wherein: The inverter is configured to be powered down based at least in part on the at least one enable signal.

5. The clock gating device according to claim 1, wherein: The output stage includes a pre-charge circuit controlled by a clock signal.

6. The clock gating device according to claim 1, wherein: The latch circuit is configured to not have a complete transition from the high power rail to the low power rail when the at least one enable signal indicates that the output signal should be disabled.

7. The clock gating device according to claim 1, wherein: The at least one enable signal includes a power mode enable signal and a test mode enable signal, and The latch circuit further includes an enable circuit, and the enable circuit is configured to generate a combined enable signal by performing a Boolean OR operation of the power mode enable signal and the test mode enable signal.

8. The clock gating device according to claim 1, wherein: The latch circuit accepts only a single clock signal as input, wherein the clock signal is directly connected to the gate terminal of the latch circuit transistor without inversion.

9. A clock gating device, comprising: A latch circuit configured to transmit a clock signal as an output signal based in part on a state of at least one enable signal, wherein the latch circuit comprises: a feedback circuit configured to maintain the output signal, wherein the feedback circuit includes an inverter powered by the output signal; and An output stage is configured to generate an output signal, wherein the output stage includes a first transistor and a second transistor, both of which are controlled by a clock signal and connected in series to reduce leakage current from the output stage.

10. The clock gating device according to claim 9, wherein: The latch circuit also includes: an input stage controlled by a clock signal and the at least one enable signal, and The input stage and the output stage share a first transistor controlled by a clock signal.

11. The clock gating device according to claim 9, wherein: The output of the inverter is configured to have a first voltage only when the clock signal is at the first voltage and the at least one enable signal is valid.

12. The clock gating device according to claim 9, wherein: The inverter is configured to be powered down based at least in part on the at least one enable signal.

13. The clock gating device according to claim 9, wherein: The latch circuit is configured to not have a complete transition from the high power rail to the low power rail when the at least one enable signal indicates that the output signal should be disabled.

14. The clock gating device according to claim 9, wherein: The at least one enable signal includes a power mode enable signal and a test mode enable signal, and The latch circuit further includes an enable circuit, and the enable circuit is configured to generate a combined enable signal by performing a Boolean OR operation of the power mode enable signal and the test mode enable signal.

15. The clock gating device according to claim 9, wherein: The latch circuit accepts only a single clock signal as input, wherein the clock signal is directly connected to the gate terminal of the latch circuit transistor without inversion.

16. A clock gating system, comprising: a clock generator circuit configured to generate a first clock signal; a clock gater circuit configured to receive as inputs a first clock signal and at least one enable signal and to generate a second clock signal; and a logic circuit configured to perform a synchronized logic function at least in part by a second clock signal; and The clock gate controller circuit includes: an input stage controlled by a first clock signal and the at least one enable signal, and output stage, configured to generate a second clock signal, and wherein the input stage and the output stage share a common transistor controlled by a first clock signal, The output stage includes a common transistor and a second transistor, both of which are controlled by a first clock signal and connected in series to reduce leakage current from the output stage.

17. The clock gating system according to claim 16, wherein: The clock gater circuit also includes a feedback circuit having an inverter, wherein the inverter is powered by the second clock signal.

18. The clock gating system according to claim 16, wherein: The clock gater circuit is configured to not have a complete transition from the high power rail to the low power rail when the at least one enable signal indicates that the second clock signal should be disabled.

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