Method and device for specifying a read voltage offset of a read command

Abstract

In one embodiment, an apparatus includes a memory array and a controller. The controller receives a first read command specifying a read voltage offset profile identifier; identifies a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile including at least one read voltage offset; and performs a first read operation specified by the first read command using at least one read voltage adjusted according to at least one read voltage offset in the read voltage offset profile.

Description

Technical Field

[0001] The present disclosure relates generally to the field of computer development and, more particularly, to memory read processes. Background Art

[0002] A computer system may include one or more central processing units (CPUs) that may be coupled to one or more storage devices. The CPU may include a processor to run software that utilizes the storage devices coupled to the CPU. The software may write data to the storage devices and read data from the storage devices. The data may be stored by the storage devices in a plurality of memory cells (e.g., NAND flash memory cells) of the storage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A block diagram illustrating components of a computer system according to certain embodiments is shown.

[0004] Figure 2 An example portion of a NAND flash memory array is shown in accordance with certain embodiments.

[0005] Figure 3 An example encoding of bits within a NAND flash memory cell is shown in accordance with certain embodiments.

[0006] Figure 4 An exemplary memory device including a memory storing a read voltage offset profile is shown in accordance with certain embodiments.

[0007] Figure 5 An example read command including a read voltage offset profile identifier in an address cycle is shown in accordance with certain embodiments.

[0008] Figure 6 An example read command including a read voltage offset profile identifier in a command cycle is shown in accordance with certain embodiments.

[0009] Figure 7 An example waveform associated with a read command including a read voltage offset profile identifier is shown in accordance with certain embodiments.

[0010] Figure 8 An example flow for performing a read operation based on a read voltage offset profile is shown in accordance with certain embodiments.

[0011] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0012] Although the drawings depict specific computer systems, the concepts of the various embodiments are applicable to any suitable integrated circuits and other logic devices. Examples of devices that can use the teachings of the present disclosure include desktop computer systems, server computer systems, storage systems, handheld devices, tablet computers, other thin laptops, system-on-chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, digital cameras, media players, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include microcontrollers, digital signal processors (DSPs), system-on-chips, network computers (NetPCs), set-top boxes, network hubs, wide area networks (WAN) switches, or any other system that can perform the functions and operations taught below. Various embodiments of the present disclosure can be used in any suitable computing environment, such as personal computing devices, servers, hosts, cloud computing service provider infrastructures, data centers, communication service provider infrastructures (e.g., one or more parts of an evolved packet core network), or other environments containing a group of computing devices.

[0013] Figure 1 A block diagram of components of a computer system 100 according to some embodiments is shown. The system 100 includes a central processing unit (CPU) 102 coupled to an external input / output (I / O) controller 104, a storage device 106, and a system memory device 107. During operation, data may be transferred between the storage device 106 or the system memory device 107 and the CPU 102. In various embodiments, certain data operations (e.g., erase, program, and read operations) involving the storage device 106 or the system memory device 107 may be managed by an operating system or other software applications executed by the processor 108.

[0014] In various embodiments, the memory device 106 may include one or more memory arrays including memory cells that each store one or more data bits. A read operation may include applying one or more read voltages to the array (e.g., to a word line of the array) and sensing the memory cells to determine whether the read voltage activates the cell (e.g., causes the memory cell to conduct). For example, a cell may be activated if the threshold voltage (Vt) of the cell is lower than the read voltage. The Vt of the cell may indicate the value of the one or more bits stored by the cell.

[0015] Over time, after being set to a particular Vt during programming, the Vt of a NAND cell can shift due to inherent charge loss. In order to accurately read the value stored by a memory cell in the array, the read voltage may need to be adjusted to account for the shift in the threshold voltage of the cell. The overhead involved in specifying individual offsets of read voltage levels for read operations can be significant and can negatively impact read performance (and the overhead can increase dramatically as the number of bits stored by the memory cells in the array increases due to the increase in the number of read voltage levels used during read operations).

[0016] In various embodiments, a read voltage offset profile may be stored in association with a memory array. The read voltage offset profile may specify a read voltage offset for each read voltage used in a read operation. For example, the read voltage offset profile may specify a first offset for a first read voltage, a second offset for a second read voltage, and so on. The read voltage offset profile may be associated with a profile identifier.

[0017] In a specific embodiment of the present disclosure, when the read voltage is to be adjusted during a read operation, a read command specifying a profile identifier of a desired read voltage offset profile may be issued to the memory array by the storage device controller 118 (e.g., a NAND controller). The memory array determines the read voltage offset profile associated with the received profile identifier and adjusts the read voltage applied during the read operation as specified by the offset in the profile. In various embodiments, the profile identifier may be specified during an address cycle of a read command or during a command cycle of a read command (e.g., by an opcode). Various embodiments of the present disclosure may significantly reduce the overhead associated with the adjustment of the read voltage. Specific embodiments may also relax the cycles of background data refresh. In some systems, in order to maintain the ability to accurately read data, it may be necessary to refresh significantly aged data (e.g., read and reprogram). The ability to adjust the read voltage without excessive overhead may allow the data to age a little more without a refresh operation while still maintaining the ability to accurately read the data.

[0018] In various embodiments, the storage device 106 includes NAND flash memory (herein, a storage device including NAND flash memory is referred to as a NAND flash memory device). In some embodiments, the storage device 106 can be a solid-state drive; a memory card; a universal serial bus (USB) flash drive; or a memory integrated in, for example, a smartphone, a camera, a media player, or other computing device. In general, storage devices with NAND flash memory are classified according to the number of bits stored in each cell of the memory. For example, each cell in a single-level cell (SLC) memory stores one bit of data, each cell in a multi-level cell (MLC) memory stores two bits of data, each cell in a triple-level cell (TLC) memory stores three bits of data, and each cell in a quad-level cell (QLC) memory stores four bits of data, but some memories can use multiple encoding schemes (e.g., MLC and TLC) on the same array or on different arrays of the same device.

[0019] The storage device 106 may include any number of memories 116, and each memory 116 may include any number of memory devices 122 (e.g., 122A-D). In certain embodiments, the memory device 122 may be or include a semiconductor package having one or more memory chips 123 (e.g., memory chips 123A-D). In the described embodiment, the memory 116 includes the memory devices 122A-D (although specific reference is made here to the memory device 122A, other memory devices may have any suitable characteristics of the memory device 122A) and a memory device controller 126.

[0020] CPU 102 includes a processor 108, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system on a chip (SOC), or other device that executes code (i.e., software instructions). In the described embodiment, processor 108 includes two processing elements (cores 114A and 114B in the described embodiment), which may include asymmetric processing elements or symmetric processing elements. However, the processor may include any number of symmetric or asymmetric processing elements.

[0021] In one embodiment, a processing element refers to hardware or logic that supports a software thread. Examples of hardware processing elements include: thread units, thread slots, threads, processing units, contexts, context units, logical processors, hardware threads, kernels, and / or any other elements that can maintain the state of a processor, such as an operational state or an architectural state. In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with a code, such as a software thread, an operating system, an application, or other code. A physical processor (or processor socket) generally refers to an integrated circuit and may include any number of other processing elements, such as a kernel or a hardware thread.

[0022] A kernel 114 may refer to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated runtime resources. A hardware thread may refer to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to runtime resources. As can be seen, when certain resources are shared and other resources are dedicated to an architectural state, the boundaries between the nomenclature of a hardware thread and a kernel overlap. However, kernels and hardware threads are typically viewed by an operating system as separate logical processors, wherein the operating system is able to schedule operations for each logical processor separately.

[0023] In various embodiments, the processing element may also include one or more arithmetic logic units (ALUs), floating point units (FPUs), caches, instruction pipelines, interrupt handling hardware, registers, or other hardware to facilitate operation of the processing element.

[0024] I / O controller 110 is an integrated I / O controller that includes logic for communicating data between CPU 102 and I / O devices, which may refer to any suitable device capable of transmitting data to and / or receiving data from an electronic system such as CPU 102. For example, I / O devices may include audio / video (A / V) device controllers, such as graphics accelerators or audio controllers; data storage device controllers, such as flash memory devices, magnetic storage disks, or optical storage disk controllers; wireless transceivers; network processors; network interface controllers; or controllers for other input devices (such as displays, printers, mice, keyboards, or scanners); or other suitable devices. In particular embodiments, I / O devices may include storage devices 106 that may be coupled to CPU 102 via I / O controller 110.

[0025] The I / O devices may communicate with the I / O controller 110 of the CPU 102 using any suitable signaling protocol, such as Peripheral Component Interconnect (PCI), PCI Express (PCIe), Universal Serial Bus (USB), Serial Attached SCSI (SAS), Serial ATA (SATA), Fibre Channel (FC), IEEE 802.3, IEEE 802.11, or other current or future signaling protocols. In certain embodiments, the I / O controller 110 and the underlying I / O devices may communicate data and commands according to a logical device interface specification such as Non-Volatile Memory Express (NVMe) (e.g., as described in one or more specifications provided at www.nvmexpress.org / specifications / ) or Advanced Host Controller Interface (AHCI) (e.g., as described by one or more AHCI specifications such as Serial ATAAHCI: http: / / www.intel.com / content / www / us / en / io / serial-ata / serial-ata-ahci-spec-revl-3-l.html, Rev. 1.3.1). In various embodiments, the I / O devices coupled to the I / O controller may be located off-chip (ie, not on the same chip as CPU 102 ) or may be integrated on the same chip as CPU 102 .

[0026] The CPU memory controller 112 is an integrated memory controller that includes logic for controlling the flow of data to and from one or more system memory devices 107. The CPU memory controller 112 may include logic operable to read from, write to, or request other operations from the system memory devices 107. In various embodiments, the CPU memory controller 112 may receive write requests from the kernel 114 and / or the I / O controller 110, and may provide the data specified in these requests to the system memory devices 107 for storage therein. The CPU memory controller 112 may also read data from the system memory devices 107 and provide the read data to the I / O controller 110 or the kernel 114. During operation, the CPU memory controller 112 may issue commands including one or more addresses of the system memory devices 107 in order to read data from or write data to memory (or perform other operations). In some embodiments, the CPU memory controller 112 may be implemented on the same chip as the CPU 102, while in other embodiments, the CPU memory controller 112 may be implemented on a chip different from the CPU 102. I / O controller 110 may perform similar operations for one or more storage devices 106 .

[0027] The CPU 102 may also be coupled to one or more other I / O devices through an external I / O controller 104. In certain embodiments, the external I / O controller 104 may couple a storage device 106 to the CPU 102. The external I / O controller 104 may include logic for managing the flow of data between one or more CPUs 102 and the I / O devices. In certain embodiments, the external I / O controller 104 is located on a motherboard with the CPU 102. The external I / O controller 104 may exchange information with components of the CPU 102 using a point-to-point or other interface.

[0028] The system memory device 107 may store any suitable data, such as data used by the processor 108 to provide the functionality of the computer system 100. For example, data associated with programs executed or files accessed by the kernel 114 may be stored in the system memory device 107. Thus, the system memory device 107 may include system memory that stores data and / or instruction sequences executed or otherwise used by the kernel 114. In various embodiments, the system memory device 107 may store persistent data (e.g., a user's files or instruction sequences) that remains stored even after power is removed from the system memory device 107. The system memory device 107 may be dedicated to a particular CPU 102 or shared with other devices of the computer system 100 (e.g., one or more other processors or other devices).

[0029] In various embodiments, the system memory device 107 may include a memory including any number of memory arrays, memory device controllers, and other supporting logic (not shown). The memory array may include non-volatile memory and / or volatile memory. Non-volatile memory is a storage medium that does not require power to maintain the state of the data stored in the medium. Non-limiting examples of non-volatile memory may include: solid-state memory (e.g., planar or 3D NAND flash memory or NOR flash memory), 3D cross-point memory, memory devices using chalcogenide phase change materials (e.g., chalcogenide glass), byte-addressable non-volatile memory devices, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory (e.g., ferroelectric polymer memory), ferroelectric transistor random access memory (Fe-TRAM), austenite memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), various other types of non-volatile random access memory (RAM), and magnetic memory. In some embodiments, the 3D crosspoint memory may include a transistor-free stackable crosspoint architecture in which memory cells are located at the intersection of word lines and bit lines and can be individually addressed, and in which bit storage is based on changes in body resistance. Volatile memory is a storage medium that requires power to maintain the state of data stored by the medium. Examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). A specific type of DRAM that can be used in the memory array is synchronous dynamic random access memory (SDRAM). In some embodiments, any portion of memory 107 that is a volatile memory may comply with JEDEC standards, including but not limited to double data rate (DDR) standards, such as DDR3, 4 and 5, or low power DDR4 (LPDDR4) and emerging standards.

[0030] Storage device 106 may store any suitable data, such as data used by processor 108 to provide the functionality of computer system 100. For example, data associated with programs executed or files accessed by kernels 114A and 114B may be stored in storage device 106. Thus, in some embodiments, storage device 106 may store data and / or instruction sequences executed or otherwise used by kernels 114A and 114B. In various embodiments, storage device 106 may store persistent data (e.g., a user's files or software application code) that is stored even after power to storage device 106 is removed. Storage device 106 may be dedicated to CPU 102 or shared with other devices of computer system 100 (e.g., another CPU or other device).

[0031] In the described embodiment, the storage device 106 includes a storage device controller 118 and a memory 116, and the memory 116 includes four memory devices 122A-D that are operable to store data, however, the storage device may include any appropriate number of memory devices. The memory device 122A includes a plurality of memory cells, each of which can be used to store one or more bits. The cells of the memory device 122A can be arranged in any appropriate manner, such as in rows (e.g., word lines) and columns (e.g., bit lines), three-dimensional structures, and / or other arrangements. In various embodiments, the cells can be logically grouped into groups, blocks, sub-blocks, planes, word lines, pages, frames, bytes, or other suitable groups. In various embodiments, the memory device 122A includes one or more NAND flash memory arrays.

[0032] The memory device 122A may include any of the volatile or nonvolatile memories listed above or other suitable memories. In a particular embodiment, the memory device 122A includes nonvolatile memory, such as planar or 3D NAND flash memory. In a particular embodiment, the memory device 122A having nonvolatile memory may comply with one or more nonvolatile memory standards published by the Joint Electron Device Engineering Council (JEDEC), such as JESD218, JESD219, JESD220-1, JESD220C, JESD223C, JESD223-1, or other suitable standards (the JEDEC standards referenced herein are available at www.jedec.org). In a particular embodiment, the storage device includes NAND flash memory that complies with one or more portions of the SDRAM memory standard published by JEDEC, such as JESD79F for double data rate (DDR) SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, or JESD79-4A for DDR4 SDRAM (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards, and the communication interface of the storage device that implements such standards may be referred to as a DDR-based interface. For example, the storage device 106 including NAND flash memory may receive a command having a format that complies with a DDR-based standard, and may convert the command into one or more commands compatible with the NAND flash memory of the storage device 106. Similarly, the storage device 106 may format the results of an operation performed on the NAND flash memory into a format that complies with the DDR-based standard before sending the results to the CPU 102.

[0033] In a particular embodiment, the memory device 122 is a semiconductor package. In various embodiments, the semiconductor package may include a housing containing one or more semiconductor dies (also referred to as chips) (e.g., memory chips 123A-D). The package may also include contact pins or leads for connecting to external circuits. However, the package is merely an example form that the memory device 122 may take, and the memory device may be any suitable arrangement of one or more memory arrays and associated logic in any suitable physical arrangement. For example, although a single physical package may include a single memory device 122, multiple memory devices 122 may reside on a single package, or the memory 122 may be distributed over multiple packages.

[0034] The memory 116 may be implemented in one or more different physical media, such as a circuit board, a die, a disk drive, other media, or any combination thereof (or in combination with one or more packages). In a particular embodiment, the memory 116 includes a circuit board coupled to a plurality of memory devices 122, each memory device 122 including a semiconductor package.

[0035] The storage device 106 may include any suitable type of memory, and is not limited to a specific speed, technology, or form factor of the memory in various embodiments. For example, the storage device 106 may be a disk drive (e.g., a solid-state drive), a flash drive, a memory integrated with a computing device (e.g., a memory integrated on a circuit board of a computing device), a memory module (e.g., a dual in-line memory module) that can be inserted into a memory slot, or other types of storage devices. In addition, the computer system 100 may include a variety of different types of storage devices. The storage device 106 may include any suitable interface to communicate with the CPU memory controller 112 or the I / O controller 110 using any suitable communication protocol such as a DDR-based protocol, PCI, PCIe, USB, SAS, SATA, FC, a system management bus (SMBus), or other suitable protocols. The storage device 106 may also include a communication interface to communicate with the CPU memory controller 112 or the I / O controller 110 according to any suitable logical device interface specification (e.g., NVMe, AHCI, or other suitable specifications). In certain embodiments, storage device 106 may include multiple communication interfaces, each of which communicates with CPU memory controller 112 and / or I / O controller 110 using a separate protocol.

[0036] The storage device controller 118 may include logic to receive requests from the CPU 102 (e.g., via the CPU memory controller 112 or the I / O controller 110), so that the request is executed for the memory 116 (or its memory devices and / or memory chips), and the data associated with the request is provided to the CPU 102 (e.g., via the CPU memory controller 112 or the I / O controller 110). The controller 118 may also be used to detect and / or correct errors encountered during memory operations. In one embodiment, the controller 118 also tracks the number of times a particular cell (or logical grouping of cells) has been written to in order to perform wear leveling and / or detect when a cell is approaching an estimated number of times it can be reliably written. When performing wear leveling, the storage device controller 118 may evenly distribute write operations between memory blocks of the memory 116 so that a particular block is not written more than other blocks. In various embodiments, the controller 118 may also monitor various characteristics of the storage device 106, such as temperature or voltage, and report relevant statistics to the CPU 102. The storage device controller 118 may be implemented on the same circuit board or device as the memory 116, or on a different circuit board or device. For example, in some environments, the storage device controller 118 may be a centralized storage controller that manages the storage operations of multiple different memories 116 (each memory 116 may be the same type of memory or a different type of memory) of the computer system 100 (and thus may provide the storage device controller functionality described herein to any memory coupled thereto).

[0037] In various embodiments, the storage device 106 also includes an address translation engine 120. In the depicted embodiment, the address translation engine 120 is shown as part of the storage device controller 118, although in various embodiments, the address translation engine 120 may be separate from and communicatively coupled to the storage device controller 118. In various embodiments, the address translation engine 120 may be integrated on the same chip or package as the storage device controller 118, or on a different chip or package.

[0038] In various embodiments, the address translation engine 120 may include logic for storing and updating a mapping between a logical address space (e.g., an address space visible to a host computing device coupled to the storage device 106) and a physical address space of a memory 116 of the storage device 106 (which may or may not be exposed to the host computing device). The logical address space may expose a plurality of logical data groups that are physically stored on corresponding physical memory groups that are addressable via the physical address space of the storage device 106. A physical address of the physical address space may include any suitable information that identifies a physical memory location of the storage device 106 (e.g., a location within a memory array of the memory 116), such as an identifier of the memory 116 where the physical memory location is located, an identifier of the memory device 122A where the physical memory location is located, one or more pages of the physical memory location, one or more sub-blocks of the physical memory location, one or more word lines of the physical memory location, one or more bit lines of the physical memory location, or other suitable identifiers or encodings.

[0039] In various embodiments, the memory device 106 also includes program control logic 124, which is used alone or in combination with the memory device controller 126 to control a programming sequence performed when data is written to the memory 116, a read sequence performed when data is read from the memory 116, or an erase sequence when data is erased from the memory 116. In various embodiments, the program control logic 124 may provide various voltages (and / or information indicating which voltages should be provided) applied to one or more memory cells, word lines, bit lines, and / or other portions of the memory array during programming, reading, and / or erasing of data, perform error correction, and perform other appropriate functions.

[0040] In various embodiments, program control logic 124 may be integrated on the same chip as storage device controller 118, or on a different chip. In the depicted embodiment, program control logic 124 is shown as part of storage device controller 118, although in various embodiments, all or a portion of program control logic 124 may be separate from and communicatively coupled to storage device controller 118. For example, all or a portion of program control logic 124 may be located on the same package or chip as memory 116 and / or memory devices 122A-D.

[0041] In some embodiments, all or part of the elements of system 100 reside on (or are coupled to) the same circuit board (e.g., motherboard). In various embodiments, there may be any suitable division between the elements. For example, the elements depicted in CPU 102 may be located on a single die (i.e., on-chip) or package, or any element of CPU 102 may be located off-chip or outside the package. Similarly, the elements depicted in storage device 106 may be located on a single chip or multiple chips. In various embodiments, storage device 106 and a host computing device (e.g., CPU 102) may be located on the same circuit board or on the same device, and in other embodiments, storage device 106 and a host computing device may be located on different circuit boards or devices.

[0042] The components of the system 100 may be coupled together in any suitable manner. For example, a bus may couple any components together. The bus may include any known interconnect, such as a multi-point bus, a mesh interconnect, a ring interconnect, a point-to-point interconnect, a serial interconnect, a parallel bus, a synchronous (e.g., cache synchronous) bus, a layered protocol architecture, a differential bus, and a radio transceiver logic (GTL) bus. In various embodiments, the integrated I / O subsystem includes point-to-point multiplexing logic between the various components of the system 100 (e.g., the kernel 114, one or more CPU memory controllers 112, the I / O controller 110, the integrated I / O device, direct memory access (DMA) logic (not shown), etc.). In various embodiments, the components of the computer system 100 may be coupled together via one or more networks, including any number of intermediate network nodes, such as routers, switches, or other computing devices. For example, a host computing device (e.g., CPU 102) and a storage device 106 may be coupled via a network communication.

[0043] Although not shown, the system 100 may use a battery and / or a power outlet connector and associated systems to receive power, a display to output data provided by the CPU 102, or a network interface to enable the CPU 102 to communicate over a network. In various embodiments, the battery, power outlet connector, display, and / or network interface may be communicatively coupled to the CPU 102. Other power sources such as renewable energy sources (e.g., solar or motion-based energy) may be used.

[0044] Figure 2An example portion of a NAND flash memory array 200 is shown in accordance with certain embodiments. In various embodiments, the memory device 122A includes an array 200 of memory cells logically arranged in rows and columns. The memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line), while the memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). In some embodiments, a single access line can be associated with more than one logical row of memory cells, and a single data line can be associated with more than one logical column. The memory cells in the array are capable of being programmed to one of at least two data states (i.e., programming levels).

[0045] The memory array 200 includes, for example, word lines 2020 to 202 N The access lines and bit lines 2040 to 204 M In some embodiments, word lines 202 may be connected to global access lines (eg, global word lines) in a many-to-one relationship.

[0046] The memory array 200 may be arranged into rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column may include a series of memory cells, such as NAND strings 2060 to 2064. M Each NAND string 206 can be connected (e.g., selectively connected) to a common source 216 and can include a plurality of memory cells. For example, NAND string 2060 includes memory cells 2080 to 208 N Memory cell 208 represents a non-volatile memory cell for data storage. Memory cell 208 of each NAND string 206 may be connected in series between a select transistor 210 (eg, a field effect transistor) and a select transistor 212 (eg, a field effect transistor). Select transistor 210 is, for example, select transistors 2100 to 2101. M One of the transistors (eg, each may be a source select transistor, commonly referred to as a select gate source), the select transistor 212 is, for example, a select transistor 2120 to 212 M One of the transistors 2100 to 210 (eg, each transistor may be a drain select transistor, often referred to as a select gate drain). Select transistors 2100 to 210 M can be commonly connected to a select line 214, such as a source select line, and select transistors 2120 to 212 MThe transistors 214 and 215 may be commonly connected to a select line 215, such as a drain select line. In certain embodiments, the drain select line may be coupled to the drain select transistors of the entire sub-block (and each sub-block may have its own drain select line), while the source select line may be coupled to the source select transistors of the entire block (and each block may have its own source select line).

[0047] The source of each select transistor 210 can be connected to the common source 216. The drain of each select transistor 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of the select transistor 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select transistor 210 can be configured to selectively couple the corresponding NAND string 206 to the common source 216. The control gate of each select transistor 210 can be connected to the select line 214.

[0048] The drain of each select transistor 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of the select transistor 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select transistor 212 can be connected to the memory cell of the corresponding NAND string 206. For example, the source of the select transistor 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Thus, each select transistor 212 may be configured to selectively connect a corresponding NAND string 206 to a corresponding bit line 204 . A control gate of each select transistor 212 may be connected to a select line 215 .

[0049] Figure 2 The memory array in may be a quasi-two-dimensional memory array and may have a generally planar structure, for example, where the common source 216, NAND strings 206, and bit lines 204 extend in substantially parallel planes. Alternatively, Figure 2 The memory array in can be a three-dimensional memory array, for example, where the NAND strings 206 can extend substantially perpendicular to a plane containing the common source 216 and a plane containing the bit lines 204 (which can be substantially parallel to the plane containing the common source 216).

[0050] The typical structure of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, a charge trap, etc.) that maintains the data state of the cell (e.g., through a change in threshold voltage) and a control gate 236. In some cases, memory cell 208 may further have a defined source 230 and a defined drain 232. Control gate 236 of memory cell 208 is connected to (and in some cases forms) word line 202.

[0051] A column of memory cells 208 is one or more NAND strings 206 that are selectively connected to a given bit line 204. A row of memory cells 208 is the memory cells that are commonly connected to a given word line 202. A row of memory cells 208 may, but need not, include all of the memory cells 208 that are commonly connected to a given word line 202. The rows of memory cells 208 may generally be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 that is commonly connected to a given word line 202. For example, a row of memory cells 208 may generally include one or more groups of physical pages of memory cells 208. N The memory cells 208 selectively connected to the even bit lines 204 (eg, bit lines 2040, 2042, 2044, etc.) may be a physical page of memory cells 208 (eg, even memory cells), while the memory cells 208 commonly connected to the word lines 202 may be a physical page of memory cells 208 (eg, even memory cells). N And the memory cells 208 selectively connected to the odd bit lines 204 (eg, bit lines 2041, 2043, 2045, etc.) may be another physical page of memory cells 208 (eg, odd memory cells). Figure 2 2043-2045 are not explicitly depicted in the figure, but it is obvious from the figure that the bit line 204 of the array of memory cells 200 can be from the bit line 2040 to the bit line 204. M Numbered consecutively. Other groups of memory cells 208 that are commonly connected to a given word line 202 may also define a physical page of memory cells 208. For some memory devices, all memory cells that are commonly connected to a given word line may be considered a physical page. For a particular memory device, all memory cells of a particular sub-block that are commonly connected to a given word line may be considered a physical page. For example, memory cells coupled to a particular word line in a sub-block may include a first physical page, memory cells coupled to a particular word line in a second sub-block may include a second physical page, and so on. One bit in each memory cell of a physical page may be considered a logical page. Therefore, a single physical page may store multiple logical pages (e.g., a TLC scheme may store three logical pages in a single physical page).

[0052] During sensing (e.g., reading) of the data state of a selected (e.g., target) memory cell, the memory cell is selectively activated in response to a particular voltage level applied to the control gate while establishing a current path from the memory cell to the data line and to the source, thereby allowing current flow, or lack of current, between the data line and the source to indicate whether the memory cell is activated in response to the particular voltage level applied to its control gate. For example, for a selected memory cell 208 of a NAND string 2060 x+i In a sensing operation, a sensing voltage (eg, a read voltage or a verification voltage) may be applied to the memory cell 208. x+iThe control gates of the NAND strings 2060 and 2080 are connected to the control gates of the NAND strings 2060 and 2080. x and 208 x+2 To 208 N 2100 and 2120, a voltage level is applied to the control gates of the select transistors 2100 and 2120 sufficient to activate those transistors. x+i Whether the sensing operation is activated in response to one or more sensing voltages can indicate one or more bits of the data state stored in the memory cell. In various embodiments, each memory cell 208 can be programmed according to SLC, MLC, TLC, QLC or other coding schemes. The threshold voltage (Vt) of each cell represents the data stored in the cell.

[0053] Although various embodiments have been described with respect to a particular type of memory array (e.g., a NAND flash memory array), the teachings of the various embodiments may be equally applicable to any type of memory array (e.g., an AND array, a NOR array, etc.), including those described herein or similar memory arrays.

[0054] Figure 3 An example encoding of bits in a NAND flash memory cell 208 according to a particular embodiment is shown. In the described embodiment, each elliptical area represents a range of threshold voltages corresponding to the value encoded within the cell. For example, in an SLC encoding scheme, a lower threshold voltage corresponds to a bit value of 1 and a higher threshold voltage corresponds to a bit value of 0. As another example, in an MLC encoding scheme, the lowest range of threshold voltages corresponds to "11", the next highest range of threshold voltages corresponds to "01", the next highest range of threshold voltages corresponds to "00", and the highest range of threshold voltages corresponds to "10". Similarly, for a TLC encoding scheme (or other encoding schemes not shown), different ranges of threshold voltages correspond to different values ​​of the bit encoded in each cell.

[0055] A programming level may refer to one of the depicted elliptical areas. In other words, a program level may correspond to one of the bit encodings used in the encoding scheme. Generally speaking, if a cell is to store a value represented by the lowest voltage region, then the cell does not need to be programmed (because in its erased state, it already has a threshold voltage in the lowest voltage region). Therefore, as used herein, the next lowest region (e.g., "01" for an MLC scheme or "011" for a TLC scheme) will be referred to as the first programming level, the next region (e.g., "00" for an MLC scheme or "001" for a TLC scheme) will be referred to as the second programming level, and so on. According to this terminology, the MLC scheme has three programming levels, the TLC scheme has seven programming levels, and the QLC scheme has fifteen programming levels. When data (e.g., one or more pages) is written to the memory 116, multiple cells may be programmed to the first programming level, multiple cells may be programmed to the second programming level, and so on.

[0056] In certain embodiments, cells may be programmed one or more pages (e.g., logical pages) at a time, where the pages are stored in groups of cells (e.g., physical pages) coupled to the same word line. For example, the group of cells being programmed may be identified by a particular word line and a particular sub-block. A group of cells may store one page of data (if the cells are encoded according to an SLC scheme) or multiple pages of data (if the cells are encoded according to an MLC, TLC, QLC, or other multi-level encoding scheme).

[0057] In various embodiments, a cell encoded to store multiple bits may form part of multiple different pages, with each bit of the cell corresponding to a different page. For example, for a cell encoded with two bits (i.e., using an MLC encoding scheme), one bit may correspond to an upper page (UP) and another bit may correspond to a lower page (LP). As another example, for a cell encoded with three bits (i.e., using a TLC encoding scheme), one bit may correspond to LP, one bit may correspond to UP, and another bit may correspond to an extra page (XP). As another example, for a cell encoded with four bits (i.e., using a QLC encoding scheme), one bit may correspond to LP, another bit may correspond to UP, another bit may correspond to XP, and the last bit may correspond to a top page (TP). Each page (e.g., LP, UP, XP, or TP) may include an aggregation of corresponding bits stored by multiple different cells (e.g., physical pages) of a word line. For example, referring to Figure 3 As shown in the encoding, all rightmost bits of multiple cells encoded using the TLC scheme can form LP, all middle bits of the multiple cells can form UP, and all leftmost bits of the multiple cells can form XP.

[0058] Figure 3The various R voltage values ​​shown (e.g., R1, R2, R3, ...) represent read voltages that may be applied to a word line when reading the value of a cell coupled to the word line. When a particular read voltage is applied, the sensing circuit may determine whether the threshold of the cell is greater than or less than the read voltage based on the voltage or current sensed by the sensing circuit via the cell's bit line. Although Figure 3 Not shown in FIG. 1 , a QLC encoding scheme may utilize a similar scheme, where 15 read voltages may be used to resolve the value of 4 bits in each cell, where R1 <R2<R3<...<R15。

[0059] The various program verification voltages depicted (PV1-PV3 in the MLC encoding scheme and PV1-PV7 in the TLC encoding scheme) represent program verification voltages that may be applied to a cell during cell programming (e.g., during a program verification operation) to determine whether the cell's threshold voltage has reached its desired level. For example, in the MLC encoding scheme, if a cell is to be programmed to "01" (i.e., programming level 1), PV1 may be applied to the cell during the verification process, and if the sensing circuit determines that the cell's threshold voltage is greater than PV1, the cell is considered to have passed programming. If the cell's threshold voltage is less than PV1, the cell is considered to have failed programming, and the storage device 106 may attempt to increase the cell's threshold voltage, or allow the cell to fail and may later attempt to correct errors on the cell. As another example, if a cell is programmed to "00" (i.e., programming level 2), PV2 may be applied to the cell during the verification process, and if the sensing circuit determines that the cell's threshold voltage is greater than PV2, the cell is considered to have passed programming. Similarly, if the cell is programmed to "10" (i.e., programming level 3), PV3 may be applied to the cell during the verification process. Any suitable programming verification voltage may be used for any encoding scheme. In a particular embodiment, as shown, the programming verification voltage may be set to a value at or near the beginning of the corresponding threshold voltage range. In various embodiments, there may be a margin between the programming verification voltage and the corresponding read level voltage to allow for a slight threshold voltage drop over time and to improve sensing accuracy. For example, the figure depicts a margin between R1 and PV1, a margin between R2 and PV2, and so on.

[0060] As described above, programming levels can move over time (i.e., the thresholds of cells programmed to a particular programming level can change). Programming levels may also not be consistent across multiple pages of a memory array. Therefore, using the same read voltage for each physical page (or even for the same physical page during different read operations) may not be ideal.

[0061] Various embodiments of the present disclosure allow a read command to specify a read voltage offset profile identifier that specifies a read voltage offset profile to be applied to one or more read operations specified by the read command. A read voltage offset profile may include one or more read voltage offsets that are used to adjust one or more read levels during a read operation. For example, a read voltage offset profile for an SLC memory may include a single read voltage offset, a read voltage offset profile for an MLC memory may include three read voltage offsets, a read voltage offset profile for a TLC memory may include seven read voltage offsets, and a read voltage offset profile for a QLC memory may include 15 read voltage offsets. For example, referring to Figure 3 , the first read voltage offset of the configuration file of the MLC memory can specify the amount by which R1 should be offset, the second read voltage offset of the configuration file can specify the amount by which R2 should be offset, and the third read voltage offset of the configuration file can specify the amount by which R3 should be offset. The read voltage offset can specify a positive amount, a negative amount, or no offset. In a particular embodiment, the read voltage offset is limited to a range. For example, the valid value of the read offset voltage can be between -1270mV and +1270mV. In other embodiments, any suitable range can be used. In a particular embodiment, the read voltage offset is constrained to a specific granularity. For example, the resolution between consecutive read voltage offsets can be 10mV or other suitable values. In various embodiments, the read voltage offset configuration file may include read voltage offsets for only a subset of the read voltages, and unspecified read voltage offsets may be assumed to be zero.

[0062] Figure 4An exemplary memory device including a memory 402 to store a read voltage offset profile according to a particular embodiment is shown. The memory device may include at least one memory chip 123 and at least one controller 126 (in various embodiments, the controller 126 may be located on a different chip from the memory chip 123 or on the same chip as the memory chip 123). In some embodiments, multiple memory chips 123 may share a controller 126. In an alternative embodiment, each memory chip 123 may have a dedicated controller 126. In various embodiments, the memory device 122 may include a controller 126 that interfaces with a storage device controller 118 and a controller on each memory chip 123 that interfaces with the previous controller (in various embodiments, the storage device controller 118 may communicate with the chip-level controller via a device-level controller). In various embodiments, any suitable control logic located on the storage device 106, the memory device 122, and / or the memory chip 123 may be considered a "controller" that performs the operations described herein (therefore, in some embodiments, the logic distributed in different components of the storage device 106 may be considered a single controller). For example, controller 126 may include control logic on memory device 122 located on a chip separate from memory chip 123, control logic located on memory chip 123, or a combination of control logic on memory device 122 located on a chip separate from memory chip 123 and control logic located on memory chip 123.

[0063] The memory device 122 may include at least one memory 402 for storing a read voltage offset profile. The memory 402 may be located on the memory chip 123 or on a different chip of the memory device 122. In certain embodiments, each memory chip 123 and / or memory array includes its own dedicated memory to store a read voltage offset profile. In some embodiments, multiple memory chips 123 and / or arrays within one or more memory chips 123 may share a memory 402.

[0064] The memory 402 may include a plurality of entries 404 (e.g., 404A, 404B, ... 404N), each including a profile identifier 406 and a corresponding set of read voltage offsets 408. The memory 402 may store any suitable number of entries 404. The depicted embodiment shows a profile for an MLC scheme using three read voltages during a read operation. In various embodiments, the memory may be adapted to store any suitable number of read voltage offsets for each profile. The memory 402 may include any suitable type of volatile or non-volatile memory. In various embodiments, the storage device controller 118 may send a command to the memory device 122 that causes one or more profiles to be stored in the memory 402 (in various embodiments, the controller 126 may facilitate this operation).

[0065] The controller 126 may perform any appropriate functions of the memory device 122. In various embodiments, the controller 126 may control programming and reading operations of one or more memory arrays 200 of one or more memory chips 123. The controller 126 may also be used to receive a read command specifying a profile identifier, retrieve a read voltage offset from the memory 402, and adjust the read voltage based on the offset for a read operation. In other embodiments, any other suitable logic of the memory device 122 or the storage device 106 (e.g., a memory chip level controller) may perform any one or more of these functions.

[0066] Figure 5 An example read command including a read voltage offset profile identifier in an address cycle according to a particular embodiment is shown. In the described embodiment, each read command includes a command cycle dedicated to transmitting an opcode, followed by a plurality of address cycles and another command cycle dedicated to transmitting another opcode. In the described embodiment, the opcode in the first command cycle (i.e., 00 represented in hexadecimal (h)) is common among the read commands, and the opcode in the second command cycle (i.e., 30h, 20h, and 31h) is unique to a particular type of read command (e.g., read page, snap read, or cache read). Each read command includes two address cycles dedicated to column addresses, four address cycles dedicated to row addresses, and a single address cycle dedicated to reading a voltage offset profile identifier. In other embodiments, the read command may include any appropriate number of command cycles and address cycles (e.g., the read command may include four address cycles, five address cycles, six address cycles, seven address cycles, eight address cycles, or other appropriate number of address cycles).

[0067] In the described embodiment, the last address cycle immediately before the last command cycle is dedicated to conveying the read voltage offset profile ID. In various embodiments, any suitable address cycle may be dedicated to conveying the read voltage offset profile ID. For example, in a particular embodiment, the first address cycle after the first command cycle may include the read voltage offset profile ID, and the remaining address cycles may include address information for the read command.

[0068] In a particular embodiment, the read command may be sent via a bus that couples the storage device controller 118 to the controller 126 of the memory device 122. In a particular embodiment, the bus may include a set of multi-purpose data lines (e.g., eight or sixteen lines) and one or more control lines that allow the memory device controller 126 to interpret the type of data sent via the multi-purpose data lines during a particular cycle. For example, when the data on the multi-purpose data lines defines a command, the bus may include a command latch enable signal (or other similar signal line) that is asserted during a command cycle. As another example, the bus may include an address latch enable signal (or other similar signal line) that is asserted during an address cycle when the data on the multi-purpose data lines defines an address. In a particular embodiment, the address latch enable signal may also be asserted during an address cycle when the data on the multi-purpose data lines defines a read voltage offset profile ID.

[0069] During an address cycle dedicated to a read voltage offset profile ID, the value on the multipurpose data line of the bus corresponds to the profile to be used for the accompanying read command. In certain embodiments, a certain value (e.g., x00 on the data line when there are eight data lines) may refer to a default profile that causes no read voltage offset to be applied in response to the command (in some embodiments, other read voltage offsets may be applied by the controller 126 independently of the read voltage offset profile). At least some of the remaining possible values ​​on the data line may be mapped to a valid read voltage offset profile ID. In various embodiments, if the number of profiles is greater than the number of profile IDs that can be represented in one address cycle, multiple address cycles may be used to transmit the profile ID.

[0070] In some embodiments, additional address cycles for read commands may be selectively enabled for the memory chip 123 by sending a command from the storage device controller 118 to the memory device controller 126. When additional address cycles are not enabled, a read command may be sent using one less address cycle than a read command sent when additional address cycles are enabled. In certain embodiments where a read command includes an additional address cycle for carrying a read voltage offset profile ID, one or more erase and program commands may also include an additional address cycle that is considered invalid (i.e., ignored by the controller 126).

[0071] Figure 6 An example read command including a read voltage offset profile identifier in a command cycle according to a particular embodiment is shown. In the described embodiment, each read command includes a command cycle dedicated to transmitting an opcode, followed by a plurality of address cycles and another command cycle dedicated to another opcode. In the described embodiment, the opcode in the first command cycle (i.e., 00h) is common between read commands, and each opcode in the second command cycle signals the type of read command (i.e., read page or capture read in the described embodiment) and the read voltage offset profile ID to be used when executing the read command. For example, 30h may specify a read page command without a read voltage offset profile, 3Ah may specify a read page command and a first read voltage offset profile, 3Bh may specify a read page command and a second read voltage offset profile, 20h may specify a capture read command without a read voltage offset profile, 2Ah may specify a capture read command and a first read voltage offset profile, and 2Bh may specify a capture read command and a second read voltage offset profile.

[0072] Each read command includes two command cycles, two address cycles dedicated to column addresses, and four address cycles dedicated to row addresses (in this embodiment, the total number of address cycles in the command is less than 100). Figure 5 In other embodiments, the read command may include any suitable number of command cycles and address cycles, wherein at least one of the command cycles provides an indication of the read voltage offset profile ID. In various embodiments, vendor-specific opcodes (e.g., as defined in the Open NAND Flash Interface Specification, Version 4.0) may be used to implement non-standard read commands (e.g., read commands that use opcodes to specify a read type and a read voltage offset profile ID).

[0073] In the described embodiment, the last command cycle is used to transmit the read voltage offset profile ID. In various embodiments, any suitable command cycle can be used to transmit the read voltage offset profile ID. For example, in a particular embodiment, the first command cycle can transmit the read voltage offset profile ID.

[0074] Figure 7 An example waveform associated with a read command including a read voltage offset profile identifier is shown according to a particular embodiment. The first waveform depicting the RDY signal can be a ready status output provided by the memory device controller 126 to the memory device controller 118 to indicate whether the memory chip 123 is ready to receive a command (e.g., when the RDY signal is low, the memory chip 123 is not available to receive a command, and when RDY goes high, the memory device controller 118 can send a new command). In a particular embodiment, the RDY signal is a bit of the read status output. The second waveform depicts the ARDY signal, which is at a low level when data is sensed from the array of the memory chip 123.

[0075] This sequence describes the performance of one Read Page and two Read Cache Random operations. A Read Cache command (e.g., Read Cache Random or Sequential Read Cache) may allow a page to be read from the cache while another page is simultaneously read from the flash array of the selected memory chip. A Read Page command is issued before the initial Sequential Read Cache or Read Cache Random command in a Read Cache sequence. After one or more Sequential Read Cache or Read Cache Random commands are issued, a Read Cache End command is issued to complete the sequence.

[0076] The described sequence begins when the storage device controller 118 sends a read page command specifying the address of page A and a first read voltage offset profile ID (either in the address cycle or the command cycle of the command) to the controller 126. The controller 126 then causes page A to be read from the memory array with the read voltage adjusted according to the offset specified in the read voltage offset profile corresponding to the ID. Once the read is complete, both the RDY and ARDY signals go high.

[0077] A read cache random command is then sent from the storage device controller 118 to the controller 126. The read cache random command specifies the address of page B and a second read voltage offset profile ID to the controller 126 (in an address cycle or a command cycle of the command). The controller 126 then causes page B to be read out of the memory array using a read voltage adjusted according to an offset specified in a different read voltage offset profile corresponding to the second ID. When page B is sensed, the storage device controller 126 may read page A from the cache. The storage device controller 118 may then send another read cache random command to the controller 126. The read cache random command specifies the address of page C and a third read voltage offset profile ID to the controller 126 (in an address cycle or a command cycle of the command). The newly specified read voltage offset profile does not take effect until the corresponding page is read (i.e., sensing of page B is allowed to continue using the voltage offset specified by profile 2, and the voltage offset specified by profile 3 is not applied to the read voltage until page C is sensed).

[0078] Once the sensing of page B is complete, the storage device controller 118 can then read page B from the cache, while the controller 126 causes page C to be read from the memory array using a read voltage adjusted according to the offset specified in the read voltage offset profile corresponding to the third ID. The controller 126 sends a read cache end command after reading page B, and then reads out page C once the sensing of page C is complete.

[0079] As described above, the cache read may include a sequential read cache command. In some embodiments, the sequential read cache command (or a standard sequential read command that does not utilize the above-described cache order) may include a single command cycle without any address cycles. Such a command may represent a request to read the next page of the array (relative to the page just read by the array). In various embodiments, when such a command is issued, the controller 126 receiving the command may apply a read voltage offset profile for the page previously read by this array. In alternative embodiments, different opcodes for a single command cycle of a sequential read command may specify different read voltage offset profile IDs. For example, a first opcode may represent a sequential read command utilizing a first read voltage offset profile, a second opcode may represent a sequential read command utilizing a second read voltage offset profile, and so on.

[0080] Figure 8 An example flow for performing a read operation based on a read voltage offset profile according to certain embodiments is shown. The flow may be performed by any suitable logic of the system 100, such as the memory device controller 126.

[0081] At 802, a read voltage offset profile configuration command is received. For example, a read voltage offset profile configuration command may be received from a storage device controller 118. In a particular embodiment, the configuration command may specify one or more read voltage offsets of a read voltage offset profile. In one embodiment, the configuration command may specify a read voltage offset for each read voltage applied during a read operation. For example, if an SLC scheme is used, the configuration command may include a single read voltage offset. As another example, if an MLC scheme is used, the configuration command may include three read voltage offsets. As another example, if a TLC scheme is used, the configuration command may include seven read voltage offsets. As yet another example, if a QLC scheme is used, the configuration command may include 15 read voltage offsets.

[0082] In certain embodiments, the configuration command may include a set of read voltage offsets for each of a plurality of read voltage offset profiles. For example, the configuration command may include a first set of voltage offsets for a first read voltage offset profile, a second set of voltage offsets for a second read voltage offset profile, and so on. In other embodiments, multiple configuration commands may be used when multiple read voltage offset profiles are to be established.

[0083] In a particular embodiment, the configuration command may include a read voltage offset profile identifier associated with a set of read voltage offsets for the profile. In another embodiment, the configuration command may include a representation of the read voltage offset profile identifier, rather than the read voltage offset profile identifier itself, such that the controller 126 may determine the read voltage offset profile identifier based on the representation. In yet another embodiment, the configuration command may be constructed in an order that allows the controller 126 to determine an association between a set of read voltage offsets and corresponding read voltage offset profile identifiers. For example, the order of the read voltage offsets included in a configuration command that specifies a plurality of different read voltage offset profiles may indicate the profile identifier to which each set of read voltage offsets belongs.

[0084] In a particular embodiment, before sending one or more configuration commands to the controller 126, the storage device controller 118 or other appropriate logic of the system 100 (e.g., system media management) can perform a series of tests on the memory chip 123 to determine the optimal read voltage offset profile. For example, the storage device controller 118 can direct the programming of each page to the array of the memory chip 123 and read these pages at different times to determine whether the optimal read voltage level has been offset. As part of this test, the storage device controller 118 can monitor the error correction logic to determine whether the various read voltage levels should be adjusted to improve the sensing accuracy. The storage device controller 118 can also direct the adjustment of each read voltage to determine the optimal read voltage offset in a specific situation (e.g., based on the amount of time since the data was refreshed or programmed or based on the location of the data). Based on these tests, the storage device controller 118 can determine one or more read voltage offset profiles to be used during the operation of the memory chip 123.

[0085] At 804, a read voltage offset profile is stored in association with a profile identifier. The read voltage offset profile and / or profile identifier may be stored in any suitable location accessible to the controller 126 or other logic, other logic being associated with the application of the read voltage during the read operation. For example, the read voltage offset profile and / or profile identifier is stored in a memory of the memory chip 123, in a memory of the controller 126, or in other memory of the memory device 122. In a particular embodiment, the read voltage offset profile and / or profile identifier is stored in a memory that can be accessed relatively quickly, such as an SRAM. In a particular embodiment, the profile identifier is not explicitly stored, but is inferred based on the location of the read voltage offset profile in the memory. For example, a read voltage offset profile stored in a first storage element of the memory may be associated with a first profile identifier, a read voltage offset profile stored in an adjacent storage element of the memory may be associated with a second profile identifier, and so on. In one embodiment, the read voltage offset profile and its corresponding profile identifier may be stored in a lookup table.

[0086] In particular embodiments, once the storage device controller 118 generates one or more read voltage offset profiles based on the above-described testing, the storage device controller 118 may send one or more configuration commands to cause the controller 126 to store the read voltage offset profiles in association with respective read voltage offset profile identifiers.

[0087] At 806, a read command is received. At 808, it is determined whether the read command includes a read voltage offset profile identifier. In certain embodiments, the read command may specify data to be read as well as a read voltage offset profile identifier. In various examples, the read voltage offset profile identifier may include or be inferred from a value contained within an address period of the read command or a command period of the read command.

[0088] If the read command does not include a read voltage offset profile identifier, the read command is executed without applying the read voltage offset profile at 810. In some embodiments, the read command may also be executed without applying the read voltage offset profile if the read command specifies a default voltage offset profile identifier.

[0089] If the read command includes a read voltage offset profile identifier, the controller 126 or other suitable logic accesses one or more read voltage offsets in a read voltage offset profile associated with the identifier at 812. A read operation is performed using voltage levels adjusted based on the read voltage offsets in the read voltage offset profile at 814. For example, a first read voltage may be adjusted by a first read voltage offset specified by the profile, a second read voltage may be adjusted by a second read voltage offset specified by the profile, and so on.

[0090] Figure 5-8 The processes described in the examples only represent operations that may occur in a particular embodiment. In other embodiments, additional operations may be performed in the processes (e.g., various memory cells that may form an array). Various embodiments of the present disclosure contemplate any suitable signaling mechanism for implementing the functions described herein. Figure 5-8 Some operations shown in the embodiments may be repeated, combined, modified or deleted where appropriate. In addition, the operations may be performed in any suitable order without departing from the scope of the specific embodiments.

[0091] In certain embodiments, the storage device controller 118 or other suitable logic of the system 100 may determine a read voltage offset profile for a read command based on any suitable information (e.g., the amount of time that has passed since the data to be read was programmed or refreshed, the location of the data to be read, or other suitable factors). For example, the storage device controller 118 may receive a data request from a host (e.g., the CPU 102), convert the request into one or more read commands and an associated read voltage offset profile identifier, and then transmit the one or more read commands to the controller 126.

[0092] Any suitable type of read operation may utilize a read voltage offset profile (wherein a read voltage offset profile identifier may be specified within a command cycle or an address cycle of a corresponding command or related commands). For example, the storage device 106 may support any one or more of the following read commands: a read page command (performing a random read of a data page), a read multi-plane command (described below), a read cache random command (described above), a read cache sequential command (described above), a capture read (performing a random read of a portion of a data page), a corrective read (described below), and a softbit read (described below).

[0093] A multi-plane read operation can specify the location of data to be read from multiple different planes simultaneously (e.g., data located at a page address of a first plane is read simultaneously with data located at a page address of a second plane). For example, a multi-plane read command can specify a common page address of the data to be read (although the column address and / or block address of each set of data to be read from each plane may be different) and how many / which planes to read from. In a particular embodiment, the multi-plane read command can specify a single read voltage offset profile identifier for each page read from each plane. In a particular embodiment, the same read voltage offset profile is used because the multi-plane read operation utilizes a single word line driver to apply the read voltage for the multiple reads performed.

[0094] The correction read may include an operation in which the programming state of one or more word lines adjacent to the word line of the data to be read is checked to determine whether one or more read voltage offsets should be applied during the read operation to correct for threshold voltage disturbance caused by programming of the adjacent word lines. When the correction read command specifies a read voltage offset profile identifier, a read voltage offset in a corresponding read voltage offset profile may be added to any read voltage offset to be applied based on the programming state of the adjacent word lines.

[0095] The soft bit read command may cause a first read operation to be performed at a default read voltage, and one or more read operations to be performed at each read voltage that is offset by a specific amount from the default read voltage. For example, a first read operation may be performed at the default read voltage, a second read operation may be performed using a read voltage that is .1v less than the default read voltage, and a third read operation may be performed using a read voltage that is .1v greater than the default read voltage. The results of the read operations may be obtained and analyzed by the storage device controller 118 to determine which sensing operation is most accurate, and these results may be returned to the requesting entity (e.g., the CPU 102). When the soft bit read command specifies a read voltage offset profile identifier, the read voltage offset in the corresponding read voltage offset profile may be added to the read voltage typically in the soft bit read command for various read operations.

[0096] As described above for soft bit read commands and correction read commands, in a particular embodiment, a read voltage adjustment based on a read voltage offset profile can be accumulated with other read voltage adjustments implemented by a storage device. A particular read voltage adjustment process implemented by a storage device is a moving read reference (MRR) operation. In a moving read reference operation, a read voltage offset can be specified for one or more read voltages. This moving read reference operation can use any appropriate granularity (e.g., block) of a memory array to adjust one or more read voltages (e.g., the adjusted read voltage can be applied to each word line of the block). During any suitable read operation, the read voltage adjustment specified by the MRR operation can be used. The read voltage offset for a read command specified by a read voltage offset profile can be accumulated with the read voltage adjustment specified by the MRR operation. In a particular embodiment, the range and resolution of the read voltage offset specified by the MRR operation can be the same as the range and resolution of the read voltage offset of the read voltage offset profile.

[0097] Another read voltage adjustment process implemented by the memory device is a channel calibration process (sometimes referred to as automatic read calibration). During the channel calibration process, the memory chip 123 calibrates a portion of its memory (e.g., a page) and stores an optimal read voltage offset based on the calibration. The stored read voltage offset can then be used for read operations involving the calibrated portion of the memory. The read voltage offset for a read command specified by the read voltage offset profile can be accumulated with the read voltage offset determined during the channel calibration process.

[0098] A design can go through different stages, from creation to simulation to manufacturing. The data representing the design can represent the design in a variety of ways. First, as useful in simulation, a hardware description language (HDL) or another functional description language can be used to represent the hardware. In addition, a circuit level model with logic and / or transistor gates can be generated at certain stages of the design process. In addition, at some stage, most designs have reached the data level representing the physical arrangement of various devices in the hardware model. In the case of using traditional semiconductor manufacturing technology, the data representing the hardware model can be data that specifies the presence or absence of various features on different mask layers of masks used to produce integrated circuits. In some embodiments, such data can be stored in a database file format (e.g., Graphic Data System II (GDS II), Open Artwork System Interchange Standard (OASIS) or similar formats).

[0099] In some embodiments, software-based hardware models, HDL and other functional description language objects may include register transfer language (RTL) files and other examples. Such objects may be machine-parseable so that a design tool may accept an HDL object (or model), parse the HDL object to obtain the properties of the hardware, and determine the physical circuit and / or on-chip layout from the object. The output of the design tool may be used to manufacture a physical device. For example, a design tool may determine the configuration of various hardware and / or firmware elements from an HDL object, such as bus width, registers (including size and type), memory blocks, physical link paths, structural topology, and other properties to be implemented in order to implement a system modeled in an HDL object. Design tools may include tools for determining the topology and structural configuration of systems on a chip (SoC) and other hardware devices. In some cases, HDL objects may be used as the basis for developing models and design files, which may be used by manufacturing equipment to manufacture the described hardware. In fact, the HDL object itself may be provided as input to the manufacturing system software to cause the described hardware.

[0100] In any representation of the design, data may be stored in any form of machine-readable medium. Memory or magnetic storage or optical storage (e.g., optical disks) may be machine-readable media for storing information transmitted via light or radio waves modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying a code or design is transmitted, a copy, buffering, or retransmission of the electrical signal is performed to some extent, making a new copy. Thus, a communications provider or network provider may store, at least temporarily, an article, such as information encoded into a carrier wave, on a tangible, machine-readable medium that embodies the techniques of embodiments of the present disclosure.

[0101] In various embodiments, a medium storing a representation of a design may be provided to a manufacturing system (e.g., a semiconductor manufacturing system capable of manufacturing integrated circuits and / or related components). The design representation may instruct the system to manufacture a device capable of performing any combination of the functions described above. For example, the design representation may instruct the system as to which components are to be manufactured, how the components should be coupled together, where the components should be placed on the device, and / or other appropriate specifications regarding the device to be manufactured.

[0102] As used herein, a module refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware associated with a non-transitory medium, such as a microcontroller, which stores code suitable for execution by the microcontroller. Therefore, in one embodiment, a reference to a module refers to hardware that is specifically configured to identify and / or run code to be stored on a non-transitory medium. In addition, in another embodiment, the use of a module refers to a non-transitory medium including a code that is specifically suitable for being run by a microcontroller to perform a predetermined operation. And it can be inferred that in yet another embodiment, the term module (in this example) may refer to a combination of a microcontroller and a non-transitory medium. Typically, the boundaries of modules described as independent typically vary and may overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

[0103] Logic may be used to implement any of the described processes or functions of various components, such as CPU 102, external I / O controller 104, processor 108, cores 114A and 114B, I / O controller 110, CPU memory controller 112, storage device 106, system memory device 107, memory 116, memory devices 122A-D, memory chips 123, controller 126, storage device controller 118, address translation engine 120, program control logic 124, memory array 200, memory 402, subcomponents thereof, or other entities or components described herein. "Logic" may refer to hardware, firmware, software, and / or a combination of each to perform one or more functions. In various embodiments, logic may include a microprocessor or other processing element operable to execute software instructions, discrete logic such as an application specific integrated circuit (ASIC), a programmable logic device (such as a field programmable gate array (FPGA), a storage device containing instructions, a combination of logic devices (e.g., as found on a printed circuit board), or other suitable hardware and / or software. Logic may include one or more gates or other circuit components. In some embodiments, logic may also be fully embodied as software. Software may be embodied as a software package, code, instructions, instruction sets, and / or data recorded on a non-transitory computer-readable storage medium. Firmware may be embodied as code, instructions, instruction sets, and / or data that is hard-coded (e.g., non-volatile) on a storage device.

[0104] In one embodiment, the use of the phrase "to" or "configured to" refers to arranging, assembling, manufacturing, offering for sale, importing and / or designing a device, hardware, logic or element to perform a specified or determined task. In this example, if the non-operating device or its element is designed, coupled and / or interconnected to perform the specified task, the non-operating device or its element is still "configured to" perform the specified task. As a purely illustrative example, a logic gate can provide a 0 or 1 during operation. However, a logic gate that is "configured to" provide an enable signal to a clock does not include every possible logic gate that can provide a 1 or 0. Instead, the logic gate is coupled in a certain way that a 1 or 0 output is to enable the clock during operation. Note again that the use of the term "configured to" does not require operation, but rather focuses on the potential state of the device, hardware and / or element, where in the potential state, the device, hardware and / or element is designed to perform a specific task when the device, hardware and / or element is operated.

[0105] Furthermore, in one embodiment, the phrases "capable / capable" and / or "operable" refer to a device, logic, hardware, and / or element designed in such a manner so as to be able to achieve the use of the device, logic, hardware, and / or element in a specified manner. As described above, in one embodiment, the use of "to", "capable", or "operable" refers to a potential state of a device, logic, hardware, and / or element, wherein the device, logic, hardware, and / or element is not operating, but is designed in such a manner that the use of the device can be achieved in a specified manner.

[0106] The value used herein includes any known representation of a number, state, logic state or binary logic state. Generally, the use of logic level, logic value or logical value is also referred to as 1 and 0, which simply represent binary logic states. For example, 1 indicates a high logic level, and 0 indicates a low logic level. In one embodiment, a storage unit such as a transistor or a flash memory cell can maintain a single logic value or multiple logic values. However, other representations of values ​​in a computer system have been used. For example, the decimal number 10 can also be represented as a binary value 1010 and a hexadecimal letter A. Therefore, a value includes any representation of information that can be stored in a computer system.

[0107] In addition, a state may be represented by a value or a portion of a value. For example, a first value (e.g., a logical 1) may represent a default state or an initial state, while a second value (e.g., a logical zero) may represent a non-default state. In addition, in one embodiment, the terms reset and set refer to a default value or state and an updated value or state, respectively. For example, a default value may include a high logic value, i.e., reset, while an updated value may include a low logic value, i.e., set. Note that any combination of values ​​may be used to represent any number of states.

[0108] Embodiments of the above methods, hardware, software, firmware, or code sets may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium that can be executed by a processing element. Non-transitory machine-accessible / readable media include any mechanism that provides (i.e., stores and / or transmits) information in a form readable by a machine (e.g., a computer or electronic system). For example, non-transitory machine-accessible media include random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage media; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for storing information received from temporary (propagating) signals (e.g., carrier waves, infrared signals, digital signals), etc., which are distinguished from non-transitory media that receive information.

[0109] Instructions for programming logic to perform embodiments of the present disclosure may be stored in a memory in the system, such as a DRAM, cache, flash memory, or other storage device. In addition, instructions may be distributed via a network or by other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to a floppy disk, an optical disk, an optical disc, a read-only memory (CD-ROM) and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an erasable programmable medium read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic card or an optical card, a flash memory, or a tangible machine-readable storage device for transmitting information via an electronic, optical, acoustic, or other form of propagation signal (e.g., a carrier wave, an infrared signal, a digital signal, etc.). Therefore, a computer-readable medium includes any type of tangible machine-readable medium suitable for storing or sending electronic instructions or information in a form readable by a machine (e.g., a computer).

[0110] In at least one embodiment, an apparatus includes: a memory array; and a controller that receives a first read command specifying a read voltage offset profile identifier; identifies a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile including at least one read voltage offset; and performs a first read operation specified by the first read command using at least one read voltage adjusted according to at least one read voltage offset in the read voltage offset profile.

[0111] In one embodiment, a read voltage offset profile identifier is specified in an address cycle of a read command. In one embodiment, a controller receives a second read command that specifies a default read voltage offset profile identifier in an address cycle of a read command; and determines that at least one read voltage is not adjusted based on the default read voltage offset profile identifier for a second read operation. In one embodiment, the read voltage offset profile identifier is specified in a last address cycle of a read command. In one embodiment, the read voltage offset profile identifier is specified in a command cycle of a first read command. In one embodiment, the read voltage offset profile identifier is specified in an opcode sent during a last command cycle of the first read command. In one embodiment, the read voltage offset profile identifier is specified in an opcode sent during a first command cycle of the first read command. In one embodiment, the controller further receives a configuration command that specifies at least one read offset voltage and a read voltage offset profile identifier; and stores at least one read offset voltage in association with the read voltage offset profile identifier in a memory. In one embodiment, the device further includes a second controller that selects the read voltage offset profile identifier from a plurality of read voltage offset profile identifiers based on the age of the data for which the read command is intended. In one embodiment, the read command is a multi-plane read command, and the at least one adjusted read voltage is applied to read data from each plane of a plurality of planes specified in the multi-plane read command.

[0112] In at least one embodiment, a method includes receiving a first read command specifying a read voltage offset profile identifier; identifying a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile including at least one read voltage offset; and performing a first read operation specified by the first read command using at least one adjusted read voltage adjusted according to at least one read voltage offset of the read voltage offset profile.

[0113] In one embodiment, the method further includes specifying a read voltage offset profile identifier in an address cycle of a read command. In one embodiment, the method further includes receiving a second read command that specifies a default read voltage offset profile identifier in an address cycle of the read command; and determining not to adjust at least one read voltage based on the default read voltage offset profile identifier for the second read operation. In one embodiment, the method further includes specifying a read voltage offset profile identifier in a last address cycle of the read command. In one embodiment, the method further includes specifying a read voltage offset profile identifier in a command cycle of a first read command. In one embodiment, the method further includes specifying the read voltage offset profile identifier in an opcode sent during a last command cycle of the first read command. In one embodiment, the method further includes specifying the read voltage offset profile identifier in an opcode sent during a first command cycle of the first read command. In one embodiment, the method further includes receiving a configuration command that specifies at least one read offset voltage and a read voltage offset profile identifier; and storing at least one read offset voltage in association with the read voltage offset profile identifier in a memory. In one embodiment, the method further includes selecting a read voltage offset profile identifier from a plurality of read voltage offset profile identifiers based on the age of the data for which the read command is intended. In one embodiment, the read command is a multi-plane read command, and the at least one adjusted read voltage is applied to read data from each plane of a plurality of planes specified in the multi-plane read command.

[0114] In at least one embodiment, a non-transitory machine-readable storage medium has instructions stored thereon that, when executed by a machine, cause the machine to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile including at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to at least one read voltage offset of the read voltage offset profile.

[0115] In one embodiment, the instructions, when executed, cause the machine to specify a read voltage offset profile identifier in an address cycle of a read command. In one embodiment, the instructions, when executed, cause the machine to specify a read voltage offset profile identifier in a command cycle of a first read command. In one embodiment, the instructions, when executed, cause the machine to receive a configuration command specifying at least one read offset voltage and a read voltage offset profile identifier; and at least one read offset voltage stored in memory in association with the read voltage offset profile identifier. In one embodiment, the instructions, when executed, cause the machine to select a read voltage offset profile identifier from a plurality of read voltage offset profile identifiers based on the age of data for which the read command is intended.

[0116] In at least one embodiment, a system includes a memory device including a memory array and a first controller; and a second controller configured to send a configuration command to the first controller, the configuration command specifying at least one read offset voltage and a read voltage offset profile identifier; and send a read command to the first controller, the read command specifying the read voltage offset profile identifier and an address of the memory array.

[0117] In one embodiment, the second controller receives data specified by an address of the memory array, i.e., data read by the first controller according to at least one read offset voltage. In one embodiment, the read command specifies a read voltage offset profile identifier in a command cycle or an address cycle of the read command. In one embodiment, the system further includes a processor that sends a read request to the memory device, and wherein the second controller sends the read command in response to receiving the read request. In one embodiment, the system further includes a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.

[0118] In at least one embodiment, a system includes a module for receiving a first read command specifying a read voltage offset profile identifier; a module for identifying a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile including at least one read voltage offset; and a module for performing a first read operation specified by the first read command using at least one read voltage adjusted according to at least one read voltage offset in the read voltage offset profile.

[0119] In one embodiment, the system further comprises means for specifying a read voltage offset profile identifier in an address cycle of a read command. In one embodiment, the system further comprises means for specifying a read voltage offset profile identifier in a command cycle of a first read command. In one embodiment, the system further comprises means for receiving a configuration command specifying at least one read offset voltage and a read voltage offset profile identifier; and means for storing at least one read offset voltage in association with the read voltage offset profile identifier in a memory. In one embodiment, the system further comprises means for selecting a read voltage offset profile identifier from a plurality of read voltage offset profile identifiers based on the age of the data for which the read command is intended.

[0120] In this specification, reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places in this specification do not necessarily all refer to the same embodiment. In addition, the particular features, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.

[0121] In the foregoing specification, a specific description has been given with reference to specific exemplary embodiments. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader disclosed spirit and scope as described in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive. Furthermore, the use of the above embodiments and other exemplary language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments, as well as potentially the same embodiment.

Claims

1. A device comprising: Memory array; and A controller for: receiving a first read command specifying a read voltage offset profile identifier; identifying a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; as well as A first read operation specified by the first read command is performed using at least one read voltage adjusted according to the at least one read voltage offset in the read voltage offset profile.

2. The apparatus of claim 1, wherein the read voltage offset profile identifier is specified in an address cycle of the read command.

3. The device according to any one of claims 1-2, wherein the controller: receiving a second read command specifying a default read voltage offset profile identifier in an address cycle of the read command; and Based on the default read voltage offset profile identifier, it is determined not to adjust the at least one read voltage for a second read operation.

4. The apparatus of any one of claims 1-3, wherein the read voltage offset profile identifier is specified in a last address cycle of the read command.

5. The apparatus of any one of claims 1-4, wherein the read voltage offset profile identifier is specified in a command cycle of the first read command.

6. The apparatus of any one of claims 1-5, wherein the read voltage offset profile identifier is specified in an opcode sent during a last command cycle of the first read command.

7. The apparatus of any one of claims 1-6, wherein the read voltage offset profile identifier is specified in an opcode sent during a first command cycle of the first read command.

8. The device according to any one of claims 1 to 7, wherein the controller further comprises: receiving a configuration command specifying the at least one read offset voltage and the read voltage offset profile identifier; and The at least one read offset voltage is stored in a memory in association with the read voltage offset profile identifier.

9. The apparatus according to any one of claims 1-8, further comprising a second controller for selecting the read voltage offset profile identifier from a plurality of read voltage offset profile identifiers based on the age of data targeted by the read command.

10. The apparatus of any one of claims 1-9, wherein the read command is a multi-plane read command, and at least one adjusted read voltage is applied to read data from each of a plurality of planes specified in the multi-plane read command.

11. A method comprising: receiving a first read command specifying a read voltage offset profile identifier; identifying a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; as well as A first read operation specified by the first read command is performed using at least one read voltage adjusted according to the at least one read voltage offset in the read voltage offset profile. 12 . The method of claim 11 , further comprising specifying the read voltage offset profile identifier in an address cycle of the read command.

13. The method according to any one of claims 11-12, further comprising: receiving a second read command specifying a default read voltage offset profile identifier in an address cycle of the read command; as well as A determination is made based on the default read voltage offset profile identifier not to adjust the at least one read voltage for a second read operation.

14. The method of any one of claims 11-13, further comprising specifying the read voltage offset profile identifier in a last address cycle of the read command.

15. The method of any one of claims 11-14, further comprising specifying the read voltage offset profile identifier in a command cycle of the first read command.

16. The method of any one of claims 11-15, further comprising specifying the read voltage offset profile identifier in an opcode sent during a last command cycle of the first read command.

17. The method of any of claims 11-16, further comprising specifying the read voltage offset profile identifier in an opcode sent during a first command cycle of the first read command.

18. The method according to any one of claims 11 to 17, further comprising: receiving a configuration command specifying the at least one read offset voltage and the read voltage offset profile identifier; as well as The at least one read offset voltage is stored in a memory in association with the read voltage offset profile identifier.

19. The method of any one of claims 11-18, further comprising selecting the read voltage offset profile identifier from a plurality of read voltage offset profile identifiers based on an age of data targeted by the read command.

20. The method of any one of claims 11-19, wherein the read command is a multi-plane read command, and at least one adjusted read voltage is applied to read data from each of a plurality of planes specified in the multi-plane read command.

21. A system comprising modules for executing the method of any one of claims 11-20.

22. The system of claim 21, wherein the module comprises machine-readable code which, when executed, causes the machine to perform one or more steps of the method of any one of claims 11-20.

23. A system comprising: Storage devices, including: a memory device comprising a memory array and a first controller; and A second controller is configured to: sending a configuration command to the first controller, the configuration command specifying at least one read offset voltage and a read voltage offset profile identifier; and A read command is sent to the first controller, the read command specifying the read voltage offset profile identifier and an address of the memory array.

24. The system of claim 23, the second controller receiving data specified by the address of the memory array, the data being read by the first controller according to the at least one read offset voltage.

25. The system of claim 23, wherein the read command specifies the read voltage offset profile identifier in a command cycle or an address cycle of the read command.

26. The system of claim 23, further comprising a processor that sends a read request to the storage device, and wherein the second controller sends the read command in response to receiving the read request.

27. The system of claim 23, further comprising a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.

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