Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device may include: forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate so that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip to the substrate by curing the adhesive film by simultaneously performing a heat pressing process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.

Description

[0001] Cross-references

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0135345 filed on November 6, 2018 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments relate to a method of bonding a semiconductor chip, and more particularly, to a method of bonding a semiconductor chip using an adhesive material. Background Art

[0004] In a method of manufacturing a semiconductor package, an adhesive material may be used to bond a semiconductor chip and a substrate. The adhesive material may be in the form of a non-conductive film (NCF) or a non-conductive paste (NCP) including a thermosetting resin.

[0005] The adhesive material may be cured through a thermal press process to form a cured film, however, the cured film may not completely cover the semiconductor chip or may protrude from the semiconductor chip due to the thermal press process, in which case the reliability of the semiconductor package may be deteriorated. Summary of the invention

[0006] Example embodiments provide a method of manufacturing a semiconductor device / package to improve the reliability of the semiconductor device / package.

[0007] According to an example embodiment, a method for manufacturing a semiconductor device is provided. The method may include: forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate so that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate by curing the adhesive film by simultaneously performing a thermal compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.

[0008] According to an example embodiment, a method for manufacturing a semiconductor device is provided. The method may include: forming a connection structure on a surface of a semiconductor chip, forming an adhesive film on the semiconductor chip to cover the connection structure, mounting the semiconductor chip on a substrate so that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate by curing the adhesive film by simultaneously performing a thermal compression process and an ultraviolet irradiation process on the adhesive film between the substrate and the semiconductor chip.

[0009] According to an example embodiment, a method for manufacturing a semiconductor device is provided. The method may include: applying an adhesive paste on a substrate including a pad, mounting a semiconductor chip on the substrate on which the adhesive paste is applied, and bonding the semiconductor chip and the substrate by curing the adhesive paste by simultaneously performing a thermal compression process and an ultraviolet irradiation process on the adhesive paste disposed between the substrate and the semiconductor chip.

[0010] A method of manufacturing a semiconductor device according to an example embodiment may include bonding a semiconductor chip to a substrate by simultaneously performing a heat press process and an ultraviolet irradiation process on an adhesive material including a thermosetting resin and a photocurable resin disposed between the semiconductor chip and the substrate to which the semiconductor chip is mounted. The heat press process may be performed under high temperature and / or high pressure conditions so as to fill a space between the semiconductor chip and the substrate including all vertex portions of the semiconductor chip in a plan view, and a portion of the adhesive material formed beyond the sides of the semiconductor chip except for the vertex portions in a plan view may be photocured by an ultraviolet irradiation process.

[0011] Therefore, the cured film formed by curing the adhesive material can be formed to fill the gap between the semiconductor chip and the substrate corresponding to all the vertex parts of the semiconductor chip in the plan view, so that no gap is formed. Moreover, the cured film formed beyond the edge of the semiconductor chip in the plan view can be minimized, for example, the overflow of the adhesive material can be minimized. As a result, the reliability of the semiconductor package can be improved.

[0012] However, the present invention is not limited to the above-described embodiments and can be variously extended, some aspects of which are described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1 to 11 1 and 2 are a plan view, a cross-sectional view, and a perspective view, respectively, illustrating a semiconductor chip bonding method according to example embodiments.

[0014] Figures 12 to 18 2 are a plan view and a cross-sectional view respectively illustrating a semiconductor chip bonding method according to example embodiments. DETAILED DESCRIPTION

[0015] Hereinafter, a semiconductor chip bonding method according to example embodiments will be described more fully with reference to the accompanying drawings.

[0016] Figures 1 to 11 are a plan view, a cross-sectional view, and a perspective view respectively showing a semiconductor chip bonding method according to an example embodiment. Specifically, Figure 1 , 7 -8 and 10-11 are floor plans, Figure 2 , Figure 4-6 and Fig. 9are cross-sectional views taken along line AA′ of the corresponding plan view, Figure 3 yes Figure 2 An enlarged perspective view of area X.

[0017] refer to Figures 1 to 3 , a conductive bump structure 140 including first and second conductive bumps 120 and 130 stacked sequentially may be formed on a semiconductor chip 100 including a chip pad 110. For example, the first and second conductive bumps 120 and 130 may be stacked sequentially on the chip pad 110.

[0018] For example, after forming a seed layer (not shown) on the chip pad 110 of the semiconductor chip 100, an electroplating process may be performed on the seed layer to form a first conductive bump layer and a second conductive bump layer, and the first conductive bump layer and the second conductive bump layer may be patterned to form a first conductive bump 120 and a second conductive bump 130. The first conductive bump 120 and the second conductive bump 130 may be stacked sequentially. For example, the first conductive bump layer and the second conductive bump layer may be patterned sequentially by two different patterning processes, or may be patterned as a whole by a patterning process. The chip pad 110 and the conductive bump structure 140 may form a connection structure together.

[0019] In one embodiment, the semiconductor chip 100 may include semiconductor elements such as transistors, contact plugs, wirings, capacitors, and the like.

[0020] Figure 1 The semiconductor chip 100 is shown to have a rectangular shape in a plan view, however, the inventive concept may not be limited thereto, and the semiconductor chip 100 may have a square shape or other polygonal shapes, such as a triangular shape, a pentagonal shape, and the like.

[0021] A plurality of chip pads 110 may be formed along a first direction substantially parallel to the upper surface of the semiconductor chip 100, and each chip pad 110 may extend in a second direction substantially parallel to the upper surface of the semiconductor chip and intersecting the first direction. In example embodiments, the first direction and the second direction may be substantially orthogonal to each other.

[0022] A plurality of conductive bump structures 140 may be formed along the second direction on the chip pad 110. Thus, the conductive bump structures 140 may be electrically connected to the chip pad 110.

[0023] In an example embodiment, the sidewall of the conductive bump structure 140 in the second direction may have an inclined slope and may not be perpendicular to the upper surface of the semiconductor chip 100, so the width of the upper surface of the second conductive bump 130 in the second direction may be less than the width of the lower surface of the first conductive bump 120 in the second direction. For example, when viewed in the first direction, the conductive bump structure 140 may have a trapezoidal shape. However, the inventive concept is not limited thereto, and the width of the upper surface of the second conductive bump 130 in the second direction may be greater than the width of the lower surface of the first conductive bump 120 in the second direction. For example, when viewed in the first direction, the conductive bump structure 140 may have an inverted trapezoidal shape.

[0024] In some embodiments, the sidewall of the conductive bump structure 140 in the second direction may be perpendicular to the upper surface of the semiconductor chip 100, and thus the upper surface of the second conductive bump 130 and the lower surface of the first conductive bump 120 may have the same width in the second direction. For example, when viewed in the first direction, the conductive bump structure 140 may have a rectangular shape.

[0025] Figure 3 The first conductive bump 120 and the second conductive bump 130 are shown to have the same width as each other in the first direction, however, the inventive concept is not limited thereto. For example, the width of the second conductive bump 130 in the first direction may increase from its upper portion toward the lower portion, and the width of the first conductive bump 120 in the first direction may increase from its lower portion toward the upper portion. Therefore, when viewed from the second direction, the conductive bump structure 140 may have an elliptical shape. For example, the width of the upper surface of the first conductive bump 120 in the first direction may be the same as the width of the lower surface of the second conductive bump 130, the width of the lower surface of the first conductive bump 120 in the first direction may be less than the width of the upper surface of the first conductive bump 120, and the width of the upper surface of the second conductive bump 130 in the first direction may be less than the width of the lower surface of the second conductive bump 130. For example, the first conductive bump 120 and the second conductive bump 130 may be a trapezoid, such as an isosceles trapezoid, from the corresponding side view of the second direction.

[0026] In example embodiments, the chip pad 110 may include polysilicon, the first conductive bump 120 may include a first conductive material such as copper (Cu), nickel (Ni), etc., and the second conductive bump 130 may include a second conductive material such as tin (Sn), tin / silver (Sn / Ag), tin / copper (Sn / Cu), tin / indium (Sn / In), etc. However, the first conductive material and the second conductive material are not limited thereto.

[0027] refer to Figure 4, an adhesive film 150 may be formed on the upper surface of the semiconductor chip 100 to cover the connection structure including the chip pad 110 and the conductive bump structure 140. The height of the upper surface of the adhesive film 150 may be higher than the height of the upper surface of the second conductive bump 130.

[0028] In example embodiments, the adhesive film 150 may be formed by, for example, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or the like.

[0029] In an exemplary embodiment, the adhesive film 150 may include a binding resin, a thermosetting resin, and a light-curing resin. The binding resin may include, for example, an acrylic resin or a phenoxy resin. The thermosetting resin may be formed by a reaction between, for example, at least one selected from the group consisting of epoxy resins, acrylic resins, and silicone resins and a thermal curing agent. The thermal curing agent may include, for example, an amine hardener, an anhydride hardener, a polyol hardener, an azine hardener, a phenol hardener, and the like. The photocurable resin can be formed by, for example, the reaction between an acrylic resin having a carbon double bond and a photocuring initiator. The acrylic resin having a carbon double bond may include, for example, 2-hydroxyethyl acrylate (HEA), 2-hydroxyethyl methacrylate (HEMA), 2,3-epoxypropyl methacrylate (EPMA), acrylic acid (AA), methacrylic acid (MAA), etc. The photocurable initiator may include, for example, isodecyl acrylate (IDA), 2-phenoxyethyl acrylate (PEA), hexanediol diacrylate (HDDA), tripropylene glycol diacrylate (TrPGDA), trimethylolpropane triacrylate (TMPTA), trimethylolpropane ethoxy triacrylate (TMPEOTA), etc.

[0030] In one embodiment, the adhesive film 150 may further include an inorganic filler, an organic filler, and / or a metal filler. The inorganic filler may include, for example, silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), titanium dioxide (TiO 2 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), boron nitride (BN), etc., the organic filler may include, for example, an acrylic copolymer containing an epoxy group having a molecular weight of about 100,000 or more, and the metal filler may include a metal such as aluminum (Al), nickel (Ni), silver (Ag), etc. The inorganic filler, the organic filler, and the metal filler may reduce the thermal expansion coefficient of the adhesive film 150, thereby controlling the subsequent thermal compression process to be stably performed, and thus the reliability of the semiconductor package may be improved.

[0031] refer to Figure 5 , the semiconductor chip 100 on which the adhesive film 150 is formed may be turned upside down.

[0032] Therefore, the adhesive film 150 covering the connection structure on the upper surface of the semiconductor chip 100 may face downward.

[0033] refer to Figure 6 , the semiconductor chip 100 may be mounted on a substrate 200 including a substrate pad 210 .

[0034] For example, the semiconductor chip 100 may be mounted on the substrate 200 so that the upper surface of the semiconductor chip 100 on which the adhesive film 150 covering the connection structure is formed may face the upper surface of the substrate 200, and the second conductive bump 130 of the connection structure and the substrate pad 210 of the substrate 200 may be aligned with each other. For example, the first conductive bump 120 and the second conductive bump 130 may overlap the substrate pad 210 in a plan view.

[0035] In one embodiment, the substrate 200 may be, for example, a printed circuit board (PCB), and the PCB may be a multilayer circuit board having vias and various circuits therein. Alternatively, the substrate 200 may be, for example, a silicon (Si) chip or a silicon (Si) wafer.

[0036] The substrate 200 may be disposed on the lower mold 10, the upper mold 20 may be disposed on the semiconductor chip 100, and the ultraviolet irradiator 30 may be disposed in a space between the lower mold 10 and the upper mold 20. The lower mold 10 may fix the substrate 200 so as not to move up and down, and when performing a subsequent heat pressing process, the upper mold 20 may press down the semiconductor chip 100 in a vertical direction substantially perpendicular to the upper surface of the substrate 200. The ultraviolet irradiator 30 may irradiate the adhesive film 150 with ultraviolet rays when performing the ultraviolet irradiation process.

[0037] Figures 4 to 6 The adhesive film 150 is shown to be formed to cover / contact the connection structure on the semiconductor chip 100, however, the inventive concept is not limited thereto. For example, the adhesive film may be manufactured separately and thus may not cover / contact the connection structure on the semiconductor chip 100. In this case, when the semiconductor chip 100 is mounted on the substrate 200, the adhesive film 150 may be disposed in a space between the semiconductor chip 100 and the substrate 200, for example, in a space between the connection structure and the substrate pad 210.

[0038] refer to Figures 7 to 10 , the thermal compression process and the ultraviolet radiation process may be simultaneously performed on the semiconductor chip 100 , the adhesive film 150 , and the substrate 200 .

[0039] Therefore, the adhesive film 150 arranged in the space between the semiconductor chip 100 and the substrate 200 can be compressed while providing heat to the adhesive film 150, so that the connection structure of the semiconductor chip 100 can contact the substrate pad 210 of the substrate 200 and be electrically connected thereto, and through hot pressing treatment and ultraviolet irradiation treatment, the adhesive film 150 can be cured to form a first cured film 160.

[0040] The heat pressing process may be performed by moving the upper mold 20 downward to press the semiconductor chip 100 onto the substrate 200 disposed on the lower mold 10, and increasing the temperature of the space between the lower mold 10 and the upper mold 20. Specifically, heat is applied from an external source, for example, by heating one or both of the lower mold 10 and the upper mold 20, or by applying heat from an external source to the atmosphere between the lower mold 10 and the upper mold 20, and the heat is then transferred to the adhesive film 150. Figure 7 As shown, the thermal compression process may be performed on portions of the adhesive film 150 corresponding to all sides including vertex portions of the polygonal shape of the semiconductor chip 100 .

[0041] The adhesive film 150 may be subjected to ultraviolet irradiation treatment by irradiating the adhesive film 150 with ultraviolet rays generated from the ultraviolet irradiator 30 at an angle of about 0° to about 90° relative to the upper surface of the substrate 200. Figure 8 As shown, the adhesive film 150 may be subjected to ultraviolet irradiation treatment on the portion corresponding to all sides of the polygonal shape of the semiconductor chip 100 except the vertex portion, or the portion corresponding to at least one side of the polygonal shape of the semiconductor chip 100. For example, the ultraviolet irradiator 30 may irradiate the adhesive film 150 with ultraviolet light at one or more side portions of the polygonal shape of the semiconductor chip 100 in a plan view. For example, the ultraviolet irradiator 30 may not irradiate the adhesive film 150 with ultraviolet light at a corner (e.g., a portion corresponding to the vertex and / or the vicinity of the vertex of the polygonal shape of the semiconductor chip 100 in a plan view). For example, the adhesive film 150 in the corner / vertex may not be cured with ultraviolet light, while the adhesive film 150 in the side region is cured with ultraviolet light. In one embodiment, the ultraviolet irradiation treatment may be performed along the first and second directions.

[0042] Therefore, even if the adhesive film 150 fills the space corresponding to the side of the polygonal shape of the semiconductor chip 100 faster than the space corresponding to the vertex portion of the polygonal shape of the semiconductor chip 100 by the hot pressing process, the adhesive film 150 can be cured by ultraviolet light by ultraviolet irradiation treatment to minimize the portion of the adhesive film 150 protruding outward from the side of the semiconductor chip 100. In this light curing process, the adhesive film 150 in the vertex portion (the vertex and its vicinity) can be cured without ultraviolet light. This is also helpful for the adhesive film 150 to expand / expand toward the vertex portion of the semiconductor chip 100. For example, in a plan view, the adhesive film 150 can expand / expand toward the side and vertex of the polygonal shape of the semiconductor chip 100 when the hot pressing process is performed, and the expansion of the adhesive film 150 toward the side can be controlled by ultraviolet light irradiation. For example, the adhesive film 150 may include both a thermosetting resin and a photocurable resin, so that the first cured film 160 can fill most of the space corresponding to the vertex portion of the polygonal shape of the semiconductor chip 100 through heat pressing treatment, and ultraviolet irradiation treatment can help minimize the protruding portion of the first cured film 160 protruding outward from the area / space corresponding to the side of the polygonal shape of the semiconductor chip 100.

[0043] In example embodiments, a difference between a maximum width of the lower surface of the first cured film 160 and a maximum width of the lower surface of the semiconductor chip 100 may be less than or approximately 500 μm. For example, a difference between a width of the lower surface of the first cured film 160 in the first direction and a width of the lower surface of the semiconductor chip 100 in the first direction may be less than or approximately 500 μm, and a difference between a width of the lower surface of the first cured film 160 in the second direction and a width of the lower surface of the semiconductor chip 100 in the second direction may also be less than or approximately 500 μm.

[0044] In an exemplary embodiment, the heat press treatment may be performed at a temperature of about 350° C. or less and a pressure of about 100 N or less, and the ultraviolet irradiation treatment may be performed at a pressure of about 5000 mJ / cm 2 or less.

[0045] Fig. 9 The sidewall of the first cured film 160 formed by curing the adhesive film 150 is shown to have a constant slope relative to the upper surface of the substrate 200, however, the present inventive concept is not limited thereto. For example, the sidewall of the first cured film 160 may have a non-constant slope relative to the upper surface of the substrate 200, for example, the sidewall of the first cured film 160 may also have an increasing slope or a decreasing slope relative to the upper surface of the substrate 200. Fig.10As shown in FIG. 1 , the adhesive film 150 may not fill all the spaces between the substrate 200 and the semiconductor chip 100. For example, in a plan view, near the apex of the semiconductor chip 100, after the thermal compression process is completed, the adhesive film 150 and / or the first curing film 160 may not fill the spaces between the semiconductor chip 100 and the substrate 200, as shown in FIG. Fig.10 For example, in a plan view, after the thermal compression process is completed, the adhesive film 150 and / or the first curing film 160 may not protrude outward from the vertex portion of the semiconductor chip 100 .

[0046] refer to Fig.11 , the first cured film 160 may fill all spaces on the substrate 200 corresponding to the semiconductor chip 100 , however, the area of ​​a portion of the first cured film 160 protruding outward from the semiconductor chip 100 may be smaller. Fig.11 An embodiment is shown in which the first cured film 160 does not protrude outward from the vertex portion of the semiconductor chip 100 in a plan view. However, the present invention is not limited thereto. For example, in some embodiments, the first cured film 160 may protrude outward from the vertex portion of the semiconductor chip 100.

[0047] As described above, when the adhesive film 150 between the semiconductor chip 100 and the substrate 200 is subjected to heat pressing treatment and ultraviolet irradiation treatment, the heat pressing treatment can be performed on the portion of the adhesive film 150 corresponding to all sides of the polygonal shape of the semiconductor chip 100 including the vertex part, however, the ultraviolet irradiation treatment can be performed only on the portion of the adhesive film 150 corresponding to all sides of the polygonal shape of the semiconductor chip 100 except the vertex part.

[0048] Therefore, the first cured film 160 formed by curing the adhesive film 150 can fill most of the space corresponding to the vertex portion of the polygonal shape of the semiconductor chip 100 through the heat press process, and is advantageous in minimizing the portion of the first cured film 160 protruding outward from the space corresponding to the side of the polygonal shape of the semiconductor chip 100. As a result, while the semiconductor chip 100 can be well bonded to the substrate 200, it is advantageous in minimizing the protrusion of the first cured film 160 outward from the semiconductor chip 100 due to overflow of the adhesive film 150, thereby reducing the degradation of the reliability of the semiconductor package.

[0049] Figures 12 to 18 1 is a plan view and a cross-sectional view showing a semiconductor chip bonding method according to an example embodiment. Specifically, Figure 14-15 and 17-18 are floor plans, Figure 12-13 16 are cross-sectional views taken along line AA′ of the corresponding plan views, respectively.

[0050] The semiconductor chip bonding method comprises: Figures 1 to 11The semiconductor chip bonding method shown in FIG. 1 is substantially the same or similar process. Therefore, the same reference numerals represent the same elements and are not described in detail herein.

[0051] refer to Fig.12 , an adhesive paste 170 including a thermosetting resin and a photocurable resin may be applied on the substrate 200 including the substrate pad 210 to cover the substrate pad 210 .

[0052] The adhesive paste 170 may include substantially the same material as the adhesive film 150 , however, may have a liquid or paste form instead of a film form.

[0053] refer to Fig.13 , a substrate 200 on which an adhesive paste 170 is applied may be disposed on a lower mold 10 , a semiconductor chip 100 may be mounted on the adhesive paste 170 , an upper mold 20 may be disposed on the semiconductor chip 100 , and an ultraviolet radiator 30 may be disposed in a space between the lower mold 10 and the upper mold 20 .

[0054] The chip pad 110 and the first conductive bump 120 and the second conductive bump 130 (which may be covered with the adhesive paste 170) included in the connection structure of the semiconductor chip 100 and the substrate pad 210 of the substrate 200 may be aligned with each other. For example, in a plan view, the connection structure of the semiconductor chip 100 may be aligned with the substrate pad 210 of the substrate 200 so as to overlap. For example, the thickness of the adhesive paste 170 formed on the substrate 200 may be greater than the thickness of the connection structure.

[0055] refer to Figures 14 to 17 , the adhesive paste 170 , the semiconductor chip 100 , and the substrate 200 may be subjected to a thermal compression process and an ultraviolet irradiation process simultaneously.

[0056] Therefore, the adhesive paste 170 arranged in the space between the semiconductor chip 100 and the substrate 200 can be compressed while providing heat to the adhesive paste 170, so that the connection structure of the semiconductor chip 100 can contact the substrate pad 210 of the substrate 200 and be electrically connected thereto, and through heat pressing treatment and ultraviolet irradiation treatment, the adhesive paste 170 can be cured to form a second cured film 180.

[0057] The heat pressing process may be performed by moving the upper mold 20 downward to press the semiconductor chip 100 onto the substrate 200 disposed on the lower mold 10, and increasing the temperature of the space between the lower mold 10 and the upper mold 20. Specifically, heat is applied from an external source, for example, by heating one or both of the lower mold 10 and the upper mold 20, or by applying heat from an external source to the atmosphere between the lower mold 10 and the upper mold 20, and the heat is then transferred to the adhesive paste 170. Fig.14As shown, the thermocompression process may be performed on portions of the adhesive paste 170 corresponding to all sides including vertex portions of the polygonal shape of the semiconductor chip 100 .

[0058] The adhesive paste 170 may be subjected to ultraviolet irradiation treatment by irradiating the adhesive paste 170 with ultraviolet rays generated from the ultraviolet irradiator 30 at an angle of about 0° to about 90° with respect to the upper surface of the substrate 200. Fig.15 As shown, the ultraviolet irradiation treatment may be performed on portions of the adhesive paste 170 corresponding to all sides of the polygonal shape of the semiconductor chip 100 except for the vertex portions, or on portions corresponding to at least one side of the polygonal shape of the semiconductor chip 100 .

[0059] In this case, the component of the second cured film 180 may be substantially the same as that of the first cured film 160 .

[0060] Fig.16 The sidewall of the second cured film 180 formed by curing the adhesive paste 170 is shown to have a constant slope relative to the upper surface of the substrate 200, however, the inventive concept is not limited thereto. For example, the sidewall of the second cured film 180 may have a non-constant slope relative to the upper surface of the substrate 200, for example, the sidewall of the second cured film 180 may have an increasing slope or a decreasing slope relative to the upper surface of the substrate 200.

[0061] refer to Fig.17 , the second cured film 180 may not fill all the spaces between the substrate 200 and the semiconductor chip 100. For example, in a plan view, near the vertex of the semiconductor chip 100, after the thermal compression process is completed, the second cured film 180 may not fill between the semiconductor chip 100 and the substrate 200. For example, in a plan view, after the thermal compression process is completed, the second cured film 180 may not protrude outward from the vertex portion of the semiconductor chip 100.

[0062] refer to Fig.18 For example, in a plan view, the second cured film 180 may fill all spaces on the substrate 200 corresponding to the semiconductor chip 100. However, the area of ​​a portion of the second cured film 180 protruding outward from the semiconductor chip 100 in a plan view may be small.

[0063] The semiconductor chip bonding method described above can be used to bond semiconductor chips including semiconductor devices such as logic devices or memory devices. For example, the bonding method can be used to bond semiconductor chips including the following devices: semiconductor chips including logic devices such as a central processing unit (CPU), a main processing unit (MPU), or an application processor (AP), volatile memory devices such as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices, or non-volatile memory devices such as flash memory devices, phase change random access memory (PRAM) devices, magnetic random access memory (MRAM) devices, and resistive random access memory (RRAM) devices.

[0064] As noted above, although the invention has been described with reference to exemplary embodiments, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the inventive concept.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming an adhesive film on a surface of a semiconductor chip; mounting the semiconductor chip on a substrate so that the adhesive film contacts an upper surface of the substrate; as well as by simultaneously performing a heat press process and an ultraviolet irradiation process on the adhesive film provided between the substrate and the semiconductor chip, bonding the semiconductor chip and the substrate by curing the adhesive film, wherein the semiconductor chip has a polygonal shape in plan view, wherein the ultraviolet irradiation treatment is performed by irradiating the adhesive film with ultraviolet light from at least one side of the polygonal shape of the semiconductor chip, and The ultraviolet light does not irradiate the adhesive film near the vertices of the polygonal shape of the semiconductor chip. 2 . The method according to claim 1 , wherein the ultraviolet irradiation treatment is performed by irradiating the adhesive film with ultraviolet light from all sides of the polygonal shape of the semiconductor chip. 3 . The method according to claim 1 , wherein the ultraviolet irradiation treatment is performed at an angle of 0° to 90° with respect to the upper surface of the substrate.

4. The method according to claim 1, wherein the ultraviolet irradiation treatment is performed at 5000 mJ / cm 2 or less.

5. The method according to claim 1, wherein the hot pressing treatment is carried out at a temperature of 350°C or less and a pressure of 100 N / mm 2 or lower pressure. The method according to claim 1 , wherein the substrate is a printed circuit board, a silicon chip or a silicon wafer. 7 . The method according to claim 1 , wherein the adhesive film is formed on the semiconductor chip by a chemical vapor deposition process or an atomic layer deposition process. 8 . The method according to claim 1 , wherein the adhesive film is cured by performing the heat pressing process and the ultraviolet irradiation process to form a cured film. 9 . The method according to claim 8 , wherein a difference between a width of a lower surface of the cured film formed by curing the adhesive film and a width of a lower surface of the semiconductor chip is 500 μm or less.

10. The method according to claim 1, wherein the adhesive film comprises a thermosetting resin and a photocurable resin.

11. The method according to claim 10, wherein the adhesive film further comprises a bonding resin, and The bonding resin comprises acrylic resin or phenoxy resin. 12 . The method according to claim 10 , wherein the thermosetting resin is formed by a reaction between at least one selected from the group consisting of epoxy resin, acrylic resin, and silicone resin and a thermal curing agent. 13 . The method according to claim 12 , wherein the thermal curing agent comprises at least one selected from the group consisting of an amine hardener, an acid anhydride hardener, a polyol hardener, an azine hardener, and a phenol hardener. 14 . The method according to claim 10 , wherein the adhesive film further comprises at least one selected from the group consisting of an inorganic filler, an organic filler, and a metal filler.

15. The method according to claim 14, wherein the inorganic filler comprises at least one selected from the group consisting of silica, alumina, titanium dioxide, aluminum nitride, silicon nitride, boron nitride, the organic filler comprises an acrylic copolymer containing an epoxy group having a molecular weight of 100,000 or more, and the metal filler comprises at least one selected from the group consisting of aluminum, nickel and silver. 16 . The method according to claim 10 , wherein the photocurable resin is formed by a reaction between an acrylic resin having a carbon double bond and a photocuring initiator. 17 . The method according to claim 16 , wherein the acrylic resin having a carbon double bond comprises at least one selected from the group consisting of 2-hydroxyethyl acrylate, 2-hydroxyethyl methacrylate, 2,3-epoxypropyl methacrylate, acrylic acid, and methacrylic acid.

18. The method according to claim 16, wherein the photocuring initiator comprises at least one selected from the group consisting of isodecyl acrylate, 2-phenoxyethyl acrylate, hexanediol diacrylate, tripropylene glycol diacrylate, trimethylolpropane triacrylate, and trimethylolpropane ethoxy triacrylate.

19. A method for manufacturing a semiconductor device, the method comprising: forming a connection structure on a surface of a semiconductor chip; forming an adhesive film on the semiconductor chip to cover the connection structure; mounting the semiconductor chip on a substrate so that the adhesive film contacts an upper surface of the substrate; as well as by simultaneously performing a heat press process and an ultraviolet irradiation process on the adhesive film between the substrate and the semiconductor chip, bonding the semiconductor chip and the substrate by curing the adhesive film, wherein the semiconductor chip has a polygonal shape in plan view, wherein the ultraviolet irradiation treatment is performed by irradiating the adhesive film with ultraviolet light from at least one side of the polygonal shape of the semiconductor chip, and The ultraviolet light does not irradiate the adhesive film near the vertices of the polygonal shape of the semiconductor chip.

20. A method for manufacturing a semiconductor device, the method comprising: applying an adhesive paste on the substrate including the pads; mounting a semiconductor chip on the substrate on which the adhesive paste is applied; as well as by simultaneously performing a heat press process and an ultraviolet irradiation process on the adhesive paste provided between the substrate and the semiconductor chip, thereby bonding the semiconductor chip and the substrate by curing the adhesive paste, wherein the semiconductor chip has a polygonal shape in plan view, wherein the ultraviolet irradiation treatment is performed by irradiating the adhesive paste with ultraviolet light from at least one side of the polygonal shape of the semiconductor chip, and The ultraviolet light does not irradiate the adhesive paste near the vertices of the polygonal shape of the semiconductor chip.

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