Method for generating an aging model and using the same to manufacture a semiconductor chip

Abstract

A method for generating an aging model used in designing a semiconductor chip includes: extracting multiple aging scenarios including usage conditions of the semiconductor chip from an aging model library of the semiconductor chip; calculating first aging parameters commonly applied to multiple semiconductor elements included in the semiconductor chip from the multiple aging scenarios; and generating characteristic degradation information due to aging of each semiconductor element through simulation using the first aging parameters and second aging parameters of each semiconductor element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0137405, entitled “Method for Generating Aging Model and Manufacturing Semiconductor Chip Using the Same,” filed on November 9, 2018 in the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a method of generating an aging model, and more particularly, to a method of generating an aging model of a semiconductor chip using a minimum aging parameter and a method of manufacturing the semiconductor chip using the same. Background Art

[0004] Aging of semiconductor chips is a phenomenon in which the performance of semiconductor chips deteriorates due to negative bias temperature instability (NBTI), hot carrier injection (HCI), etc. as the chips are used for a longer time.

[0005] Since semiconductor chips need to maintain a certain level of performance during the warranty period, aging characteristics are an essential consideration in chip design. Specifically, in applications where uninterrupted operation is essential (such as in an electronic control unit (ECU) of a vehicle or a server device), aging characteristics become an important consideration in chip design.

[0006] By using the aging model of semiconductor chips, the aging degree of semiconductor chips (e.g., threshold voltage variation, timing delay, etc.) can be predicted. The aging model of semiconductor chips requires a large number of aging parameters and worst-case scenarios to increase prediction accuracy, which increases modeling complexity and cost. Summary of the invention

[0007] According to an embodiment, a method for generating an aging model for designing a semiconductor chip may include: extracting multiple aging scenarios including usage conditions of the semiconductor chip from an aging model library of the semiconductor chip; calculating first aging parameters commonly applied to multiple semiconductor elements included in the semiconductor chip based on the multiple aging scenarios; and generating characteristic degradation information due to aging of each semiconductor element through simulation using the first aging parameters and second aging parameters of each semiconductor element.

[0008] According to an embodiment, a method for generating an aging model for designing a semiconductor chip may include: calculating a first aging parameter of the semiconductor chip based on a plurality of usage conditions defined in an aging model library of the semiconductor chip; using a first aging parameter and a second aging parameter of each semiconductor element included in the semiconductor chip to generate characteristic degradation information due to aging of each semiconductor element; and using the characteristic degradation information of each semiconductor element and a third aging parameter to generate timing information due to aging of the semiconductor chip.

[0009] According to an embodiment, a method for manufacturing a semiconductor chip may include: loading multiple aging scenarios from an aging model library of a semiconductor chip including multiple semiconductor elements; obtaining global aging parameters commonly applied to the semiconductor elements from the multiple aging scenarios; using the global aging parameters and the instant aging parameters to calculate one or more first timing delays of the semiconductor chip; calculating a second timing delay of the semiconductor chip by summing the first timing delays; using the first timing delay and the second timing delay to determine whether the semiconductor chip violates a timing constraint; and when the semiconductor chip does not violate the timing constraint, manufacturing the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 An aging modeling system for a semiconductor chip according to an example embodiment is shown;

[0012] Figure 2 A flowchart illustrating a method of generating an aging model of a semiconductor chip according to example embodiments;

[0013] Figure 3 The structure of a machine learning model for generating an aging model according to an example embodiment is shown by way of example;

[0014] Figure 4 Show Figure 2 A flowchart of the detailed operation of S200;

[0015] Figure 5A and Figure 5B Show Figure 2 An exemplary diagram of detailed operations of S200 in FIG.

[0016] Figure 6 Show Figure 2 A flowchart of the detailed operation of S300 in FIG.

[0017] Figure 7 Show Figure 2 An exemplary circuit diagram of the detailed operation of S300 in FIG.

[0018] Figure 8 Show Figure 2 A table of exemplary values ​​of input and output parameters of S300 in FIG.

[0019] Fig. 9 A flowchart illustrating a method of generating an aging model of a semiconductor chip according to example embodiments;

[0020] Fig. 10A and Fig. 10B Show Fig. 9 An exemplary diagram of detailed operations of S800 in FIG.

[0021] Fig.11 Show Fig. 9 A table of exemplary values ​​of input and output parameters of S800 in FIG.

[0022] Fig.12 A flowchart illustrating a static timing analysis method of a semiconductor chip according to an example embodiment; and

[0023] Fig.13 A computing system that performs a method of generating an aging model of a semiconductor chip according to example embodiments is illustrated. DETAILED DESCRIPTION

[0024] Figure 1 An aging modeling system according to an example embodiment is shown. Figure 1 The aging modeling system 100 may be a computer-based simulation system that creates and updates an aging model of a semiconductor chip. For example, the aging modeling system 100 may simulate the aging degree of a semiconductor chip using a plurality of aging parameters, and may calculate an aging model of a corresponding semiconductor chip based on the corresponding simulation results. In an example embodiment, the aging modeling system 100 may include an aging model library 10, an aging modeling module 20, and a static timing analysis (STA) module 30.

[0025] The aging model library 10 may include a netlist 11 , an aging scenario database (DB) 13 , and an aging model database (DB) 15 .

[0026] The netlist 11 is data defining a semiconductor chip, and may include information on the types of a plurality of semiconductor elements included in the semiconductor chip, connection relationships of the semiconductor elements, etc. In addition, the netlist 11 may include operating conditions of the semiconductor chip, such as an operating voltage Vop and an operating temperature Top, input and output signal information, etc. The netlist 11 may be implemented in the form of a file having a preset format.

[0027] The aging scenario DB 13 may be a database storing various aging scenarios of semiconductor chips. Each aging scenario may include a unique usage condition of the semiconductor chip and aging information associated therewith.

[0028] In example embodiments, the use condition of the semiconductor chip may include bias information of the semiconductor chip, use time information, etc. For example, the bias information of the semiconductor chip may include a bias voltage Vb, a bias temperature Tb, etc., and the use time information of the semiconductor chip may include a ratio of the use time to the life of the corresponding semiconductor chip (hereinafter referred to as a "use time duty cycle").

[0029] In addition, the aging information of the semiconductor chip may include characteristic degradation information due to aging, timing information, etc. For example, the aging information of the semiconductor chip may include threshold voltage variation, timing delay variation, and the like.

[0030] As described above, the aging scenario DB 13 may be implemented in a file format in which various aging scenarios of semiconductor chips are stored in various formats such as a table, a graph, a combination of the two, and the like.

[0031] The aging model DB 15 may be a database storing a plurality of aging models of semiconductor chips. The aging model may be a model for predicting the degree of aging (e.g., threshold voltage variation or timing delay, etc.) of a corresponding semiconductor chip or each semiconductor element in the corresponding semiconductor chip using predetermined aging parameters. In an example embodiment, the aging model may be implemented as a machine learning model. In this case, information about input and output parameters of the corresponding machine learning model may be stored in the aging model DB 15.

[0032] The various components 11 to 15 of the aging model library 10 may be distributed to a non-volatile memory device, a storage device, etc. to form a single logical entity. For example, the netlist 11 may be implemented in a NAND flash memory, while the aging scenario DB 13 and the aging model DB 15 may be implemented in a storage device.

[0033] The STA module 30 may be implemented at the level of software (ie, programming code) for performing static timing analysis of a semiconductor chip or hardware using VHDL (VHISC (Very High Speed ​​Integrated Circuit) Hardware Description Language), or the like.

[0034] The STA module 30 may perform a simulation function of generating aging information using various aging parameters of the semiconductor chip. In addition, the STA module 30 may perform a function of simulating and verifying the timing delay of the semiconductor chip or each semiconductor element in the corresponding semiconductor chip using a free variation format (LVF) standard library including the timing delay and change model of the semiconductor chip.

[0035] The aging modeling module 20 may calculate the aging degree of the semiconductor chip generated by various aging scenarios, and may generate an aging model of the corresponding semiconductor chip based on the calculation result.

[0036] In order to perform the above functions, the aging modeling module 20 may include a scene converter 21, an aging information calculator 23 and an aging model generator 25. The specific contents of each component will be referred to in Figure 2 to describe.

[0037] Figure 2 is a flowchart illustrating a method of generating an aging model of a semiconductor chip according to example embodiments.

[0038] Reference Figure 1 and Figure 2 In S100 , the scenario converter 21 may extract a plurality of aging scenarios to be applied to the semiconductor chip from the aging model library 10 . For example, the scenario converter 21 may load various combinations of aging scenarios from the aging scenario DB 13 .

[0039] In S200, the scene converter 21 may aggregate the multiple aging scenes extracted in S100 to calculate a first aging parameter of the semiconductor chip. The first aging parameter may be a representative parameter having a common impact on the aging of all semiconductor elements in the semiconductor chip. For example, the first aging parameter may be provided as a global aging parameter.

[0040] In example embodiments, the first aging parameter may include an effective stress time ST_eff commonly applied to all semiconductor elements in the semiconductor chip. The effective stress time may be a time that actually affects aging of the corresponding semiconductor chip during the use time of the semiconductor chip.

[0041] In S300, the aging information calculator 23 may generate individual aging information of each corresponding semiconductor element based on a simulation result using the first aging parameter of the semiconductor chip and the second aging parameter of the semiconductor chip calculated in S200. For example, the aging information calculator 23 provides the first aging parameter received from the scene converter 21 and the second aging parameter of each semiconductor element to the STA module 30 to perform simulation, and may generate individual aging information of each semiconductor element using the corresponding simulation result.

[0042] The second aging parameter may be an individual aging parameter that affects the aging of each semiconductor element. The second aging parameter may be provided as an instant aging parameter. In an example embodiment, the second aging parameter may include a probability that each semiconductor element in the corresponding semiconductor chip is under stress conditions during the use of the semiconductor chip. The STA module 30 may include a software tool for predicting the aging characteristics of a circuit, for example, an open source tool such as the Simulation Program for Integrated Circuit Emphasis (SPICE), a commercially available tool such as the Proteus design suite of Labcenter Electronics, etc. The individual aging information is characteristic degradation information due to the aging of each semiconductor element, and may include, for example, a threshold voltage change ΔVth of a transistor element, etc.

[0043] In S400, the aging model generator 25 may generate an individual aging model for predicting the degree of aging of each semiconductor element based on the individual aging information calculated in S300. For example, the aging model generator 25 may generate an individual aging model for each semiconductor element based on the correlation between the first aging parameter and the second aging parameter and the individual aging information. The individual aging model generated in S400 is stored in the aging model DB 15 and can be used for static timing analysis of the corresponding semiconductor chip.

[0044] In an example embodiment, the aging model generator 25 may use the individual aging parameters of each semiconductor element and the individual aging information about the individual aging parameters as training data to train the machine learning model, and may set the trained machine learning model as the individual aging model. For example, the aging model generator 25 may set the first aging parameter received from the scene converter 21 and the second aging parameter of each semiconductor element as input data, use the individual aging information of each semiconductor element calculated by the aging information calculator 23 as an output label corresponding to the corresponding input data to train the machine learning model, and set the trained machine learning model as the individual aging model for predicting the individual aging degree of each semiconductor element.

[0045] The machine learning model to be applied to the example embodiments may include a network that generates desired output data by combining extracted feature vectors after extracting feature vectors from predetermined input data, for example, an artificial neural network (ANN), a recurrent neural network (RNN), a regression support vector machine (SVM), etc.

[0046] Figure 3 An example of an artificial neural network to be applied to a method of generating an aging model of a semiconductor chip according to an example embodiment is shown. Figure 3, the artificial neural network 300 may include an input layer 310, a plurality of hidden layers 330, and an output layer 350. When one or more aging parameters of a semiconductor chip are input through the input layer 310, feature points are extracted through the plurality of hidden layers 330, and at least one piece of aging information of a corresponding semiconductor chip is output from the corresponding feature points through the output layer 350.

[0047] The method of generating an aging model of a semiconductor chip according to the above-described example embodiment calculates a single representative parameter from a plurality of aging scenarios of the semiconductor chip and generates an aging model using the calculated representative parameter, thereby having the effect of reducing the complexity of aging modeling.

[0048] In the following, reference is made to Figures 4 to 5B , will be described in more detail Figure 2 The detailed operation contents of S200. Figure 4 It is shown Figure 2 A flowchart of the detailed operation of S200 is shown in FIG. Figure 5A and Figure 5B It is shown Figure 2 An exemplary diagram of the detailed operation of S200 in FIG.

[0049] First, refer to Figure 4 Calculating a representative parameter (eg, effective stress time (ST_eff)) from a plurality of aging scenarios of a semiconductor chip (S200) may include aggregating a plurality of aging scenarios (S210) and calculating a representative parameter using the aggregated result and a reference aging scenario (S230).

[0050] In an example embodiment, in S210, the scene converter 21 may aggregate multiple aging scenes to generate aging information of the semiconductor chip under specific usage conditions. The specific usage conditions may include bias information and usage time information of the semiconductor chip. In addition, the specific usage conditions may be pre-set considering the aging properties of the semiconductor chip (e.g., the size of the process change, etc.) or the requirements of the device using the semiconductor chip (e.g., the requirements for seamless service, etc.). For example, the specific usage conditions may be pre-set to one of the worst case where the aging speed of the corresponding semiconductor chip is the fastest, the average case where the aging speed is the average speed, and the best case where the aging speed is the slowest.

[0051] Figure 5A A specific example of S210 is shown. Figure 5A In FIG. 1 , curves “a” to “c” are aging curves showing changes in threshold voltage according to the use time of the semiconductor chip. Figure 5AIn the figure, curves "a" to "c" correspond to various aging scenarios of semiconductor chips. For example, curve "a" corresponds to the best case where the aging degree of the semiconductor chip is the slowest, curve "b" corresponds to the average case where the aging degree of the semiconductor chip is average, and curve "c" corresponds to the worst case where the aging degree of the semiconductor chip is the fastest.

[0052] exist Figure 5A In the example, curve "a" is the aging curve under the bias condition of [1V, 100℃], curve "b" is the aging curve under the bias condition of [2V, 80℃], and curve "c" is the aging curve under the bias condition of [3V, 120℃]. Figure 5A , assuming that the semiconductor chip is used for a total of three years, the semiconductor chip is used under the bias condition of [1V, 100℃] for the first one year period, under the bias condition of [2V, 80℃] for the next one year period, and under the bias condition of [3V, 120℃] for the last one year period.

[0053] Reference Figure 5A , under the first bias condition of [1V, 100℃] in the first one-year period, the threshold voltage of the semiconductor chip cumulatively changes to "Vth1". Under the second bias condition of [2V, 80℃] in the next one-year period, the threshold voltage of the semiconductor chip cumulatively changes to "Vth2". Under the third bias condition of [3V, 120℃] in the last one-year period, the threshold voltage of the semiconductor chip cumulatively changes to "Vth3". In this case, when the total usage time of the corresponding semiconductor chip (i.e., three years) is converted to the bias condition of [3V, 120℃], the usage time is "t3" (here, t3<3 years).

[0054] As a result, a total of three aging scenarios in which the semiconductor chip is used for one year under the first bias condition, one year under the second bias condition, and one year under the third bias condition can be aggregated into a single aging scenario in which the semiconductor chip is used for a time "t3" under the third bias condition. In this case, the threshold voltage change (aging information) of the corresponding semiconductor chip can be "Vth3".

[0055] Again, refer to Figure 4 In S230, the scenario converter 21 may calculate a representative parameter by projecting the aging information of the semiconductor chip into a preset reference aging scenario under the specific usage condition calculated in S210. For example, the representative parameter (e.g., effective stress time (ST_eff)) is a global aging parameter to be commonly applied to aging modeling of all semiconductor elements of the semiconductor chip.

[0056] The reference aging scenario may include aging information and corresponding conditions under a reference use condition. The reference aging scenario is preset as a value obtained by repeated simulation statistics and may be stored in the aging scenario DB 13.

[0057] Figure 5B A specific example of S230 is shown. Figure 5B In the figure, curves "a" to "c" are as shown in FIG. Figure 5A The aging curve described above, and the curve "ref" may be an aging curve corresponding to a reference aging scenario. Figure 5B In the example of , the curve “ref” may be a reference aging curve in which the aging degree is statistically calculated in a case where the semiconductor chip is used for a total of three years under a reference bias condition of [2.5 V, 100° C.].

[0058] Reference Figure 5B , when Figure 5A When the threshold voltage change "Vth3" of the semiconductor chip determined in the above is projected onto the curve "ref", the usage time of the corresponding semiconductor chip in the reference aging scenario is "teff" (here, teff < 3 years). Here, "teff" is the time that actually affects the aging of the corresponding semiconductor chip in a total of three years of using the corresponding semiconductor chip in three aging scenarios, that is, the effective stress time ST_eff.

[0059] Next, refer to Figures 6 to 8 , will be described in more detail Figure 2 The detailed operation contents of S300. Figure 6 It is shown Figure 2 The flowchart of the detailed operation of S300 is shown in FIG. Figure 7 It is used to explain Figure 6 A circuit diagram of a specific example, Figure 8 It shows that according to Figure 6 Table of input and output parameter values ​​for the examples.

[0060] First, refer to Figure 6 Generating individual aging information using the representative parameters of the semiconductor chip and the instantaneous aging parameters of each configuration element (S300) may include: calculating the instantaneous aging parameters (S310). Generating individual aging information of each semiconductor element using the calculated instantaneous aging parameters and the representative parameters of the semiconductor chip (S330).

[0061] In S310, as an example embodiment, the aging information calculator 23 may calculate individual aging parameters of each semiconductor element in the semiconductor chip, that is, instant aging parameters. In an example embodiment, the instant aging parameters may include the probability that each semiconductor element is under stress conditions during use of the semiconductor chip, that is, the individual conduction probability.

[0062] As the aging degree of the semiconductor chip increases, the characteristics of each of the multiple semiconductor elements included in the corresponding semiconductor chip will deteriorate. For example, in a semiconductor element such as a field effect transistor (FET), the degradation of negative bias temperature instability (NBTI) or hot carrier injection (HCI) increases due to aging, so that a change in threshold voltage may occur. In this case, the degree of change in the threshold voltage of each semiconductor element may vary according to the operating time of each element. Therefore, in the method of generating an aging model according to an example embodiment, the probability that each semiconductor element is under stress conditions during the use of the semiconductor chip is used to generate aging information for each corresponding semiconductor element.

[0063] In S330, the aging information calculator 23 performs simulation using the instantaneous aging parameter of each semiconductor element calculated in S310 and the global aging parameter (e.g., effective stress time ST_eff) commonly applied to the corresponding semiconductor element, thereby generating individual aging information of each corresponding semiconductor element. The individual aging information may include characteristic degradation information (e.g., threshold voltage variation of a transistor element) due to aging of each semiconductor element, and may be calculated as a simulation result by the STA module 30.

[0064] Will use Figure 7 An exemplary circuit diagram is described in more detail Figure 6 Each operation. Figure 7 An example of a semiconductor chip 700 including four transistors, ie, first to fourth transistors m1 to m4 is shown.

[0065] Reference Figure 7 , the semiconductor chip 700 has two input terminals in1 and in2 and a single output terminal out. The semiconductor chip 700 may include a first transistor m1 and a second transistor m2 connected in series to each other and connected to the input terminals in1 and in2, respectively, and a third transistor m3 and a fourth transistor m4 connected in parallel to a drain terminal n of the second transistor m2 (e.g., having a gate electrode connected to the drain terminal n of the second transistor m2). Here, the first transistor m1 to the third transistor m3 are PMOS transistors, and the fourth transistor m4 is an NMOS transistor.

[0066] When the input is "low", the first transistor m1 to the third transistor m3 are turned on. When the input is "high", the fourth transistor m4 is turned on. Therefore, the probability of each of the transistors m1 to m4 being turned on can be calculated as the probability that the input of each transistor has a specific value. The probability P1 of the first transistor m1 being turned on is "P(in1 = 'low')", and the probability P2 of the second transistor m2 being turned on is "P(in2 = 'low')". In addition, the probability P3 of the third transistor m3 being turned on is "1-P1×P2", and the probability P4 of the fourth transistor m4 being turned on is "P1×P2".

[0067] According to an example embodiment, the aging information calculator 23 performs simulation using the effective aging time ST_eff of the corresponding semiconductor chip 700 and the probability P1 to P4 that each transistor m1 to m4 is turned on under the reference bias condition after the semiconductor chip 700 is decomposed into each transistor m1 to m4, thereby calculating the degree of characteristic degradation caused by aging of each of the transistors m1 to m4, for example, the threshold voltage changes ΔVth,m1 to ΔVth,m4. As described above, when each semiconductor element is decomposed and the simulation is performed, the parasitic resistance and parasitic capacitance components can be ignored. In this case, the file size of the netlist is reduced, thereby reducing the simulation cost.

[0068] exist Figure 7 In the example, the input and output parameter values ​​used to generate aging information can be compared to Figure 8 The same as those shown in . Figure 7 Show Figure 8 A specific example in the table of , i.e., where P1 is 0.1 and P2 is 0.5. Figure 8 As can be seen from the table therein, when the probability of each transistor m1 to m4 being turned on increases, the degree of characteristic degradation (i.e., threshold voltage variation ΔVth) due to aging of each transistor m1 to m4 increases. In addition, when the effective stress time ST_eff increases, the degree of characteristic degradation due to aging of each transistor m1 to m4 increases.

[0069] The aging model of the semiconductor chip generated based on the input parameters and the aging information calculated through the above process may be expressed as Equation 1.

[0070] [Equation 1]

[0071] ΔVth mi =F mi (ST_eff, P 0 , P 1 , ..., P n )

[0072] Here, ΔVth miRefers to the threshold voltage change of each semiconductor element in the semiconductor chip, F mi () is the aging model for each semiconductor element in the semiconductor determined by machine learning, ST_eff refers to the effective stress time to be applied to all semiconductor elements, P 0 To P n Refers to the probability value used to calculate the operating probability of each semiconductor element, that is, F mi () Using ST_eff and P i To determine each ΔVth mi .

[0073] Fig. 9 is a flow chart illustrating a method for generating an aging model of a semiconductor chip according to another example embodiment. Fig. 9 In the method for generating an aging model, multiple aging information can be used to generate an aging model of a semiconductor chip. In addition, in order to describe Fig. 9 The method of generating the aging model will be omitted or briefly described with reference to Figure 2 The described example embodiments overlap the description of the content.

[0074] Reference Figure 1 and Fig. 9 In S500 , the scenario converter 21 may extract a plurality of aging scenarios of the semiconductor chip from the aging model library 10 .

[0075] In S600 , the scenario converter 21 may aggregate the plurality of aging scenarios extracted in S500 to calculate a first aging parameter of the semiconductor chip.

[0076] The first aging parameter may be a representative parameter having a common influence on all semiconductor elements in the semiconductor chip and may be provided as a global aging parameter. In example embodiments, the first aging parameter may include an effective stress time ST_eff of the semiconductor chip.

[0077] In S700 , the aging information calculator 23 may generate first aging information based on a simulation result using the first aging parameter of the semiconductor chip calculated in S600 and the second aging parameter of the semiconductor chip.

[0078] The second aging parameter may be an individual aging parameter having an influence on the aging of each semiconductor element, and may be provided as an instant aging parameter. In an example embodiment, the second aging parameter may include a probability that each semiconductor element in the corresponding semiconductor chip is under a stress condition during use of the semiconductor chip. The second aging information is characteristic degradation information due to aging of each semiconductor element, and may include, for example, a threshold voltage change ΔVth of a transistor element.

[0079] In S800 , the aging information calculator 23 may generate second aging information based on a simulation result using the first aging parameter calculated in S700 and a third aging parameter of the semiconductor chip.

[0080] The third aging parameter may be an instantaneous aging parameter of each semiconductor element. For example, the third aging parameter may include the load capacitance ( Fig. 10A information showing the direction of change of the output voltage (or current) (“rising” or “falling”, Fig. 10B "Drop" in the output voltage (or current) and the output voltage (or current) slew information ( Fig. 10B In addition, the third aging parameter may further include an operating condition of each semiconductor element, for example, an operating voltage Vop and an operating temperature Top.

[0081] The third aging parameter may include a timing delay sensitivity of each semiconductor element. The timing delay sensitivity refers to a ratio of a timing delay variation of a semiconductor chip to a threshold voltage variation of each semiconductor element, and may be expressed as Equation 2.

[0082] [Equation 2]

[0083]

[0084] Here, "S mi " refers to the timing delay sensitivity of each semiconductor element. "rise_fall" refers to the output transition direction information of each semiconductor element (i.e., rise or fall), and "slew" refers to the output transition slew information of each semiconductor element ( Fig. 10B ), “load” refers to the output load value of each semiconductor element (e.g., output capacitance) ( Fig. 10A ), "V op ” and “T op ” refer to the operating voltage and operating temperature of each semiconductor element, respectively. “dDelay” refers to the timing delay variation of the semiconductor chip, and “dσVth.mi” refers to the variation of the deviation (σ) of the threshold voltage Vth of each semiconductor element.

[0085] The deviation (σ) of the threshold voltage Vth refers to a process deviation that may vary according to a manufacturing process of a semiconductor element, and an average value of the threshold voltage Vth may be provided from a manufacturer.

[0086] The timing delay sensitivity of each semiconductor element may be generated as an intermediate value of a characterization process in a variable free format (LVF) for semiconductor chip characterization.

[0087] In the process of generating the second aging information S800, Fig.11 Detailed examples of parameter values ​​are shown in . Fig.11, global aging parameters ST_eff and immediate aging parameters (such as P 0 , P 1 The input parameters of the aging model and the timing delay variation Δdelay may be output parameters of the corresponding aging model. In an example embodiment, the above input parameters and output parameters may be used as training data for a machine learning model, and the trained machine learning model may be set as an aging model for a semiconductor chip.

[0088] In S900, the aging model generator 25 may generate an aging model of the semiconductor chip based on the first aging information and the second aging information (S800). For example, the aging model generator 25 may generate a global aging model for predicting the aging degree of the semiconductor chip based on the correlation between the effective stress time ST_eff, the individual aging parameters (instant parameters) of each semiconductor element, and the second aging information (i.e., the timing information of the semiconductor chip).

[0089] The individual aging parameters may include the individual conduction probability P of each semiconductor element. 0 To P n , output slew information, load value, operating voltage and operating temperature. In this case, the generated individual aging model is stored in the aging model DB 15 and can be used for static timing analysis of the corresponding semiconductor chip. The aging model of the semiconductor chip generated in S900 can be expressed as Equation 3.

[0090] [Equation 3]

[0091] ΔTiming k =G k (slew, load, V op , T op ,ST_eff,P 0 , P 1 , ..., P n )

[0092] Here, “ΔTiming k ” refers to the timing information of the semiconductor chip, while “G k ()” refers to the aging model of the corresponding semiconductor chip. “slew” refers to the output transition slew information of each semiconductor element, “load” refers to the output load value (e.g., output capacitance) of each semiconductor element, and “V op ” and “T op ” refer to the operating voltage and operating temperature of each semiconductor element, respectively. “ST_eff” refers to the aging parameter (i.e., representative parameter) commonly applied to all semiconductor elements in the semiconductor chip, while P 0 To P nRefers to the probability that each semiconductor element will be under stress conditions during the use of the semiconductor chip.

[0093] As a timing effect generated due to aging of the semiconductor chip, the timing information of the semiconductor chip may include timing delay, transition information, etc. FIG. 10A to FIG. 11 The aging model G of Equation 3 corresponding to the semiconductor chip is shown when predicting information (eg, timing delay) of the semiconductor chip. k () can be expressed as Equation 4.

[0094] [Equation 4]

[0095]

[0096] in

[0097] Here, Δdelay specifies the delay variation as the aging information of the semiconductor chip, F mi () refers to the aging model of each semiconductor element in Equation 1 (with the effective aging time (ST eff ) and individual conduction probability (P i ), and the output is individual threshold voltage variation), S mi () refers to the timing delay sensitivity of each semiconductor element in equation 2.

[0098] Referring to Equation 4, the timing delay variation (i.e., F mi ()×S mi ()) is summed to calculate the timing delay variation of the semiconductor chip.

[0099] As described above, the method of generating an aging model according to example embodiments may reduce modeling cost and complexity by generating aging information using intermediate values ​​of timing delay sensitivity and LVF characterization processes instead of using a plurality of aging parameters themselves.

[0100] Fig.12 is a flowchart illustrating a static timing analysis method of a semiconductor chip according to example embodiments.

[0101] Reference Figure 1 and Fig.12 In S1000, the scenario converter 21 may load a plurality of aging scenarios from the aging model library 10. The aging model library 10 may be a logical entity, including: a netlist 11, in which the types of semiconductor elements included in the semiconductor chip and their connection relationships are defined; an aging scenario DB 13, in which the use conditions of the corresponding semiconductor chip and the aging information according to the use conditions are defined in a graphical or table format; and at least one aging model DB 15 corresponding to the semiconductor chip.

[0102] In S1100, the scenario converter 21 may obtain global aging parameters, i.e., representative parameters, to be commonly applied to multiple semiconductor elements from the multiple aging scenarios loaded in S1000. For example, the scenario converter 21 calculates the total aging degree (e.g., threshold voltage change) of the semiconductor chip through multiple aging scenarios, and projects the total aging degree into the reference aging scenario, thereby obtaining the time actually affected by aging (i.e., effective stress time) in the total use time of the corresponding semiconductor chip as a representative parameter.

[0103] In S1200, the aging information calculator 23 may calculate a first timing delay (local timing delay) using the global aging parameter calculated in S1100 and the instantaneous aging parameter of each semiconductor element. The first timing delay may be a value at a standard cell level including one or more semiconductor elements, or may be a value to be applied to each semiconductor element. For example, the aging information calculator 21 uses the effective stress time ST_eff and the probability P that each semiconductor element is under stress during use of the semiconductor chip. 0 To P n The threshold voltage variation of each corresponding semiconductor element is calculated, and the first timing delay is calculated by multiplying the corresponding threshold voltage variation of each corresponding semiconductor element and the timing delay sensitivity. In this case, the calculated first timing delay can be expressed as Equation 5.

[0104] [Equation 5]

[0105] Δdelay,mi=ΔVth,mi×S,mi

[0106] Here, "Δdelay,mi" refers to the first timing delay, "ΔVth,mi" refers to the threshold voltage change of each semiconductor element calculated using equation 1, and "S,mi" refers to the timing delay sensitivity of each semiconductor element calculated using equation 2. The method of calculating the threshold voltage change ΔVth,mi of each semiconductor element is as described above with reference to Figure 2 and Fig. 9 described.

[0107] In S1300, the aging information calculator 23 may calculate the second timing delay Δdelay by summing the first timing delays Δdelay,mi calculated in S1200. In this case, the calculated second timing delay may be expressed as Equation 6.

[0108] [Equation 6]

[0109]

[0110] Here, “Δdelay” refers to the second timing delay, and “Δdelay,mi” refers to the first timing delay calculated using Equation 5.

[0111] In S1400, the STA module 30 receives the first timing delay Δdelay,mi calculated in S1200 and the second timing delay Δdelay calculated in S1300, and uses the input information to perform static timing analysis (STA) to determine whether the semiconductor chip violates the timing constraint (e.g., whether the delay exceeds a predetermined threshold). When the design of the semiconductor chip does not violate the timing constraint, the semiconductor chip can be manufactured according to the design.

[0112] Fig.13 is a block diagram illustrating a computing system that performs a method of generating an aging model of a semiconductor chip according to example embodiments. Fig.13 , the computing system 1300 may include a processor 1310 , a memory 1330 , a storage unit 1350 , a user interface 1370 , and a display unit 1390 .

[0113] The processor 1310 controls the overall operation of the computing system 1300 and may process or execute programs and / or data stored in the memory 1330. For example, the processor 1310 may execute the STA module to generate an aging model of a semiconductor chip and perform static timing analysis of the semiconductor chip.

[0114] The processor 1310 may be implemented by hardware, software, and a combination thereof, and may include a controller, a microprocessor, and the like.

[0115] The memory 1330 may store various program codes and data for generating an aging model of a semiconductor chip and performing static timing analysis. For example, the memory 1330 may store an aging modeling module or a STA module implemented using program code. The memory 1330 may include a non-volatile memory, a volatile memory, and the like.

[0116] The storage unit 1350 may store various program codes and data for executing the method of generating an aging model according to an example embodiment. For example, the storage unit 1350 may store a netlist of a semiconductor chip or a plurality of aging scenarios. The program code stored in the storage unit 1350 is loaded into the memory 1330 to be executed by the processor 1310, and the execution result thereof may be output through the display unit 1390. The storage unit 1350 may include a hard disk drive (HDD), a solid state drive (SSD), etc.

[0117] The user interface 1370 may include various input devices such as buttons, keys, touch screens, etc. A user of the aging modeling system according to example embodiments may input and output various data required to generate an aging model (eg, aging scenarios of semiconductor chips, etc.) through the user interface 1370 .

[0118] The display unit 1390 may output various result values ​​of the aging modeling process under the control of the processor 1310. For example, the display unit 1390 may output aging information (e.g., threshold voltage variation, etc.) of the semiconductor chip generated from a plurality of aging scenarios. The display unit 1390 may include a display device such as an LCD, an OLED display, etc.

[0119] As described above, the method of generating an aging model of a semiconductor chip according to example embodiments may be performed by a user such as Fig.13 The method of generating an aging model of a semiconductor chip may be used to perform static timing analysis of various semiconductor chips, and may be used to design semiconductor chips based on the analysis results. For example, the method of generating an aging model of a semiconductor chip may be used to design various semiconductor chips included in an electronic control unit (ECU) of a vehicle or a server.

[0120] By way of summary and review, according to one or more embodiments, a global aging parameter (first aging parameter) and an individual aging parameter (second aging parameter) of each semiconductor element on the semiconductor chip may be used to generate an aging model of the semiconductor chip. According to one or more embodiments, an instantaneous aging parameter (third aging parameter) for each semiconductor element on the semiconductor chip may be used to generate an aging model. According to one or more embodiments, an aging model may be generated using the product of the individual aging parameter and the instantaneous aging parameter. According to one or more embodiments, an aging model may be generated using the sum of the products of the individual aging parameter and the instantaneous aging parameter chip. According to one or more embodiments, an aging model generated using the sum of the products of the individual aging parameter and the instantaneous aging parameter chip may be used to determine whether a semiconductor chip violates a timing constraint.

[0121] As described above, according to example embodiments, a method of generating an aging model of a semiconductor chip can significantly reduce the number of aging parameters required to generate an aging model of a semiconductor chip or semiconductor elements forming the semiconductor chip, thereby reducing modeling cost and complexity.

[0122] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art from the time of filing this application, unless otherwise specifically indicated, the features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A method for generating an aging model for use in designing a semiconductor chip, the semiconductor chip comprising a plurality of semiconductor elements, the method comprising the steps of: extracting a plurality of aging scenarios including usage conditions of the semiconductor chip from an aging model library of the semiconductor chip; calculating a first aging parameter commonly applied to each of the plurality of semiconductor components according to the plurality of aging scenarios, wherein the first aging parameter has a same value for each of the plurality of semiconductor components; and Characteristic degradation information due to aging of each of the plurality of semiconductor elements is generated through simulation using the first aging parameter and a second aging parameter, wherein a value of the second aging parameter corresponds to an individual semiconductor element of the plurality of semiconductor elements.

2. The method according to claim 1, wherein: Each of the plurality of aging scenarios includes bias information and usage time information of the semiconductor chip.

3. The method according to claim 1, wherein: The first aging parameter includes stress time information affecting characteristic degradation of the semiconductor chip.

4. The method according to claim 1, wherein: The step of calculating the first aging parameter comprises: Acquire at least one aging information from the plurality of aging scenarios; and The first aging parameter is calculated using the acquired aging information and a reference aging scenario stored in the aging model library.

5. The method according to claim 1, wherein: The second aging parameter includes a probability that each of the plurality of semiconductor elements is under a stress condition during use of the semiconductor chip.

6. The method according to claim 1, wherein: The simulation is individually performed for each of the plurality of semiconductor elements at a preset reference operating voltage and a reference operating temperature.

7. The method according to claim 1, wherein: The characteristic degradation information includes a threshold voltage variation of each of the plurality of semiconductor elements. 8 . The method according to claim 1 , further comprising the step of generating an aging model for each of the plurality of semiconductor elements based on correlation between the first aging parameter and the second aging parameter and the characteristic degradation information.

9. The method according to claim 8, wherein: The aging model is a machine learning model trained using the first aging parameter and the second aging parameter and the characteristic degradation information.

10. A method for generating an aging model for use in designing a semiconductor chip, the semiconductor chip comprising a plurality of semiconductor elements, the method comprising the steps of: Calculating a first aging parameter of the semiconductor chip according to a plurality of usage conditions defined in an aging model library of the semiconductor chip; generating characteristic degradation information due to aging of each of the plurality of semiconductor elements included in the semiconductor chip using the first aging parameter and the second aging parameter; as well as generating timing information due to aging of the semiconductor chip using characteristic degradation information of each of the plurality of semiconductor elements and a third aging parameter, wherein the first aging parameter has the same value for each of the plurality of semiconductor components, and The value of the second aging parameter corresponds to an individual semiconductor component among the plurality of semiconductor components.

11. The method according to claim 10, wherein: After merging the aging information of the semiconductor chip obtained from the plurality of usage conditions, the first aging parameter is calculated by projecting the merged aging information to a value under a preset reference usage condition.

12. The method according to claim 10, wherein: The first aging parameter includes stress time information affecting characteristic degradation of the semiconductor chip.

13. The method according to claim 10, wherein: The second aging parameter comprises a probability that each of the semiconductor elements is under a stress condition during use of the semiconductor chip.

14. The method according to claim 10, wherein: The third aging parameters include slew information, an output load value, and sensitivity information about a timing delay variation of each of the semiconductor elements.

15. The method according to claim 14, wherein: The sensitivity information is calculated in a free-changing format characterization process of the semiconductor chip. 16 . The method according to claim 10 , further comprising the step of generating an aging model of the semiconductor chip based on correlations between the first to third aging parameters and the timing information.

17. The method according to claim 16, wherein: The aging model is a machine learning model trained using the first to third aging parameters and the timing information.

18. A method for manufacturing a semiconductor chip, the method comprising the steps of: loading a plurality of aging scenarios from an aging model library of a semiconductor chip including a plurality of semiconductor elements; Acquire a global aging parameter commonly applied to the plurality of semiconductor components from the plurality of aging scenarios, wherein the global aging parameter has a same value for each semiconductor component in the plurality of semiconductor components; calculating one or more first timing delays of the semiconductor chip using the global aging parameter; calculating a second timing delay of the semiconductor chip by summing the first timing delays; determining whether the semiconductor chip violates a timing constraint using the second timing delay; and When the semiconductor chip does not violate the timing constraint, the semiconductor chip is manufactured.

19. The method according to claim 18, wherein: The global aging parameters include stress time information that affects characteristic degradation of the semiconductor chip.

20. The method according to claim 18, wherein: The first timing delay is calculated using characteristic degradation information and timing delay sensitivity information of each of the semiconductor elements.

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