Live detection clock circuit and system

Abstract

The present invention provides a power-on detection clock circuit and system, which relate to the technical field of integrated circuits. The power-on detection clock circuit includes a bias circuit, a conversion circuit, a power-on detection circuit and a clock circuit. The power-on detection circuit and the clock circuit are connected to the conversion circuit, and the clock circuit and the conversion circuit are connected to the bias circuit; the bias circuit is also connected to an external power supply, and is used to provide a bias current to the conversion circuit and input the bias current into the conversion circuit; the conversion circuit is used to convert the bias current into a conversion electrical signal and then input it into the power-on detection circuit and the clock circuit; the power-on detection circuit is used to generate a detection electrical signal based on the conversion electrical signal to detect the power state of the external power supply; the clock circuit is used to generate a clock electrical signal based on the bias circuit and the conversion electrical signal; this circuit can detect the state of the external power supply, and simplifies the clock circuit, saves chip area, reduces usage costs, and thus improves user experience.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit technology, and in particular to a live detection clock circuit and system. Background Art

[0002] With the development of integrated circuit technology, clock circuits are applied to various integrated circuits to generate system clocks so that the integrated circuits can operate normally.

[0003] However, the existing clock circuit does not have a circuit for detecting the external power supply state. Moreover, the existing clock circuit wastes a large amount of chip area due to its complex structure, thereby increasing the use cost and reducing the user experience. Summary of the Invention

[0004] In view of this, an object of the present invention is to provide a power-on detection clock circuit and system to alleviate the above technical problems.

[0005] In a first aspect, an embodiment of the present invention provides a power-on detection clock circuit, wherein the power-on detection clock circuit includes: a bias circuit, a conversion circuit, a power-on detection circuit and a clock circuit, wherein the power-on detection circuit and the clock circuit are connected to the conversion circuit, and the clock circuit and the conversion circuit are connected to the bias circuit; wherein the bias circuit is also connected to an external power supply, for providing a bias current for the conversion circuit, and inputting the bias current into the conversion circuit; the conversion circuit is used to convert the bias current into a conversion electrical signal and then input it into the power-on detection circuit and the clock circuit; the power-on detection circuit is used to generate a detection electrical signal based on the conversion electrical signal to detect the power state of the external power supply; and the clock circuit is used to generate a clock electrical signal based on the bias circuit and the conversion electrical signal.

[0006] In combination with the first aspect, an embodiment of the present invention provides a first possible implementation scheme of the first aspect, wherein the bias circuit includes a current bias circuit and a start-up circuit connected to the current bias circuit, the current bias circuit and the start-up circuit are both connected to an external power supply, the start-up circuit is also connected to a powered detection circuit, and the current bias circuit is connected to a conversion circuit; the start-up circuit is used to start the current bias circuit according to an electrical signal from the external power supply and a detection electrical signal, so that the current bias circuit generates a bias current to be input to the conversion circuit.

[0007] In combination with the first possible implementation of the first aspect, an embodiment of the present invention provides a second possible implementation of the first aspect, wherein the conversion circuit includes a first conversion circuit and a second conversion circuit, wherein the first conversion circuit and the second conversion circuit are both connected to the power detection circuit, and the second conversion circuit is also connected to the clock circuit; the first conversion circuit is used to convert the bias current into a first conversion electrical signal, and input the first conversion electrical signal to the power detection circuit; the second conversion circuit is used to convert the bias current into a second conversion electrical signal, and input the second conversion electrical signal to the power detection circuit and the clock circuit.

[0008] In combination with the second possible implementation of the first aspect, an embodiment of the present invention provides a third possible implementation of the first aspect, wherein the charged detection circuit includes a first comparator and an inverter connected to the output end of the first comparator, the negative input end of the first comparator is connected to the first conversion circuit, and the positive input end of the first comparator is connected to the second conversion circuit; the first comparator is used to calculate a comparison electrical signal based on the first conversion electrical signal and the second conversion electrical signal, and input the comparison electrical signal to the inverter; the inverter is used to invert the comparison electrical signal to obtain a detection electrical signal.

[0009] In combination with the third possible implementation of the first aspect, an embodiment of the present invention provides a fourth possible implementation of the first aspect, wherein the first conversion circuit includes a first MOS transistor and a second MOS transistor connected in sequence, the source of the first MOS transistor is connected to the drain of the second MOS transistor, the source of the second MOS transistor is grounded, the gate of the first MOS transistor and the gate of the second MOS transistor are both connected to the drain of the first MOS transistor, and the drain of the first MOS transistor is further connected to the current bias circuit and the negative input terminal of the first comparator; the first MOS transistor and the second MOS transistor are used to convert the bias current into a first conversion electrical signal.

[0010] In combination with the fourth possible implementation manner of the first aspect, an embodiment of the present invention provides a fifth possible implementation manner of the first aspect, wherein the second conversion circuit includes a third MOS transistor, a fourth MOS transistor, and a fifth MOS transistor connected in sequence, wherein the source of the third MOS transistor is connected to the drain of the fourth MOS transistor, the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, the drain of the fifth MOS transistor is grounded, the gates of the third MOS transistor, the gates of the fourth MOS transistor, and the gates of the fifth MOS transistor are all connected to the drain of the third MOS transistor, and the drain of the third MOS transistor is further connected to the current bias circuit and the positive input terminal of the first comparator; the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are used to convert the bias current into a second converted electrical signal; wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are all of the same model.

[0011] In combination with the second possible implementation of the first aspect, an embodiment of the present invention provides a sixth possible implementation of the first aspect, wherein the clock circuit includes a first output circuit, a second output circuit and a latch circuit, the first output circuit and the second output circuit are both connected to the latch circuit, and the first output circuit and the second output circuit are both connected to the current bias circuit and the second conversion circuit.

[0012] In combination with the second possible implementation of the first aspect, an embodiment of the present invention provides a seventh possible implementation of the first aspect, wherein the first output circuit includes a second comparator, a sixth MOS transistor, and a first grounding capacitor, the drain of the sixth MOS transistor is connected to the negative input terminal of the second comparator and the current bias circuit, the source of the sixth MOS transistor is connected to the positive input terminal of the second comparator and the first grounding capacitor, the gate of the sixth MOS transistor is connected to the second conversion circuit, and the output terminal of the second comparator is connected to the latch circuit.

[0013] In combination with the seventh possible implementation of the first aspect, an embodiment of the present invention provides an eighth possible implementation of the first aspect, wherein the second output circuit includes a third comparator, a seventh MOS tube, and a second grounding capacitor, the drain of the seventh MOS tube is connected to the negative input terminal of the third comparator and the current bias circuit, the source of the seventh MOS tube is connected to the positive input terminal of the third comparator and the second grounding capacitor, the gate of the seventh MOS tube is connected to the second conversion circuit, and the output terminal of the third comparator is connected to the latch circuit; wherein the second comparator and the third comparator are of the same model, the sixth MOS tube and the seventh MOS tube are of the same model, and the first grounding capacitor and the second grounding capacitor are of the same model.

[0014] In a second aspect, an embodiment of the present invention further provides a power-on detection clock system, wherein the power-on detection clock system is configured with the above-mentioned power-on detection clock circuit.

[0015] The embodiments of the present invention bring the following beneficial effects:

[0016] An embodiment of the present invention provides a power-on detection clock circuit and system, which includes a bias circuit, a conversion circuit, a power-on detection circuit and a clock circuit. The power-on detection circuit and the clock circuit are connected to the conversion circuit, and the clock circuit and the conversion circuit are connected to the bias circuit; the bias circuit is also connected to an external power supply, and is used to provide a bias current to the conversion circuit and input the bias current into the conversion circuit; the conversion circuit is used to convert the bias current into a conversion electrical signal and then input it into the power-on detection circuit and the clock circuit; the power-on detection circuit is used to generate a detection electrical signal based on the conversion electrical signal to detect the power status of the external power supply; the clock circuit is used to generate a clock electrical signal based on the bias circuit and the conversion electrical signal; this circuit can detect the status of the external power supply, and simplify the clock circuit, thereby saving chip area, reducing usage costs, and improving user experience.

[0017] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0018] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 A schematic structural diagram of a power-on detection clock circuit provided by an embodiment of the present invention;

[0021] Figure 2 A schematic structural diagram of another power-on detection clock circuit provided by an embodiment of the present invention;

[0022] Figure 3 A circuit diagram of a bias circuit provided by an embodiment of the present invention;

[0023] Figure 4 A circuit diagram of a conversion circuit and a charged detection circuit provided by an embodiment of the present invention;

[0024] Figure 5 A circuit diagram of a clock circuit provided by an embodiment of the present invention;

[0025] Figure 6 A timing diagram of an embodiment of the present invention is provided. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present invention.

[0027] Currently, existing clock circuits lack circuitry for detecting the external power supply status. Furthermore, their complex structures waste a significant amount of chip area, increasing operating costs and reducing user experience. Therefore, the embodiments of the present invention provide a live detection clock circuit and system that can alleviate these technical issues.

[0028] To facilitate understanding of this embodiment, a power-on detection clock circuit disclosed in an embodiment of the present invention is first introduced in detail.

[0029] Example 1:

[0030] The embodiment of the present invention provides a power detection clock circuit, such as Figure 1 A schematic diagram of a live detection clock circuit is shown in FIG. Figure 1 As shown, the power detection clock circuit includes: a bias circuit 100, a conversion circuit 101, a power detection circuit 102 and a clock circuit 103. The power detection circuit 102 and the clock circuit 103 are connected to the conversion circuit 101, and the clock circuit 103 and the conversion circuit 101 are connected to the bias circuit 100.

[0031] Specifically, the bias circuit is also connected to the external power supply, used to provide a bias current for the conversion circuit, and input the bias current into the conversion circuit; the conversion circuit is used to convert the bias current into a conversion electrical signal and then input it into the charged detection circuit and the clock circuit; the charged detection circuit is used to generate a detection electrical signal based on the conversion electrical signal to detect the charged state of the external power supply; the clock circuit is used to generate a clock electrical signal based on the bias circuit and the conversion electrical signal.

[0032] In specific implementation, the powered detection circuit in the above-mentioned powered detection clock circuit can detect the powered state of the external power supply in real time, thereby preventing circuit damage caused by power failure of the external power supply; further, the existing clock circuit uses an external reference voltage to generate a clock signal, while in this circuit, a bias circuit and a conversion circuit are used to generate two comparison voltages in the clock circuit, so that the clock circuit can generate a clock signal, thereby avoiding the circuit that uses an external reference voltage to generate a clock signal. Therefore, the powered detection clock circuit provided in this embodiment saves chip area and reduces overall power consumption.

[0033] An embodiment of the present invention provides a power-on detection clock circuit, which includes a bias circuit, a conversion circuit, a power-on detection circuit and a clock circuit. The power-on detection circuit and the clock circuit are connected to the conversion circuit, and the clock circuit and the conversion circuit are connected to the bias circuit; the bias circuit is also connected to an external power supply, and is used to provide a bias current to the conversion circuit and input the bias current into the conversion circuit; the conversion circuit is used to convert the bias current into a conversion electrical signal and then input it into the power-on detection circuit and the clock circuit; the power-on detection circuit is used to generate a detection electrical signal based on the conversion electrical signal to detect the power status of the external power supply; the clock circuit is used to generate a clock electrical signal based on the bias circuit and the conversion electrical signal; the circuit can be in working condition all the time when the circuit enters low power consumption and sleep mode, providing an ultra-low power consumption clock for chip wake-up and real-time detection of the external power supply. The circuit saves chip area, reduces usage cost, and thus improves user experience.

[0034] Figure 2 FIG. 1 shows a schematic diagram of another structure of a power-on detection clock circuit. Figure 2 As shown, the bias circuit includes a current bias circuit 200 and a start-up circuit 201 connected to the current bias circuit. Both the current bias circuit and the start-up circuit are connected to an external power supply Vc. The start-up circuit 201 is also connected to a charged detection circuit 102, and the current bias circuit 200 is connected to a conversion circuit 101. The start-up circuit is used to start the current bias circuit according to an electrical signal from an external power supply and a detection electrical signal, so that the current bias circuit generates a bias current to be input to the conversion circuit.

[0035] For ease of understanding, Figure 3 A circuit diagram of a bias circuit is shown, as Figure 3As shown, the circuit on the left side of the dotted line is a current bias circuit, and the circuit on the right side of the dotted line is a startup circuit, wherein the current bias circuit includes MOS transistors M1, M2, M3, and M4. The sources of M3 and M4 are all connected to an external power supply, and the gate of M3 is connected to the gate and drain of M4, the drain of M3 is connected to the drain of M1, and the drain of M4 is also connected to the drain of M2; the gate and drain of M1 are both connected to the gate of M2, the source of M2 is also grounded through a resistor R0, and the source of M1 is grounded, wherein, as shown in FIG. Figure 3 As shown, the voltage between the gate and drain of M4 is Vbp1, and the voltage between the gate and drain of M1 is Vgs1.

[0036] Specifically, if Figure 3 As shown, the startup circuit includes MOS transistors M5, M6, M7, M8, and M9, wherein the sources of M7 and M5 are connected to an external power supply, the drain of M7 is connected to the gate of M5 and the drain of M8; the drain of M5 is connected to the drain of M6 and the gate of M9; the drain of M9 is connected to the drains of M4 and M2, and the sources of M9, M6, and M8 are all grounded. The gate of M7 is driven by the above-mentioned Vbp1, the gate of M6 is driven by the above-mentioned Vgs1, and the gate of M8 is driven by the inverted electrical signal Pon1 of the detection electrical signal generated by the charged detection circuit; when Pon1 is 1, Vbp1 is 1, and Vgs1 is 0, the startup circuit starts the current bias circuit to enable the current bias circuit to generate a bias current I0; when Pon1 is 0, Vbp1 is 0, and Vgs1 is 1, it indicates that the current bias circuit can operate normally, and the startup circuit is then turned off to save energy.

[0037] like Figure 2 As shown, the conversion circuit includes a first conversion circuit 202 and a second conversion circuit 203, wherein the first conversion circuit and the second conversion circuit are both connected to the power detection circuit 102, and the second conversion circuit is also connected to the clock circuit 103; the first conversion circuit is used to convert the bias current into a first conversion electrical signal, and input the first conversion electrical signal to the power detection circuit; the second conversion circuit is used to convert the bias current into a second conversion electrical signal, and input the second conversion electrical signal to the power detection circuit and the clock circuit.

[0038] In actual use, such as Figure 2As shown, the charged detection circuit includes a first comparator 204 and an inverter 205 connected to the output end of the first comparator, the negative input end of the first comparator is connected to the first conversion circuit 202, and the positive input end of the first comparator is connected to the second conversion circuit 203; the first comparator is used to calculate a comparison electrical signal based on the first conversion electrical signal and the second conversion electrical signal, and input the comparison electrical signal to the inverter; the inverter is used to invert the comparison electrical signal to obtain a detection electrical signal.

[0039] For ease of understanding, Figure 4 A schematic diagram of a conversion circuit and a charged detection circuit is shown, as shown in FIG. Figure 4 As shown, the first conversion circuit includes a first MOS transistor M9 and a second MOS transistor M10 connected in sequence. The source of the first MOS transistor is connected to the drain of the second MOS transistor, the source of the second MOS transistor is grounded, the gate of the first MOS transistor and the gate of the second MOS transistor are both connected to the drain of the first MOS transistor, and the drain of the first MOS transistor is also connected to the current bias circuit 200 and the negative input terminal of the first comparator 204. The first MOS transistor and the second MOS transistor are used to convert the bias current into a first conversion electrical signal Vref1.

[0040] Further, if Figure 4 As shown, the second conversion circuit includes a third MOS transistor M11, a fourth MOS transistor M12, and a fifth MOS transistor M13 connected in sequence, wherein the source of the third MOS transistor is connected to the drain of the fourth MOS transistor, the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, the drain of the fifth MOS transistor is grounded, the gates of the third MOS transistor, the gates of the fourth MOS transistor, and the gates of the fifth MOS transistor are all connected to the drain of the third MOS transistor, and the drain of the third MOS transistor is further connected to the current bias circuit 200 and the positive input terminal of the first comparator 204; the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are used to convert the bias current into a second conversion electrical signal Vref2; wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are all of the same model.

[0041] In specific use, the first comparator 204 is a hysteresis comparator. During the detection process of power-on reset and power-off reset of the external power supply using the power-on detection circuit, a very small bias current is used to generate Vref1 and Vref2 in the first conversion circuit and the second conversion circuit, respectively. Because the bias current flowing into the first and second conversion circuits is the same, but the number of MOS transistors in the first and second conversion circuits is different, a voltage difference exists between Vref1 and Vref2 during the stable state. During the power-on process, Vref1 and Vref2 also slowly rise until the difference between the two exceeds the flip-up threshold of the first comparator, causing the comparison signal to flip, and ultimately the detection signal to change from low to high. Because the first comparator 204 is a hysteresis comparator, the power-on reset voltage and the power-off reset voltage are different in the power-on detection circuit. In this embodiment, the flip-up threshold of the first comparator is slightly higher than the flip-down threshold. This is to ensure that small ripples on the power supply during the power-on process or normal operation will not easily trigger a power-off.

[0042] Specifically, if Figure 2 As shown, the clock circuit includes a first output circuit 206, a second output circuit 207 and a latch circuit 208. The first output circuit and the second output circuit are both connected to the latch circuit. The first output circuit and the second output circuit are both connected to the current bias circuit 200 and the second conversion circuit 203.

[0043] For ease of understanding, Figure 5 A circuit diagram of a clock circuit is shown, Figure 5 As shown, the first output circuit includes a second comparator CMP1, a sixth MOS transistor Mc1 and a first grounding capacitor C1. The drain of the sixth MOS transistor is connected to the negative input terminal of the second comparator and the current bias circuit 200. The source of the sixth MOS transistor is connected to the positive input terminal of the second comparator and the first grounding capacitor. The gate of the sixth MOS transistor is connected to the second conversion circuit. The output terminal of the second comparator is connected to the latch circuit 208. Figure 5 As shown, the gate of the sixth MOS transistor is driven by the second conversion electrical signal Vref2 generated by the second conversion circuit.

[0044] Further, if Figure 5As shown, the second output circuit includes a third comparator CMP2, a seventh MOS transistor Mc2, and a second grounding capacitor C2. The drain of the seventh MOS transistor is connected to the negative input terminal of the third comparator and the current bias circuit 200, the source of the seventh MOS transistor is connected to the positive input terminal of the third comparator and the second grounding capacitor, the gate of the seventh MOS transistor is connected to the second conversion circuit, and the output terminal of the third comparator is connected to the latch circuit 208. The second comparator and the third comparator are of the same model, the sixth MOS transistor and the seventh MOS transistor are of the same model, and the first grounding capacitor and the second grounding capacitor are of the same model.

[0045] In actual use, the output electrical signals generated by the first output circuit and the second output circuit are differential mode signals. For ease of understanding, Figure 6 A timing relationship diagram is shown, such as Figure 6 As shown, out1 is the electrical signal generated by the first output circuit, out2 is the electrical signal generated by the second output circuit, Vc1 and Vref_c1 represent the source voltage and drain voltage of Mc1, respectively. Specifically, the source voltage Vc1 and the drain voltage Vref_c1 of Mc1 are used as the input of the second comparator CMP1. During the process of the current bias circuit 200 charging the capacitor C1, the source voltage Vc1 and the drain voltage Vref_c1 of Mc1 gradually increase, and Mc1 gradually enters the saturation region from the linear region. The difference between Vc1 and Vref_c1 will gradually increase. When the difference exceeds the comparison threshold of the second comparator, out1 changes from high to low. In order to reduce power consumption, after completing the charging of C1, the part of the circuit that generates out1, that is, the first output circuit, is turned off by the latch circuit. At this time, the part of the circuit that generates out2 starts to work.

[0046] Similarly, the operating process of the second output circuit that generates out2 is the same as that of the first output circuit. Specifically, the source voltage Vc2 and the drain voltage Vref_c2 of Mc2 are used as inputs of the third comparator CMP2. As the current bias circuit 200 charges the capacitor C2, the source voltage Vc2 and the drain voltage Vref_c2 of Mc2 gradually increase, and Mc2 gradually enters the saturation region from the linear region. The difference between Vc2 and Vref_c2 gradually increases. When the difference exceeds the comparison threshold of the third comparator, out2 changes from high to low. To reduce power consumption, after charging C2 is completed, the part of the circuit that generates out2, namely the second output circuit, is turned off by the latch circuit. At this time, the first output circuit resumes operation, and this cycle repeats to generate the 32K clock signal.

[0047] Typically, existing clock circuits require a fixed reference voltage and then compare the voltage generated by charging a capacitor with the reference voltage to generate an output clock. However, this structure requires a bias circuit in the circuit that can generate a stable reference voltage. Therefore, existing clock circuits waste chip area and power consumption. In this embodiment, the voltage across the source and drain of the MOS transistor is used as the input of the comparator to output the clock, thereby saving chip area. At the same time, because the output circuit is shut down immediately after completing charging the capacitor, power consumption is reduced.

[0048] Example 2:

[0049] An embodiment of the present invention provides a live detection clock system, wherein the live detection clock system is configured with the above-mentioned live detection clock circuit.

[0050] The live detection clock system provided by the embodiment of the present invention has the same technical features as the live detection clock circuit provided by the above embodiment, and therefore can also solve the same technical problems and achieve the same technical effects.

[0051] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working process of the system described above can refer to the corresponding process in the aforementioned circuit embodiment, and will not be repeated here.

[0052] In addition, in the description of the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0053] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0054] Finally, it should be noted that the above embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A live detection clock circuit, characterized in that: The charged detection clock circuit includes: a bias circuit, a conversion circuit, a charged detection circuit and a clock circuit, wherein the charged detection circuit and the clock circuit are connected to the conversion circuit, and the clock circuit and the conversion circuit are connected to the bias circuit; Wherein, the bias circuit is further connected to an external power supply, for providing a bias current for the conversion circuit, and inputting the bias current into the conversion circuit; The conversion circuit is used to convert the bias current into a converted electrical signal and then input it into the charged detection circuit and the clock circuit; The charged detection circuit is used to generate a detection electrical signal according to the converted electrical signal, so as to detect the charged state of the external power supply; The clock circuit is used to generate a clock electrical signal according to the bias circuit and the converted electrical signal; The bias circuit includes a current bias circuit and a startup circuit connected to the current bias circuit, the current bias circuit and the startup circuit are both connected to the external power supply, the startup circuit is also connected to the charged detection circuit, and the current bias circuit is connected to the conversion circuit; The conversion circuit includes a first conversion circuit and a second conversion circuit, wherein the first conversion circuit and the second conversion circuit are both connected to the charged detection circuit, and the second conversion circuit is also connected to the clock circuit; The charged detection circuit includes a first comparator and an inverter connected to the output end of the first comparator, the negative input end of the first comparator is connected to the first conversion circuit, and the positive input end of the first comparator is connected to the second conversion circuit; The first conversion circuit includes a first MOS transistor and a second MOS transistor connected in sequence, wherein the source of the first MOS transistor is connected to the drain of the second MOS transistor, the source of the second MOS transistor is grounded, the gates of the first MOS transistor and the second MOS transistor are both connected to the drain of the first MOS transistor, and the drain of the first MOS transistor is further connected to the current bias circuit and the negative input terminal of the first comparator; the first MOS transistor and the second MOS transistor are used to convert the bias current into a first conversion electrical signal; The second conversion circuit includes a third MOS transistor, a fourth MOS transistor, and a fifth MOS transistor connected in sequence, wherein the source of the third MOS transistor is connected to the drain of the fourth MOS transistor, the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, the drain of the fifth MOS transistor is grounded, the gates of the third MOS transistor, the gates of the fourth MOS transistor, and the gates of the fifth MOS transistor are all connected to the drain of the third MOS transistor, and the drain of the third MOS transistor is also connected to the current bias circuit and the positive input terminal of the first comparator; the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are used to convert the bias current into a second converted electrical signal; wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are all of the same model; The clock circuit includes a first output circuit, a second output circuit and a latch circuit, wherein the first output circuit and the second output circuit are both connected to the latch circuit, and the first output circuit and the second output circuit are both connected to the current bias circuit and the second conversion circuit; The first output circuit includes a second comparator, a sixth MOS transistor and a first grounded capacitor, the drain of the sixth MOS transistor is connected to the negative input terminal of the second comparator and the current bias circuit, the source of the sixth MOS transistor is connected to the positive input terminal of the second comparator and the first grounded capacitor, the gate of the sixth MOS transistor is connected to the second conversion circuit, and the output terminal of the second comparator is connected to the latch circuit; The second output circuit includes a third comparator, a seventh MOS transistor, and a second grounding capacitor, wherein the drain of the seventh MOS transistor is connected to the negative input terminal of the third comparator and the current bias circuit, the source of the seventh MOS transistor is connected to the positive input terminal of the third comparator and the second grounding capacitor, the gate of the seventh MOS transistor is connected to the second conversion circuit, and the output terminal of the third comparator is connected to the latch circuit; The second comparator and the third comparator are of the same model, the sixth MOS transistor and the seventh MOS transistor are of the same model, and the first grounding capacitor and the second grounding capacitor are of the same model.

2. The power detection clock circuit according to claim 1, characterized in that: The startup circuit is used to start the current bias circuit according to the electrical signal of the external power supply and the detection electrical signal, so that the current bias circuit generates the bias current to be input to the conversion circuit.

3. The power detection clock circuit according to claim 2, characterized in that: The first conversion circuit is used to convert the bias current into a first conversion electrical signal, and input the first conversion electrical signal into the charged detection circuit; The second conversion circuit is used to convert the bias current into a second conversion electrical signal, and input the second conversion electrical signal into the charged detection circuit and the clock circuit.

4. The power detection clock circuit according to claim 3, characterized in that: The first comparator is used to calculate a comparison electrical signal according to the first converted electrical signal and the second converted electrical signal, and input the comparison electrical signal to the inverter; The inverter is used to perform inversion processing on the comparison electrical signal to obtain the detection electrical signal.

5. A live detection clock system, characterized in that: The power-on detection clock system is equipped with the power-on detection clock circuit according to any one of claims 1 to 4.

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