Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same, wherein the method for manufacturing the semiconductor device comprises forming a first conductive component in a dielectric layer, selectively etching back the first conductive component, forming an etch stop layer on the first conductive component and the dielectric layer, wherein the height of the etch stop layer on the first conductive component is different from the height of the etch stop layer on the dielectric layer, patterning the etch stop layer to expose the top surface of the first conductive component, laterally etching the etch stop layer, and depositing a conductive material on the first conductive component to form a second conductive component.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to a semiconductor device with improved electrical connection and a method for manufacturing the same. Background Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller, more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This process of shrinking dimensions often brings benefits, such as increased production efficiency and lower associated costs.

[0003] The shrinking dimensions also increase the complexity of IC processes and manufacturing, and similar developments are needed in IC processes and manufacturing to achieve these advances. For example, as the width of interconnects continues to shrink, the contact area between the barrier layer at the bottom of the via and the metal conductor becomes smaller and smaller, which results in higher contact resistance between the via and the metal conductor. It is especially desirable to reduce this contact resistance as the technology node shrinks. Summary of the invention

[0004] A method for manufacturing a semiconductor device includes: forming a first conductive component in a dielectric layer. Selectively etching back the first conductive component. Forming an etch stop layer on the first conductive component and the dielectric layer, wherein the height of the etch stop layer on the first conductive component is different from the height of the etch stop layer on the dielectric layer. Patterning the etch stop layer to expose the top surface of the first conductive component. Laterally etching the etch stop layer. Depositing a conductive material on the first conductive component to form a second conductive component.

[0005] A method for manufacturing a semiconductor device includes: performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer, performing a second etching process to remove the etch stop layer and expose a top surface of a lower component, performing a third etching process to laterally recess the etch stop layer and deposit a conductive material on the lower component to form a conductive component directly contacting the lower component.

[0006] A semiconductor device includes: a first conductive component embedded in a first dielectric layer such that a top surface of the first dielectric layer is higher than a top surface of the first conductive component. A contact etch stop layer (CESL) is disposed on the first dielectric layer. A second conductive component is embedded in the second dielectric layer. The second dielectric layer is disposed on the CESL, and the second conductive component extends through the CESL and is in direct contact with the first conductive component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description in conjunction with the accompanying drawings of the specification can better understand the content of the embodiments of this article. It should be emphasized that according to standard practices in the industry, many components (features) are not drawn to scale. In fact, in order to clearly discuss, the sizes of various components may be arbitrarily enlarged or reduced.

[0008] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G to Figure 1H is a diagram showing an illustrative process for forming an improved electrical connection between two conductive components, according to one embodiment of principles described herein.

[0009] Figure 2A to Figure 2B is a diagram showing various underlying components according to one embodiment of principles described herein.

[0010] Figure 3 is a diagram showing more detail of a conductive feature formed on an underlying feature, according to one embodiment of principles described herein.

[0011] Figure 4 is a flow chart showing an illustrative method for forming an improved electrical connection between two conductive components, according to one embodiment of principles described herein.

[0012] Figure 5 is a flow chart showing an illustrative method for forming an improved electrical connection between two conductive components, according to one embodiment of principles described herein.

[0013] Description of reference numerals:

[0014] 102~dielectric layer;

[0015] 104~conductive parts;

[0016] 106~Etching process;

[0017] 108~Deposition process;

[0018] 110~CESL;

[0019] 112~dielectric layer;

[0020] 114~Etching process;

[0021] 115~groove;

[0022] 116~Etching process;

[0023] 118~Etching process;

[0024] 120~Deposition process;

[0025] 122~conductive parts;

[0026] 202~gate device;

[0027] 204~gate device;

[0028] 302 ~ upper part;

[0029] 304~middle part;

[0030] 306~lower part;

[0031] 308~width;

[0032] 310~width;

[0033] 312~width;

[0034] 400~Method;

[0035] 402-412 ~ Process;

[0036] 500~method;

[0037] 502-508~Process. DETAILED DESCRIPTION

[0038] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific embodiments or examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, component sizes are not limited to the disclosed ranges or values, but may depend on process conditions and / or desired characteristics of the device. Furthermore, if the description mentions that the first component is formed on the second component, it may include an embodiment in which the first and second components are directly connected, and it may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not directly connected. In addition, the embodiments of the present invention may repeat component symbols and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0039] Furthermore, spatially relative terms may be used herein, such as "under", "beneath", "below", "above", "above" and other similar terms may be used herein to describe the relationship between an element or component as shown in the figures and other elements or components. Such spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the drawings. When the device is rotated to other orientations (rotated 90 degrees or other orientations), the spatially relative descriptions used herein may also be interpreted based on the rotated orientation.

[0040] As described above, the shrinking of integrated circuits has also increased the complexity of IC processing and manufacturing, and similar developments in IC processing and manufacturing are needed to achieve these advances. For example, as the width of the interconnect line continues to shrink, the contact area between the bottom layer of the via and the metal conductor becomes smaller and smaller, which results in a higher contact resistance between the via and the metal conductor. Especially as the technology node shrinks, it is more desirable to reduce this contact resistance. According to the principles described in this article, the connection between two conductive components is improved by performing a lateral recess on the etch stop layer before depositing the material for one of the conductive components. This increases the contact area between the two conductive components, thereby reducing the contact resistance.

[0041] In one embodiment, after forming a first conductive component in a first dielectric layer (e.g., an interlayer dielectric (ILD) layer), a selective etching process is performed to selectively etch back the first conductive component. Next, an etch stop layer is formed on the first conductive component and the first dielectric layer. A second dielectric layer is then formed on the etch stop layer. The second dielectric layer and the etch stop layer are then patterned to expose the first conductive component. Then, a lateral etching process is performed to laterally etch the etch stop layer. After the lateral etching process, an upper conductive component is formed on the conductive component. Because the etch stop layer is laterally etched during the lateral etching process, the conductive component below has more contact area with the newly formed conductive component. This reduces the contact resistance between the conductive component below and the newly formed conductive component.

[0042] The principles described herein also provide other advantages. For example, the corners of the etch stop layer protect the bridge between the conductive component below and the conductive component above. In addition, since a portion of the conductive component below is replaced by the conductive component above, the sheet resistance can be reduced.

[0043] Figures 1A to 1H An illustrative process for forming an improved electrical connection between two conductive components is shown. Figure 1AConductive features 104 are shown formed within a dielectric layer, such as an interlayer dielectric (ILD) layer. Dielectric layer 102 may be made of a nitride material, such as silicon nitride. Dielectric layer 102 may be formed on a semiconductor substrate. The semiconductor substrate may be a silicon substrate. However, in some embodiments, the substrate may be a silicon germanium substrate. Other types of semiconductor substrates are also contemplated for use.

[0044] In one embodiment, the conductive component 104 may be a via contact. A via contact is a conductive structure that connects a contact (e.g., a gate contact or a source / drain contact) to an upper conductive component (e.g., a metal interconnect). In some embodiments, the conductive component 104 may be a via connected to a metal interconnect layer below. Other types of conductive structures may also be considered. The conductive component may include a metal material, such as copper, cobalt, nickel, tungsten, or ruthenium.

[0045] Conductive component 104 can be formed in one of many ways. In one embodiment, a photolithographic patterning process is applied to dielectric layer 102. For example, a photoresist can be applied to dielectric layer 102. Then, the photoresist can be exposed to a light source through a mask. After exposure, the photoresist can be developed in a developer solution. This will remove the exposed or unexposed portions of the photoresist. Then, the dielectric layer 102 below can be subjected to an etching process through the exposed portion of the photoresist. The etching process forms a groove in dielectric layer 102. This groove can then be filled with a conductive material such as a metal material to form conductive component 104.

[0046] Figure 1B An etching process 106 is shown for selectively etching back the conductive features 104. The etching process is selective because it is designed to primarily remove the conductive features 104 without substantially affecting the dielectric layer 102. The etching process 106 may remove material from the conductive features 104 to a thickness of about 0.1 to 50 nm. After the etching process 106, the top surface of the conductive features 104 will be lower than the top surface of the dielectric layer 102. In one embodiment, the etching process 106 may be one of a variety of etching processes, for example, the etching process 106 may be a wet etching process. In one embodiment, the etching process 106 is a dry etching process.

[0047] Figure 1CA deposition process 108 is shown to form a contact etch-stop layer (CESL) 110. The CESL 110 may be used to provide better control of a subsequently performed etching process to avoid unnecessary etching processes on the conductive features 104 or the dielectric layer 102. The CESL 110 has a top surface with a portion above the conductive features 104 being lower than a portion above the dielectric layer 102.

[0048] The CESL 110 may be made of a variety of materials. In one embodiment, the CESL may include a high dielectric constant material such as silicon oxynitride (SiON), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), zirconium oxide (ZrO2), an aluminum-containing oxide layer, a nitrogen-containing oxide layer, an oxynitride, a metal oxide dielectric, a hafnium-containing oxide, a tantalum-containing oxide, a titanium-containing oxide, a chromium-containing oxide, an aluminum-containing oxide, a lanthanum-containing oxide, or other high dielectric constant materials. The CESL may be a different dielectric material than the dielectric layer 102 or the metal gate spacer used to form the gate device. The CESL may be made of multiple dielectric layers.

[0049] Figure 1D A second dielectric layer 112 is shown formed on CESL 110. In some embodiments, dielectric layer 112 may be made of the same material as dielectric layer 102. However, in some embodiments, the material of dielectric layer 112 may be different than dielectric layer 102. The dielectric layer may include a low-k dielectric material such as silicon oxide or silicon nitride.

[0050] Figure 1E An etching process 114 is shown to form trenches 115 in the second dielectric layer 112. The etching process 114 may be a dry etching process. The etching process 114 may use a fluorine-based etchant. The etching process 114 may be performed as part of a photolithographic patterning process. Thus, the etching process 114 is applied only to certain portions of the dielectric layer 112. The etching process is performed until the CESL 110 is reached. This is because the etching process 114 is selective and the materials of the CESL and the dielectric layer 112 are selected such that the etching process 114 removes the dielectric layer without substantially affecting the CESL 110.

[0051] Figure 1F Another etching process 116 is shown to remove the CESL layer. In one embodiment, the etching process 116 is a dry etching process. The dry etching process is anisotropic. In other words, the etching process etches in a single direction. The etching process 116 may use a chlorine-based etchant. The etching process 116 removes the CESL 110 to expose the top surface of the conductive feature 104. However, at this time, the entire top surface of the conductive feature 104 is not exposed.

[0052] Figure 1G Another etching process 118 is shown that laterally recesses the CESL 110 to expose more of the top surface of the conductive features. The lateral etching process may be an isotropic etching process, such as a wet etching process. In some embodiments, the etching process 118 may use an ammonia-based etchant or a standard cleaning solution SC1.

[0053] Figure 1H A deposition process 120 is shown to form a second conductive feature 122 within the trench 115. The conductive feature 122 may include a metallic material, such as copper, cobalt, nickel, tungsten, or ruthenium. Because the CESL 110 is laterally etched during the etching process 118, there is more contact area between the underlying conductive feature 104 and the newly formed conductive feature 122. This reduces the contact resistance between the underlying conductive feature 104 and the newly formed conductive feature 122. In some embodiments, after forming the conductive feature 122, a chemical mechanical polish (CMP) process may be performed to planarize the top surface of the conductive feature 122 and the dielectric layer 112.

[0054] Because the etch stop layer is laterally etched during the lateral etching process, there is more contact area between the conductive component below and the newly formed conductive component. This reduces the contact resistance between the conductive component below and the newly formed conductive component. In addition, the corners of the etch stop layer protect the bridge between the conductive component below and the conductive component above. In addition, since a portion of the conductive component below is replaced by the conductive component above, the sheet resistance can be reduced.

[0055] When using the processes described herein, the CESL 110 has a tapered portion where it contacts the conductive feature 122. Specifically, the tapered portion extends from the top surface of the dielectric layer 102 downward toward the first conductive feature 104. In some implementations, the apex of the tapered portion can contact the conductive feature 104. In some implementations, the apex of the tapered portion may not extend to the conductive feature 104.

[0056] Figure 2A-2B Displays various components below. Figure 2A An example is shown where the lower conductive component is a source / drain component. In this case, the upper conductive component 122 can be a source / drain contact adjacent to the gate device 202. The gate device 202 can have a top surface that is coplanar or at the same level as the top surface of the upper conductive component 122. In some embodiments, the source / drain component can be an epitaxially grown source / drain component. The source / drain component can include a semiconductor material such as silicon or silicon germanium. The source / drain component can be doped with n-type or p-type dopants.

[0057] In one embodiment, after forming the source / drain component, a selective etching process is performed to selectively etch back the source / drain component. Next, an etch stop layer is formed on the source / drain component and the first dielectric layer. Then a second dielectric layer is formed on the etch stop layer. Then the second dielectric layer and the etch stop layer are patterned to expose the source / drain component. Then, a lateral etching process is performed to etch the etch stop layer laterally. After the lateral etching process, an upper conductive component is formed on the source / drain component. Because the etch stop layer is etched laterally during the lateral etching process, there is more contact area between the source / drain component and the newly formed conductive component. This reduces the contact resistance between the source / drain component and the newly formed conductive component.

[0058] Figure 2B An illustrative embodiment is shown in which the underlying conductive feature is a gate device 204. In this embodiment, the gate device 204 is recessed as described above. Next, a layer of CESL 110 is placed over the recessed gate device 204 and dielectric layer 102. By applying the principles described herein to the case where the underlying conductive feature is a gate device, better contact can be made between the gate device 204 and the gate contact (e.g., 122).

[0059] In one embodiment, after forming a gate device in a dielectric layer (e.g., an ILD), a selective etching process is performed to selectively etch back the gate device. Next, an etch stop layer is formed on the gate device and the first dielectric layer. A second dielectric layer is then formed on the etch stop layer. The second dielectric layer and the etch stop layer are then patterned to expose the gate device. A lateral etching process is then performed to laterally etch the etch stop layer. After the lateral etching process, an upper conductive component is formed on the gate component. Because the etch stop layer is laterally etched during the lateral etching process, there is more contact area between the gate component and the newly formed conductive component. This reduces the contact resistance between the gate component and the newly formed conductive component.

[0060] Figure 3 More details of the conductive features formed on the underlying feature 104 are shown. In particular, Figure 3 Various dimensional relationships of the upper conductive component 122 produced by applying the principles described herein are shown. In this embodiment, the conductive component 122 has an upper portion 302, a middle portion 304, and a lower portion 306. The width 312 of the lower portion 306 is greater than the width 310 of the middle portion 304. In addition, the width 308 of the upper portion 302 is greater than the width 310 of the middle portion 304 and the width 312 of the lower portion 306.

[0061] Figure 4A flow chart showing an illustrative method for forming an improved electrical connection between two conductive components. According to the present embodiment, method 400 includes a process 402 for forming a first conductive component (e.g., 104) within a dielectric layer (e.g., 102). The dielectric layer can be made of a nitride material such as silicon nitride. The dielectric layer can be formed on a semiconductor substrate. The semiconductor substrate can be a silicon substrate. However, in some embodiments, the substrate can be a silicon germanium substrate. Other types of semiconductor substrates are also contemplated.

[0062] In one embodiment, the conductive component can be a via contact. A via contact is a conductive structure that connects a contact (e.g., a gate contact or a source / drain contact) to an upper conductive component (e.g., a metal interconnect). In some embodiments, the conductive component can be a via to an underlying metal interconnect layer. Other types of conductive structures are also contemplated.

[0063] The conductive component can be formed in one of a variety of ways. In one embodiment, a photolithography patterning process is applied to the dielectric layer. For example, a photoresist can be applied to the dielectric layer. Then, the photoresist can be exposed to a light source through a mask. After exposure, the photoresist can be developed in a developer solution. This will remove the exposed or unexposed portions of the photoresist. The dielectric layer below can then be subjected to an etching process through the exposed portions of the photoresist. The etching process forms a groove in the dielectric layer. This groove can then be filled with a conductive material, such as a metallic material, to form the conductive component.

[0064] The method 400 also includes a process 404 for selectively etching back the conductive component. The etching process is selective because it is designed to primarily remove the conductive component without substantially affecting the dielectric layer. The etching process can remove material from the conductive component by about 0.1 to 50 nm. After the etching process, the top surface of the conductive component will be lower than the top surface of the dielectric layer. In one embodiment, the etching process can be one of a plurality of etching processes, for example, the etching process can be a wet etching process. In one embodiment, the etching process is a dry etching process.

[0065] The method 400 also includes a process 406 for forming an etch stop layer (e.g., CESL 110) on the conductive component and the dielectric layer, the etch stop layer having a different height on the first conductive component than on the dielectric layer. The CESL can be used to provide better control of a subsequently performed etching process to avoid unnecessary etching processes on the conductive component or the dielectric layer. The CESL has a top surface, a portion of which is lower above the conductive component than a portion above the dielectric layer. The CESL can be made of a variety of materials. In one embodiment, the CESL can include a high dielectric constant material, such as silicon oxynitride (SiON), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), zirconium oxide (ZrO2), an aluminum oxide layer, a nitrogen oxide layer, an oxide nitride, a metal oxide dielectric, a hafnium oxide, a tantalum oxide, a titanium oxide, a chromium oxide, an aluminum oxide, a lanthanum oxide, or other high dielectric constant materials. The CESL can be a dielectric material different from the dielectric layer or metal gate spacer used to form the gate device. The CESL can be made of multiple dielectric layers.

[0066] The method 400 further includes a process 408 for patterning the etch stop layer to expose the top surface of the first conductive component. For example, this can be accomplished by using an etching process (e.g., 116) to remove the CESL layer. In one embodiment, the etching process is a dry etching process. The dry etching process is anisotropic. In other words, the etching process etches in a single direction. The etching process can use a chlorine-based etchant. The etching process removes the CESL to expose the top surface of the conductive component. However, at this time, the entire top surface of the conductive component is not exposed.

[0067] The method 400 also includes a process 410 for laterally etching the etch stop layer. This can be accomplished by using an etching process (e.g., 118) to laterally etch back the CESL to expose more of the top surface of the conductive features. The lateral etching process can be an isotropic etching process, such as a wet etching process. In some embodiments, the etching process can use an amino etchant or a standard cleaning solution SC1.

[0068] The method 400 also includes a process 412 for depositing a conductive material over the first conductive feature to form a second conductive feature. Because the CESL is laterally etched during the lateral etching process, there is more contact area between the underlying conductive feature and the newly formed conductive feature. This reduces the contact resistance between the underlying conductive feature and the newly formed conductive feature. In some embodiments, after forming the conductive feature, a chemical mechanical polishing (CMP) process can be performed to planarize the top surface of the conductive feature and the dielectric layer.

[0069] Figure 5is a flow chart showing an illustrative method for forming an improved electrical connection between two conductive components. According to the present embodiment, method 500 includes a process 502 for performing a first etching process (e.g., 114) to pattern a dielectric layer (e.g., 112) and expose a contact etch stop layer (e.g., 110). The etching process can form a groove (e.g., 115) in the second dielectric layer. The first etching process can be a dry etching process. The first etching process can use a fluorine-based etchant. The first etching process can be performed as part of a photolithography patterning process. Therefore, the first etching process is only applied to certain portions of the dielectric layer. The etching process is performed until the CESL is reached. This is because the first etching process is selective and the materials of the CESL and the dielectric layer are selected so that the first etching process removes the dielectric layer without substantially affecting the CESL. The CESL can be made of a variety of materials. In one embodiment, the CESL may include a high dielectric constant material such as silicon oxynitride (SiON), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), zirconium oxide (ZrO2), an aluminum-containing oxide layer, a nitrogen-containing oxide layer, an oxynitride, a metal oxide dielectric, a hafnium-containing oxide, a tantalum-containing oxide, a titanium-containing oxide, a chromium-containing oxide, an aluminum-containing oxide, a lanthanum-containing oxide, or other high dielectric constant materials. The CESL may be a different dielectric material than the dielectric layer or metal gate spacer used to form the gate device. The CESL may be made of multiple dielectric layers.

[0070] In some embodiments, the CESL is formed on another dielectric layer (e.g., 102). This dielectric layer may be, for example, an interlayer dielectric (ILD) layer. The dielectric layer may be made of a nitride material such as silicon nitride. The dielectric layer may be formed on a semiconductor substrate. The semiconductor substrate may be a silicon substrate. However, in some embodiments, the substrate may be a silicon germanium substrate. Other types of semiconductor substrates may also be considered for use.

[0071] In one embodiment, the conductive component can be a via contact. A via contact is a conductive structure that connects a contact (e.g., a gate contact or a source / drain contact) to an upper conductive component (e.g., a metal interconnect). In some embodiments, the conductive component can be a via to a metal interconnect layer below. Other types of conductive structures are also contemplated.

[0072] The conductive component can be formed in one of many ways. In one embodiment, a photolithography patterning process is applied to the dielectric layer. For example, a photoresist can be applied to the dielectric layer. The photoresist can then be exposed to a light source through a mask. After exposure, the photoresist can be developed in a developer solution. This will remove the exposed or unexposed portions of the photoresist. The dielectric layer below can then be subjected to an etching process through the exposed portions of the photoresist. The etching process forms a groove in the dielectric layer. This groove can then be filled with a conductive material, such as a metallic material, to form the conductive component.

[0073] The method 500 also includes a process 504 for performing a second etching process (e.g., 116) to remove the etch stop layer and expose the top surface of the underlying component. In one embodiment, the second etching process is a dry etching process. The dry etching process is anisotropic. In other words, the etching process etches in a single direction. The second etching process can use a chlorine-based etchant. The second etching process removes the CESL to expose the top surface of the conductive component. However, at this time, the entire top surface of the conductive component is not exposed.

[0074] The method 500 also includes a process 506 for performing a third etching process to etch the etch stop layer laterally recessed. This exposes more of the top surface of the conductive component. The lateral etching process can be an isotropic etching process, such as a wet etching process. In some embodiments, the third etching process can use an amino etchant or a standard cleaning solution SC1.

[0075] The method 500 also includes a flow 508 for depositing a conductive feature on the underlying feature to create a conductive feature in direct contact with the underlying feature. Because the CESL is laterally etched during the lateral etching process, there is more contact area between the underlying conductive feature and the newly formed conductive feature. This reduces the contact resistance between the underlying conductive feature and the newly formed conductive feature. In some embodiments, after forming the conductive feature, a chemical mechanical polishing (CMP) process can be performed to planarize the top surface of the conductive feature and the dielectric layer.

[0076] By applying the principles described herein, improved methods and structures can be achieved. For example, because the etch stop layer is laterally etched during the lateral etching process, there is more contact area between the conductive component below and the newly formed conductive component. This reduces the contact resistance between the conductive component below and the newly formed conductive component. In addition, the corners of the etch stop layer protect the bridge between the conductive component below and the conductive component above. In addition, because a portion of the conductive component below is replaced by the conductive component above, the sheet resistance can be reduced.

[0077] According to some embodiments of the present invention, a method for manufacturing a semiconductor device includes: forming a first conductive component in a dielectric layer. Selectively etching back the first conductive component. Forming an etch stop layer on the first conductive component and the dielectric layer, wherein the height of the etch stop layer on the first conductive component is different from the height of the etch stop layer on the dielectric layer. Patterning the etch stop layer to expose a top surface of the first conductive component. Laterally etching the etch stop layer. Depositing a conductive material on the first conductive component to form a second conductive component.

[0078] In one embodiment, the first conductive component includes a via contact.

[0079] In one embodiment, the first conductive component includes a back end of line (BEOL) via.

[0080] In one embodiment, the first conductive component comprises a gate device.

[0081] In one embodiment, the first conductive feature includes a source / drain feature.

[0082] In one embodiment, patterning the etch stop layer includes a first etching process that uses a fluorine-based etchant to remove the dielectric layer.

[0083] In one embodiment, patterning the etch stop layer includes a second etching process that uses a chlorine-based etchant to remove the etch stop layer.

[0084] In one embodiment, laterally etching the etch stop layer includes a wet etching process.

[0085] In one embodiment, the first conductive feature is selectively etched back to remove approximately 0.1-50 nanometers of material.

[0086] In one embodiment, the second conductive component has a lower portion, a middle portion and an upper portion, the middle portion is narrower than the lower portion, and the upper portion is wider than the middle portion and the lower portion.

[0087] According to some embodiments of the present invention, a method for manufacturing a semiconductor device includes: performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer. Performing a second etching process to remove the etch stop layer and expose a top surface of a lower component. Performing a third etching process to laterally recess the etch stop layer and deposit a conductive material on the lower component to form a conductive component directly contacting the lower component.

[0088] In one embodiment, the first etching process uses a fluorine-based etchant.

[0089] In one embodiment, the second etching process uses a chlorine-based etchant.

[0090] In one embodiment, the third etching process uses ammonia.

[0091] In one embodiment, before performing the first etching process, the underlying component is etched back.

[0092] In one embodiment, after etching back the underlying features, a contact etch stop layer is deposited.

[0093] In one embodiment, a dielectric layer is deposited on the etch stop layer.

[0094] According to some embodiments of the present invention, a semiconductor device includes: a first conductive component embedded in a first dielectric layer such that a top surface of the first dielectric layer is higher than a top surface of the first conductive component. A contact etch stop layer (CESL) is disposed on the first dielectric layer. A second conductive component is embedded in the second dielectric layer. The second dielectric layer is disposed on the CESL, and the second conductive component extends through the CESL and directly contacts the first conductive component.

[0095] In one embodiment, the second conductive component has an upper portion, a middle portion and a lower portion, wherein the middle portion is narrower than the lower portion.

[0096] In one embodiment, the upper portion is wider than the middle portion and the lower portion.

[0097] The above summarizes the components of several embodiments so that technicians in the technical field to which the present invention belongs can better understand the viewpoints of the embodiments of the present invention. It should be understood by technicians in the technical field to which the present invention belongs that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments introduced herein. It should also be understood by technicians in the technical field to which the present invention belongs that such equivalent structures do not deviate from the concept and scope of the present invention, and they can make various changes, substitutions and replacements without violating the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined as defined by the claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first conductive component in a dielectric layer; Selectively etching back the first conductive component so that a top surface of the entire first conductive component is lower than a top surface of the dielectric layer; forming an etch stop layer on the first conductive component and the dielectric layer, wherein the height of the etch stop layer on the first conductive component is different from the height of the etch stop layer on the dielectric layer; patterning the etch stop layer to expose a top surface of the first conductive component; Laterally etching the etch stop layer below the top surface of the dielectric layer to expose the entire top surface of the first conductive component; as well as A conductive material is deposited on the first conductive component to form a second conductive component. 2 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the first conductive component comprises a via contact. 3 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the first conductive component comprises a back-end process via. 4 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the first conductive component comprises a gate device. 5 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the first conductive component comprises a source / drain component. 6 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the step of patterning the etch stop layer comprises a first etching process, wherein the first etching process uses a fluorine-based etchant to remove the etch stop layer. 7 . The method for manufacturing a semiconductor device as claimed in claim 6 , wherein the step of patterning the etch stop layer comprises a second etching process, wherein the second etching process uses a chlorine-based etchant to remove the etch stop layer. 8 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the step of laterally etching the etch stop layer comprises a wet etching process.

9. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of selectively etching back the first conductive component removes 0.1-50 nanometers of material. 10 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the second conductive component has a lower portion, a middle portion and an upper portion, the middle portion is narrower than the lower portion, and the upper portion is wider than the middle portion and the lower portion.

11. A method for manufacturing a semiconductor device, comprising: performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer; performing a second etching process to remove the contact etch stop layer and expose a top surface of a lower component; Performing a third etching process to laterally recess the contact etch stop layer and expose the entire top surface of the underlying component; as well as A conductive material is deposited on the lower component to form a conductive component directly contacting the lower component.

12. The method for manufacturing a semiconductor device as claimed in claim 11, wherein the first etching process uses a fluorine-based etchant.

13. The method for manufacturing a semiconductor device as claimed in claim 11, wherein the second etching process uses a chlorine-based etchant.

14. The method for manufacturing a semiconductor device as claimed in claim 11, wherein the third etching process uses ammonia. 15 . The method for manufacturing a semiconductor device as claimed in claim 11 , further comprising etching back the underlying component before performing the first etching process. 16 . The method for manufacturing a semiconductor device as claimed in claim 15 , further comprising depositing the contact etching stop layer after the step of etching back the underlying component. 17 . The method for manufacturing a semiconductor device as claimed in claim 15 , further comprising depositing the dielectric layer on the contact etch stop layer.

18. A semiconductor device comprising: a first conductive component embedded in a first dielectric layer, such that a top surface of the first dielectric layer is higher than a top surface of the entire first conductive component; a contact etch stop layer disposed on the first dielectric layer; A second conductive component is embedded in a second dielectric layer, the second dielectric layer is disposed on the contact etch stop layer, and the second conductive component extends through the contact etch stop layer and directly contacts the first conductive component, the second conductive component converges from above and below to a narrow point, and the narrow point is lower than a top surface of the contact etch stop layer.

19. The semiconductor device of claim 18, wherein the second conductive component comprises an upper portion, a middle portion, and a lower portion, and wherein the middle portion is narrower than the lower portion.

20. The semiconductor device of claim 19, wherein the upper portion is wider than the middle portion and the lower portion.

21. A method for manufacturing a semiconductor device, comprising: forming a first conductive component in a dielectric layer; selectively etching back the first conductive component; forming an etch stop layer on the first conductive component and the dielectric layer; patterning the etch stop layer to expose a top surface of the first conductive component; Laterally etching the etch stop layer below a top surface of the dielectric layer to expose the entire top surface of the first conductive component; as well as A conductive material is deposited on the first conductive component to form a second conductive component.

22. The method for manufacturing a semiconductor device as claimed in claim 21, wherein the first conductive component comprises a via contact. 23 . The method for manufacturing a semiconductor device as claimed in claim 21 , wherein the first conductive component comprises a back-end process via.

24. The method for manufacturing a semiconductor device as claimed in claim 21, wherein the first conductive component comprises a gate device. 25 . The method for manufacturing a semiconductor device as claimed in claim 21 , wherein the first conductive component comprises a source / drain component. 26 . The method for manufacturing a semiconductor device as claimed in claim 21 , wherein the step of patterning the etch stop layer comprises a first etching process, wherein the first etching process uses a fluorine-based etchant to remove the etch stop layer. 27 . The method for manufacturing a semiconductor device as claimed in claim 26 , wherein the step of patterning the etch stop layer comprises a second etching process, wherein the second etching process uses a chlorine-based etchant to remove the etch stop layer.

28. The method for manufacturing a semiconductor device as claimed in claim 21, wherein the step of laterally etching the etch stop layer comprises a wet etching process.

29. The method for manufacturing a semiconductor device as claimed in claim 21, wherein the step of selectively etching back the first conductive component removes 0.1-50 nanometers of material.

30. The method for manufacturing a semiconductor device as claimed in claim 21, wherein the second conductive component has a lower portion, a middle portion and an upper portion, the middle portion is narrower than the lower portion, and the upper portion is wider than the middle portion and the lower portion.

31. A method for manufacturing a semiconductor device, comprising: Etching back a lower component in a first dielectric layer; performing a first etching process to pattern a second dielectric layer and expose a contact etch stop layer; performing a second etching process to remove the contact etch stop layer below a top surface of the first dielectric layer; performing a third etching process to laterally recess the contact etching stop layer; as well as A conductive material is deposited on the lower component to form a conductive component directly contacting the lower component.

32. The method for manufacturing a semiconductor device as claimed in claim 31, wherein the first etching process uses a fluorine-based etchant.

33. The method for manufacturing a semiconductor device as claimed in claim 31, wherein the second etching process uses a chlorine-based etchant.

34. The method for manufacturing a semiconductor device as claimed in claim 31, wherein the third etching process uses ammonia.

35. The method for manufacturing a semiconductor device as claimed in claim 31, wherein the conductive material forms a conductive component, the conductive component having a lower portion, a middle portion and an upper portion, the middle portion is narrower than the lower portion, and the upper portion is wider than the middle portion and the lower portion. 36 . The method for manufacturing a semiconductor device as claimed in claim 31 , wherein the contact etching stop layer is deposited after the step of etching back the underlying component. 37 . The method for manufacturing a semiconductor device as claimed in claim 31 , further comprising depositing the second dielectric layer on the contact etch stop layer.

38. A semiconductor device comprising: a first conductive component embedded in a first dielectric layer such that a top surface of the first dielectric layer is higher than a top surface of the first conductive component; a contact etch stop layer disposed on the first dielectric layer; A second conductive component extends through the contact etch stop layer and directly contacts the first conductive component, the second conductive component converges from above and below to a narrow point, and the narrow point is lower than a top surface of the contact etch stop layer.

39. The semiconductor device of claim 38, wherein the second conductive component comprises an upper portion, a middle portion, and a lower portion, and wherein the middle portion is narrower than the lower portion.

40. The semiconductor device of claim 39, wherein the upper portion is wider than the middle portion and the lower portion.

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