Semiconductor device with integrated MOS gate diode or Schottky diode

Abstract

A semiconductor device with an integrated MOS-gated diode or Schottky diode is disclosed. The semiconductor device includes a semiconductor substrate and a plurality of transistor cells. Each transistor cell includes: a gate trench structure formed in the semiconductor substrate and surrounding the transistor cell; a needle-shaped field electrode trench structure formed in the semiconductor substrate and inwardly separated from the gate trench structure; a source region of a first conductivity type formed in the semiconductor substrate adjacent to the gate trench structure; a body region of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate below the source region; and a drift zone of the first conductivity type formed in the semiconductor substrate below the body region. The semiconductor device further includes a plurality of MOS-gated diodes or Schottky diodes, each diode being formed in the semiconductor substrate at the intersection of four adjacent transistor cells. A corresponding manufacturing method is also described.

Description

Background Art

[0001] In many applications, especially in low voltage drive applications, MOSFETs (metal oxide semiconductor field effect transistors) with low Rdson (on-state resistance), low gate charge, and built-in body diodes are used to achieve high efficiency. Body diodes with low forward voltage (Vf) and low reverse recovery (Qrr) help reduce overall losses and can be critical in some applications. As such, low diode forward voltage drop is typically one of the highest priorities, if not the highest priority, among all device electrical parameters.

[0002] Bipolar operation of the body diode with a typical forward voltage of 0.8V to ~1V is undesirable for reliable device operation and reduced conduction losses. A unipolar diode based on a Schottky contact may be connected to the MOSFET in parallel externally as a separate chip (die) to accommodate current in the reverse direction. However, this approach increases the package size and implementation cost in the power converter. This approach also introduces a high degree of parasitic inductance between the separately packaged devices, reducing efficiency and switching frequency. In the case of a diode integrated with the MOSFET, the parasitic inductance is significantly reduced. However, this approach conventionally utilizes the MOSFET conductive (active) area and therefore has a significant adverse effect on Rdson.

[0003] Therefore, there is a need for a semiconductor device having a low Rdson and having an integrated diode with a low diode forward voltage and low reverse recovery. Summary of the invention

[0004] According to an embodiment of the semiconductor device, the semiconductor device includes a semiconductor substrate and a plurality of transistor units. Each transistor unit includes: a gate trench structure formed in the semiconductor substrate and surrounding the transistor unit; a needle-shaped field electrode trench structure formed in the semiconductor substrate and separated from the gate trench structure inwardly; a source region of a first conductivity type formed in the semiconductor substrate adjacent to the gate trench structure; a body region of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate below the source region; and a drift zone of the first conductivity type formed in the semiconductor substrate below the body region. The semiconductor device further includes a plurality of MOS-selected diodes or Schottky diodes, each of which is formed in the semiconductor substrate at the intersection of four adjacent transistor units.

[0005] In a first embodiment, a MOS-gated diode is formed in a semiconductor substrate at the intersection of four adjacent transistor cells. Each MOS-gated diode may include: an electrode trench formed in the semiconductor substrate and laterally separated from the gate trench structures of the four adjacent transistor cells; a first region of a second conductivity type formed in the semiconductor substrate adjacent to the electrode trench; a first region of a first conductivity type formed in the first region of a second conductivity type; and a conductive material electrically connecting the first region of the first conductivity type and the first region of the second conductivity type to the electrode in the electrode trench. Separately or in combination, each MOS-gated diode may further include a second region of the first conductivity type formed in a recessed section of the first region of the second conductivity type, and the conductive material may contact the first region of the first conductivity type and the second region of the first conductivity type. Separately or in combination, each MOS-gated diode may further include a contact trench that laterally surrounds the electrode trench and laterally separates from the gate trench structures of the four adjacent transistor cells, and the contact trench may be filled with a conductive material. Separately or in combination, each MOS-enabled diode may further include a second region of the second conductivity type formed in the first region of the second conductivity type, the second region of the second conductivity type may be more heavily doped than the first region of the second conductivity type, and the conductive material may contact the second region of the second conductivity type.

[0006] In a second embodiment, a Schottky diode is formed in a semiconductor substrate at the intersection of four adjacent transistor cells. Each Schottky diode may include a metal or metal alloy in contact with a region of the first conductivity type of the semiconductor substrate. Separately or in combination, each Schottky diode may include: an electrode trench formed in the semiconductor substrate and laterally separated from the gate trench structures of the four adjacent transistor cells; and a metal that electrically connects the electrode in the electrode trench to a region of the second conductivity type of the semiconductor substrate adjacent to the electrode trench. Separately or in combination, a section of the region of the second conductivity type of the semiconductor substrate adjacent to each electrode trench may be recessed below the main surface of the semiconductor substrate. Separately or in combination, the metal of each Schottky diode may contact a region of the first conductivity type of the semiconductor substrate formed above a recessed section of a region of the second conductivity type of the semiconductor substrate.

[0007] According to an embodiment of a method for manufacturing a semiconductor device, the method includes: forming a plurality of transistor units in a semiconductor substrate, each transistor unit including: a gate trench structure formed in the semiconductor substrate and surrounding the transistor unit; a needle-shaped field electrode trench structure formed in the semiconductor substrate and separated inwardly from the gate trench structure; a source region of a first conductive type formed in the semiconductor substrate adjacent to the gate trench structure; a body region of a second conductive type opposite to the first conductive type formed in the semiconductor substrate below the source region; and a drift zone band of the first conductive type formed in the semiconductor substrate below the body region, and the method includes: forming a plurality of MOS-selected diodes or Schottky diodes in the semiconductor substrate, each diode being formed in the semiconductor substrate at the intersection of four adjacent transistor units.

[0008] Forming multiple MOS-gated diodes or Schottky diodes in a semiconductor substrate may include: using a general trench etching process, etching electrode trenches of multiple MOS-gated diodes or Schottky diodes into the semiconductor substrate while etching gate trenches of multiple transistor units into the semiconductor substrate; forming a first dielectric on the sidewalls and bottoms of the gate trenches and the electrode trenches; after forming the first dielectric, forming electrodes in the electrode trenches to form an electrode trench structure; forming a first region of a second conductivity type in the semiconductor substrate adjacent to each electrode trench; forming a first region of a first conductivity type in each first region of a second conductivity type; and forming a conductive material that electrically connects the first region of the first conductivity type and the first region of the second conductivity type to the electrodes in each electrode trench.

[0009] Separately or in combination, forming the gate trench structure may include: forming a second dielectric on a sidewall and a bottom of the gate trench, the second dielectric being thicker than the first dielectric; and forming an electrode in the gate trench after forming the second dielectric.

[0010] Separately or in combination, a general body implantation process may be used to form a first region of the second conductivity type in the semiconductor substrate adjacent to each electrode trench while forming body regions of the plurality of transistor cells.

[0011] Separately or in combination, forming multiple MOS-gated diodes or Schottky diodes in a semiconductor substrate may further include: forming a second region of the second conductivity type in each first region of the second conductivity type, wherein the second region of the second conductivity type is more heavily doped than the first region of the second conductivity type, and wherein the conductive material contacts the second region of the second conductivity type.

[0012] Separately or in combination, forming a plurality of MOS-gated diodes or Schottky diodes in a semiconductor substrate may further include recessing the electrode trench structure and segments of the first region of the second conductivity type to reduce a thickness of the first region of the second conductivity type along sidewalls of the electrode trench.

[0013] Separately or in combination, the first region of the first conductivity type may be formed in a recessed section of the first region of the second conductivity type.

[0014] Separately or in combination, forming multiple MOS-gated diodes or Schottky diodes in a semiconductor substrate may further include: etching multiple contact trenches into the semiconductor substrate, each contact trench laterally surrounding one of the electrode trenches and laterally separated from the gate trench structures of four adjacent transistor units; and filling the multiple contact trenches with conductive material.

[0015] Separately or in combination, forming a plurality of MOS gated diodes or Schottky diodes in a semiconductor substrate may include depositing a conductive material in direct contact with the semiconductor substrate at intersections of four adjacent transistor cells.

[0016] Separately or in combination, forming multiple MOS-gated diodes or Schottky diodes in a semiconductor substrate may include: etching multiple electrode trenches into the semiconductor substrate, each electrode trench being laterally separated from the gate trench structures of four adjacent transistor cells; and depositing metal that electrically connects the electrode in each electrode trench to a region of the semiconductor substrate adjacent to the electrode trench.

[0017] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The elements of the drawings are not necessarily to scale with respect to each other. The same reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are depicted in the drawings and are detailed in the subsequent description.

[0019] Figure 1 illustrates a top-down plan view of a section of a semiconductor device having a power transistor and a MOS gated diode (MGD) or Schottky diode integrated in a single chip (die);

[0020] Figures 2 to 5 and Figures 7 to 10 Each of the diagrams is based on different embodiments along the Figure 1 A corresponding cross-sectional view of the semiconductor device taken along the line labeled AA';

[0021] FIG. 6A to FIG. 6K Respective partial cross-sectional views are illustrated during different stages of a method of fabricating a semiconductor device in which an MGD is formed at the intersection of every four adjacent transistor cells. DETAILED DESCRIPTION

[0022] The described embodiments integrate a power MOSFET with a MOS gated diode (MGD) or Schottky diode in a single chip (die) in a monolithic manner. The non-conductive area of ​​the chip is used for the diode with low forward voltage drop, and therefore has no adverse effect on the transistor gate length or Rdson. Compared with the conventional built-in body diode, the integrated MGD or Schottky diode reduces the forward voltage (Vf) drop of the built-in body diode by, for example, almost 50% or more, and also has a lower reverse recovery charge (Qrr). The integrated MGD or Schottky diode is formed in the non-conductive (non-active) area of ​​the power MOSFET, and therefore has minimal impact on the current path of the semiconductor device. Compared with conventional solutions using additional discrete diode chips, the embodiments described herein provide an integrated solution with reduced parasitic inductance and increased switching frequency in the circuit. The contact for the MGD or Schottky diode can be disconnected simultaneously with the contact for the transistor unit. Any desired ratio of MGD / Schottky to active area can be achieved.

[0023] In some embodiments, both the MOSFET and the integrated diode not only share the forward conducting layer of the device, but they also share the edge termination region, so that a large amount of die / wafer area can be saved. In addition, the embodiments described herein reduce the number of packages and the cost of implementing semiconductor devices in power converter applications, and also improve efficiency and increase switching frequency by eliminating parasitic inductance between separately packaged MOSFET and diode devices.

[0024] Figure 1 A top-down plan view of a section of a semiconductor device with a power transistor and a MOS gated diode (MGD) or Schottky diode integrated in a single chip (die) is illustrated. Figures 2 to 5 and Figures 7 to 10 Illustrations according to different embodiments Figure 1 The corresponding cross-sectional view of the semiconductor device is taken along the line labeled AA′ in FIG.

[0025] The semiconductor device includes a semiconductor substrate 100 and a plurality of transistor cells 102 formed in the semiconductor substrate 100. The transistor cells 102 integrally produce a power transistor, such as a power MOSFET. In one embodiment, the semiconductor substrate 100 is a silicon substrate, which may include one or more Si epitaxial layers. In general, the semiconductor substrate 100 described herein may be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, but are not limited to: elemental semiconductor materials, such as silicon (Si) or germanium (Ge); IV group compound semiconductor materials, such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary or quaternary III-V group semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), etc.

[0026] Each transistor cell 102 formed in the semiconductor substrate 100 includes: a gate trench structure 104 formed in the semiconductor substrate 100 and surrounding the transistor cell 102; a pin-shaped field electrode trench structure 106 formed in the semiconductor substrate 100 and spaced apart inwardly from the gate trench structure 104; a source region 108 of a first conductivity type formed in the semiconductor substrate 100 adjacent to the gate trench structure 104; a body region 110 of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate 100 below the source region 108; and a drift zone 112 of a first conductivity type formed in the semiconductor substrate 100 below the body region 110. In the case of an n-channel transistor device, the source region 108 and the drift zone 112 are n-type and the body region 110 is p-type. In the case of a p-channel transistor device, the source region 108 and the drift zone 112 are p-type and the body region 110 is n-type. A drain region or collector region of the semiconductor device is disposed at a bottom main surface of the semiconductor substrate 100 , which is out of view in the figures.

[0027] The term “needle-shaped” as used herein means a narrow and long structure in the depth direction of the semiconductor substrate 100. For example, the needle-shaped field electrode trench structure 106 may be similar to a needle, a column, or a needle-shaped body in the depth direction of the semiconductor substrate 100. Each needle-shaped field electrode trench structure 106 is surrounded by the gate trench structure 104 in the lateral direction. Therefore, the gate trench structure 104 has a different shape from the field electrode trench structure 106.

[0028] The gate trench structure 104 of the semiconductor device may include a gate electrode 114 insulated from the surrounding semiconductor substrate 100 by a gate dielectric 116 such as a gate oxide. The pin-shaped field electrode trench structure 106 of the semiconductor device may include a pin-shaped field electrode 118 insulated from the surrounding semiconductor substrate 100 by a field dielectric 120 such as a field oxide. The field oxide 120 may be thicker than the gate dielectric 116. The pin-shaped field electrode 118 may extend deeper into the semiconductor substrate 100 than the gate electrode 114. The pin-shaped field electrode 118 is shown as Figure 1 The pin-shaped field electrode 118 may have an octagonal shape in a horizontal cross-sectional plane extending parallel to the top main surface 101 of the semiconductor substrate 100. The pin-shaped field electrode 118 may have another shape in a horizontal cross-sectional plane, such as but not limited to a hexagon, a circle, a square, a rectangle, etc. The pin-shaped field electrode trench structure 106 may be recessed below the top main surface 101 of the semiconductor substrate 100 to facilitate contact between the stacked metal layer 120 and the pin-shaped field electrode 118, the side of the source region 108, and the highly doped (e.g., p+ region in the case of an n-channel device, or n+ region in the case of a p-channel device) body contact region 122 formed in the body region 110. An interlayer dielectric 124 such as an oxide may separate the metal layer 120 from the gate trench structure 104 of the semiconductor device.

[0029] The gate intersection region of the semiconductor device—i.e., the intersection of four adjacent transistor cells 102—does not contribute to the current flow of the power transistor formed by the transistor cells 102. The embodiments described herein utilize this region of the semiconductor device to integrate a plurality of MGDs 126 or Schottky diodes 126'. Each diode 126 / 126' is formed in the semiconductor substrate 100 at the intersection of four adjacent transistor cells 102. Figure 1 Certain regions of the interlayer dielectric 124 are omitted to better illustrate the transistor cells 102 and the MGD 126 in a top-down plan view of the device. Figure 1 is covered by the interlayer dielectric 124, so Figure 1 The gate trench structure 104 is illustrated by a dotted octagon.

[0030] According to Figures 2 to 5, MGDs 126 are formed in the semiconductor substrate 100 at the intersection of four adjacent transistor cells 102. Each MGD 126 includes an electrode trench 128 formed in the semiconductor substrate 100 and laterally separated from the gate trench structures 104 of the four adjacent transistor cells 102. The MGD electrode trench 128 may include an electrode 130 insulated from the surrounding semiconductor substrate 100 by a dielectric 132, which may be the same or different dielectric than the gate dielectric 116 in the transistor cells 102. The MGD trench dielectric 132 may be thinner than the gate trench dielectric 116 in the transistor cells 102, for example, about one-tenth of the gate trench dielectric 116 or thinner. In one embodiment, the MGD dielectric 132 is about 6 to 7 nm (nanometers) thick, and the gate dielectric 116 in the transistor cells 102 is about 60 nm or thicker.

[0031] A second conductivity type region 134 is formed in the semiconductor substrate 100 adjacent to the electrode trench 128 of each MGD 126. This region 134 is similar to the body region 110 in the transistor cell 102, but is not part of the current path of the semiconductor device. The doping concentration of the second conductivity type region 134 of the MGD 126 can be set to be different from the doping concentration of the body region 110 of the transistor cell 102.

[0032] According to Figure 2 , Figure 3 and Figure 5 1, each MGD 126 further includes a region 136 of a first conductivity type that is highly doped (e.g., an n+ region in the case of an n-channel device, or a p+ region in the case of a p-channel device) that is formed in a region 134 of a second conductivity type that is adjacent to the electrode trench 128 of the MGD 126. A conductive material 138, such as a metal or metal alloy, doped polysilicon, or the like, electrically connects the highly doped region 136 of the first conductivity type and the region 134 of the second conductivity type to the electrode 130 in the electrode trench 128 of each MGD 126. The MGD contact opening may be formed simultaneously with the contact opening to the pin-shaped field electrode trench structure 106 in the transistor cell 102. The conductive material 138 may be the same layer as the metal layer 120 that contacts the pin-shaped field electrode 120, the side of the source region 108, and the highly doped body contact region 122 in the transistor cell 102. The conductive material 138 may alternatively be a different metal layer at the same or different potential than the metal layer 120 that contacts the needle-shaped field electrodes 118, the sides of the source regions 108, and the highly doped body contact regions 122 in the transistor cell 102. The MGD electrode trench 128 may be formed as in Figure 2As shown in FIG. 1 , the top major surface 101 of the semiconductor substrate 100 is recessed below the top major surface 101 of the semiconductor substrate 100 to facilitate more reliable contact between the conductive material 138 and the first conductivity type highly doped region 136, the second conductivity type region 134 and the electrode 130 in the electrode trench 128 of each MGD 126.

[0033] According to Figure 2 In the embodiment illustrated in FIG. 1 , an additional mask (not shown) may be provided for implanting a highly doped region 136 of the first conductivity type in the region of the MGD 126. In the region of the MGD 126, the additional mask also blocks the implant for forming the highly doped body contact region 122 in the transistor cell 102. The source mask for forming the source region 108 in the transistor cell 102 may be modified to block the source implant in the region of the MGD 126.

[0034] exist Figure 3 The MGD embodiment shown in Figure 2 The embodiment shown in FIG. 1 differs in that each MGD 126 further includes an additional region 140 of the first conductivity type formed in the region 134 of the second conductivity type adjacent to the electrode trench 128 of the MGD 126. The additional region 140 of the first conductivity type may be formed using the same mask as that used to form the source region 108 in the transistor cell 102. That is, Figure 2 Unlike the embodiment illustrated in , the source mask used to form the source region 108 in the transistor cell 102 is not modified to block source implants in the region of the MGD 126. According to this embodiment, the overlying conductive material 138 contacts both the highly doped region 136 of the first conductivity type and the additional region 140 of the first conductivity type.

[0035] exist Figure 4 The MGD embodiment shown in Figure 3 The embodiment shown in is different in that each MGD 126 further includes a contact trench 142, which laterally surrounds the electrode trench 128 and is laterally separated from the gate trench structures 104 of the four adjacent transistor cells 102. The MGD contact trench 142 may extend through the upper region 140 of the first conductivity type and into the lower region 134 of the second conductivity type. The MGD contact trench 142 is filled with a conductive material 138, which contacts the region 140 of the first conductivity type of the MGD 126 and the electrode 130 in the electrode trench 128. According to this embodiment, the highly doped region 136 of the first conductivity type may be omitted. Separately or in combination, the MGD electrode trench 128 may not be recessed below the top main surface 101 of the semiconductor substrate, as in Figure 4An additional contact trench 144 may be formed in the electrode 130 of each MGD electrode trench 128 , and a conductive material 138 may fill the additional trench 144 to contact the electrode 130 in the corresponding electrode trench 128 of the MGD 126 .

[0036] exist Figure 5 The MGD embodiment shown in Figure 2 The embodiment shown in FIG. 1 differs in that each MGD 126 further includes a highly doped region 146 of the second conductivity type (e.g., a p+ region in the case of an n-channel device, or an n+ region in the case of a p-channel device) formed in a region 134 of the second conductivity type adjacent to the electrode trench 128 of the MGD 126. The highly doped region 146 of the second conductivity type is more heavily doped than the region 134 of the second conductivity type adjacent to the electrode trench 128 of the MGD 126, and the conductive material 138 also contacts the highly doped region 146 of the second conductivity type.

[0037] FIG. 6A to FIG. 6K Respective partial cross-sectional views during different stages of a method of manufacturing a semiconductor device are illustrated, and wherein an MGD 200 is formed at the intersection of every four adjacent transistor cells 202 . FIG. 6A to FIG. 6K MGD 200 and two adjacent transistor cells 202 are shown.

[0038] Fig. 6A The semiconductor substrate 204 is shown after forming a needle-shaped field electrode trench structure 206, a gate trench 208, and a MGD electrode trench 210 in the semiconductor substrate 204. The needle-shaped field electrode trench structure 206 may include a needle-shaped field electrode 212 insulated from the surrounding semiconductor substrate 204 by a field dielectric 214 such as a field oxide.

[0039] The gate trench 208 and the MGD electrode trench 210 may be formed by a typical etching process. In one embodiment, the MGD electrode trench 210 is etched into the semiconductor substrate 204 simultaneously with the gate trench 208 of the transistor cell 202 using a general trench etching process. A dielectric 216 is also formed in the gate trench 208 and the MGD electrode trench 210, for example, by thermal oxidation, oxide deposition, etc. According to this embodiment, the dielectric 216 forms a dielectric liner 216' in the MGD electrode trench 210, and is thinner than the gate trench dielectric to be formed in the transistor cell 202.

[0040] Figure 6BThe semiconductor substrate 204 is shown after the gate trench 208 and the MGD electrode trench 210 are filled with a conductive material such as a metal or metal alloy, doped polysilicon, etc. The conductive material 218 is planarized, such as by chemical mechanical polishing (CMP), to form a MGD trench electrode 218'.

[0041] Figure 6C The semiconductor substrate 204 is shown after a mask 220 such as silicon dioxide, silicon nitride, photoresist, etc. is formed over the MGD electrode trench 210 to protect the electrode 218' and the dielectric 216' in the MGD electrode trench 210. The conductive material 218 is then removed from the unprotected gate trench 208 in the transistor cell 202 using a typical etching process such as a wet or dry chemical etch.

[0042] Fig.6D The semiconductor substrate 204 is shown after forming a gate dielectric 222 in the gate trench 208 of the transistor cell 202. The dielectric 216 forming the dielectric liner 216' in the MGD electrode trench 210 may be removed from the gate trench 208 before forming the gate dielectric 222, or the gate dielectric may be deposited on the underlying dielectric 216 if still present when the gate dielectric is formed. The gate oxide 222 may be formed by a typical oxide formation process such as thermal oxidation, deposition, etc. As mentioned above, according to this embodiment, the MGD trench dielectric 216' is thinner than the gate trench dielectric 222 in the transistor cell 202 (e.g., about one-tenth of the gate trench dielectric 222 or thinner) to ensure proper operation of the MGD 200. Typical gate dielectric thicknesses of about 60 nm or more may be too thick to ensure proper MGD operation. Therefore, there is a separate MGD oxide formation process. If the gate dielectric material and thickness are sufficient to ensure proper MGD operation, the separate MGD oxide formation process may be omitted.

[0043] Fig. 6E Semiconductor substrate 204 is shown after planarizing gate dielectric 222 , for example by CMP, removing MGD mask 220 , and filling gate trench 208 with a conductive material such as a metal or alloy, doped polysilicon, etc. The conductive material is planarized, for example by CMP, to form gate electrode 224 of transistor cell 202 .

[0044] Fig. 6FSemiconductor substrate 204 is shown after body dopants of the second conductivity are implanted into transistor cell 202 and MGD 200 using a common body implant process, and after source dopants of the first conductivity are implanted into transistor cell 202 but not into MGD 200. The implanted dopants are annealed at some point to form body regions 226 of the second conductivity type in transistor cell 202 and regions 228 of the second conductivity type in MGD 200, and source regions 230 of the first conductivity type in transistor cell 202 but not in MGD 200. A source implant mask (not shown) may be modified to block the source dopants from being implanted into MGD 200.

[0045] Figure 6G Semiconductor substrate 204 is shown after forming a contact mask 232 such as silicon dioxide, silicon nitride, photoresist, etc. on the dielectric material 216 / 222 remaining on the top major surface of semiconductor substrate 204, and after etching contact openings 234 through dielectric material 216 / 222 and into semiconductor substrate 204 in the areas exposed by the openings in contact mask 232. Contact openings 234 for transistor cells 202 may be formed using any typical dielectric and semiconductor etching process.

[0046] Figure 6H The semiconductor substrate 204 is shown after removing the transistor cell contact mask 232 and forming a MGD implant mask 236 such as silicon dioxide, silicon nitride, photoresist, etc. (and having openings 236' exposing the MGD region of the device). The dielectric material 216 / 222 remaining on the top major surface of the semiconductor substrate 204 and exposed by the openings in the MGD implant mask 236 is removed, such as by etching. The exposed portion of the MGD region is then implanted with a dopant substance 238 of the second conductivity type to adjust the threshold in the MGD region of the device. This step can be omitted if MGD threshold adjustment is not required.

[0047] Fig.6I Semiconductor substrate 204 is shown after forming highly doped contact regions 240 of the second conductivity type in transistor cells 202 of the device and in MGD 200. Highly doped contact regions 240 enable low ohmic contact to body regions 226 of the second conductivity type in transistor cells 202 and to regions 228 of the second conductivity type in MGD 200.

[0048] Figure 6JThe semiconductor substrate is shown after forming a MGD contact mask 242 such as a photoresist. The MGD contact mask 242 has an opening 242' vertically aligned with the electrode trench 210 of the MGD 200. The exposed portion of the semiconductor substrate 204 in the MGD region, including the segment of the highly doped contact region 240 of the second conductivity type, is then etched to reduce the thickness of the more lightly doped region 228 of the second conductivity type disposed along the sidewalls of the MGD electrode trench 210, and thereby provide a shallower contact depth for the MGD 200. The shallower contact depth ensures that the channel length of the MGD 200 is comparable to the channel length of the transistor cell 202.

[0049] Figure 6K The semiconductor substrate 204 is shown after implanting dopants of the first conductivity type into the recessed portions of the second conductivity type, more lightly doped MGD regions 228. The MGD contact mask 242 is then removed and the semiconductor substrate 204 is annealed to form highly doped regions 244 of the MGD 200.

[0050] The contact openings formed in the transistor cell 202 and in the MGD 200 may then be filled with a conductive material such as a metal or metal alloy, doped polysilicon, etc. to form respective contacts for the transistor cell 202 and the MGD 200. Figure 5 It is shown in FIG. 6A to FIG. 6K The resulting semiconductor device is formed by the manufacturing method illustrated in FIG.

[0051] exist FIG. 6A to FIG. 6K The manufacturing method illustrated in the figure may be modified to form an alternative Figures 2 to 4 For example, in order to manufacture any semiconductor device shown in Figure 2 In the semiconductor device shown in FIG. 1 , an additional mask may be provided for implanting a highly doped region of the first conductivity type in the region of MGD 200. The mask also blocks the implantation for forming a highly doped body contact region 240 in the transistor cell 202 in the region of MGD 200, and the source mask for forming a source region 230 in the transistor cell 202 may be modified to block the source implantation in the region of MGD 200. Figure 3 In the semiconductor device shown in FIG. 1 , the additional region of the first conductivity type may be formed using the same mask as the mask used to form the source region 230 in the transistor unit 202. Figure 4 In the semiconductor device shown in FIG. 1 , a contact trench may be etched into the semiconductor substrate 204 in each MGD 200 . The contact trench laterally surrounds the corresponding MGD electrode trench 210 and is laterally separated from the gate trenches 208 of the four adjacent transistor cells 202 adjoining the MGD 200 .

[0052] Figures 7 to 10 A corresponding embodiment is illustrated in which a Schottky diode is formed in a semiconductor substrate of a semiconductor device at the intersection of four adjacent transistor cells instead of a MGD.

[0053] According to Figure 7 In the Schottky diode embodiment illustrated in , each Schottky diode 126' at the intersection of four adjacent transistor cells 102 includes a metal or metal alloy 300 in direct contact with a region 302 of the first conductivity type of the semiconductor substrate 100. The result of this contact is a Schottky barrier (rectifying contact) in which the junction is conductive for one bias polarity and non-conductive for the other bias polarity. The metal or metal alloy 300 can be the same or a different metal layer than the metal layer 120 that contacts the needle-shaped field electrode 118, the source region 108, and the highly doped body contact region 122 in the transistor cell 102. The Schottky diode 126' can be formed by modifying the mask used to implant the source region 108 and the body region 110 in the transistor cell 102 to block the source implant and the body implant in the region of the Schottky diode 126'. An additional mask (not shown) may be used to block the implantation in the region of the Schottky diode 126 ′ for forming the highly doped body contact region 122 in the transistor cell 102 .

[0054] exist Figure 8 The Schottky diode embodiment shown in Figure 7 The embodiment shown in FIG. 1 differs in that each Schottky diode 126′ further includes an electrode trench 304 formed in the semiconductor substrate 100 and laterally separated from the gate trench structures 104 of four adjacent transistor cells 102. The Schottky barrier is still provided by the contact between the metal or metal alloy 300 and the region 302 of the first conductivity type of the semiconductor substrate 100. However, the metal or metal alloy 300 also electrically connects the electrode 306 in the Schottky electrode trench 304 to the region 302 of the first conductivity type of the semiconductor substrate 100 disposed adjacent to the Schottky electrode trench 304. The electrode 306 in each Schottky electrode trench 304 is insulated from the surrounding semiconductor substrate 100 by a dielectric 308 such as an oxide.

[0055] exist Fig. 9 The Schottky diode embodiment shown in Figure 8The embodiment shown in FIG. 1 differs in that a region 310 of the second conductivity type of the semiconductor substrate 100 is disposed adjacent to the electrode trench 304 of each Schottky diode 126′ below the region 302 of the first conductivity type of the semiconductor substrate 100. The Schottky region 310 of the second conductivity type may be formed by the same implantation process as that used to form the body region 110 in the transistor cell 102. The Schottky barrier is again provided by the contact between the metal or metal alloy 300 and the region 302 of the first conductivity type of the semiconductor substrate 100. The metal or metal alloy 300 also electrically connects the electrode 306 in the Schottky electrode trench 304 to both: the region 310 of the second conductivity type of the semiconductor substrate 100 adjacent to the Schottky electrode trench 304 and the overlapping region 302 of the first conductivity type of the semiconductor substrate 100. The overlapping region 302 of the first conductivity type may be formed using the same mask as that used to form the source region 108 in the transistor cell 102. The electrode trenches 304 of the Schottky diode 126′ may be recessed below the top main surface 101 of the semiconductor substrate 100. For example, a section of the second conductivity type region 310 of the semiconductor substrate 100 adjacent to each Schottky electrode trench 304 and a section of the first conductivity type overlapping region 302 of the semiconductor substrate 100 may be recessed below the top main surface 101 of the semiconductor substrate 100.

[0056] exist Fig.10 The Schottky diode embodiment shown in Fig. 9 3. The embodiment shown in FIG. 1 differs in that the region 302 of the first conductivity type of the semiconductor substrate 100 disposed above the region 310 of the second conductivity type adjacent to each Schottky electrode trench 304 of the semiconductor substrate 100 is omitted. The overlapping region 302 of the first conductivity type may be omitted by modifying the mask used to form the source region 108 in the transistor cell 102. According to this embodiment, the Schottky barrier is provided by the contact between the metal or metal alloy 300 and the region 310 of the second conductivity type of the semiconductor substrate 100. According to this embodiment, the electrode trench 304 of the Schottky diode 126' may or may not be recessed below the top main surface 101 of the semiconductor substrate 100.

[0057] Terms such as "first", "second", etc. are used to describe various elements, regions, sections, etc., and are not intended to be limiting. The same terms refer to the same elements throughout the description.

[0058] As used herein, the terms "having," "containing," "including," and "comprising" and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The quantifiers "a," "an," and the pronoun "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0059] It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0060] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various replacements and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention is limited only by the claims and their equivalents.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; A power transistor comprising a plurality of transistor cells, each of the plurality of transistor cells comprising: A gate trench structure is formed in the semiconductor substrate and surrounds the transistor unit; a needle-shaped field electrode trench structure formed in the semiconductor substrate and spaced inwardly from the gate trench structure; A source region of a first conductivity type is formed in the semiconductor substrate adjacent to the gate trench structure; a body region of a second conductivity type opposite to the first conductivity type, formed in the semiconductor substrate below the source region; and a drift zone of a first conductivity type formed in the semiconductor substrate below the body region, and A plurality of MOS gated diodes or Schottky diodes, each of the plurality of MOS gated diodes or Schottky diodes is formed in an inactive region of the power transistor between adjacent ones of the transistor cells.

2. The semiconductor device according to claim 1, wherein: Each of the plurality of MOS gated diodes is formed in an inactive region of the power transistor between adjacent ones of the transistor cells.

3. The semiconductor device according to claim 2, wherein: Each of the plurality of MOS-gated diodes comprises: an electrode trench formed in an inactive region of the power transistor between adjacent ones of the transistor cells; a first region of a second conductivity type adjacent to the electrode trench; a first region of a first conductivity type formed in the first region of a second conductivity type; and A conductive material electrically connects the first region of the first conductivity type and the first region of the second conductivity type to the electrode in the electrode trench.

4. The semiconductor device of claim 3 , wherein each of the plurality of MOS-gated diodes further comprises a second region of the first conductivity type formed in a recessed section of the first region of the second conductivity type, and wherein the conductive material contacts the first region of the first conductivity type and the second region of the first conductivity type.

5. The semiconductor device of claim 3 , wherein each of the plurality of MOS-gated diodes further comprises a contact trench laterally surrounding the electrode trench and laterally separated from a gate trench structure of an adjacent transistor cell in the transistor cell, and wherein the contact trench is filled with a conductive material.

6. A semiconductor device as described in claim 3, wherein each of the multiple MOS-enabled diodes further includes a second region of the second conductivity type formed in the first region of the second conductivity type, wherein the second region of the second conductivity type is more heavily doped than the first region of the second conductivity type, and wherein the conductive material contacts the second region of the second conductivity type. 7 . The semiconductor device of claim 1 , each of the plurality of Schottky diodes being formed in an inactive region of the power transistor between adjacent ones of the transistor cells. 8 . The semiconductor device of claim 7 , wherein each of the plurality of Schottky diodes comprises a metal or a metal alloy in contact with a region of the first conductivity type of the semiconductor substrate.

9. The semiconductor device of claim 7, wherein each of the plurality of Schottky diodes comprises: an electrode trench formed in an inactive region of the power transistor between adjacent ones of the transistor cells; as well as A metal electrically connects the electrode in the electrode trench to a region of the semiconductor substrate of the second conductivity type adjacent to the electrode trench.

10. The semiconductor device according to claim 9, wherein A segment of a second conductive type region of the semiconductor substrate adjacent to each electrode groove is recessed below the main surface of the semiconductor substrate, and wherein a metal contact of each Schottky diode among the plurality of Schottky diodes is formed in a first conductive type region of the semiconductor substrate above the recessed segment of the second conductive type region of the semiconductor substrate.

11. The semiconductor device according to claim 9, wherein: A section of the region of the second conductivity type of the semiconductor substrate adjacent to each electrode trench is recessed below the main surface of the semiconductor substrate.

12. A method for manufacturing a semiconductor device, the method comprising: A power transistor is formed, the power transistor comprising: A plurality of transistor cells, each of the plurality of transistor cells comprising: a gate trench structure formed in the semiconductor substrate and surrounding the transistor unit; a needle-shaped field electrode trench structure formed in the semiconductor substrate and spaced inwardly from the gate trench structure; A source region of a first conductivity type is formed in the semiconductor substrate adjacent to the gate trench structure; a body region of a second conductivity type opposite to the first conductivity type, formed in the semiconductor substrate below the source region; and a drift zone of a first conductivity type formed in the semiconductor substrate below the body region, and A plurality of MOS gated diodes or Schottky diodes are formed in a semiconductor substrate, each of the plurality of MOS gated diodes or Schottky diodes being formed in an inactive region of a power transistor between adjacent ones of the transistor cells.

13. The method of claim 12, wherein forming the plurality of MOS-gated diodes or Schottky diodes in a semiconductor substrate comprises: Using a common trench etching process, while etching the gate trenches of the plurality of transistor cells into the semiconductor substrate, the electrode trenches of the plurality of MOS gated diodes or Schottky diodes are etched into the semiconductor substrate; forming a first dielectric on sidewalls and bottoms of the gate trench and the electrode trench; After forming the first dielectric, forming an electrode in the electrode trench to form an electrode trench structure; forming a first region of a second conductivity type in the semiconductor substrate adjacent to each electrode trench; forming a first region of the first conductivity type in each first region of the second conductivity type; as well as A conductive material is formed that electrically connects the first region of the first conductivity type and the first region of the second conductivity type to the electrode in each electrode trench.

14. The method of claim 13, wherein forming the gate trench structure comprises: forming a second dielectric on the sidewalls and the bottom of the gate trench, the second dielectric being thicker than the first dielectric; as well as After forming the second dielectric, an electrode is formed in the gate trench.

15. The method of claim 13, wherein: Using a common body implantation process, a first region of a second conductivity type is formed in the semiconductor substrate adjacent to each electrode trench while forming body regions of a plurality of transistor cells.

16. The method of claim 13, wherein: Forming the plurality of MOS-gated diodes or Schottky diodes in the semiconductor substrate further comprises: forming a second region of the second conductivity type in each first region of the second conductivity type, wherein the second region of the second conductivity type is more heavily doped than the first region of the second conductivity type, The conductive material contacts the second region of the second conductivity type.

17. The method of claim 13, wherein: Forming the plurality of MOS-gated diodes or Schottky diodes in the semiconductor substrate further comprises: The electrode trench structure and sections of the first region of the second conductivity type are recessed to reduce a thickness of the first region of the second conductivity type along sidewalls of the electrode trench.

18. The method of claim 17, wherein: The first region of the first conductivity type is formed in the recessed section of the first region of the second conductivity type.

19. The method of claim 13, wherein: Forming the plurality of MOS-gated diodes or Schottky diodes in the semiconductor substrate further comprises: etching a plurality of contact trenches into the semiconductor substrate, each contact trench laterally surrounding one of the electrode trenches and laterally spaced apart from the gate trench structures of adjacent ones of the transistor cells; and The plurality of contact trenches are filled with a conductive material.

20. The method of claim 12, wherein forming the plurality of MOS-gated diodes or Schottky diodes in a semiconductor substrate comprises: A conductive material is deposited in direct contact with an inactive region of the power transistor between adjacent ones of the transistor cells.

21. The method of claim 12, wherein forming the plurality of MOS-gated diodes or Schottky diodes in a semiconductor substrate comprises: etching a plurality of electrode trenches into the semiconductor substrate, each electrode trench being laterally spaced apart from a gate trench structure of an adjacent one of the transistor cells; as well as Metal is deposited that electrically connects the electrode in each electrode trench to a region of the semiconductor substrate adjacent to the electrode trench.

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