Chip packaging module, packaging method and electronic device having the module

Abstract

The present invention discloses a chip packaging module and a packaging method, wherein the chip packaging module comprises: a chip; a packaging substrate, which is opposite to the chip and forms a cavity therebetween; a first packaging layer, which packages the chip on the packaging substrate; and a second packaging layer, which covers the outer side of the first packaging layer, wherein: the first packaging layer comprises an extension portion extending outwardly along the packaging substrate, the lower side of the extension portion covers the upper side of the packaging substrate, and the end of the second packaging layer forms a surface contact with the upper side of the extension portion. The present invention also discloses an electronic device having the chip packaging module.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a chip packaging structure, a chip packaging method, and an electronic device with a chip packaging module. Background Art

[0002] As the basic elements of electronic devices, electronic devices have been widely used, including mobile phones, automobiles, household appliances, etc. In addition, technologies such as artificial intelligence, the Internet of Things, and 5G communications that will change the world in the future still need to rely on electronic devices as a foundation.

[0003] Film Bulk Acoustic Resonator (FBAR, also known as BAW) as an important member of piezoelectric devices is playing an important role in the communication field, especially FBAR filters have an increasingly larger market share in the field of radio frequency filters. FBAR has excellent characteristics such as small size, high resonant frequency, high quality factor, large power capacity, and good roll-off effect. Its filters are gradually replacing traditional surface acoustic wave (SAW) filters and ceramic filters, playing a huge role in the field of wireless communication radio frequency. Its high sensitivity advantage can also be applied to biological, physical, medical and other sensing fields.

[0004] Usually, thin film bulk acoustic wave resonators have specific packaging requirements in different application environments. At present, the more common one is wafer-level packaging, which not only increases the size of the device, but also has a large number of packaging steps, which increases the packaging cost. In recent years, with the rapid development of wireless mobile communication technology, wireless communication equipment has gradually developed in the direction of portable, multi-functional, high-performance and low-cost, which has prompted electronic components to develop in the direction of miniaturization, high integration, high reliability and high yield, and RF filters are no exception.

[0005] In recent years, based on meeting packaging needs, packaging technology with simple processes and low costs has developed rapidly. However, the airtightness and reliability of the packaging structure still need to be improved.

[0006] Fig. 9 FIG. 1 is a schematic diagram of a chip packaging structure in the prior art. Fig. 9 middle:

[0007] 10 is a substrate, which can be made of ceramic or organic materials, and includes three parts: a bottom substrate 101, a conductive layer 103, and an oil filter layer 105;

[0008] 11 is a chip welding structure, which can be MBM, solder ball, copper pillar, etc.;

[0009] 13 is a pad;

[0010] 15 is an unpackaged filter chip, which may be a FBAR chip, a SAW chip or a BAW chip;

[0011] 17 is an adhesive layer between chips and a peripheral protection layer;

[0012] 19 is the bonding layer between chips and the peripheral protection layer.

[0013] exist Fig. 9 In the structure shown, the outer protective layer 17 and the substrate 10 are vacuum pressed together, and the sealing and adhesion at the contact point are poor. In addition, moisture can easily penetrate the oil filter layer 105, destroying the cavity structure required by the filter chip 15 and affecting the device performance. Summary of the invention

[0014] The present invention is proposed to solve or alleviate at least one aspect of the technical problems existing in the prior art.

[0015] According to one aspect of an embodiment of the present invention, a chip packaging module is provided, comprising:

[0016] chip;

[0017] A packaging substrate, facing the chip and forming a cavity therebetween;

[0018] A first packaging layer, packaging the chip on a packaging substrate;

[0019] A second packaging layer is arranged to cover the outer side of the first packaging layer,

[0020] in:

[0021] The first encapsulation layer includes an extension portion extending outwardly along the transverse direction of the encapsulation substrate, the lower side of the extension portion covers the upper side of the encapsulation substrate, and the end of the second encapsulation layer forms a surface contact with the upper side of the extension portion.

[0022] The embodiment of the present invention further provides a chip packaging method, comprising the steps of:

[0023] Providing a packaging substrate;

[0024] Provide unpackaged chips;

[0025] Solder the chip upside down to the upper side of the package substrate;

[0026] Providing a first packaging layer, so that the first packaging layer packages the chip onto the packaging substrate, the first packaging layer has an extension portion extending outwardly along the packaging substrate, and the lower side of the extension portion covers the upper side of the packaging substrate;

[0027] A second encapsulation layer covering the first encapsulation layer is provided, and an end portion of the second encapsulation layer is in surface contact with an upper side of the extension portion.

[0028] An embodiment of the present invention also relates to an electronic device, comprising the above-mentioned chip packaging module or the chip packaging module manufactured according to the above-mentioned packaging method. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The following description and accompanying drawings may better help understand these and other features and advantages of various embodiments disclosed by the present invention, in which the same reference numerals always represent the same components, wherein:

[0030] Figure 1 is a schematic cross-sectional view of a chip packaging module according to an exemplary embodiment of the present invention;

[0031] Figure 2 is a schematic cross-sectional view of a chip packaging module according to an exemplary embodiment of the present invention;

[0032] Figure 2A for Figure 2 A partial enlarged schematic diagram of the contact portion between the first encapsulation layer and the substrate;

[0033] Figure 3 is a schematic cross-sectional view of a chip packaging module according to an exemplary embodiment of the present invention;

[0034] Figure 3A for Figure 3 A partial enlarged schematic diagram of the contact portion between the first encapsulation layer and the substrate;

[0035] Figure 4 is a schematic top view of a packaging structure of a chip packaging module according to an exemplary embodiment of the present invention;

[0036] Figure 4A for Figure 4 An enlarged schematic diagram of part A in FIG.

[0037] Figure 5 is a schematic top view of a packaging structure of a chip packaging module according to an exemplary embodiment of the present invention;

[0038] Figure 5A for Figure 5 An enlarged schematic diagram of part A in FIG.

[0039] Figure 5B for Figure 5 An enlarged schematic diagram of part A in FIG.

[0040] Figure 6 is a schematic top view of a packaging structure of a chip packaging module according to an exemplary embodiment of the present invention;

[0041] Fig. 6A for Figure 6 An enlarged schematic diagram of part A in FIG.

[0042] Figures 7A-7D A process diagram of a chip packaging method according to an embodiment of the present invention is exemplarily shown;

[0043] Figure 8 is a schematic cross-sectional view of a chip packaging module according to an exemplary embodiment of the present invention, which shows two chips;

[0044] Fig. 9 It is a schematic diagram of a chip packaging structure in the prior art. DETAILED DESCRIPTION

[0045] The technical solution of the present invention is further specifically described below by examples and in conjunction with the accompanying drawings. In the specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation of the present invention.

[0046] Figure 1 FIG. 1 is a schematic cross-sectional view of a chip packaging module according to an exemplary embodiment of the present invention. Figure 1 middle:

[0047] 10 is a substrate, which can be made of ceramics and organic materials. In an exemplary embodiment, the substrate 10 includes three parts: a bottom substrate 101, a conductive layer 103, and an oil filter layer 105;

[0048] 11 is a chip welding structure, which can be MBM, solder ball, copper pillar, etc.;

[0049] 13 is a soldering pad;

[0050] 15 is an unpackaged filter chip, which may be a FBAR chip, a SAW chip or a BAW chip;

[0051] 17 is a first packaging layer, i.e., an adhesive layer between chips and a peripheral protection layer;

[0052] Reference numeral 19 denotes a second packaging layer, which may also be an adhesive layer between chips and a peripheral protection layer.

[0053] like Figure 1 As shown, the first packaging layer 17 includes an extension portion extending outwardly along the packaging substrate (in FIG. 1 , that is, the lateral portion in contact with the substrate), and the lower side of the extension portion covers the upper side of the packaging substrate. Figure 1 As shown, the end of the second encapsulation layer 19 is in surface contact with the upper side of the extension portion.

[0054] In the present invention, "up" and "down" are determined in such a way that the substrate is below and the chip is above. In the present invention, the lateral direction is the direction parallel to the surface of the chip or the substrate. More specifically, in the drawings, it may correspond to the left - right direction in the figures.

[0055] In Figure 1 's structure, since the extension portion increases the contact area between the first encapsulation layer and the substrate, thereby increasing the adhesion between the first encapsulation layer and the substrate and improving the sealing effect.

[0056] Figure 2 FIG. is a schematic cross - sectional view of a chip packaging module according to an exemplary embodiment of the present invention. Figure 2A is Figure 2 A partial enlarged schematic view of the contact portion between the first encapsulation layer and the substrate in. As Figure 2 shown, the substrate is provided with a recess 107 at the position where it contacts the extension portion, which is beneficial to increasing the adhesion between the first encapsulation layer and the substrate and improving the sealing effect.

[0057] As Figure 2 shown, the height of the cavity is H1, 10μm ≤ H1 ≤ 150μm, the depth of the recess is H2, 0.05μm ≤ H2 ≤ 10μm; the range of the width W3 of the recess is: W3 ≥ H2.

[0058] In a further embodiment, as Figure 2 and 2A shown, the first encapsulation layer 17 includes a vertical portion covering the side surface of the semiconductor chip, and the vertical portion is connected to the extension portion; and the angle θ formed between the surface of the vertical portion facing the cavity and the upper side of the substrate is: 60 < θ < 90. As Figure 2A shown, in one embodiment, the side - wall roughness, that is, Figure 2A the roughness of the vertical surface AA' in

[0059] In a further embodiment of the present invention, as Figure 2 shown, the first width W1 of the first encapsulation layer is less than the second width W2 of the second encapsulation layer, and the first width W1 depends on the thickness of the first encapsulation layer, and its range can be 0 < W1 ≤ 50μm, the second width W2 ≥ 15μm, and the upper limit of the second width depends on the difference between the packaging size and the chip size. Based on the process capabilities and the difference between the packaging size and the chip size, the specific value of the width W2 is determined.

[0060] Figure 3 FIG. is a schematic cross - sectional view of a chip packaging module according to an exemplary embodiment of the present invention. Wherein, the portion of the substrate in contact with the extension portion is provided with a protrusion. Figure 3AFIG. 1 is a partial enlarged schematic diagram of the contact portion between the first packaging layer and the substrate. Figure 2 The sizes of the recesses shown in the figure can be similar, for example, the height of the cavity is H1, 10μm≤H1≤150μm, the height of the protrusion is H2, 0.05μm≤H2≤10μm; the width W3 of the protrusion is in the range of: W3≥H2. In addition, when the protrusion is provided, the height of the protrusion can be the same as the thickness of the metal layer on the surface of the substrate.

[0061] Figure 4 is a schematic top view of a packaging structure of a chip packaging module according to an exemplary embodiment of the present invention, Figure 4A for Figure 4 An enlarged schematic diagram of part A in FIG. Figure 4 As shown, the structure for increasing sealing provided on the substrate is annular. Figure 4A As shown, the depression 107 is a strip-shaped depression, and the number of the depressions may be multiple.

[0062] Figure 5 is a schematic top view of a packaging structure of a chip packaging module according to an exemplary embodiment of the present invention, Figure 5A for Figure 5 An enlarged schematic diagram of part A in FIG. Figure 5B for Figure 5 FIG. 1 is an enlarged schematic diagram of another embodiment of part A in FIG. Figure 5 As shown, the structure for increasing sealing provided on the substrate is annular (formed by discontinuous structures). Figure 5A As shown, the recess 107 has a rectangular shape. Figure 5B In the embodiment, the discretely distributed rectangular recesses 107 are staggered, which is beneficial to enhancing the resistance to gas passage in the lateral direction.

[0063] Figure 6 is a schematic top view of a packaging structure of a chip packaging module according to an exemplary embodiment of the present invention, Fig. 6A for Figure 6 This is an enlarged schematic diagram of part A in FIG. Figure 6 and 6A In the figure, the depression 107 is a circular depression.

[0064] Attached Figure 2-6A The sealing reinforcement part is shown to be formed of protrusions and / or depressions, etc. However, the sealing reinforcement part is not limited thereto, and for example, the sealing reinforcement part may include a rough surface structure disposed on the upper side of the package substrate 10 .

[0065] Figures 7A-7D The process diagram of the chip packaging method according to an embodiment of the present invention is exemplarily shown. Figures 7A-7D A chip packaging method is exemplarily described.

[0066] like Fig. 7A As shown, the oil filter layer 105 of the substrate 10 is etched to expose the required conductive portion 103, the protrusion 107 and the portion of the substrate 101 that needs to be pressed and contacted later.

[0067] like Figure 7B As shown, a plurality of unpackaged filter chips 15 are soldered upside down on the substrate 10 .

[0068] like Figure 7C As shown, vacuum pressing is used for sealing. After the first sealing layer 17 and the second sealing layer 19 are formed, an air cavity is provided for the filter chip 15, and then laser cutting (along the vertical dotted line) is performed.

[0069] It should be noted that when multiple chips are invertedly soldered to a substrate, the multiple chips are spaced apart from each other in the lateral direction, and the width of the extension portion between two adjacent chips is greater than or equal to 30 μm, and is twice or greater than twice the first width. As can be understood, twice here is an approximate number, for example, within the range of 1.5 times to 2.5 times.

[0070] like Fig.7D As shown, packaged chips are obtained after cutting.

[0071] It should be pointed out that the above packaging method can also be used to integrate multiple filter chips, or multiple active chips and filter chips. Figure 8 1 is a schematic cross-sectional view of a chip packaging module according to an exemplary embodiment of the present invention, which shows two chips. In the present invention, the filter chip includes at least one of a bulk acoustic wave filter and a surface acoustic wave filter.

[0072] Based on the above, the present invention proposes the following technical solutions:

[0073] 1. A chip packaging module, comprising:

[0074] chip;

[0075] A packaging substrate, facing the chip and forming a cavity therebetween;

[0076] A first packaging layer, packaging the chip on a packaging substrate;

[0077] A second packaging layer is arranged to cover the outer side of the first packaging layer,

[0078] in:

[0079] The first encapsulation layer includes an extension portion extending outwardly along the transverse direction of the encapsulation substrate, the lower side of the extension portion covers the upper side of the encapsulation substrate, and the end of the second encapsulation layer forms a surface contact with the upper side of the extension portion.

[0080] 2. The chip packaging module according to 1, wherein:

[0081] A sealing reinforcement portion is provided at least on a portion of the package substrate covered by the extension portion.

[0082] 3. The chip packaging module according to 2, wherein:

[0083] The sealing reinforcement portion includes a concave structure or a convex structure disposed on the upper side of the packaging substrate.

[0084] 4. The chip packaging module according to 3, wherein:

[0085] The concave structure or convex structure includes a strip-shaped ring or rectangular array or circular array structure formed by concave or convex.

[0086] 5. The chip packaging module according to 3, wherein:

[0087] The height of the cavity is H1, 10 μm≤H1≤150 μm;

[0088] The depth of the concave structure or the height of the convex structure is H2, 0.05 μm≤H2≤10 μm;

[0089] The width W3 of the concave structure or the convex structure is in the range of: W3 ≥ H2.

[0090] 6. The chip packaging module according to 2, wherein:

[0091] The sealing reinforcement portion includes a rough surface structure disposed on an upper side of the packaging substrate.

[0092] 7. The chip packaging module according to any one of 1 to 6, wherein:

[0093] The sealing reinforcement portion is arranged in a ring shape.

[0094] 8. The chip packaging module according to item 7, wherein:

[0095] The sealing reinforcement portion includes a discontinuous structure which is arranged in a ring shape as a whole.

[0096] 9. The chip packaging module according to item 1, wherein:

[0097] In a cross-sectional view extending through the chip and parallel to the upper surface of the chip, a first width W1 of the first encapsulation layer is smaller than a second width W2 of the second encapsulation layer.

[0098] 10. The chip packaging module according to 9, wherein:

[0099] The range of the first width W1 is: 0 < W1 ≤ 50 μm, and the range of the second width W2 is: W2 ≥ 15 μm.

[0100] 11. The chip packaging module according to any one of 1 - 10, wherein:

[0101] The first encapsulation layer includes a vertical portion covering the side surface of the semiconductor chip, and the vertical portion is connected to the extending portion; and

[0102] The angle θ formed between the surface of the vertical portion facing the cavity and the upper side of the substrate is: 60 < θ < 90.

[0103] 12. The chip packaging module according to any one of 1 - 10, wherein:

[0104] The chip at least includes a filter chip, and the filter chip at least includes one of a bulk acoustic wave filter or a surface acoustic wave filter.

[0105] 13. The chip packaging module according to 12, wherein:

[0106] The chip is a chip group composed of multiple chips arranged on the same layer and spaced apart in the lateral direction;

[0107] The multiple chips are spaced apart from each other in the lateral direction by the first encapsulation layer; and

[0108] The extending portion of the first encapsulation layer is provided outside the chip group.

[0109] 14. The chip packaging module according to 13, wherein:

[0110] The chip group includes multiple filter chips, or the chip group includes a filter chip and an active chip.

[0111] 15. A chip packaging method, comprising the steps of:

[0112] Providing a packaging substrate;

[0113] Providing an unpackaged chip;

[0114] Inverting and soldering the chip to the upper side of the packaging substrate;

[0115] Providing a first encapsulation layer such that the first encapsulation layer encapsulates the chip onto the packaging substrate, and the first encapsulation layer has an extending portion extending laterally outward along the packaging substrate, and the lower side of the extending portion covers the upper side of the packaging substrate;

[0116] Providing a second encapsulation layer covering the first encapsulation layer, and an end portion of the second encapsulation layer forms a surface contact with the upper side of the extending portion.

[0117] 16. The method according to 15, wherein:

[0118] The step of “providing a packaging substrate” further includes disposing a sealing reinforcement portion at a predetermined position of the packaging substrate, wherein the predetermined position is covered by the extension portion.

[0119] 17. The method according to 15 or 16, wherein:

[0120] The step of “upside down soldering the chip to the upper side of the package substrate” includes upside down soldering a plurality of chips to the upper side of the package substrate, wherein the plurality of chips are spaced apart from each other in a lateral direction;

[0121] The first encapsulation layer has a first width W1 , and in the step of “providing a first encapsulation layer”, the width of the extension portion between two adjacent chips is not less than 30 μm and is twice or greater than twice the first width W1 .

[0122] 18. The method according to 17, wherein:

[0123] The step of "upside down soldering the chip to the upper side of the packaging substrate" includes upside down soldering a plurality of filter chips to the upper side of the packaging substrate, or upside down soldering the filter chip and the active chip to the upper side of the packaging substrate.

[0124] 19. The method according to 17 or 18, further comprising:

[0125] The cutting step is to cut between predetermined adjacent chips to form a plurality of independent chip packaging modules.

[0126] 20. An electronic device, comprising the chip packaging module according to any one of 1 to 14 or the chip packaging module manufactured by the chip packaging method according to any one of 15 to 19.

[0127] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A chip packaging module, comprising: A chip; A packaging substrate, disposed opposite to the chip and forming a cavity therebetween; A first packaging layer for packaging the chip on the packaging substrate; A second packaging layer, covering the outside of the first packaging layer; Wherein: The first packaging layer includes an extension portion extending laterally outward along the packaging substrate, the lower side of the extension portion covers the upper side of the packaging substrate, and the end of the second packaging layer forms a surface contact with the upper side of the extension portion; At least a portion of the packaging substrate covered by the extension portion is provided with a sealing reinforcement portion, the extension portion completely covers the sealing reinforcement portion along the lateral direction of the packaging substrate, and the extension portion covers at least a partial area of the upper surface of the packaging substrate inside the sealing reinforcement portion.

2. The chip packaging module according to claim 1, wherein: The sealing reinforcement portion includes a concave structure or a convex structure provided on the upper side of the packaging substrate.

3. The chip packaging module according to claim 2, wherein: The concave structure or the convex structure includes a strip-shaped ring or a rectangular array or a circular array structure formed by a depression or a protrusion.

4. The chip packaging module according to claim 2, wherein: The height of the cavity is H1, 10μm ≤ H1 ≤ 150μm; The depth of the concave structure or the height of the convex structure is H2, 0.05μm ≤ H2 ≤ 10μm; The width W3 of the concave structure or the convex structure ranges from: W3 ≥ H2.

5. The chip packaging module according to claim 1, wherein: The sealing reinforcement portion includes a rough surface structure provided on the upper side of the packaging substrate.

6. The chip packaging module according to any one of claims 1-5, wherein: The sealing reinforcement portion is arranged in a ring shape.

7. The chip packaging module according to claim 6, wherein: The sealing reinforcement portion includes an intermittent structure arranged integrally in a ring shape.

8. The chip packaging module according to claim 1, wherein: In a cross-sectional view extending across the chip and parallel to the upper surface of the chip, a first width W1 of the first packaging layer is smaller than a second width W2 of the second packaging layer.

9. The chip packaging module according to claim 8, wherein: The range of the first width W1 is: 0 < W1 ≤ 50μm, and the range of the second width W2 is: W2 ≥ 15μm.

10. The chip packaging module according to any one of claims 1-5, 8, 9, wherein: The first packaging layer includes a vertical portion covering the side surface of the semiconductor chip, and the vertical portion is connected to the extension portion; and An angle θ formed between the surface of the vertical portion facing the cavity and the upper side of the packaging substrate is: 60 < θ < 90.

11. The chip packaging module according to any one of claims 1-5, 8, 9, wherein: The chip at least includes a filtering chip, and the filtering chip at least includes one of a bulk acoustic wave filter or a surface acoustic wave filter.

12. The chip packaging module according to claim 11, wherein: The chip is a chip group composed of multiple chips arranged in the same layer and spaced apart in the lateral direction; The plurality of chips are spaced apart from each other in a lateral direction by the first packaging layer.

13. The chip packaging module according to claim 12, wherein: The chipset includes a plurality of filter chips, or the chipset includes a filter chip and an active chip.

14. A chip packaging method, comprising the steps of: Providing a packaging substrate; Provide unpackaged chips; Solder the chip upside down to the upper side of the package substrate; Providing a first packaging layer, so that the first packaging layer packages the chip onto the packaging substrate, the first packaging layer has an extension portion extending outwardly along the packaging substrate, and the lower side of the extension portion covers the upper side of the packaging substrate; providing a second encapsulation layer covering the first encapsulation layer, wherein an end of the second encapsulation layer forms a surface contact with an upper side of the extension portion; The step of "providing a packaging substrate" also includes setting a sealing reinforcement portion at a predetermined position of the packaging substrate, wherein the predetermined position is completely covered by the extension portion, and the extension portion covers at least a portion of the upper surface of the packaging substrate located inside the sealing reinforcement portion.

15. The method according to claim 14, wherein: The step of "upside down soldering the chip to the upper side of the package substrate" includes upside down soldering a plurality of chips to the upper side of the package substrate, wherein the plurality of chips are spaced apart from each other in a lateral direction; The first encapsulation layer has a first width W1. In the step of “providing the first encapsulation layer”, the width of the extension portion between two adjacent chips is not less than 30 μm and is twice or greater than twice the first width W1.

16. The method of claim 15, wherein: The step of "invertedly soldering the chip to the upper side of the packaging substrate" includes invertedly soldering multiple filter chips to the upper side of the packaging substrate, or invertedly soldering the filter chip and the active chip to the upper side of the packaging substrate.

17. The method according to claim 15 or 16, further comprising: The cutting step is to cut between predetermined adjacent chips to form a plurality of independent chip packaging modules.

18. An electronic device, comprising the chip packaging module according to any one of claims 1 to 13 or the chip packaging module manufactured by the chip packaging method according to any one of claims 14 to 17.

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