Arbitrary depth asynchronous FIFO memory

Abstract

An arbitrary depth asynchronous FIFO memory is provided. The asynchronous FIFO memory includes a dual port memory, a write address decoder, a read address decoder, a full detection unit, a read pointer synchronization unit, an empty detection unit, and a write pointer synchronization unit. The write pointer decoder, the full detection unit, and the read pointer synchronization unit are located in a first clock domain. The read pointer decoder, the empty detection unit, and the write pointer synchronization unit are located in a second clock domain. The write pointer decoder is coupled to a write port of the dual port memory and provides a write pointer to the write port of the dual port memory. The read pointer decoder is coupled to a read port of the dual port memory and provides a read pointer to the write port of the dual port memory.

Description

TECHNICAL FIELD

[0001] The present application relates to storage circuits, in particular, to an asynchronous FIFO (First In First Out) memory of arbitrary depth. BACKGROUND

[0002] In the design of a SOC (System On Chip) with multiple clock domains, an asynchronous FIFO is often used to solve the problem of data transmission between different clock domains. After years of development, the design of an asynchronous FIFO has become mature, which not only makes the timing requirements of data transmission between different clock domains relaxed, but also improves the transmission efficiency between them.

[0003] Figure 1 A block diagram of an asynchronous FIFO of the prior art is shown.

[0004] Referring to Figure 1 , the asynchronous FIFO includes three main components, a FIFO memory (a dual-port memory (DualPort RAM) in the prior art), a write unit and a read unit. Figure 1 The left part in the figure is the write unit for writing data into the FIFO memory, and the right part is the read unit for reading data from the FIFO memory. The write unit and the read unit are located in different clock domains, which are called the write clock domain and the read clock domain, respectively. Figure 1

[0005] The write unit writes data into the FIFO memory, and the read unit reads data from the FIFO memory. The FIFO memory is regarded as a ring queue, for example, the write operation to it occurs at the tail of the queue, and the read operation occurs at the head. Thus, the write unit maintains the write pointer (wptr) of the FIFO memory, and each write operation to the FIFO memory writes data into the position of the FIFO memory indicated by the write pointer (wptr). After each write operation to the FIFO memory is completed, the wptr is incremented. When the wptr reaches the maximum value, it wraps around. The read unit maintains the read pointer (rptr) of the FIFO memory, and each read operation to the FIFO memory accesses the FIFO memory according to the read pointer (rptr) and obtains the read data. After each read operation to the FIFO memory is completed, the rptr is incremented. When the rptr reaches the maximum value, it wraps around.

[0006] The FIFO memory can be in an empty state or a full state. When the FIFO is in the empty state, reading data from it is prohibited; when the FIFO is in the full state, writing data into it is prohibited. Whether the FIFO memory is in the empty state or the full state is identified by comparing the values of the read pointer rptr and the write pointer wptr.

[0007] ​Since the read unit and the write unit are in two clock domains respectively, the asynchronous FIFO storage also includes two synchronization modules: "synchronize to write clk" and "synchronize to read clk". The function of "synchronize to write clk" is to transmit the read pointer rptr generated by the read unit for reading data from the FIFO storage to the write clock domain, and the function of "synchronize to read clk" is to transmit the write pointer wptr used by the write unit for writing data to the FIFO storage to the read clock domain.

[0008] Thus, the write unit can compare the write pointer wptr maintained by itself with the read pointer rptr provided by "synchronize to write clk", so as to generate the full flag. Similarly, the read unit compares the read pointer rptr maintained by itself with the write pointer provided by "synchronize to read clk", so as to generate the empty flag.

[0009] In the process of pointer synchronization, if a binary counter is directly used, the pointer synchronization error can be caused due to the flip of multiple data bits during the value jump. For example, when the pointer changes from 0b0111 to 0b1000, each bit of the data bit is flipped, and if the asynchronous clock of the receiving end is directly used to sample it at this time, any intermediate value can be appeared (it is possible that the receiving end sees 0b0111→0b0101→0b1000), so that the full / empty judgment error can be caused to cause the misreading or miswriting of the FIFO storage.

[0010] Therefore, in the design of the asynchronous FIFO storage, the Gray code in which only 1 bit of adjacent data is changed is usually selected to transmit the read / write pointer. In the change of 0b0111→0b1000 in the above example, the corresponding Gray code is 0b0100→0b1100. Thus, even if the receiving end samples the metastable pointer value, the sampled value is either 0b0100 or 0b1100, and no other unpredictable value can be appeared.

[0011] Taking an asynchronous FIFO with a depth of 8 as an example, 4-bit Gray code is needed as the value of the read / write pointer. Table 1 shows the relationship between the read / write pointer and the Gray code.

[0012] The rightmost column of Table 1, "Pointer," represents the read / write pointer value for accessing the FIFO memory. As an example, the FIFO memory has 8 memory cells. The "Pointer" value sequentially changes from 0 to 7, with each value representing a memory cell of the FIFO memory. In a full cycle, the "Pointer" value goes through two rounds of change from 0 to 7. When the "Pointer" value is 7, the next time the "Pointer" value for accessing the FIFO memory wraps around to 0.

[0013] The leftmost column of Table 1, "Decimal," represents the state of the pointer. For a FIFO memory with a depth of 8, the pointer has 16 states (0-15), each corresponding to a value of the "Pointer" during the two rounds of change from 0 to 7 in a full cycle.

[0014] The "Binary Count" column of Table 1, each value of which corresponds to each value of the "Decimal" column, is the binary representation of the value of the "Decimal" column. The "Gray Code" column of Table 1, each value of which corresponds to each value of the "Binary Count" column, is the corresponding Gray code of the value of the "Binary Count" column.

[0015] Table 1

[0016]

[0017] The asynchronous FIFO memory also maintains empty and full flags. The full detection unit of the write cell (Full flag Logic) generates a full status flag (denoted as Full). The empty detection unit of the read cell (Empty flag Logic) generates an empty status flag (denoted as Empty).

[0018] The empty detection unit compares the read pointer rptr maintained by the read cell with the write pointer (denoted as (wptr_sync)) provided by the "synchronization module to the read cell," where the empty status flag Empty = (wptr_sync == rptr)? 1'b1 : 1'b0. The full detection unit compares the write pointer wptr maintained by the write cell with the read pointer (denoted as rptr_sync) provided by the "synchronization module to the write cell," where the full status flag Full = (wptr_bin[n]!= rptr_sync_bin[n])?(wptr_bin[n-1:0] == rptr_sync_bin[n-1:0]): 1'b0.

[0019] When the read and write pointers are equal, the FIFO is empty; when the read and write pointers differ by the FIFO depth, the FIFO is full. Because the depth of an asynchronous FIFO memory is a power of two (e.g., 8 = 2^3), the fullness check is also very simple: convert both pointers to binary, and when the highest bits are not equal but all the lower bits are equal, the FIFO is full. SUMMARY

[0020] Figure 1 The FIFO design of the prior art is simple, but has the disadvantage that the depth can only be a power of two, greatly limiting its use. If an asynchronous FIFO of depth 11 is to be designed, using the current design, a memory of depth 16 (the closest power of two to 11) is actually required, with the extra 5 depth being used only to accommodate the encoding, and not actually contributing to the transmission efficiency or storage capacity. In short, the extra 5 depth wastes chip area, and is unnecessary.

[0021] According to a first aspect of the present application, there is provided a first asynchronous FIFO memory according to the first aspect of the present application, comprising a dual-port memory, a write address decoder, a read address decoder, a full detection unit, a read pointer synchronization unit, an empty detection unit and a write pointer synchronization unit; the write pointer decoder, the full detection unit and the read pointer synchronization unit are located in a first clock domain; the read pointer decoder, the empty detection unit and the write pointer synchronization unit are located in a second clock domain; the write pointer decoder is coupled to the write port of the dual-port memory and provides a write pointer to the write port of the dual-port memory; the read pointer decoder is coupled to the read port of the dual-port memory and provides a read pointer to the write port of the dual-port memory; characterized in that the write pointer decoder comprises a first state counter, a write pointer counter, a first Gray code decoder and a reverse Gray code decoder; the read pointer decoder comprises a second state counter, a read pointer counter and a Gray code decoder; the first state counter and the second state counter each continuously count in binary from 0 to M-1 and then from 2^(n+1)-M to 2^(n+1)-1 with a step of 1, where M is the depth of the asynchronous FIFO memory; the first state counter is coupled to the write pointer counter, the first Gray code decoder and the reverse Gray code decoder; the write pointer counter continuously counts in binary from 0 to M-1 with a step of 1, and the count value of the write pointer counter is taken as the write pointer provided by the write pointer decoder to the write port of the dual-port memory; the first Gray code decoder converts the binary count value provided by the first state counter into a Gray code; the reverse Gray code decoder converts the binary count value provided by the first state counter into a reverse Gray code; the output of the first Gray code decoder is coupled to the write pointer synchronization unit; the output of the reverse Gray code decoder is coupled to the full detection unit.

[0022] According to the first asynchronous FIFO memory according to the first aspect of the present application, there is provided a second asynchronous FIFO memory according to the first aspect of the present application, wherein the second state counter is coupled to the read pointer counter and the second Gray code decoder; the read pointer counter continuously counts in binary from 0 to M-1 with a step of 1, and the count value of the read pointer counter is taken as the read pointer provided by the read pointer decoder to the read port of the dual-port memory; the second Gray code decoder converts the binary count value provided by the second state counter into a Gray code; the output of the second Gray code decoder is coupled to the read pointer synchronization unit; the output of the second Gray code decoder is also coupled to the empty detection unit.

[0023] According to the first or second asynchronous FIFO memory of the first aspect of the present application, there is provided a third asynchronous FIFO memory according to the first aspect of the present application, wherein if the count value i outputted by the first state counter is in the range of 0 to (M-1), the reverse Gray code decoder converts the count value i outputted by the first state counter into G(M-1-i), wherein G(i) represents the Gray code of the binary value i; if the count value 2^(n+1)-M+i outputted by the first state counter is in the range of 2^(n+1)-M to 2^(n+1)-1, the reverse Gray code decoder converts the count value 2^(n+1)-M+i outputted by the first state counter into G(2^(n+1)-1-i), wherein n is the result of rounding up Log2(M).

[0024] According to the second or third asynchronous FIFO memory of the first aspect of the present application, there is provided a fourth asynchronous FIFO memory according to the first aspect of the present application, wherein the output of the read pointer synchronization unit and the output of the reverse Gray code decoder are coupled to the full detection unit; the output of the write pointer synchronization unit and the output of the second Gray code decoder are coupled to the empty detection unit.

[0025] According to the fourth asynchronous FIFO memory of the first aspect of the present application, there is provided a fifth asynchronous FIFO memory according to the first aspect of the present application, wherein the full detection unit outputs a full state flag according to the output of the read pointer synchronization unit and the output of the reverse Gray code decoder being opposite in the highest bit and same in other bits, and outputs a non-full state flag otherwise.

[0026] According to the fourth or fifth asynchronous FIFO memory of the first aspect of the present application, there is provided a sixth asynchronous FIFO memory according to the first aspect of the present application, wherein the empty detection unit outputs an empty state flag according to the output of the write pointer synchronization unit and the output of the second Gray code decoder being same, and outputs a non-empty state flag otherwise.

[0027] The first clock domain and the second clock domain are different clock domains.

[0028] According to a second aspect of the present application, there is provided a first asynchronous FIFO memory according to the second aspect of the present application, comprising a dual-port memory, a write address decoder, a read address decoder, a full detection unit, a read pointer synchronization unit, an empty detection unit and a write pointer synchronization unit; the write pointer decoder, the full detection unit and the read pointer synchronization unit are located in a first clock domain; the read pointer decoder, the empty detection unit and the write pointer synchronization unit are located in a second clock domain; the write pointer decoder is coupled to a write port of the dual-port memory and provides a write pointer to the write port of the dual-port memory; the read pointer decoder is coupled to a read port of the dual-port memory and provides a read pointer to the write port of the dual-port memory; characterized in that the write pointer decoder comprises a first state counter, a write pointer counter and a first Gray code decoder; the read pointer decoder comprises a second state counter, a read pointer counter, a second Gray code decoder and a reverse Gray code conversion unit; the first state counter and the second state counter each continuously count in binary from 0 to M-1 and then from 2^(n+1)-M to 2^(n+1)-1 with a step of 1, where M is the depth of the asynchronous FIFO memory; the first state counter is coupled to the write pointer counter and the first Gray code decoder; the second state counter is coupled to the read pointer counter and the second Gray code decoder; the read pointer counter continuously counts in binary from 0 to M-1 with a step of 1, and the count value of the read pointer counter is taken as the read pointer provided by the read pointer decoder to the read port of the dual-port memory; the second Gray code decoder converts the binary count value provided by the second state counter into a Gray code; the output of the reverse Gray code conversion unit is coupled to the read pointer synchronization unit; the output of the second Gray code decoder is coupled to the empty detection unit; the reverse Gray code conversion unit converts the output of the second Gray code decoder into a reverse Gray code.

[0029] According to the first asynchronous FIFO memory according to the second aspect of the present application, there is provided a second asynchronous FIFO memory according to the second aspect of the present application, wherein the first state counter is coupled to the write pointer counter and the first Gray code decoder; the write pointer counter continuously counts in binary from 0 to M-1 with a step of 1, and the count value of the write pointer counter is taken as the write pointer provided by the write pointer decoder to the write port of the dual-port memory; the first Gray code decoder converts the binary count value provided by the first state counter into a Gray code; the output of the first Gray code decoder is coupled to the write pointer synchronization unit; the output of the first Gray code decoder is also coupled to the full detection unit.

[0030] According to the first or second asynchronous FIFO memory of the second aspect of the present application, there is provided a third asynchronous FIFO memory according to the second aspect of the present application, wherein if the Gray code outputted by the second Gray code decoder is G(i), where i is the value of the second state counter in the range of 0-(M-1), the reverse Gray code conversion unit converts the output of the second Gray code decoder into G(M-1-i); if the count value outputted by the second state counter is 2^(n+1)-M+i in the range of 2^(n+1)-M to 2^(n+1)-1, the reverse Gray code conversion unit converts the output of the second Gray code decoder into G(2^(n+1)-1-i), where n is the result of rounding up Log2(M).

[0031] According to the second or third asynchronous FIFO memory of the second aspect of the present application, there is provided a fourth asynchronous FIFO memory according to the second aspect of the present application, wherein the output of the read pointer synchronization unit and the output of the first Gray code decoder are coupled to the full detection unit; the output of the write pointer synchronization unit and the output of the second Gray code decoder are coupled to the empty detection unit.

[0032] According to the fourth asynchronous FIFO memory of the second aspect of the present application, there is provided a fifth asynchronous FIFO memory according to the second aspect of the present application, wherein the full detection unit outputs a full state flag according to the output of the read pointer synchronization unit and the output of the first Gray code decoder, where the highest bit is opposite and the other bits are the same, otherwise a non-full state flag is outputted.

[0033] According to the fourth or fifth asynchronous FIFO memory of the second aspect of the present application, there is provided a sixth asynchronous FIFO memory according to the second aspect of the present application, wherein the empty detection unit outputs an empty state flag according to the output of the write pointer synchronization unit and the output of the first Gray code decoder, where they are the same, otherwise a non-empty state flag is outputted.

[0034] According to a third aspect of the present application, there is provided a first asynchronous FIFO memory according to the third aspect of the present application, comprising a dual-port memory, a write address decoder, a read address decoder, a full detection unit, a read pointer synchronization unit, an empty detection unit and a write pointer synchronization unit; the write pointer decoder, the full detection unit and the read pointer synchronization unit are located in a first clock domain; the read pointer decoder, the empty detection unit and the write pointer synchronization unit are located in a second clock domain; the write pointer decoder is coupled to a write port of the dual-port memory and provides a write pointer to the write port of the dual-port memory; the read pointer decoder is coupled to a read port of the dual-port memory and provides a read pointer to the write port of the dual-port memory; characterized in that the write pointer decoder comprises a first state counter, a write pointer counter and a first Gray code decoder; the read pointer decoder comprises a second state counter, a read pointer counter and a second Gray code decoder; the first state counter and the second state counter each continuously count in a range of 0 to M-1 in binary and then 2^(n+1)-M to 2^(n+1)-1 in binary with a step of 1, where M is the depth of the asynchronous FIFO memory; the first state counter is coupled to the write pointer counter and the first Gray code decoder; the write pointer counter continuously counts in a range of 0 to M-1 in binary with a step of 1, and the count value of the write pointer counter is taken as the write pointer provided by the write pointer decoder to the write port of the dual-port memory; the first Gray code decoder converts the binary count value provided by the first state counter into a Gray code; the output of the first Gray code decoder is coupled to the write pointer synchronization unit; the output of the first Gray code decoder is coupled to the full detection unit; the asynchronous FIFO memory further comprises a reverse Gray code conversion unit located in the first clock domain, the input of the reverse Gray code conversion unit is coupled to the output of the read pointer synchronization unit, the output of the reverse Gray code conversion unit is coupled to the input of the full detection unit, and the reverse Gray code decoder converts the Gray code of the read pointer output by the read pointer synchronization unit into a reverse Gray code.

[0035] According to the first asynchronous FIFO memory according to the third aspect of the present application, there is provided a second asynchronous FIFO memory according to the third aspect of the present application, wherein the second state counter is coupled to the read pointer counter and the second Gray code decoder; the read pointer counter continuously counts in a range of 0 to M-1 in binary with a step of 1, and the count value of the read pointer counter is taken as the read pointer provided by the read pointer decoder to the read port of the dual-port memory; the second Gray code decoder converts the binary count value provided by the second state counter into a Gray code; the output of the second Gray code decoder is coupled to the read pointer synchronization unit; the output of the second Gray code decoder is also coupled to the empty detection unit.

[0036] According to the first or second asynchronous FIFO memory of the third aspect of the present application, there is provided a third asynchronous FIFO memory according to the third aspect of the present application, wherein if the Gray code outputted by the second Gray code decoder is G(i), where i is the value of the second state counter in the range of 0-(M-1), the reverse Gray code conversion unit converts the Gray code outputted by the read pointer synchronization unit into G(M-1-i); if the count value 2^(n+1)-M+i outputted by the second state counter is in the range of 2^(n+1)-M to 2^(n+1)-1, the reverse Gray code conversion unit converts the Gray code outputted by the read pointer synchronization unit into G(2^(n+1)-1-i), where n is the result of rounding up Log2(M).

[0037] According to the third or fourth asynchronous FIFO memory of the third aspect of the present application, there is provided a fifth asynchronous FIFO memory according to the third aspect of the present application, wherein the output of the first Gray code decoder and the output of the reverse Gray code conversion unit are coupled to the full detection unit; the output of the write pointer synchronization unit and the output of the second Gray code decoder are coupled to the empty detection unit.

[0038] According to the fifth asynchronous FIFO memory of the third aspect of the present application, there is provided a sixth asynchronous FIFO memory according to the third aspect of the present application, wherein the full detection unit outputs a full state flag according to the output of the read pointer synchronization unit and the output of the reverse Gray code conversion unit, i.e. the most significant bit is opposite and the other bits are the same, otherwise a non-full state flag is outputted.

[0039] According to the fifth or sixth asynchronous FIFO memory of the third aspect of the present application, there is provided a seventh asynchronous FIFO memory according to the third aspect of the present application, wherein the empty detection unit outputs an empty state flag according to the output of the write pointer synchronization unit and the output of the second Gray code decoder, i.e. the same, otherwise a non-empty state flag is outputted.

[0040] According to a fourth aspect of the present application, there is provided a first asynchronous FIFO memory according to the fourth aspect of the present application, comprising a dual-port memory, a write address decoder, a read address decoder, a full detection unit, a read pointer synchronization unit, an empty detection unit and a write pointer synchronization unit; the write pointer decoder, the full detection unit and the read pointer synchronization unit are located in a first clock domain; the read pointer decoder, the empty detection unit and the write pointer synchronization unit are located in a second clock domain; the write pointer decoder is coupled to the write port of the dual-port memory and provides a write pointer to the write port of the dual-port memory; the read pointer decoder is coupled to the read port of the dual-port memory and provides a read pointer to the write port of the dual-port memory; characterized in that the write pointer decoder comprises a write pointer counter, a first Gray code generation unit and a reverse Gray code generation unit; the read pointer decoder comprises a read pointer counter and a second Gray code generation unit; the read pointer counter and the write pointer counter each continuously count in the range of 0 to M-1 in binary with a step size of 1, where M is the depth of the asynchronous FIFO memory; the read pointer counter and the write pointer counter each further comprise a cycle marker register, which flips every time the counter's count value wraps from M-1 to 0; the write pointer counter is coupled to the first Gray code generation unit and the reverse Gray code generation unit; the count value of the write pointer counter is provided as the write pointer of the write pointer decoder to the write port of the dual-port memory; the first Gray code generation unit converts the value of the write pointer counter and the cycle marker into a Gray code; the reverse Gray code generation unit converts the value of the write pointer counter and the cycle marker into a reverse Gray code; the output of the first Gray code generation unit is coupled to the write pointer synchronization unit; the output of the reverse Gray code decoder is coupled to the full detection unit.

[0041] According to the first asynchronous FIFO memory according to the fourth aspect of the present application, there is provided a second asynchronous FIFO memory according to the fourth aspect of the present application, wherein the read pointer counter is coupled to the second Gray code generation unit; the count value of the read pointer counter is provided as the read pointer of the read pointer decoder to the read port of the dual-port memory; the second Gray code generation unit converts the value of the write pointer counter and the cycle marker into a Gray code; the output of the second Gray code generation unit is coupled to the read pointer synchronization unit; the output of the second Gray code generation unit is also coupled to the empty detection unit.

[0042] According to the first or second asynchronous FIFO memory of the fourth aspect of the present application, the third asynchronous FIFO memory of the fourth aspect of the present application is provided, wherein if the cycle mark of the write pointer counter is the first value, the first Gray code generating unit converts the output of the write pointer counter into a Gray code G(i), wherein i is the value of the write pointer counter, and the reverse Gray code generating unit converts the output of the write pointer counter into a Gray code G(M-1-i); if the cycle mark of the write pointer counter is the second value, the first Gray code generating unit converts the output of the write pointer counter into a Gray code G(2^(n+1)-M+i), and the reverse Gray code generating unit converts the output of the write pointer counter into a Gray code G(2^(n+1)-1-i), wherein n is the result of rounding up Log2(M).

[0043] According to the second or third asynchronous FIFO memory of the fourth aspect of the present application, the fourth asynchronous FIFO memory of the fourth aspect of the present application is provided, wherein the output of the reverse Gray code generating unit and the output of the read pointer synchronization unit are coupled to the full detection unit; and the output of the write pointer synchronization unit and the output of the second Gray code generating unit are coupled to the empty detection unit.

[0044] According to the fourth asynchronous FIFO memory of the fourth aspect of the present application, the fifth asynchronous FIFO memory of the fourth aspect of the present application is provided, wherein the full detection unit outputs a full state mark according to the output of the read pointer synchronization unit and the highest bit of the output of the reverse Gray code generating unit being opposite and other bits being same, and outputs a non-full state mark otherwise.

[0045] According to the fourth or fifth asynchronous FIFO memory of the fourth aspect of the present application, the sixth asynchronous FIFO memory of the fourth aspect of the present application is provided, wherein the empty detection unit outputs an empty state mark according to the output of the write pointer synchronization unit and the output of the second Gray code generating unit being same, and outputs a non-empty state mark otherwise. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0047] Figure 1 A block diagram of an asynchronous FIFO of the prior art is shown;

[0048] Figure 2A A block diagram of an asynchronous FIFO memory according to an embodiment of the present application is shown.

[0049] Figure 2B Figures 3A-3C show mapping tables of various encodings according to embodiments of the present application;

[0050] Figure 3A 3B Figures 3A-3C show mapping tables of various encodings according to embodiments of the present application;

[0051] Figure 4 Figure 4 shows a block diagram of an asynchronous FIFO memory according to another embodiment of the present application;

[0052] Figure 5 Figure 4 shows a block diagram of an asynchronous FIFO memory according to another embodiment of the present application; and

[0053] Figure 6 Figure 4 shows a block diagram of an asynchronous FIFO memory according to another embodiment of the present application. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person skilled in the art without any creative work fall within the protection scope of the present application.

[0055] Figure 2A Figure 4 shows a block diagram of an asynchronous FIFO memory according to another embodiment of the present application.

[0056] Referring to Figure 2A , the depth of the asynchronous FIFO memory according to the embodiment of the present application is M (M is a positive integer). For example, M can be a non-2 integer power. The asynchronous FIFO memory comprises a dual-port memory 210, a write address decoding unit 240 and a read address decoding unit 270. The write address decoding unit 240 is coupled to a write port of the dual-port memory 210, and provides a write pointer for writing data to the write port, the value range of the write pointer being 0-(M-1). The read address decoding unit 270 is coupled to a read port of the dual-port memory 210, and provides a read pointer for reading out data from the read port, the value range of the read pointer being 0-(M-1). The write address decoding unit 240 and the read address decoding unit 270 are respectively located in different clock domains.

[0057] It can be understood that, for operating the dual-port memory 210, control signals are further provided to the dual-port memory 210 to implement read / write operations, and write data or output data are provided to or received from the dual-port memory 210. These are not shown in Figure 2A .

[0058] Figure 2A ​The asynchronous FIFO memory also includes a read pointer synchronization unit 252, a write pointer synchronization unit 282, a full detection unit 254, and an empty detection unit 284.

[0059] The read pointer synchronization unit 252 provides the read pointer obtained from the read address decoding unit 270 to the full detection unit 254. The full detection unit compares the read pointer provided by the synchronization unit 252 with the write pointer obtained from the write address decoding unit 240, and generates a full status flag indicating whether the FIFO memory is "full". Data can be written to the FIFO memory only when it is not full.

[0060] The write pointer synchronization unit 282 provides the write pointer obtained from the write address decoding unit 240 to the empty detection unit 284. The empty detection unit 284 compares the write pointer provided by the synchronization unit 282 with the read pointer obtained from the read address decoding unit 270, and generates an empty status flag indicating whether the FIFO memory is "empty". Data can be read from the FIFO memory only when it is not empty.

[0061] The write address decoding unit 240 includes a state counter 242, a write pointer counter 244, a Gray code decoder 246, and a reverse Gray code decoder 248.

[0062] The depth of the asynchronous FIFO according to the embodiment of the present application is M, and the integer M is expressed by n bits, so that n is the result of rounding up Log2(M). For example, M = 15, and n is 4.

[0063] The state counter 242 is incremented in response to each write of data to the dual-port memory 210. The state counter 242 is a binary code counter, and its bit width is n+1. The counting value of the state counter 242 ranges over two continuous parts, from binary 0 to M-1, and from binary 2^(n+1)-M to 2^(n+1)-1. Within each range part, the state counter 242 counts continuously in binary code with a step of 1. When the state counter 242 counts to the end of the first range part, M-1, the value of the next count is 2^(n+1)-M; when the state counter 242 counts to the end of the second range part, 2^(n+1)-1, the value of the next count is 0.

[0064] The state counter 242 of the write address decoding unit 240 is also coupled to the write pointer counter 244, the Gray code decoder 246 and the reverse Gray code decoder 248, respectively. The binary count value of the state counter 242 is provided to the Gray code decoder 246 and the reverse Gray code decoder 248 simultaneously, to generate corresponding Gray code and reverse Gray code, respectively, according to the binary count value. In response to each count, the state counter 242 provides a signal to the write pointer counter 244 to cause the write pointer counter 244 to count accordingly. The write pointer counter 244 is a binary code counter, with a bit width of n, and a count range from binary 0 to M-l. When the write pointer counter 244 counts to the end of the count range portion, M-l, the value of the next count is 0. Alternatively, in response to each write of data to the dual-port memory 210, the write address decoding unit 240 provides a count signal to the write pointer counter 244.

[0065] The count value of the write pointer counter 244 is provided to the dual-port memory 210 as the write pointer provided by the write address decoding unit 240 to the dual-port memory 210, to indicate the address for writing data to the dual-port memory 210.

[0066] The bit width of each of the Gray code decoder 246 and the reverse Gray code decoder 248 is n+1. There are various conversion schemes from binary code to Gray code in the prior art, all of which can be used for the Gray code decoder 246 according to embodiments of the present application.

[0067] The count value of the state counter 242 ranges over two consecutive parts, the first range from binary 0 to M-1, and the second range from binary 2^(n+1)-M to 2^(n+1)-1. The count value of the state counter 242 is provided to the Gray code decoder 246, so that the Gray code decoder 246 also outputs the Gray code corresponding to the binary number in the two ranges accordingly. And in each range, the binary number outputted by the state counter 242 is sequentially increasing, so that the Gray code outputted by the Gray code counter 246 is also in order. The Gray code outputted by the Gray code counter 246 in the first range is sequentially recorded as P(0), P(1),... P(M-1). Accordingly, the corresponding output of the reverse Gray code counter 248 in the first range is P(M-1), P(M-2),... P(0) according to the embodiment of the present application. That is, the result outputted by the reverse Gray code counter 248 is symmetric about the midpoint of the consecutive range of the count value of the state counter 242, as the result outputted by the Gray code counter 246. So for the count value i outputted by the state counter 242 (in the range of 0~M-1), the Gray code decoder 246 converts the count value to the corresponding Gray code (recorded as G(i), representing the Gray code of i), while the reverse Gray code counter 248 converts the count value to (G(M-1-i)). Similarly, so for the count value 2^(n+1)-M+i outputted by the state counter 242 (i in the range of 0~M-1), the Gray code decoder 246 converts the count value to the corresponding Gray code (recorded as G(2^(n+1)-M+i)), while the reverse Gray code counter 248 converts the count value to (G(2^(n+1)-1-i)).

[0068] The Gray code outputted by the Gray code decoder 246 is provided to the write pointer synchronization unit 282. The reverse Gray code outputted by the reverse Gray code decoder 248 is provided to the full detection unit 254.

[0069] The full detection unit 254 receives the output of the reverse Gray code decoder 248 (recorded as wptr_rev, bit width n+1), and also receives the output of the synchronization unit 252 (recorded as rptr_sync, bit width n+1). The full detection unit 254 generates the full state flag Full = (wptr_rev[n]!= rptr_sync[n])?(wptr_rev[n-1:0] == rptr_sync[n-1:0]):1'b0. When the full state flag Full indicates that the FIFO memory is not full, data is written to the dual-port memory 210.

[0070] The read address decoding unit 270 includes a state counter 272, a read pointer counter 274 and a Gray code decoder 276.

[0071] The state counter 272 is incremented in response to each read of data from the dual-port memory 210. The state counter 272 is a binary counter with a bit width of n+1. The count value of the state counter 272 ranges over two consecutive parts, from binary 0 to M-1, and from binary 2^(n+1)-M to 2^(n+1)-1. Within each range part, the state counter 272 counts consecutively in binary with a step of 1. When the state counter 272 counts to the end of the first range part, M-1, the next count value is 2^(n+1)-M; when the state counter 272 counts to the end of the second range part, 2^(n+1)-1, the next count value is 0. Optionally, the state counter 272 is the same as the state counter 242.

[0072] The state counter 272 of the read address decoding unit 270 is further coupled to a read pointer counter 274 and a Gray code decoder 276, respectively. The binary count value of the state counter 272 is provided to the Gray code decoder 276 to generate a corresponding Gray code from the binary count value. The Gray code decoder 276 has a bit width of n+1. In response to each count, the state counter 272 provides a signal to the read pointer counter 274 to cause the read pointer counter 274 to count accordingly. The read pointer counter 274 is a binary counter with a bit width of n and a count range from binary 0 to M-1. When the read pointer counter 274 counts to the end of the count range part, M-1, the next count value is 0. Optionally, the read address decoding unit 270 provides a count signal to the read pointer counter 274 in response to each read of data from the dual-port memory 210.

[0073] The count value of the read pointer counter 274 is provided to the dual-port memory 210 as a read pointer provided by the read address decoding unit 270 to the dual-port memory 210 to indicate an address from which data is read from the dual-port memory 210.

[0074] The output of the Gray code decoder 276 is provided to the read pointer synchronization unit 252 and the empty detection unit 284.

[0075] The empty detection unit 284 receives the output of the Gray code decoder 276 (denoted as rptr with a bit width of n+1) and also receives the output of the synchronization unit 282 (denoted as wptr_sync with a bit width of n+1). The empty detection unit 284 generates an empty status flag Empty = (wptr_sync == rptr)? 1’b1 : 1’b0. Data is read from the dual-port memory 210 only when the empty status flag Empty indicates that the FIFO memory is not empty.

[0076] Figure 2B Mapping tables for various encodings according to embodiments of the present application are shown.

[0077] The "state counter" column of the mapping table indicates the state represented by the state counter (242, 272, see also Fig. 2) but not the count value of the state counter. For the example of an asynchronous FIFO memory with a depth of M, the state counter accordingly has 2M states, and the mapping table accordingly has 2M rows, each row corresponding to one state of the state counter. The states of the state counter are divided into two groups, the first group being states S_0 to S_(M-1) and the second group being states S_M to S_(2M-1). Figure 2A The "binary code" column of the mapping table indicates the binary count value corresponding to the state of the state counter (242, 272) as indicated in the "state counter" column. For the first group of states S_0 to S_(M-1), the count value of the state counter (242, 272) is BIN(0) to BIN(M-1), respectively. For the second group of states S_M to S_(2M-1), the count value of the state counter (242, 272) is BIN(2^(n+1)-M) to BIN(2^(n+1)-1), respectively. For each group of states, the count value of the state counter (242, 272) is continuously incremented. However, when entering from one group of states to the other group of states, the count value of the state counter (242, 272) is discontinuously jumped by a jump value of 2^(n+1)-2M+1. That is, the count value of the state counter (242, 272) for the last state of the first group of states is BIN(M-1), and the count value after the next jump is BIN(2^(n+1)-M).

[0078] It is to be understood that, although

[0079] is shown by a unified mapping table, Figure 2B the state counters (242, 272) in Figure 2A respectively record the states.

[0080] The "address pointer" column of the mapping table indicates the address provided by the write pointer counter (244) or the read address counter (274) to the dual-port memory 210. Also, the rows of the mapping table indicate the relationship between the address pointer and the binary code output by the state counter. In short, the write pointer counter (244) and the read address counter (274) each count from 0 to M-1.

[0081] The "gray code" column of the mapping table indicates the gray code corresponding to the binary code. The gray code decoder 246 converts the binary number output by the state counter 242 to a gray code and provides it to the synchronization unit 282. The gray code decoder 276 converts the binary number output by the state counter 272 to a gray code and provides it to the synchronization unit 252.

[0082] The "reverse Gray code" column of the mapping table indicates the reverse Gray code corresponding to the binary code. The mapping table also indicates the correspondence between the reverse Gray code and the Gray code. In the range from Gray code G(0) to G(M-l), the reverse Gray code corresponding to a certain Gray code is the Gray code symmetrical to the certain Gray code about the middle value of the range. In the range from Gray code G(2^(n+1)-M) to G(2^(n+1)-l), the reverse Gray code corresponding to a certain Gray code is the Gray code symmetrical to the certain Gray code about the middle value of the range. The size of the range is the same as the depth M of the FIFO memory. The reverse Gray code decoder 248 converts the binary number output by the state counter 242 into a reverse Gray code and provides the full detection unit 254 with the reverse Gray code.

[0083] Referring back to Figure 2A , in response to data to be written into the asynchronous FIFO memory according to the embodiment of the application, first, it is acquired from the full detection unit 254 whether the FIFO memory is full. If the FIFO is not full, the value of the write pointer counter 244 is provided as a write address to the dual-port memory 210, and the data to be written is also provided to the dual-port memory 210. In response to the data being written into the dual-port 210, the state counter 242 is incremented (incremented according to the state counter counting rule indicated in the table), and the write pointer counter 244 is also incremented (incremented according to the binary code counting rule indicated in the table). The count value of the state counter 242 is provided to the Gray code decoder 246 and the reverse Gray code decoder 248. The synchronization unit 282 synchronizes the value of the Gray code decoder 246 to the empty detection unit 284. Figure 2B Figure 2B In response to data to be written into the asynchronous FIFO memory according to the embodiment of the application, first, it is acquired from the full detection unit 254 whether the FIFO memory is full. If the FIFO is not full, the value of the write pointer counter 244 is provided as a write address to the dual-port memory 210, and the data to be written is also provided to the dual-port memory 210. In response to the data being written into the dual-port 210, the state counter 242 is incremented (incremented according to the state counter counting rule indicated in the table), and the write pointer counter 244 is also incremented (incremented according to the binary code counting rule indicated in the table). The count value of the state counter 242 is provided to the Gray code decoder 246 and the reverse Gray code decoder 248. The synchronization unit 282 synchronizes the value of the Gray code decoder 246 to the empty detection unit 284.

[0084] In response to data to be written into the asynchronous FIFO memory according to the embodiment of the application, first, it is acquired from the full detection unit 254 whether the FIFO memory is full. If the FIFO is not full, the value of the write pointer counter 244 is provided as a write address to the dual-port memory 210, and the data to be written is also provided to the dual-port memory 210. In response to the data being written into the dual-port 210, the state counter 242 is incremented (incremented according to the state counter counting rule indicated in the table), and the write pointer counter 244 is also incremented (incremented according to the binary code counting rule indicated in the table). The count value of the state counter 242 is provided to the Gray code decoder 246 and the reverse Gray code decoder 248. The synchronization unit 282 synchronizes the value of the Gray code decoder 246 to the empty detection unit 284. Figure 2B Figure 2B In response to data to be written into the asynchronous FIFO memory according to the embodiment of the application, first, it is acquired from the full detection unit 254 whether the FIFO memory is full. If the FIFO is not full, the value of the write pointer counter 244 is provided as a write address to the dual-port memory 210, and the data to be written is also provided to the dual-port memory 210. In response to the data being written into the dual-port 210, the state counter 242 is incremented (incremented according to the state counter counting rule indicated in the table), and the write pointer counter 244 is also incremented (incremented according to the binary code counting rule indicated in the table). The count value of the state counter 242 is provided to the Gray code decoder 246 and the reverse Gray code decoder 248. The synchronization unit 282 synchronizes the value of the Gray code decoder 246 to the empty detection unit 284.

[0085] The asynchronous FIFO memory according to the embodiment of the application with a depth of M is analyzed from a mathematical theory as follows.

[0086] Figure 3A 、 3B ​​Fig. 3C shows a diagram of mapping table of decimal number, binary number and its Gray code.

[0087] Figure 3A In the above, the binary number and the Gray code have n+1 bits, n = Log2(M) rounded up. Figure 3A The first column (column title "Decimal") of Fig. 3C lists all decimal numbers that can be expressed by n+1 bits binary number in ascending order from top to bottom.

[0088] Select any one of the decimal numbers X, its binary code is A n A n-1 A n-2 ..A1A0. Figure 3A The decimal number in the first column has a middle position (2 n -1 and 2 n ). According to the middle position, fold in half, the position symmetric to the decimal number X is 2^(n+1)-1-X.

[0089] Thus, we have

[0090] 2 n+1 -1-X=1 n+1 0 n 0 n-1 0 n-2 ..0100B-1-X

[0091] =1 n 1 n-1 1 n-2 ..1110B-X

[0092] =1 n 1 n-1 1 n-2 ..1110B-A n A n-1 A n-2 ..A1A0

[0093] =~(A n A n-1 A n-2 ..A1A0)

[0094] According to the conversion formula of binary and Gray code, for X, assume its Gray code is G n G n-1 G n-2 ..G1G0:

[0095] G n =A n

[0096] G n-1 =A n ⊕An-1

[0097] G n-2 =A n-1 ⊕A n-2 ...

[0099] G0=A1⊕A0

[0100] The number that is symmetrical to X about the middle position: 2 n+1 -1–X, assuming its Gray code is P n P n-1 P n-2 …P1P 0:

[0101] P n =~A n =~G n

[0102] P n-1 =(~A n ⊕~A n-1 ) = A n ⊕A n-1 =G n-1

[0103] P n-2 =(~A n-1 ⊕~A n-2 ) = A n-1 ⊕A n-2 =G n-2 ...

[0105] P0=(~A1⊕~A0)=A1⊕A0=G0

[0106] Thus, it can be seen that, apart from the highest digit being different, these two numbers (X and 2) are identical. n+1 The Gray codes of (-1–X) are all equal starting from bit n-1. Based on this theory, an asynchronous FIFO memory of arbitrary depth is designed in the embodiments according to this application. Assuming the required depth M of the FIFO memory (whose binary encoding requires n bits) is X, then bits from 0 to (X-1) and the same... Figure 3A The range "0 to (X-1)" in the "decimal" column is symmetrical about the middle position (2 n+1 -1–(X-1))~(2 n +1 -1) to map the pointer to the FIFO memory, and... Figure 3A Delete the rest of the "decimal" column. That is, delete... Figure 3A From X to 2 n+1 All codes between -1 and X.

[0107] As an example, when the counter indicates "decimal number", when the counter counts to X-1, the next time the counter is incremented, the counter jumps directly to 2 n+1 -1 - (X-1). Taking the asynchronous FIFO memory with depth 7 as an example, n = Log2(7) is rounded up to 3, in the table, X = 7, n = 3, correspondingly, 7 and 8 and their corresponding rows are deleted in the "decimal" column. The result is shown in Figure 3A Figure 3B

[0108] For such a FIFO memory, the calculation of empty state and the power of 2 FIFO memory is the same, that is, to judge whether the two pointers are the same. But to calculate the full state is more complicated, because the depth of the FIFO is not the power of 2, then only judging the highest bit of the binary code is different and the rest is the same rule does not work.

[0109] If you want to judge the FIFO state by the difference between the pointers, according to the difference between the pointers is equal to the depth of the FIFO, you need to specially consider the intermediate deleted pointer. Taking the above figure as an example, when the read pointer corresponds to the decimal number 0 and the write pointer corresponds to the decimal number 9, the FIFO is full decimal. 9-0-2*(8-7) = 7 = FIFO depth, which can be determined as full state, where 2*(8-7) is the number of intermediate skipped pointers. The full decimal calculated in this way is more complicated, and the calculation delay is also larger, because there is subtraction, and the judgment of the upper and lower half of the decimal number (when the two decimal numbers are in the same half, the number of skipped pointers does not need to be subtracted).

[0110] It can be considered to simplify the judgment of full pointer by using the axial symmetry relationship of Gray code again:

[0111] As shown in Figure 3C , the depth of the FIFO memory is 7. According to the "decimal" column of Figure 3C , the decimal numbers (together with their corresponding rows) are divided into two halves. The decimal numbers in the upper half range from 0 to 6, and the decimal numbers in the lower half range from 9 to 15. Correspondingly, Figure 3C , the numbers in the "Gray code" column are also divided into two halves.

[0112] Exchange the positions of the "Gray code" column in each half with the middle position of the order in the respective half as the axis of symmetry, exchange the positions of the first Gray code and the last Gray code in the respective half, exchange the positions of the second Gray code and the second last Gray code, and so on, and the result is shown in the "reverse Gray code" column of Figure 3C .

[0113] For example, refer to Figure 3C ​​The first Gray code in the upper half of the "Gray Code" column is "0000", and the last Gray code is "0101", and correspondingly, the first reverse Gray code in the "Reverse Gray Code" column is "0101", and the last reverse Gray code is "0000".

[0114] After such conversion, the forward Gray code in the upper half and the reverse Gray code in the lower half will present a one-to-one correspondence, i.e. two pointers with an interval of the FIFO depth, and the forward Gray code and the reverse Gray code in the other half only differ in the highest bit and are the same in other bits. For example, refer to Figure 3C The first Gray code "1101" in the lower half of the "Gray Code" column and the first Gray code "0101" in the upper half of the "Reverse Gray Code" column are in the interval of 7 (the depth of the FIFO memory) in the row of Figure 3C and the two codes only differ in the highest bit and are the same in other bits.

[0115] This feature can be used to determine the full state of the FIFO. For example, the write pointer is converted into a reverse Gray code (denoted as wptr_rev), and the read pointer is still a Gray code (denoted as rptr_sync), and the following formula can realize the determination of the full state Full of the FIFO:

[0116] Full = (wptr_rev[n]!= rptr_sync[n])? (wptr_rev[n-1:0] == rptr_sync[n-1:0]):1'b0;

[0117] Thus, the determination of the full state of the FIFO is much simpler relative to the subtraction of the pointers. This feature can be used to design a parameterized asynchronous FIFO, and the depth is defined as a parameter. Through the parameterized design, an asynchronous FIFO memory of any depth is realized. In the design, only the following points need to be considered:

[0118] (1) When the pointer jumps, the boundary position of the half is the depth M-1 of the FIFO memory;

[0119] (2) A parameterized (the parameter is n+1, where n is the integer part of Log2(M)) reverse Gray code generation unit is provided.

[0120] Figure 4 A block diagram of an asynchronous FIFO memory according to yet another embodiment of the application is shown.

[0121] Refer to Figure 4The depth of the asynchronous FIFO memory according to the embodiment of the present application is M (M is a positive integer). The asynchronous FIFO memory comprises a dual-port memory 410, a write address decoding unit 420 and a read address decoding unit 470. The write address decoding unit 420 is coupled to the write port of the dual-port memory 410 and provides a write pointer for writing data to the write port, the value of the write pointer ranges from 0 to (M-1). The read address decoding unit 470 is coupled to the read port of the dual-port memory 410 and provides a read pointer for reading data from the read port, the value of the read pointer ranges from 0 to (M-1). The write address decoding unit 420 and the read address decoding unit 470 are located in different clock domains respectively.

[0122] Figure 4 The asynchronous FIFO memory shown further comprises a read pointer synchronization unit 452, a write pointer synchronization unit 482, a full detection unit 454 and an empty detection unit 484.

[0123] The read pointer synchronization unit 452 provides the read pointer obtained from the read address decoding unit 470 to the full detection unit 454. The full detection unit compares the read pointer provided by the read pointer synchronization unit 452 with the write pointer obtained from the write address decoding unit 420 and generates a full status flag indicating whether the FIFO memory is full.

[0124] The write pointer synchronization unit 482 provides the write pointer obtained from the write address decoding unit 420 to the empty detection unit 484. The empty detection unit 484 compares the write pointer provided by the write pointer synchronization unit 482 with the read pointer obtained from the read address decoding unit 470 and generates an empty status flag indicating whether the FIFO memory is empty.

[0125] The write address decoding unit 420 comprises a state counter 422, a write pointer counter 424 and a Gray code decoder 426. The state counter 422 is coupled to the write port of the dual-port memory 410 and provides a state pointer for writing data to the write port, the value of the state pointer ranges from 0 to (M-1). Figure 2A The write address decoding unit 420 of the asynchronous FIFO memory embodiment shown is different in that it does not comprise a reverse Gray code decoder.

[0126] The state counter 422 is incremented in response to each time data is written to the dual-port memory 410. The state counter 422 is a binary code counter and its bit width is n+1. The counting value of the state counter 422 ranges over two continuous parts, from binary 0 to M-1 and from binary 2^(n+1)-M to 2^(n+1)-1. Within each range part, the state counter 422 counts continuously in binary code with a step of 1. When the state counter 422 counts to the end of the first range part, M-1, the value of the next count is 2^(n+1)-M; when the state counter 422 counts to the end of the second range part, 2^(n+1)-1, the value of the next count is 0.

[0127] The state counter 422 of the write address decode unit 420 is also coupled to the write pointer counter 424 and the Gray code decoder 426, respectively. The bit width of the Gray code decoder 426 is n+1. The binary count value of the state counter 422 is provided to the Gray code decoder 246 to generate a corresponding Gray code according to the binary count value. In response to each count, the state counter 422 provides a signal to the write pointer counter 424 to cause the write pointer counter 424 to count accordingly. The write pointer counter 424 is a binary code counter with a bit width of n and a count range from binary 0 to M-1. When the write pointer counter 244 counts to the end of the count range portion M-1, the value of the next count is 0. Optionally, in response to each write of data to the dual-port memory 410, the write address decode unit 440 provides a count signal to the write pointer counter 424.

[0128] The count value of the write pointer counter 424 is provided to the dual-port memory 210 as the write pointer provided by the write address decoder 420 to the dual-port memory 410 to indicate the address to write data to the dual-port memory 410.

[0129] The Gray code output by the Gray code decoder 426 is provided to the full detection unit 454 and the write pointer synchronization unit 482.

[0130] The full detection unit 454 receives the output of the Gray code decoder 426 (denoted as wptr with a bit width of n+1) and also receives the output of the read pointer synchronization unit 452 (denoted as rptr rev sync with a bit width of n+1). The full detection unit 454 generates a full status flag Full = (wptr[n]!= rptr rev sync[n])? (wptr[n-1:0] == rptr rev sync[n-1:0]): 1'0. Data is written to the dual-port memory 410 only when the full status flag Full indicates that the FIFO memory is not full.

[0131] The read address decode unit 470 includes a state counter 472, a read pointer counter 474, an inverse Gray code decoder 476 and a Gray code decoder 478.

[0132] In response to each read of data from the dual-port memory 410, the state counter 472 is incremented. The state counter 472 is a binary code counter with a bit width of n+1. Optionally, the state counter 472 is the same as the state counter 422.

[0133] The state counter 472 of the read address decoding unit 470 is also coupled to the read pointer counter 474 and the Gray code decoder 476 respectively. The binary count value of the state counter 472 is provided to the Gray code decoder 478 to generate a corresponding Gray code according to the binary count value. The bit width of the Gray code decoder 478 is n+1. The Gray code decoder 478 also provides the generated Gray code to the reverse Gray code converter 476. The reverse Gray code converter 476 converts the Gray code input thereto into a reverse Gray code, and provides the generated reverse Gray code (denoted as rptr_rev) to the read pointer synchronization unit 452.

[0134] In response to each count, the state counter 472 provides a signal to the read pointer counter 474 to count accordingly. The read pointer counter 474 is a binary counter, whose bit width is n, and the count range is from binary 0 to M-1.

[0135] The count value of the read pointer counter 474 is provided to the dual-port memory 210 as the read pointer provided by the read address decoding unit 470 to the dual-port memory 410, to indicate the address for reading data out from the dual-port memory 410.

[0136] The empty detection unit 484 receives the output of the Gray code decoder 478 (denoted as rptr, whose bit width is n+1), and also receives the output of the write pointer synchronization unit 482 (denoted as wptr_sync, whose bit width is n+1). The empty detection unit 484 generates an empty status flag Empty = (wptr_sync == rptr)? 1’b1 : 1’b0. Data is read out from the dual-port memory 410 only when the empty status flag Empty indicates that the FIFO memory is not empty.

[0137] Figure 5 A block diagram of an asynchronous FIFO memory according to yet another embodiment of the present application is shown.

[0138] Referring to Figure 5 The depth of the asynchronous FIFO memory according to the embodiment of the present application is M (M is a positive integer). The asynchronous FIFO memory comprises a dual-port memory 510, a write address decoding unit 520 and a read address decoding unit 570. The write address decoding unit 520 provides a write pointer to the dual-port memory 510 for writing data, and the value range of the write pointer is 0~(M-1). The read address decoding unit 570 provides a read pointer to the read port of the dual-port memory 510 for reading data, and the value range of the read pointer is 0~(M-1). The write address decoding unit 520 and the read address decoding unit 570 are in different clock domains respectively.

[0139] Figure 5The asynchronous FIFO memory also includes a read pointer synchronization unit 552, a write pointer synchronization unit 582, a full detection unit 554, and an empty detection unit 584.

[0140] The read pointer synchronization unit 552 provides the read pointer obtained from the read address decode unit 570 to the reverse Gray code converter 560, the output of which is provided to the full detection unit 554. The full detection unit compares the read pointer provided by the reverse Gray code converter 560 with the write pointer obtained from the write address decode unit 520 and generates a full status flag indicating whether the FIFO memory is "full."

[0141] The write pointer synchronization unit 582 provides the write pointer obtained from the write address decode unit 520 to the empty detection unit 584. The empty detection unit 584 compares the write pointer provided by the write pointer synchronization unit 582 with the read pointer obtained from the read address decode unit 570 and generates an empty status flag indicating whether the FIFO memory is "empty."

[0142] The write address decode unit 520 includes a state counter 522, a write pointer counter 524, and a Gray code decoder 526.

[0143] The state counter 522 is incremented in response to each write to the dual port memory 510. The state counter 422 is a binary counter with a bit width of n+1. Alternatively, the state counter 522 can be a Gray code counter. Figure 4 The state counter 422 is consistent with the state counter 522, the write pointer counter 524 is consistent with the write pointer counter 424, and the Gray code decoder 526 is consistent with the Gray code decoder 426. Figure 4 The write pointer counter 424 is consistent with the write pointer counter 524, and the Gray code decoder 426 is consistent with the Gray code decoder 526. Figure 4 The Gray code decoder 426 is consistent with the Gray code decoder 526.

[0144] The Gray code output by the Gray code decoder 526 is provided to the full detection unit 554 and the write pointer synchronization unit 582.

[0145] The write pointer synchronization unit 582 obtains the Gray code of the read pointer from the read address decode unit 570 and provides it to the reverse Gray code converter 560 (denoted as rptr sync). The reverse Gray code converter 560 converts the received Gray code of the read pointer (rptr sync) to a reverse Gray code (denoted as rptr rev sync) and provides it to the full detection unit 554.

[0146] The full detection unit 554 receives the output of the Gray code decoder 526 (denoted as wptr, bit width n+1) and also receives the output of the reverse Gray code converter 560 (denoted as rptr_rev_sync, bit width n+1). The full detection unit 554 generates a full status flag Full = (wptr[n]!= rptr_rev_sync[n])?(wptr[n-1:0] == rptr_rev_sync[n-1:0]):1'b0.

[0147] The read address decoding unit 570 includes a state counter 572, a read pointer counter 574, and a Gray code decoder 576.

[0148] The state counter 572 is consistent with the state counter 472 of the write address decoding unit 520. Figure 4 The read pointer counter 574 is consistent with the read pointer counter 474 of the read address decoding unit 570. Figure 4 The read pointer counter 574 is consistent with the read pointer counter 474 of the read address decoding unit 570.

[0149] The state counter 572 of the read address decoding unit 570 is also coupled to the read pointer counter 574 and the Gray code decoder 576, respectively. The binary count value of the state counter 572 is provided to the Gray code decoder 576 to generate a corresponding Gray code according to the binary count value. The bit width of the Gray code decoder 576 is n+1. The Gray code converter 576 provides the generated Gray code to the read pointer synchronization unit 552.

[0150] The empty detection unit 584 receives the output of the Gray code decoder 576 (denoted as rptr, bit width n+1) and also receives the output of the write pointer synchronization unit 582 (denoted as wptr_sync, bit width n+1). The empty detection unit 584 generates an empty status flag Empty = (wptr_sync == rptr)?1'b1:1'b0.

[0151] Figure 6 A block diagram of an asynchronous FIFO memory according to yet another embodiment of the present application is shown.

[0152] Referring to Figure 6 The depth of the asynchronous FIFO memory according to the embodiment of the present application is M (M is a positive integer). The asynchronous FIFO memory includes a dual-port memory 610, a write address decoding unit 620, and a read address decoding unit 670. The write address decoding unit 620 provides a write pointer for writing data to the dual-port memory 610, and the value range of the write pointer is 0-(M-1). The read address decoding unit 670 provides a read pointer for reading data from the read port of the dual-port memory 610, and the value range of the read pointer is 0-(M-1). The write address decoding unit 620 and the read address decoding unit 670 are located in different clock domains, respectively.

[0153] The full detection unit 554 receives the output of the Gray code decoder 526 (denoted as wptr, bit width n+1) and also receives the output of the reverse Gray code converter 560 (denoted as rptr_rev_sync, bit width n+1). The full detection unit 554 generates a full status flag Full = (wptr[n]!= rptr_rev_sync[n])?(wptr[n-1:0] == rptr_rev_sync[n-1:0]):1'b0.

[0147] The read address decoding unit 570 includes a state counter 572, a read pointer counter 574, and a Gray code decoder 576.

[0148] The state counter 572 is consistent with the state counter 472 of the write address decoding unit 520. Figure 4 The read pointer counter 574 is consistent with the read pointer counter 474 of the read address decoding unit 570. Figure 4 The read pointer counter 574 is consistent with the read pointer counter 474 of the read address decoding unit 570.

[0149] The state counter 572 of the read address decoding unit 570 is also coupled to the read pointer counter 574 and the Gray code decoder 576, respectively. The binary count value of the state counter 572 is provided to the Gray code decoder 576 to generate a corresponding Gray code according to the binary count value. The bit width of the Gray code decoder 576 is n+1. The Gray code converter 576 provides the generated Gray code to the read pointer synchronization unit 552.

[0150] The empty detection unit 584 receives the output of the Gray code decoder 576 (denoted as rptr, bit width n+1) and also receives the output of the write pointer synchronization unit 582 (denoted as wptr_sync, bit width n+1). The empty detection unit 584 generates an empty status flag Empty = (wptr_sync == rptr)?1'b1:1'b0.

[0151] Figure 6 A block diagram of an asynchronous FIFO memory according to yet another embodiment of the present application is shown.

[0152] Referring to Figure 6 The depth of the asynchronous FIFO memory according to the embodiment of the present application is M (M is a positive integer). The asynchronous FIFO memory includes a dual-port memory 610, a write address decoding unit 620, and a read address decoding unit 670. The write address decoding unit 620 provides a write pointer for writing data to the dual-port memory 610, and the value range of the write pointer is 0-(M-1). The read address decoding unit 670 provides a read pointer for reading data from the read port of the dual-port memory 610, and the value range of the read pointer is 0-(M-1). The write address decoding unit 620 and the read address decoding unit 670 are located in different clock domains, respectively.

[0153] Figure 6 The asynchronous FIFO memory also includes a read pointer synchronization unit 652, a write pointer synchronization unit 682, a full detection unit 654, and an empty detection unit 684.

[0154] The read pointer synchronization unit 652 provides the read pointer obtained from the read address decoding unit 670 to the full detection unit 654. The full detection unit 654 compares the read pointer provided by the read pointer synchronization unit 652 with the write pointer obtained from the write address decoding unit 620 and generates a full status flag indicating whether the FIFO memory is "full."

[0155] The write pointer synchronization unit 682 provides the write pointer obtained from the write address decoding unit 620 to the empty detection unit 684. The empty detection unit 684 compares the write pointer provided by the write pointer synchronization unit 682 with the read pointer obtained from the read address decoding unit 670 and generates an empty status flag indicating whether the FIFO memory is "empty."

[0156] The write address decoding unit 620 includes a write pointer counter 624, a Gray code generation unit 626, and a reverse Gray code generation unit 628.

[0157] In response to each write of data to the dual-port memory 610, the write pointer counter is counted, and its count value is incremented. The write pointer counter 624 is a binary counter with a bit width of n and a count range from binary 0 to M-1. When the write pointer counter 624 counts to the end of the count range portion M-1, the value of the next count is 0. The write pointer counter 624 also includes a wrap-around flag D. The wrap-around flag D is, for example, a 1-bit register indicating the range or half-region to which the count value of the write pointer counter 624 corresponds (see also Figure 2B or Figure 3C ). For example, the value of the wrap-around flag D of the write pointer counter 624 is 0 after initialization, and the value of the wrap-around flag is flipped each time the write pointer counter 624 jumps from the end of the count range portion M-1 to the beginning of the count range portion 0.

[0158] The count value of the write pointer counter 624 and the value of the wrap-around flag D are provided to the Gray code generation unit 626 and the reverse Gray code generation unit 628. The count value of the write pointer counter 624 (as "address pointer") and the value of the wrap-around flag D (as indication of the range or half-region) together uniquely identify, for example, Figure 2B or Figure 3C a row, so that there is a corresponding Gray code and reverse Gray code for the identified row. The Gray code generation unit 626 converts the received count value of the write pointer counter 624 and the value of the wrap-around flag D to a Gray code. The reverse Gray code generation unit 628 converts the received count value of the write pointer counter 624 and the value of the wrap-around flag D to a reverse Gray code.

[0159] The count value of the write pointer counter 624 is provided to the dual-port memory 610 as the write pointer provided by the write address decoding unit 620 to the dual-port memory 610.

[0160] The Gray code generated by the Gray code generation unit 626 is provided to the write pointer synchronization unit 682.

[0161] The reverse Gray code generated by the reverse Gray code generation unit 628 is provided to the full detection unit 654.

[0162] The write pointer synchronization unit 682 obtains the Gray code of the read pointer from the read address decoding unit 670 and provides it to the full detection unit 654 (denoted as rptr_sync).

[0163] The full detection unit 654 receives the output of the reverse Gray code generation unit 628 (denoted as wptr_rev, bit width n+1) and also receives the output of the synchronization unit 652 (denoted as rptr_sync, bit width n+1). The full detection unit 654 generates the full status flag Full = (wptr_rev[n]!= rptr_sync[n])? (wptr_rev[n-1:0] == rptr_sync[n-1:0]): 1’b0.

[0164] The read address decoding unit 670 includes a read pointer counter 674 and a Gray code generation unit 676.

[0165] Optionally, the read pointer counter 674 is identical to the write pointer counter 624. The Gray code generation unit 676 is identical to the Gray code generation unit 626.

[0166] The binary count value of the read pointer counter 674 and the cycle flag D are provided to the Gray code generation unit 676 to generate the corresponding Gray code. The Gray code generation unit 676 provides the generated Gray code to the read pointer synchronization unit 652.

[0167] The empty detection unit 684 receives the output of the Gray code generation unit 676 (denoted as rptr, bit width n+1) and also receives the output of the write pointer synchronization unit 682 (denoted as wptr_sync, bit width n+1). The empty detection unit 684 generates the empty status flag Empty = (wptr_sync == rptr)? 1’b1: 1’b0.

[0168] While the preferred embodiments of the application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the foregoing description without departing from the spirit and scope of the application. Accordingly, many modifications can be made by those skilled in the art without departing from the scope of the application. It is therefore intended that such modifications and variations be included within the scope of the application.

Claims

1. An asynchronous FIFO memory, comprising a dual-port memory, a write address decoder, a read address decoder, a full detection unit, a read pointer synchronization unit, an empty detection unit, and a write pointer synchronization unit; The write address decoder, full detection unit, and read pointer synchronization unit are located in the first clock domain; the read address decoder, empty check unit, and write pointer synchronization unit are located in the second clock domain. The write address decoder is coupled to the write port of the dual-port memory and provides a write pointer to the write port of the dual-port memory; The read address decoder is coupled to the read port of the dual-port memory and provides a read pointer to the read port of the dual-port memory; Its features are, The write address decoder includes a first state counter, a write pointer counter, a first Gray code decoder, and an inverse Gray code decoder; The first state counter continuously counts in binary from 0 to M-1 and then from 2^(n+1)-M to 2^(n+1)-1 in a step of 1, where M is the depth of the asynchronous FIFO memory and n is the result of rounding up Log2(M). The first state counter is coupled to the write pointer counter, the first Gray code decoder, and the inverse Gray code decoder; The write pointer counter continuously counts in binary from 0 to M-1 in a step of 1. The count value of the write pointer counter is provided by the write address decoder to the write port of the dual-port memory as the write pointer. The output of the first Gray code decoder is coupled to the write pointer synchronization unit; The output of the reverse Gray code decoder is coupled to the full detection unit.

2. The asynchronous FIFO memory according to claim 1, wherein The read address decoder includes a second state counter, a read pointer counter, and a second Gray code decoder; The second state counter continuously cycles through the range of binary from 0 to M-1 and then from 2^(n+1)-M to 2^(n+1)-1 with a step size of 1, where M is the depth of the asynchronous FIFO memory; The second state counter is coupled to the read pointer counter and the second Gray code decoder; The read pointer counter continuously counts in binary from 0 to M-1 in steps of 1, and the count value of the read pointer counter is provided by the read address decoder to the read port of the dual-port memory as the read pointer. The second Gray code decoder converts the binary count value provided by the second state counter into Gray code; The output of the second Gray code decoder is coupled to the read pointer synchronization unit; The output of the second Gray code decoder is also coupled to the empty detection unit.

3. The asynchronous FIFO memory according to claim 2, wherein If the count value i output by the first state counter is in the range of 0 to (M-1), the reverse Gray code decoder converts the count value i output by the first state counter into G(M-1-i), where G(i) represents the Gray code of the binary value i. If the count value 2^(n+1)-M+i output by the first state counter is in the range of 2^(n+1)-M to 2^(n+1)-1, the reverse Gray code decoder converts the count value 2^(n+1)-M+i output by the first state counter to G(2^(n+1)-1-i).

4. The asynchronous FIFO memory according to claim 2 or 3, wherein the output of the read pointer synchronization unit is coupled to the output of the inverse Gray code decoder to the full detection unit; The output of the write pointer synchronization unit is coupled to the output of the second Gray code decoder and then to the empty detection unit.

5. The asynchronous FIFO memory according to claim 4, wherein The full detection unit outputs a full status flag if the output of the read pointer synchronization unit is opposite to the highest bit of the output of the inverse Gray code decoder while the other bits are the same; otherwise, it outputs a non-full status flag.

6. The asynchronous FIFO memory according to claim 5, wherein The empty detection unit outputs an empty state flag if the output of the write pointer synchronization unit is the same as the output of the second Gray code decoder; otherwise, it outputs a non-empty state flag.

7. An asynchronous FIFO memory, comprising a dual-port memory, a write address decoder, a read address decoder, a full detection unit, a read pointer synchronization unit, an empty detection unit, and a write pointer synchronization unit; The write address decoder, full detection unit, and read pointer synchronization unit are located in the first clock domain; the read address decoder, empty check unit, and write pointer synchronization unit are located in the second clock domain. The write address decoder is coupled to the write port of the dual-port memory and provides a write pointer to the write port of the dual-port memory; The read address decoder is coupled to the read port of the dual-port memory and provides a read pointer to the read port of the dual-port memory; Its features are, The write address decoder includes a first state counter, a write pointer counter, and a first Gray code decoder; The read address decoder includes a second state counter, a read pointer counter, a second Gray code decoder, and an inverse Gray code conversion unit; The first state counter and the second state counter are each continuously cyclically counted in binary from 0 to M-1 and then from 2^(n+1)-M to 2^(n+1)-1 with a step size of 1, where M is the depth of the asynchronous FIFO memory and n is the result of rounding up Log2(M). The second state counter is coupled to the read pointer counter and the second Gray code decoder; The read pointer counter continuously counts in binary from 0 to M-1 in steps of 1, and the count value of the read pointer counter is provided by the read address decoder to the read port of the dual-port memory as the read pointer. The second Gray code decoder converts the binary count value provided by the second state counter into Gray code; The output of the reverse Gray code conversion unit is coupled to the read pointer synchronization unit; The output of the second Gray code decoder is coupled to the empty detection unit; The inverse Gray code conversion unit converts the output of the second Gray code decoder into inverse Gray code.

8. The asynchronous FIFO memory according to claim 7, wherein The first state counter is coupled to the write pointer counter and the first Gray code decoder; The write pointer counter continuously counts in binary from 0 to M-1 in a step of 1. The count value of the write pointer counter is provided by the write address decoder to the write port of the dual-port memory as the write pointer. The first Gray code decoder converts the binary count value provided by the first state counter into Gray code; The output of the first Gray code decoder is coupled to the write pointer synchronization unit; The output of the first Gray code decoder is also coupled to the full detection unit.

9. An asynchronous FIFO memory, comprising a dual-port memory, a write address decoder, a read address decoder, a full detection unit, a read pointer synchronization unit, an empty detection unit, and a write pointer synchronization unit; The write address decoder, full detection unit, and read pointer synchronization unit are located in the first clock domain; the read address decoder, empty check unit, and write pointer synchronization unit are located in the second clock domain. The write address decoder is coupled to the write port of the dual-port memory and provides a write pointer to the write port of the dual-port memory; The read address decoder is coupled to the read port of the dual-port memory and provides a read pointer to the read port of the dual-port memory; Its features are, The write address decoder includes a first state counter, a write pointer counter, and a first Gray code decoder; The read address decoder includes a second state counter, a read pointer counter, and a second Gray code decoder; The first state counter and the second state counter are each continuously cyclically counted in binary from 0 to M-1 and then from 2^(n+1)-M to 2^(n+1)-1 with a step size of 1, where M is the depth of the asynchronous FIFO memory and n is the result of rounding up Log2(M). The first state counter is coupled to the write pointer counter and the first Gray code decoder; The write pointer counter continuously counts in binary from 0 to M-1 in a step of 1. The count value of the write pointer counter is provided by the write address decoder to the write port of the dual-port memory as the write pointer. The first Gray code decoder converts the binary count value provided by the first state counter into Gray code; The output of the first Gray code decoder is coupled to the write pointer synchronization unit; The output of the first Gray code decoder is coupled to the full detection unit; The asynchronous FIFO memory further includes an inverse Gray code conversion unit located in the first clock domain. The input of the inverse Gray code conversion unit is coupled to the output of the read pointer synchronization unit, and the output of the inverse Gray code conversion unit is coupled to the input of the full detection unit. The inverse Gray code decoder converts the Gray code of the read pointer output by the read pointer synchronization unit into inverse Gray code.

10. An asynchronous FIFO memory, comprising a dual-port memory, a write address decoder, a read address decoder, a full detection unit, a read pointer synchronization unit, an empty detection unit, and a write pointer synchronization unit; The write address decoder, full detection unit, and read pointer synchronization unit are located in the first clock domain; the read address decoder, empty check unit, and write pointer synchronization unit are located in the second clock domain. The write address decoder is coupled to the write port of the dual-port memory. And provide a write pointer to the write port of the dual-port memory; The read address decoder is coupled to the read port of the dual-port memory. And provide a read pointer to the read port of the dual-port memory; Its features are, The write address decoder includes a write pointer counter, a first Gray code generation unit, and a reverse Gray code generation unit; The read address decoder includes a read pointer counter and a second Gray code generation unit; The read pointer counter and the write pointer counter each continuously cycle and count in binary from 0 to M-1 with a step size of 1, where M is the depth of the asynchronous FIFO memory; The read pointer counter and the write pointer counter each also include a register as a loop marker, which flips whenever the counter value wraps around from M-1 to 0; The write pointer counter is coupled to the first Gray code generation unit and the reverse Gray code generation unit; The count value of the write pointer counter is provided by the write address decoder to the write port of the dual-port memory as the write pointer; The first Gray code generation unit converts the value of the write pointer counter and the loop marker into Gray code; The reverse Gray code generation unit converts the value of the write pointer counter and the loop marker into reverse Gray code; The output of the first Gray code generation unit is coupled to the write pointer synchronization unit; The output of the reverse Gray code decoder is coupled to the full detection unit.

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