Semiconductor devices

Abstract

A semiconductor device is provided. The semiconductor device includes a first storage component, the first storage component includes a first storage area and a first logic area electrically connected to the first storage area, the first logic area includes a cache memory and an interface port. The first storage component performs data transmission and reception operations with a storage component adjacent to the first storage component via the interface port and the cache memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority benefit of Korean Patent Application No. 10-2018-0153279 filed in the Korean Intellectual Property Office on December 3, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices having improved processing speed and accuracy. Background Art

[0004] Artificial intelligence (AI) systems are computer systems that can perform tasks that normally require human intelligence, unlike rule-based intelligent systems. AI systems can understand user preferences more precisely. Machine learning is a data analysis method that automates the construction of analytical models. Machine learning is a branch of AI based on the idea that systems can learn from data, recognize patterns, and make decisions with minimal human intervention. As a result, rule-based intelligent systems are gradually being replaced by AI systems based on machine learning.

[0005] Technical areas such as language understanding, visual understanding, inference / prediction, knowledge representation, and motion control can take advantage of machine learning-based AI systems.

[0006] Machine learning algorithms require operations that can process large amounts of data. The more data that can be processed in the same operation, the higher the accuracy of the results calculated by the machine learning algorithm.

[0007] Artificial neural networks using deep learning are trained using large amounts of data and perform operations in parallel through multiple operators to increase the speed of operation. Summary of the invention

[0008] At least one exemplary embodiment of the inventive concept provides a semiconductor device including a memory and a processor having improved processing speed and accuracy by performing data transmission and reception between the memories.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device is provided, including a first storage component, the first storage component including a first storage area and a first logic area electrically connected to the first storage area. The first logic area includes a cache memory and an interface port for performing data transmission and reception operations. The first storage component uses the cache memory to perform the data transmission and reception operations with a storage component adjacent to the first storage component via the interface port.

[0010] According to an exemplary embodiment of the inventive concept, there is provided a semiconductor device, comprising: a plurality of first storage components, each of the plurality of first storage components including a cache memory and an interface port; and a first processing unit, the first processing unit being electrically connected to the plurality of first storage components and performing an operation based on data stored in the plurality of first storage components. The plurality of first storage components perform data transmission and reception operations between the plurality of first storage components using the cache memory and the interface port.

[0011] According to an exemplary embodiment of the present invention, a semiconductor device is provided, including: a first processing unit, a second processing unit, a plurality of first storage components, a plurality of second storage components, and a scheduler. The plurality of first storage components are electrically connected to the first processing unit, and the plurality of first storage components each include a first storage area and a first cache area. The first storage area and the first cache area share a logical address. The plurality of second storage components are electrically connected to the second processing unit, and the plurality of second storage components each include a second storage area and a second cache area. The second storage area and the second cache area share the logical address. The scheduler schedules the sending and receiving paths of the target data stored in the first storage area or the second storage area between the first storage component and the second storage component. The scheduler schedules the sending and receiving paths based on the path information stored in the first cache area or the second cache area.

[0012] According to an exemplary embodiment of the present invention, a semiconductor device is provided, including a first processor and a compiler. The first processor is electrically connected to a first storage component including at least one memory, and performs an operation on a training data set. The compiler generates a scheduling code for a path of data to be moved during the operation of the training data. The scheduling code includes information about a first path for data to move between the first processor and the first storage component and a second path for data to move between memories included in the first storage component. The first processor performs the operation on the training data set based on the scheduling code. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0014] Figure 1 is a schematic block diagram for explaining a configuration of a storage component according to an exemplary embodiment of the inventive concept;

[0015] Figure 2is a block diagram for explaining a configuration of two storage components connected via an interface port according to an exemplary embodiment of the inventive concept;

[0016] Figure 3 is a cross-sectional view for explaining a storage unit of a cache memory and an interface port disposed in a logic area according to an exemplary embodiment of the inventive concept;

[0017] Figure 4 is a block diagram for explaining a configuration of three storage components connected via an interface port according to an exemplary embodiment of the inventive concept;

[0018] Figure 5 is a block diagram for explaining a configuration of a processing unit and two storage components connected to the processing unit according to an exemplary embodiment of the inventive concept;

[0019] Figure 6 is a cross-sectional view of a processing unit and a storage component, for illustrating a connection between the processing unit and two storage components according to an exemplary embodiment of the inventive concept;

[0020] Figure 7 and Figure 8 is a block diagram for explaining communication between a storage component and a server implemented via an interface connected to the storage component according to an exemplary embodiment of the inventive concept;

[0021] Fig. 9 is a block diagram for explaining a semiconductor device including a plurality of processing units according to an exemplary embodiment of the inventive concept;

[0022] Fig.10 is a block diagram for explaining communication between two processing units according to an exemplary embodiment of the inventive concept;

[0023] Fig.11A is a diagram for explaining a data set trained according to an exemplary embodiment of the inventive concept;

[0024] Fig. 11B It is used to describe the processing unit processing Fig.11A a flowchart of the process of obtaining the data included in the dataset;

[0025] Fig. 11C is a diagram for explaining in detail a process in which a plurality of processing units share and process calculated data;

[0026] Fig.12 is a block diagram for explaining the configuration of data stored in a logic area;

[0027] Fig.13is a mapping table for describing the mapping between the physical address and the logical address of each of the storage area and the logical area;

[0028] Fig.14A is a diagram for explaining storage component ID information stored in a cache control area as an example;

[0029] Fig. 14B is a diagram for explaining state information stored in a cache control area as an example;

[0030] Fig. 14C is a diagram for explaining instructions stored in a cache control area as an example;

[0031] Figures 15 to 18 is a block diagram for explaining a semiconductor device including a scheduler according to an exemplary embodiment of the inventive concept;

[0032] Figures 19 to 21 is a diagram for explaining a process of transmitting target data stored in a source storage component to a destination storage component based on scheduling of a scheduler according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0033] Figure 1 is a schematic block diagram for explaining a configuration of a storage unit (eg, a memory device) according to an exemplary embodiment of the inventive concept.

[0034] Reference Figure 1 , a semiconductor device 1 according to an embodiment of the inventive concept includes a memory unit 100 including a memory area 110 and a logic area 130. In an exemplary embodiment, the memory area 110 is implemented by a nonvolatile memory.

[0035] User data requested by a user, data processed by a processing unit, or data to be processed may be stored in the storage area 110 .

[0036] The logic area 130 may include a storage buffer (Buffer) 131, a port physical layer (PHY) 132, a cache memory (Cache) 133, an interface port (Port) 134, and an interface controller 135 (e.g., a control circuit). In one embodiment, the PHY 132 is a circuit required to implement a physical layer function. The PHY 132 may connect a link layer device to a physical medium such as an optical fiber or a copper wire. The interface port 134 may be used as an interface between the semiconductor device 1 and a device outside the semiconductor device 1.

[0037] The storage buffer 131 may read and buffer the data stored in the storage area 110, and transmit the data to the cache memory 133 or the PHY 132. In addition, the storage buffer 131 may receive data from the processing unit ( Figure 5 10) Receive commands, addresses, data, etc.

[0038] The PHY 132 may output the data stored in the storage buffer 131 or the cache memory 133 to the processing unit ( Figure 5 10 in the figure). That is, the processing unit and the storage component 100 can be connected to each other via the PHY 132. Figure 5 Data transmission and reception between the storage section 100 and a processing unit connected to the storage section 100 is described.

[0039] The cache memory 133 may temporarily store data stored in the storage area 110 or data to be stored in the storage area 110 under the control of the interface controller 135. According to one embodiment, data stored in the storage area 110 for data transfer to the adjacent storage unit 100 is stored in the storage buffer 131, and the cache memory 133 receives and stores the data from the storage buffer 131. According to one embodiment, the cache memory 133 temporarily stores data received from the adjacent storage unit 100.

[0040] The interface port 134 may transmit and receive data to and from an adjacent storage component adjacent to the storage component 100. According to one embodiment, the interface port 134 transmits data stored in the cache memory 133 to the adjacent storage component under the control of the interface controller 135. According to one embodiment, the interface port 134 transmits data received from the adjacent storage component to the cache memory 133 under the control of the interface controller 135.

[0041] According to one embodiment, the interface port 134 uses a serial interface to perform data transmission and reception operations with adjacent storage components. For example, the interface port 134 can apply its own standard serial interface, or can adopt at least one of the following serial interface rules: PCIe (Peripheral Component Interconnect Express), NVMe (Non-Volatile Memory Express), UFS (Universal Flash), USB (Universal Serial Bus), SCSI (Small Computer System Interface), SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), SD (Secure Digital) card, and eMMC (Embedded Multimedia) card, which are all standard serial interface rules.

[0042] The interface controller 135 may control data transmission and reception operations with the adjacent storage components. For example, the interface controller 135 may control the storage area 110, the storage buffer 131, the cache memory 133, and the interface port 134 to receive data from the adjacent storage components and store the data in the cache memory 133 or the storage area 110 of the storage component 100. In an exemplary embodiment, the interface controller 135 performs control so that after the data received from the adjacent storage component via the interface port 134 is stored in the cache memory 133, the data is stored in a specific area of ​​the storage area 110 via the storage buffer 131.

[0043] According to an exemplary embodiment, the interface controller 135 controls the interface port 134 and the cache memory 133 to send the received data to another adjacent storage component after receiving the data from the adjacent storage component. Specifically, after the data received via the interface port 134 is stored in the cache memory 133, the interface controller 135 can control the cache memory 133 and the interface port 134 to send the data stored in the cache memory 133 to another adjacent storage component. For example, the interface controller of the first storage component can receive data from the second storage component, temporarily store the received data in the cache memory of the first storage component, and then send the data stored in the cache memory of the first storage component to the third storage component, which can bypass the storage of data in the storage area of ​​the first storage component. In an exemplary embodiment, the logic area 130 also includes an interface port for communicating with another adjacent storage component. For example, the interface port 134 may include a first interface port for communicating with the second storage component and a second interface port for communicating with the third storage component, or the interface port 134 may be a single port capable of communicating with multiple external storage components. According to this embodiment, the interface port 134 can be used to perform communication with adjacent storage components that are different from each other. That is, data transmission and reception can be performed using one interface port 134 with adjacent storage components different from each other.

[0044] According to an exemplary embodiment, the storage area 110, the storage buffer 131, the cache memory 133 and the interface port 134 may be controlled to transmit the data stored in the storage area 110 to the adjacent storage component. Specifically, the data stored at a specific address in the storage area 110 is read and stored in the storage buffer 131, the data is cached in the cache memory 133, and then the data stored in the cache memory 133 is transmitted to the adjacent storage component via the interface port 134.

[0045] For convenience of explanation, the interface controller 135 is illustrated as being located in the logic area 130 of the memory unit 100 , but is not limited thereto, and the interface controller 135 may be provided in an external area of ​​the memory unit 100 .

[0046] Figure 2 is a block diagram for explaining a configuration of two storage components connected via an interface port according to an exemplary embodiment of the inventive concept.

[0047] Reference Figure 2 The semiconductor device 1 according to the embodiment of the present invention includes a first storage unit 100 and a second storage unit 200. The first storage unit 100 includes a first storage area 110 and a first logic area 130, and the second storage unit 200 includes a second storage area 210 and a second logic area 230. The first storage unit 100 is connected to Figure 1 The second storage area 210 and the second logic area 230 of the second storage unit 200 can be configured in the same manner as the storage unit 100 of the first storage unit 100. In addition, the configuration of the second storage area 210 and the second logic area 230 of the second storage unit 200 can perform the same operation as the configuration of the first storage area 110 and the first logic area 130 of the first storage unit 100. The second logic area 230 includes a second storage buffer (Buffer) 231, a second PHY 232, a second cache memory (Cache) 233, a second interface port (Port) 234 and a second interface controller 235.

[0048] The semiconductor device 1 according to the embodiment of the present invention can perform data transmission and reception operations between adjacent storage components. The first storage component 100 and the second storage component 200 are arranged adjacent to each other, and data transmission and reception are performed via the first interface port 134 and the second interface port 234. The first interface controller 135 controls the input operation of receiving data at the first interface port 134 or the output operation of sending data from the first interface port 134, and the second interface controller 235 controls the input operation of receiving data at the second interface port 234 or the output operation of sending data from the second interface port 234.

[0049] Figure 3 1 is a cross-sectional view of a memory unit for explaining a cache memory and an interface port provided in a logic area according to an exemplary embodiment of the inventive concept. For ease of explanation, a stacked memory unit is shown as an example to which an embodiment of the inventive concept can be applied, but the inventive concept is not limited thereto, and the embodiment of the inventive concept can be applied to a memory unit having the same Figure 3 The illustrated arrangements are different from those of single-layer type memories or stacked type memories.

[0050] Reference Figure 3, a semiconductor device 1 according to an exemplary embodiment of the inventive concept includes a substrate 5 , an interposer 3 stacked on the substrate 5 , and a first memory unit 100 and a second memory unit 200 both disposed on the interposer 3 .

[0051] The first storage unit 100 may include a first logic area 130 and a first storage area 110, the first storage area 110 including a plurality of memory chips 111, 113, 115, and 117 stacked on the first logic area 130 in a vertical direction. The first storage area 110 may include at least one first memory chip 111, 113, 115, and 117, each of which includes a plurality of memory cells storing data. Each of the memory chips 111, 113, 115, and 117 and the first logic area 130 may be connected to each other via TSV (silicon through-hole). For ease of explanation, the first storage area 110 is illustrated as including four chips 111, 113, 115, and 117, but is not limited thereto, and may include less than four memory chips or more than four memory chips. In addition, Figure 3 Exemplary cross-sectional views of possible configurations of memory components are illustrated, but other forms of memory may also be applied.

[0052] The second storage unit 200 may have the same configuration as the first storage unit 100. That is, the second storage unit 200 may include a second logic area 230 and a second storage area 210, the second storage area 210 includes a plurality of memory chips 211, 213, 215, and 217 stacked on the second logic area 230 in a vertical direction, and each of the memory chips 211, 213, 215, and 217 and the first logic area 130 are connected to each other via TSVs, and data may be transmitted and received. The second storage area 210 may include at least one second memory chip 211, 213, 215, and 217, the second memory chip including a plurality of memory cells storing data.

[0053] The semiconductor device 1 according to at least one embodiment of the present inventive concept can perform data transmission and reception operations between adjacent storage components by setting the cache memory 133 and the interface port 134 in the logic area 130 and setting the cache memory 233 and the interface port 234 in the logic area 230. By setting the cache memories 133 and 233 and the interface ports 134 and 234 in the logic areas 130 and 230 that do not include storage units storing user data or data to be processed by the processing unit, direct data transmission and reception between adjacent storage components can be achieved without significantly increasing the area of ​​the semiconductor device 1. In addition, as described above, data transmission and reception between adjacent storage components can be performed using a serial interface.

[0054] Figure 4 1 is a block diagram for explaining a configuration of three storage components connected via an interface port according to an exemplary embodiment of the inventive concept. For example, the semiconductor device 1 may further include a third storage component 300, the third storage component 300 including a third storage area 310 and a third logic area 330. For example, the third logic area 330 may include a third storage buffer 331, a third PHY 332, a third cache memory 333, and a third interface port 334. Assume Figure 4 The first storage unit 100 has Figure 1 The configuration of the storage unit 100 is the same as that of the storage unit 100. Moreover, for the convenience of explanation, the first logic area 130, the second logic area 230 and the third logic area 330 are illustrated as not including the interface controller, but the first logic area 130, the second logic area 230 and the third logic area 330 may each include an interface controller for controlling data transmission and reception with adjacent storage units. In addition, it is assumed that the first storage unit 100 and the second storage unit 200 are arranged adjacent to each other, the second storage unit 200 and the third storage unit 300 are arranged adjacent to each other, and the first storage unit 100 and the third storage unit 300 are not arranged adjacent to each other.

[0055] Reference Figure 4 , a semiconductor device 1 according to an embodiment of the inventive concept includes a storage unit 200 having a plurality of interface ports 234_0 and 234_1. As illustrated in the figure, the second logic area 230 of the second storage unit 200 includes two second interface ports 234_0 and 234_1. That is, the second logic area 230 may include second interface ports 234_0 and 234_1 for performing data transmission and reception with the first storage unit 100 and the third storage unit 300 as adjacent storage units, respectively. Data transmission and reception between the first storage unit 100 and the second storage unit 200 may be performed using the first interface port 134 of the first storage unit 100 and the second interface port 234_0 of the second storage unit 200, and data transmission and reception between the second storage unit 200 and the third storage unit 300 may be performed using the third interface port 334 of the third storage unit 300 and the second interface port 234_1 of the second storage unit 200. As another example, the interface port for data transmission and reception with different adjacent storage units may be shared. That is, the second storage component 200 may perform data transmission and reception with the first storage component 100 and the third storage component 300 using the second interface port 234_0 or may perform data transmission and reception with the first storage component 100 and the third storage component 300 using the second interface port 234_1.

[0056] According to at least one embodiment of the present inventive concept, data received from an adjacent storage component is not stored in the storage area, but is sent to another adjacent storage component. In other words, when the storage component is not the destination storage component to which the data finally arrives, data is received from the adjacent storage component and stored in the cache memory, and then the data stored in the cache memory is sent to another adjacent storage component. Hereinafter, a process of storing data stored in the first storage area 110 in the third storage area 310 will be described.

[0057] When target data as a target of data transmission and reception between storage components is stored in a specific address of the first storage area 110 included in the first storage component 100 as a source storage component and the target data is to be stored in the third storage area 310, the second storage component 200 can receive the target data from the first interface port 134 via the second interface port 234_0. Since the second storage component 200 is not a destination storage component to which the data finally arrives, the second storage component 200 does not store the target data in the second storage area 210, but sends the target data to the third storage component 300 via the second interface port 234_1. In one embodiment, the target data is sent using a serial interface between the second interface port 234_1 and the third interface port 334. The target data sent to the third storage component 300 via the third interface port 334 is stored in the third cache memory 333, and then, can be stored in the third storage buffer 331 and the specific address of the third storage area 310 in sequence.

[0058] According to one embodiment, the semiconductor device 1 may further include a scheduler ( Fig.15 30), which schedules the transmission and reception paths between the plurality of storage components connected to the second storage component 200. Figures 15 to 19 To describe the process of moving data based on the scheduler's schedule.

[0059] Figure 5 1 is a block diagram for explaining the configuration of a processing unit and two storage components connected to the processing unit according to an exemplary embodiment of the inventive concept. Figure 1 and Figure 4 Repeated description of the configuration and operation of the storage component described.

[0060] Reference Figure 5, a semiconductor device 1 according to an embodiment of the inventive concept includes a processing unit 10 electrically connected to a plurality of memory components 100 and 200. The processing unit 10 may be a graphics processing unit (GPU) that performs operations based on data stored in the plurality of memory components 100 and 200, but the inventive concept is not limited thereto, as different types of processors may be applied.

[0061] According to an embodiment, the processing unit 10 includes a processor core 11 , an interface controller 13 , and a buffer 15 .

[0062] The processor core 11 performs operations based on data stored in the storage components 100 and 200 electrically connected to the processing unit 10. For example, the processor core 11 may perform processing operations based on data stored in the first storage area 110 of the first storage component 100 and data stored in the second storage area 210 of the second storage component 200.

[0063] The interface controller 13 may control data transmission and reception operations between the storage components 100 and 200 electrically connected to the processing unit 10. Figure 1 and Figure 2 As shown, the interface controller 13 may be disposed in the logic area 130 included in the storage component 100 and in the logic area 230 included in the storage component 200 , or may be included in the processing unit 10 , through which the storage components 100 and 200 are electrically connected to each other.

[0064] The buffer 15 may store data received from the storage components 100 and 200 electrically connected to the processing unit 10 or data to be transmitted to the storage components 100 and 200. The buffer 15 may receive data from the first storage component 100 via the PHY 132 and the PHY 17_0, and may receive data from the second storage component 200 via the second PHY 232 and the PHY 17_1.

[0065] The plurality of storage components 100 and 200 electrically connected to the processing unit 10 may perform data transmission and reception operations with each other. That is, the first storage component 100 and the second storage component 200 connected to the processing unit 10 may include a first interface port 134 and a second interface port 234, respectively, and may directly transmit and receive data with each other using the corresponding interface ports 134 and 234.

[0066] According to some embodiments, the processing unit 10 may include, for example, a GPU module, a TPU (tensor processing unit) module, a DPU (data processing unit) module, an MPU (main processing unit) module, etc. In the case of including a GPU module and a TPU module, the processing unit may include a GPU or a TPU, respectively, and may include a plurality of supporting chips. The TPU may be implemented, for example, on an application specific integrated circuit (ASIC), and may be configured or optimized for machine learning. According to at least one exemplary embodiment, the DPU may operate similarly to other accelerators such as a TPU or a GPU.

[0067] Figure 6 2 is a cross-sectional view of a processing unit and a storage component, which is used to illustrate the connection between the processing unit and the two storage components according to an exemplary embodiment of the present invention. Figure 3 The content of the description.

[0068] Reference Figure 6 , a semiconductor device 1 according to an exemplary embodiment of the inventive concept includes a processing unit 10 and a plurality of storage components 100 and 200 connected to the processing unit 10. In an exemplary embodiment, the processing unit 10 is provided with PHYs 17_0 and 17_1, the first storage component 100 is provided with PHY 132, the second storage component 200 is provided with PHY 232, and PHYs 17_0, 17_1, 132, and 232 are electrically connected to each other via an interposer 3. For example, PHY 132 may be electrically connected to PHY 17_0 via interposer 3, and PHY 232 may be electrically connected to PHY 17_1 via interposer 3.

[0069] As shown in the figure, the PHY 132 is arranged in the first logic area 130 of the first storage component 100, the processing unit 10 includes a plurality of PHYs 17_0 and 17_1, and the PHY 232 is arranged in the second logic area 230 of the second logic unit 230. The processing unit 10 can be connected to the first storage component 100 via the PHY 17_0 and the PHY 132, and can be connected to the second storage component 200 via the PHY 17_1 and the PHY 232 to send and receive data, commands, etc.

[0070] Figure 7 and Figure 8 is a block diagram for explaining communication between a storage component and a server via an interface connected to the storage component according to an exemplary embodiment of the inventive concept.

[0071] Reference Figure 7, a semiconductor device 1 according to an exemplary embodiment of the inventive concept includes a processing unit 10, a system memory 50, a CPU 60, a first interface 70, and a data bus 90. In addition, the semiconductor device 1 may include a first storage unit 100, a second storage unit 200, a third storage unit 300, and a fourth storage unit 400 connected to the processing unit 10, and may also include a second interface 80 electrically connected to the first storage unit 100, the second storage unit 200, the third storage unit 300, and the fourth storage unit 400.

[0072] When user data stored in a storage component electrically connected to the processing unit 10, data processed by the processing unit 10, etc. is transmitted to the server 2 (e.g., a data storage server) or data is received from the server 2, the processing unit 10 receives the data from the storage component storing the data via the control of the CPU 60, stores the received data in the system memory 50 via the data bus 90, and needs to communicate with the server 2 via the first interface 70 based on the received data. In addition, when data needs to be moved between the plurality of storage units (MU) 100, 200, 300, and 400 connected to the processing unit 10, the data may be transmitted via the processing unit 10. However, the efficiency of performing the transmission using the processing unit 10 is not high.

[0073] When multiple processing units (e.g., GPUs) are used to perform parallel operations, the accuracy of artificial neural networks trained by data exchange between processing units can be improved. However, the frequent occurrence of data loading between processing units and data exchange between processing units may reduce the utilization of processing units. Therefore, by sharing data between storage components via direct communication without sending and receiving data via processing units connected to storage components, the utilization of processing units can be improved.

[0074] When data needs to be exchanged between multiple storage components 100, 200, 300 and 400 connected to the processing unit 10, according to an exemplary embodiment of the present invention, direct communication between the multiple storage components 100, 200, 300 and 400 can be achieved by directly exchanging data between the storage components 100, 200, 300 and 400 without the intervention of intermediate paths such as the processor and the data bus 90, thereby improving the efficiency of the system.

[0075] Furthermore, since communication with the server 2 can be achieved via the second interface 80 connected to the respective storage components 100, 200, 300 and 400, and data transmission and reception with the server 2 can be achieved without intervention of the CPU 60 or the like, the efficiency of the system can be improved.

[0076] According to an exemplary embodiment, under the control of the interface controller 13 included in the processing unit 10, data sending and receiving between multiple storage components 100, 200, 300 and 400 electrically connected to the processing unit 10, data sending and receiving between the multiple storage components 100, 200, 300 and 400 and the second interface 80, and communication between the second interface 80 and the server 2 are performed.

[0077] For example, when the first target data DT_t0 stored in the first storage part 100 is transmitted to the server 2 , the first target data DT_t0 stored in the first storage part 100 is transmitted to the server 2 via the second interface 80 under the control of the interface controller 13 .

[0078] Reference Figure 8 , the interface may be connected to one of the plurality of storage components 100, 200, 300, and 400 electrically connected to the processing unit 10. As shown in the figure, the first storage component 100 and the second interface 80 may be connected to each other.

[0079] In the case of transmitting the first target data DT_t0 stored in the second storage part 200 to the server 2, the second storage part 200 transmits the first target data DT_t0 to the first storage part 100 through the serial interface, and the first storage part 100 transmits the first target data DT_t0 to the server 2 via the second interface 80 connected to the first storage part 100. When the second interface 80 is not connected to all of the plurality of storage parts 100, 200, 300, and 400, the number of ports arranged in each of the storage parts 100, 200, 300, and 400 is reduced, so that the circuit can be simplified.

[0080] Fig. 9 is a block diagram for explaining a semiconductor device including a plurality of processing units according to an exemplary embodiment of the inventive concept.

[0081] Reference Fig. 9 , a semiconductor device 1 according to an embodiment of the inventive concept includes a plurality of processing units 10 and 20. As an example, it is assumed that the semiconductor device 1 includes a first processing unit 10 and a second processing unit 20. In addition, the first processing unit 10 is electrically connected to a first storage unit 100, a second storage unit 200, a third storage unit 300, and a fourth storage unit 400, and the second processing unit 20 is electrically connected to a fifth storage unit 500, a sixth storage unit 600, a seventh storage unit 700, and an eighth storage unit 800.

[0082] According to the embodiment, data transmission and reception can be achieved between the second storage component 200 connected to the first processing unit 10 and the fifth storage component 500 connected to the second processing unit 20, and direct communication can be achieved between the fourth storage component 400 connected to the first processing unit 10 and the seventh storage component 700 connected to the second processing unit 20. That is, data transmission and reception between storage components connected to different processing units from each other can be achieved.

[0083] When performing deep learning or machine learning, a large-capacity storage component and multiple processing units (e.g., GPU) are required. When data transmission and reception between multiple processing units are frequently requested but data transmission and reception between processing units cannot be realized, communication via the data bus may be temporarily damaged (temporal damage). Even when data transmission and reception between processing units can be realized, the processing unit reads data from the storage component electrically connected to the processing unit, and in the process of sending data to another processing unit, the I / O operation of the storage component stops.

[0084] According to an embodiment of the present invention, the resources of the processing unit used can be reduced by sending and receiving data between adjacent storage components to reduce power consumption. In addition, even in the process of sending and receiving data between storage components, the utilization rate of the processing unit can be improved.

[0085] Fig.10 is a block diagram for explaining communication between two processing units according to one embodiment of the inventive concept.

[0086] Reference Fig.10 , a semiconductor device 1 according to an embodiment of the present invention transmits and receives data between a plurality of processing units. As shown in the figure, the first processing unit 10 and the second processing unit 20 can directly transmit and receive data. In the case where direct communication between processing units different from each other can be achieved, by transmitting and receiving data with fewer paths, the time required for operation can be shortened and the resources consumed in the system can be minimized compared to the case where an intermediate path such as a data bus is used. For example, there may be a dedicated and direct channel between the first processing unit 10 and the second processing unit 20, so that they can exchange data with each other.

[0087] Fig.11A is a diagram for explaining a data set trained according to an exemplary embodiment of the inventive concept, Fig. 11B It is used to describe the processing unit Fig.11A A flowchart of the process of processing the data included in the data set. Fig. 11C It is used to explain in detail Fig. 11BAn illustration of the process of processing and sharing calculated data between multiple processing units during processing of .

[0088] In operations such as deep learning, training is performed using large amounts of data, and the larger the data size for a single operation, the faster the training speed.

[0089] Reference Fig.11A , multiple subsets may be included in a data set that is a training object using an artificial neural network. Each subset may include data on multiple layers L1 to Lm. More than three subsets may be included in the data set, but for ease of explanation, it is assumed below that the data set includes two subsets (Sub-Set 1, Sub-Set 2). As used herein, a data set may be represented as a training data set, and a subset may be represented as a sub-data set. Moreover, transmission / processing of the "nth layer" may represent "transmission / processing of data on the nth layer".

[0090] Reference Fig. 11B , the first processing unit 10 and the second processing unit 20 according to an embodiment of the inventive concept can learn from the data included in the data set and can improve the inference accuracy through mutual data exchange. Fig. 11B In the description, it is illustrated that the first processing unit 10 and the second processing unit 20 process data through data sharing, but the present invention is not limited thereto, and more than three processing units can be implemented through data sharing.

[0091] In step S1100, the first processing unit 10 loads at least some data included in the first subset (Sub-Set 1). Hereinafter, it is assumed that data on the first layer L1 to the m-th layer Lm are loaded to become training targets.

[0092] In step S2100, the second processing unit 20 loads at least some of the data included in the second subset (Sub-Set2). Similarly, data on the first layer L1 to the m-th layer Lm may be loaded to become a training target.

[0093] In step S1200, the first processing unit 10 performs operations in the order of the first layer L1 to the mth layer Lm. In step S2200, the second processing unit 20 performs operations in the order of the first layer L1 to the mth layer Lm.

[0094] In step S1300, the first processing unit 10 calculates intermediate results of the first layer L1 to the mth layer Lm in the order of the mth layer Lm to the first layer L1 based on the performed operation. In step S2300, the second processing unit 20 calculates intermediate results of the first layer L1 to the mth layer Lm in the order of the mth layer Lm to the first layer L1 based on the performed operation. In an exemplary embodiment, the intermediate result calculated by the first processing unit 10 and the intermediate result calculated by the second processing unit 20 include information about the gradient of the data calculated by each of them.

[0095] In steps S1400 and S2400, the intermediate result calculated by the first processing unit 10 is sent to the second processing unit 20, and the intermediate result calculated by the second processing unit 20 is sent to the first processing unit 10. That is, the intermediate result calculated by each of the first processing unit 10 and the second processing unit 20 can be shared.

[0096] In step S1500 , the first processing unit 10 performs an update operation of data on the first layer L1 to the m-th layer Lm based on the intermediate result calculated by the first processing unit 10 and the intermediate result received from the second processing unit 20 .

[0097] In step S2500 , the second processing unit 20 performs an update operation of data on the first layer L1 to the m-th layer Lm based on the intermediate result calculated by the second processing unit 20 and the intermediate result received from the first processing unit 10 .

[0098] In step S1600, the first processing unit 10 determines whether all the data in the first subset (Sub-Set1) are loaded. If it is determined that all the data in the first subset (Sub-Set1) are loaded and the data have been operated, the operation of the processing operation ends; if it is determined that there is unloaded data in the data in the first subset (Sub-Set1), the unloaded data can be loaded and the operation processing according to steps S1100 to S1500 can be repeatedly performed.

[0099] In step S2600, the second processing unit 20 determines whether all the data in the second subset (Sub-Set2) are loaded. If it is determined that all the data in the second subset (Sub-Set2) are loaded and the data have been operated, the operation of the processing operation ends; if it is determined that there is unloaded data in the data in the second subset (Sub-Set2), the unloaded data can be loaded and the operation processing according to steps S2100 to S2500 can be repeatedly performed.

[0100] Reference Fig. 11B and Fig. 11C, step S1300 may include steps S1310 to S1370, and step S1400 may include steps S1410 to S1450. In addition, step S2300 may include steps S2310 to S2370, and step S2400 may include steps S2410 to S2450.

[0101] As described above, in steps S1200 and S2200, the first processing unit 10 and the second processing unit 20 respectively perform operations on the data included in the first subset and the second subset (Sub-Set 1 and Sub-Set 2) in the order of the first layer L1 to the mth layer Lm. The operation performed at this time may be a model evaluation operation for each layer. In steps S1300 and S2300, the first processing unit 10 and the second processing unit 20 respectively perform calculations on the intermediate results of the operations performed in steps S1200 and S2200. In one embodiment, the intermediate results may include gradient information of the evaluated data, and the gradient calculation operation may be performed in the reverse order of the evaluation operations performed in steps S1200 and S2200. That is, the operation may be performed in the order from the mth layer Lm to the first layer L1.

[0102] In steps S1310 and S2310, the first processing unit 10 and the second processing unit 20 respectively perform gradient calculation operations on the mth layer Lm of the first subset and the second subset (Sub-Set 1 and Sub-Set 2). In steps S1410 and S2410, the first processing unit 10 and the second processing unit 20 share the calculated gradient information of the mth layer Lm.

[0103] In steps S1330 and S2330, the first processing unit 10 and the second processing unit 20 perform gradient calculation operations on the m-1th layer (Lm-1) of the first subset and the second subset (Sub-Set 1 and Sub-Set 2), respectively. In one embodiment, the data evaluated for the m-1th layer (Lm-1) and the gradient information about the m-th layer Lm can be used in the gradient calculation operation for the m-1th layer (Lm-1). That is, in addition to the information evaluated in S1200 and S2200, the gradient information calculated for the m-th layer Lm can be used, and the gradient information calculated in another processing unit can be used. For example, in the gradient calculation of the m-1th layer (Lm-1), in addition to the information evaluated for the m-1th layer (Lm-1) of the first subset (Sub-Set 1) and the gradient information calculated for the mth layer Lm of the first subset (Sub-Set 1), the first processing unit 10 may also use the gradient information calculated for the mth layer Lm of the second subset (Sub-Set 2) in the second processing unit 20. These operations may be repeated until the gradient calculation operations for all layers Lm to L1 are performed.

[0104] According to some embodiments, a gradient calculation operation for a specific layer and an operation of sharing the calculated gradient of a previous layer may be performed simultaneously by the corresponding processing units 10 and 20. For example, when a gradient calculation operation for an m-1th layer (Lm-1) is performed by the first processing unit 10 and the second processing unit 20, the calculated gradient of the m-th layer Lm may be sent and received between storage components electrically connected to the first processing unit 10 and the second processing unit 20. That is, according to an embodiment of the inventive concept, when a processing unit performs an operation via an interface between storage components, the efficiency of the processing unit performing the operation may be improved by sharing data required for the current operation or the next operation between the storage components.

[0105] According to at least one exemplary embodiment of the inventive concept, intermediate results calculated by each of a plurality of processing units may be shared, and the reasoning accuracy of a trained artificial neural network may be improved through an update operation based on the shared information.

[0106] When data transmission and reception between adjacent storage components are performed according to at least one exemplary embodiment of the present invention, in the exchange process of the required intermediate results (e.g., calculated data) that frequently occurs during the operation, since the transmission and reception of data are directly performed between multiple storage components without passing through multiple processing units, the utilization of the processing units can be improved. In addition, when the data size shared between the processing units is smaller than the data size sent and received between the storage component and the processing unit and a high transmission speed is not required, the data transmission and reception between the multiple storage components does not require high speed. In addition, since the training sequence or training form (e.g., the process of performing an operation, the order of data performing an operation, etc.) is relatively constant, the timing and order of data transmission and reception between the storage components can be easily predicted.

[0107] Fig.12 is a block diagram for explaining the configuration of data stored in a logic area.

[0108] Reference Fig.12 , a storage unit 100 according to an embodiment of the inventive concept includes a storage area 110 and a logic area 130. According to an embodiment, the logic area 130 includes a cache storage area 138 and a cache control area 139. In one embodiment, the cache storage area 138 is an area for temporarily storing data to be sent to or received from an adjacent storage unit. In one embodiment, the cache control area 139 is an area for storing information and instructions 1300 required for the storage unit 100 to communicate with the adjacent storage unit. According to one embodiment, the cache storage area 138 and the cache control area 139 are included in a single cache memory ( Figure 1 130) in the area.

[0109] According to one embodiment, storage unit ID information (INF_ID(MU)) 1100 , storage unit status information (INF_Status(MU)) 1200 , instructions 1300 , and control ID status information (INF_Status(Ctrl ID)) 1400 are stored in the cache control area 139 .

[0110] Reference Fig.10 and Fig.12, a semiconductor device 1 according to an embodiment of the inventive concept includes a compiler that generates a scheduling code for a data path that moves in an operation process of data performed by processing units 10 and 20. For example, the scheduling code may include information about a first path in which data moves between a processing unit (e.g., 10) and a storage unit 100, 200, 300, and 400 connected to the processing unit 10, and a second path in which data moves between a plurality of storage units 500, 600, 700, and 800 connected to the same processing unit (e.g., 20). According to some embodiments, the scheduling code may include information about a third path in which data moves between storage units (e.g., 400 and 700) that are respectively connected to processing units 10 and 20 that are different from each other. According to some embodiments, the scheduling code may include information about a fourth path in which data moves between a plurality of processing units 10 and 20 that are different from each other.

[0111] The processing unit 10 may perform operations on data based on the scheduling code generated by the compiler. For example, when a small amount of data for operation is sent to the storage component in units of queues, the input queue may be scheduled so that the data is sent to the processing unit in the form of FIFO (first in first out). According to some embodiments, the input queue may be stored in the logic area 130 of the storage component 100. According to some embodiments, the input queue may be stored in the cache storage area 138 of the logic area 130. According to some embodiments, the scheduling code may include such information: the information is suitable for transmitting the queue stored in the logic area 130 to the processing unit 10 via the second path and transmitting the data required for the operation (e.g., gradient data) from the storage area 110 to the processing unit 10 through the first path. In addition, the scheduling code may include such information: the information is suitable for storing the data processed by the processing unit 10 in the logic area 130 and sending the processed data to the storage component (e.g., 500) electrically connected to another processing unit 20 through the third path.

[0112] Fig.13 It is a mapping table for describing the mapping between the physical address and the logical address in each of the storage area and the logical area.

[0113] Reference Fig.12 and Fig.13, a storage unit 100 according to an embodiment of the present invention includes a storage area 110 and a logical area 130. In one embodiment, the storage area 110 and the logical area 130 share the same logical address. In other words, the storage area 110 and the logical area 130 each have a unique physical address, and each physical address can be mapped to a logical address having an index different from each other. As shown in the figure, it is assumed that the storage area 110 of the storage unit 100 has a storage area physical address value MPA of a physical address MPA_0 to a physical address MPA_999, and the logical area 130 has a logical area physical address LPA of a physical address LPA_0 to a physical address LPA_499. Specifically, it is assumed that the cache storage area 138 and the cache control area 139 included in the logical area 130 have a logical area physical address LPA of a physical address LPA_0 to a physical address LPA_399 and a logical area physical address LPA of a physical address LPA_400 to a physical address LPA_499, respectively.

[0114] Physical addresses MPA_0 to MPA_999 of the storage area 110 may be mapped to logical addresses LA_0 to LA_999, respectively. For example, the location of the storage area 110 having the physical address MPA_1 has the logical address LA_1. In addition, physical addresses LPA_0 to LPA_399 of the cache storage area 138 may be mapped to logical addresses LA_1000 to LA_1399, respectively. For example, the location of the cache storage area 138 having the physical address LPA_399 has the logical address LA_1399. In addition, physical addresses LPA_400 to LPA_499 of the cache control area 139 may be mapped to logical addresses LA_1400 to LA_1499, respectively. For example, the location of the cache control area 139 having the physical address LPA_400 has the logical address LA_1400.

[0115] Since the storage area 110 and the logic area 130 share the same logical address, the processing unit ( Figure 5 10) No separate hardware is required for sending and receiving addresses that are different from each other.

[0116] According to one embodiment, the mapping table may be stored in the storage area 110, the cache storage area 138 or the cache control area 139 of the storage component 100. According to another embodiment, the mapping table may be stored in other storage areas of the processing unit 10.

[0117] also, Fig.14A1 is a diagram for explaining storage unit ID information (INF_ID(MU)) 1100 stored in the cache control area 139 as an example. Fig.12 and Fig.14A Described is the storage unit ID information (INF_ID(MU)) 1100 stored in the cache control area 139. As shown in the figure, it is assumed that a plurality of storage units are respectively located in n+1 rows and m+1 columns.

[0118] The storage unit ID information (INF_ID(MU)) 1100 may include information about the locations of multiple storage units. That is, it may include information identifying the row and column where a specific storage unit is located. For example, the storage unit 1110 located at the i-th row and j-th column may be represented in the form of (i, j).

[0119] According to one embodiment, the storage component ID information (INF_ID (MU)) 1100 includes information about neighboring storage components adjacent to each storage component. For example, when the position in the storage component ID information 1100 of the storage component 1110 is (i, j) (which means the i-th row and j-th column), the storage component (i-1, j) located at the i-th row and j-th column, the storage component (i, j+1) located at the i-th row and j+1 column, the storage component (i, j-1) located at the i-th row and j-1 column, and the storage component (i+1, j) located at the i+1 row and j-th column correspond to the neighboring storage components, and the ID information of the storage component (i-1, j), the storage component (i, j+1), the storage component (i, j-1), and the storage component (i+1, j) which are the neighboring storage components of the storage component 1110 can be stored in the storage component ID information (INF_ID (MU)) 1100. At this time, the neighboring storage components can be defined as storage components that can directly transmit and receive data between them. That is, storage component 1110 can directly send and receive data with storage component (i-1, j), storage component (i, j+1), storage component (i, j-1) and storage component (i+1, j). For example, storage component 1110 can receive data from storage component (i-1, j) and forward the data to storage component (i, j+1).

[0120] According to another embodiment, by storing the ID information of the storage components that are not adjacent to each storage component in the cache control area of ​​the storage component, data can also be transferred to the non-adjacent storage components. Figure 4, when the first storage component 100, the second storage component 200 and the third storage component 300 are storage components located at (i, j-1), (i, j) and (i, j+1), respectively, the first storage component 100 is not adjacent to the third storage component 300, but since the second storage component 200 adjacent to the first storage component 100 stores the ID information of other storage components including the third storage component 300, the data included in the first storage component 100 can be transferred to the third storage component 300 without the intervention of other processing units, etc. In one embodiment, the data stored in the first storage component 100 is transferred in the order of the first storage component 100, the second storage component 200 and the third storage component 300, and can be stored in the third storage area 310, the third storage buffer 331 or the cache memory 333 of the third storage component 300.

[0121] Fig. 14B 1 is a diagram illustrating, as an example, state information stored in the cache control area 139. Fig.12 , Fig.13 , Fig.14A and Fig. 14B The storage unit status information (INF_Status(MU)) 1200 stored in the cache control area 139 is described.

[0122] As described above, the neighboring storage components of the storage component 1110 are defined as storage component (i-1, j), storage component (i, j+1), storage component (i, j-1), and storage component (i+1, j), and their information may be stored in the storage component ID information (INF_ID (MU)) 1100. In one embodiment, the storage component status information (INF_Status (MU)) 1200 stored in the cache control area 139 indicates whether the status of the neighboring storage component is a ready state or a busy state. In one embodiment, the ready state means that the neighboring storage component is in a state capable of data transmission and reception, and the busy state means that the neighboring storage component is in a state incapable of data transmission and reception.

[0123] As shown in the figure, storage components (i-1, j), storage components (i, j+1) and storage components (i+1, j) among the adjacent storage components of storage component 1110 are in the ready state, and storage component (i, j-1) is in the busy state. In other words, storage components (i-1, j), storage components (i, j+1) and storage components (i+1, j) are in a state where data can be sent and received with storage component 1110, and storage component (i, j-1) is in a state where data cannot be sent and received with storage component 1110.

[0124] Fig. 14C 1 is a diagram for explaining an instruction 1300 stored in the cache control area 139 as an example. Figure 5 , Fig.12 , Fig.13 and FIG. 14A to FIG. 14C Describes the information contained in instruction 1300.

[0125] Instructions 1300 may be stored in cache control area 139 by the processing unit, or may be transferred and stored between storage components via a serial interface.

[0126] The control instruction (Ctrl Instruction) may include information about the operation performed when the data transmission and reception operation with the adjacent storage component is performed. For example, when the data received from the second storage component 200 and stored in the first cache memory 133 is transmitted to the first storage area 110, the starting address of the first cache memory 133 storing the data to be transmitted, the size (or length) of the data, and the starting address of the first storage area 110 storing the data may be included in the control instruction (Ctrl Instruction) of the first storage component.

[0127] As another example, when data stored in the first storage area 110 is sent to the second storage component 200, the starting address of the first storage area 110 storing the data to be sent, the size (or length) of the data to be sent, and the starting address of the first cache memory 133 storing the data may be included in a control instruction (Ctrl Instruction) of the first storage component.

[0128] The active information (Active) may define a mode for performing an operation according to the control instruction (Ctrl Instruction). For example, the active information (Active) may include information about a first mode in which data is sent and received between storage components according to the control instruction (Ctrl Instruction) when the processing unit stores the instruction 1300 in the cache control area 139, or a second mode in which data is sent and received between processing units according to the control instruction (Ctrl Instruction) when a start command of the processing unit is received.

[0129] The source storage unit ID information (ID_MU(Src)) may be the storage unit ID information of the source storage unit in which the target data as the target of the operation according to the control instruction (Ctrl Instruction) is stored. In addition, the destination storage unit ID information (ID_MU((Dst))) may be the storage unit ID information of the destination storage unit to which the target data finally arrives.

[0130] The start address information (ADD_MU(Start)) may represent address information of a source storage unit, and the size information (Length) may represent a size of target data or an address length of a source storage unit storing the target data.

[0131] According to one embodiment, the instructions 1300 also include priority order information about the source storage component and the destination storage component, and the scheduler ( Fig.15 30) can determine the sending and receiving paths between the storage components based on the priority order information.

[0132] According to one embodiment, the scheduler schedules the path of the target data based on the storage unit ID information (INF_ID(MU)) 1100, the storage unit status information (INF_Status(MU)) 1200 and the instruction 1300 stored in the cache control area 139. The scheduling operation of the scheduler will be described later.

[0133] Figures 15 to 18 is a block diagram for explaining a semiconductor device including a scheduler according to an exemplary embodiment of the present invention. Figures 1 to 10 Description of the configuration and operation.

[0134] Reference Figures 12 to 15 , the semiconductor device 1 according to the embodiment of the inventive concept further includes a scheduler 30. The scheduler 30 can schedule the transmission and reception paths between the storage components based on the path information. For example, the path information can include at least one of the storage component ID information, the storage component status information and the instruction.

[0135] Reference Fig.16 , the schedulers 19 and 29 are respectively included in the first processing unit 10 and the second processing unit 20. In this case, the first scheduler 19 schedules the transmission and reception paths of the target data in the first storage component 100, the second storage component 200, the third storage component 300, and the fourth storage component 400 connected to the first processing unit 10. In addition, the second scheduler 29 schedules the transmission and reception paths of the target data in the fifth storage component 500, the sixth storage component 600, the seventh storage component 700, and the eighth storage component 800 connected to the second processing unit 20.

[0136] Reference Fig.17 , schedulers 190, 290, 390, 490, 590, 690, 790 and 890 are respectively included in each storage component. For example, the first storage component 100, the second storage component 200, the third storage component 300, the fourth storage component 400, the fifth storage component 500, the sixth storage component 600, the seventh storage component 700 and the eighth storage component 800 may respectively include scheduler 190, scheduler 290, scheduler 390, scheduler 490, scheduler 590, scheduler 690, scheduler 790 and scheduler 890. Each scheduler can schedule the sending and receiving paths of the target data in the storage component including the scheduler.

[0137] Reference Fig.18 , the semiconductor device 1 according to an exemplary embodiment of the present invention further includes a scheduler 31. The scheduler 31 schedules the transmission and reception paths between the storage components based on the path information. For example, the path information may include storage component ID information ( Fig.12 1100), storage component status information ( Fig.12 1200) and the instruction ( Fig.12 1300). As shown in the figure, the scheduler 31 can be connected to each storage component 100 to 800 included in the semiconductor device 1. In this case, the scheduler 31 can directly receive path information from each storage component 100 to 800, and can schedule the data transmission and reception path between the storage components based on the path information. In an exemplary embodiment, there is a direct channel between the first processing unit 10 and the second processing unit 20 that enables them to exchange data with each other. In an exemplary embodiment, during a first operating mode, the storage components exchange data with each other without passing through the channel, and in a second other operating mode, the channel is used to transmit data of a storage component connected to one processing unit to a storage component connected to other processing units.

[0138] Figures 19 to 21 is a diagram for explaining a process of transmitting target data stored in a source storage component to a destination storage component based on scheduling of a scheduler according to one embodiment of the inventive concept.

[0139] exist Fig.19 and Fig.21In the description of FIG. 1 , it is assumed that a third processing unit 3000 connected to a first storage unit 3100, a second storage unit 3200, a third processing unit 3300, and a fourth storage unit 3400, a fourth processing unit 4000 connected to a fifth storage unit 4100, a sixth storage unit 4200, a seventh storage unit 4300, and an eighth storage unit 4400, a fifth processing unit 5000 connected to a ninth storage unit 5100, a tenth storage unit 5200, an eleventh storage unit 5300, and a twelfth storage unit 5400, and a sixth processing unit 6000 connected to a thirteenth storage unit 6100, a fourteenth storage unit 6200, a fifteenth storage unit 6300, and a sixteenth storage unit 6400 are arranged, and each storage unit connected to the same processing unit can perform data transmission and reception via a serial interface. Moreover, data transmission and reception can be realized between adjacent storage units connected to different processing units, as indicated by a double-headed arrow in the figure. In addition, it is assumed that the first target data DT_t1 is stored in the seventh storage unit 4300 and the second target data DT_t2 is stored in the fourteenth storage unit 6200 .

[0140] According to an exemplary embodiment, Figures 19 to 21 Each of the first storage part 3100, the second storage part 3200, the third storage part 3300, the fourth storage part 3400, the fifth storage part 4100, the sixth storage part 4200, the seventh storage part 4300, the eighth storage part 4400, the ninth storage part 5100, the tenth storage part 5200, the eleventh storage part 5300, the twelfth storage part 5400, the thirteenth storage part 6100, the fourteenth storage part 6200, the fifteenth storage part 6300 and the sixteenth storage part 6400 corresponds to Figure 5 The first storage unit 100 or the second storage unit 200 may have the same configuration as the first storage unit 100 or the second storage unit 200. Figures 19 to 21 The third processing unit 3000, the fourth processing unit 4000, the fifth processing unit 5000 and the sixth processing unit 6000 correspond to Figure 5 The processing unit 10 may include Figure 5 The same configuration as illustrated in . In addition, Figures 19 to 21 The serial interface between the storage components may correspond to Figure 5 The first interface port 134 of the first storage component 100 or the second interface port 234 of the second storage component 200.

[0141] Reference Fig.19, an operation of sending the first target data DT_t1 to the first storage unit 3100 is performed. At this time, the seventh storage unit 4300 as a storage unit storing the first target data DT_t1 is defined as a source storage unit, and the storage unit 3100 as a storage unit to which the first target data DT_t1 finally arrives is defined as a destination storage unit.

[0142] According to an embodiment, the scheduler schedules the path for sending the first target data DT_t1. In one embodiment, the path can be determined based on path information including instructions, storage component ID information, and storage component status information. The instruction may include priority order information between adjacent storage components. An embodiment of selecting a path based on priority order information will be described below.

[0143] First, the scheduler may determine the neighboring storage components by referring to the storage component ID information. The neighboring storage components of the seventh storage component 4300 as the source storage component may be determined as the fourth storage component 3400, the fifth storage component 4100, the eighth storage component 4400, and the thirteenth storage component 6100.

[0144] Thereafter, a path is selected based on the priority order information between adjacent storage components. As shown in the figure, the fifth storage component 4100 is selected, and the first target data DT_t1 is sent along the first path P1 accordingly. For example, since the priority order information indicates that the fifth storage component 4100 has a higher priority than the fourth storage component 3400, the eighth storage component 4400 and the thirteenth storage component 6100, the fifth storage component 4100 can be selected.

[0145] Thereafter, the scheduler may select a path through the same process, and the first target data DT_t1 reaches the first storage unit 3100 through the second path P2 and may be stored.

[0146] In another embodiment, the second target data DT_t2 stored in the fourteenth storage unit 6200 may reach the first storage unit 3100 as a destination storage unit through the third path P3 and the fourth path P4 by scheduling of the scheduler and may be stored.

[0147] For the sake of convenience of explanation, the data transmission and reception between adjacent storage components is illustrated, but the present invention is not limited thereto, and data transmission and reception between non-adjacent storage components can be implemented. For example, data transmission and reception can be implemented between the first storage component 3100 connected to the third processing unit 3000 and the eighth storage component 4400 connected to the fourth processing unit 4000.

[0148] Reference Fig. 20, a semiconductor device according to an embodiment of the present invention can perform data transmission and reception between processing units. As shown in the figure, data transmission and reception can be implemented between the third processing unit 3000 and the fourth processing unit 4000, between the fourth processing unit 4000 and the sixth processing unit 6000, between the fifth processing unit 5000 and the sixth processing unit 6000, and between the third processing unit 3000 and the fifth processing unit 5000, which are adjacent storage components.

[0149] Reference Fig. 20 , an operation of sending the first target data DT_t1 to the first storage unit 3100 is performed. At this time, the seventh storage unit 4300 as a storage unit storing the first target data DT_t1 is defined as a source storage unit, and the first storage unit 3100 as a storage unit to which the first target data DT_t1 finally arrives is defined as a destination storage unit. The first target data DT_t1 is scheduled by the path of the scheduler, arrives at the first storage unit 3100 as the destination storage unit through the first path P1 and the second path P2, and can be stored.

[0150] In the case of the path of the second target data DT_t2, select Fig.19 A path different from the path determined in. According to one embodiment of the present inventive concept, data transmission and reception can be implemented between processing units, and the scheduler can determine the data transmission and reception path between the processing units as the path of the second target data DT_t2 based on the path information. As shown in the figure, the data is sent from the fourteenth storage component 6200 as the source storage component to the sixth processing unit 6000 along the fifth path P5, and the second target data DT_t2 is sent to the fifth processing unit 5000 as the processing unit adjacent to the sixth processing unit 6000 along the sixth path P6. Thereafter, the second target data DT_t2 is sent from the fifth processing unit 5000 to the third processing unit 3000 along the seventh path P7, and is sent to and stored in the first storage component 3100 connected to the third processing unit 3000, that is, the destination storage component, along the eighth path P8.

[0151] Reference Fig.21 , the path of the target data can be scheduled based on the storage component status information. As shown in the figure, it is assumed that the status information of the second storage component 3200 and the ninth storage component 5100 includes a busy state.

[0152] In the case of the first target data DT_t1, the scheduler may determine the thirteenth path P13 and the fourteenth path P14 as the transmission paths of the first target data DT_t1. Fig.19 and Fig. 20In the case of the second path P2 described in the embodiment, it includes the second storage component 3200 in a busy state, so the scheduler selects a path that does not include the storage component in a busy state.

[0153] Similarly, in the case of the second target data DT_t2, the second target data DT_t2 is sent from the fourteenth storage component 6200 as the source storage component to the tenth storage component 5200 via the ninth path P9, is sent from the tenth storage component 5200 to the fourth storage component 3400 via the tenth path P10, is sent to the third storage component 3300 via the eleventh path P11, and reaches the first storage component 3100 as the destination storage component through the twelfth path P12 and is stored therein.

[0154] At the conclusion of the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the exemplary embodiments without substantially departing from the principles of the inventive concept.

Claims

1. A semiconductor device comprising: a first storage component including a first storage area and a first logic area electrically connected to the first storage area, the first logic area including a cache memory and an interface port for performing data transmission and reception operations, and a scheduler that schedules a data transmission and reception path including an adjacent storage component adjacent to the first storage component, wherein the first storage component uses the cache memory to perform the data transmission and reception operations with the adjacent storage component via the interface port, and Wherein, the data sending and receiving operations are based on the path information identifying the adjacent storage component stored in the cache memory and the state information indicating whether the state of the adjacent storage component is a ready state or a busy state stored in the cache memory, and the target data is transmitted from the first storage component to the destination storage component via the adjacent storage component, and the scheduler determines the data sending and receiving path that only includes the adjacent storage components in the ready state.

2. The semiconductor device according to claim 1, wherein The first storage section performs the data transmission and reception operations between the first storage section and the adjacent storage section using a serial interface.

3. The semiconductor device according to claim 1, in, The scheduler schedules the data transmission and reception paths between one or more second storage components electrically connected to the first storage component, The first storage component performs the data sending and receiving operation with one of the second storage components through the data sending and receiving path scheduled by the scheduler.

4. A semiconductor device comprising: a plurality of first storage components, each of the plurality of first storage components comprising a cache memory and an interface port, a first processing unit electrically connected to the plurality of first storage components and performing an operation based on data stored in the plurality of first storage components, and a scheduler that schedules a transmission and reception path of target data between the plurality of first storage components based on path information stored in the cache memory, the path information identifying a source storage component storing the target data and an adjacent storage component adjacent to the source storage component through which the target data passes before reaching a destination storage component, wherein the plurality of first storage components perform data transmission and reception operations between the plurality of first storage components through the transmission and reception paths using the cache memory and the interface port, and Wherein, the first processing unit includes an interface controller for controlling the data sending and receiving operations between the plurality of first storage components.

5. The semiconductor device according to claim 4, wherein: The plurality of first storage components perform the data transmission and reception operations between the plurality of first storage components using a serial interface.

6. The semiconductor device according to claim 4, further comprising: a plurality of second storage components, each of the plurality of second storage components comprising a cache memory and an interface port; and a second processing unit electrically connected to the plurality of second storage components and performing an operation based on the data stored in the plurality of second storage components, Wherein, the target data required for the operation of the first processing unit or the second processing unit is, according to the operation mode: i) sent or received between the multiple first storage components and the multiple second storage components, or ii) sent or received between the first processing unit and the second processing unit.

7. A semiconductor device comprising: a first processing unit and a second processing unit; a plurality of first storage components, the plurality of first storage components being electrically connected to the first processing unit, and the plurality of first storage components each comprising a first storage area and a first cache area, the first storage area and the first cache area sharing a logical address; a plurality of second storage components, the plurality of second storage components being electrically connected to the second processing unit, and the plurality of second storage components each comprising a second storage area and a second cache area, the second storage area and the second cache area sharing the logical address; and a scheduler, the scheduler being used to schedule a sending and receiving path between the first storage component and the second storage component for target data stored in the first storage area or the second storage area, wherein the scheduler schedules the sending and receiving paths based on the path information stored in the first cache area or the second cache area, The path information identifies a source storage component storing the target data and an adjacent storage component adjacent to the source storage component, and the target data passes through the adjacent storage component before reaching the destination storage component.

8. The semiconductor device according to claim 7, wherein: The path information includes ID information of each of the first storage component and the second storage component, ID information of the source storage component and ID information of the adjacent storage component, status information of the adjacent storage component, and instructions on scheduling the transmission and reception paths, and The scheduler determines the transmission and reception path to the destination storage component where the target data finally arrives based on the path information.

9. The semiconductor device according to claim 8, wherein: The state information indicates whether the state of the adjacent storage component is a ready state or a busy state, and The scheduler determines the transmit and receive paths that include only neighboring storage components that are in a ready state.

10. The semiconductor device according to claim 8, wherein The instruction includes priority order information about the source storage component and the destination storage component, and The scheduler determines the transmission and reception paths based on the priority order information.

11. The semiconductor device according to claim 8, wherein The path information further includes operation mode information including a first mode of transmitting and receiving data between the first storage component and the second storage component and a second mode of transmitting and receiving data between the first processing unit and the second processing unit, and The scheduler determines the transmission and reception paths based on the operation mode information.

12. The semiconductor device according to claim 7, wherein: The scheduler is included in the first cache area included in each of the plurality of first storage components and in the second cache area included in each of the plurality of second storage components, and Each of the schedulers schedules the transmission and reception paths of the target data in a storage component including the scheduler.

13. The semiconductor device according to claim 7, wherein: The scheduler is included in each of the first processing unit and the second processing unit, and Each of the schedulers schedules the transmission and reception paths of the target data in a storage section connected to a processing unit including the scheduler.

14. The semiconductor device according to claim 7, further comprising: an interface controller, the interface controller controlling the sending and receiving of the target data in the first storage component and the second storage component, The interface controller controls the sending and receiving of the target data based on the scheduled sending and receiving paths.

15. The semiconductor device according to claim 14, wherein: The interface controller is included in the first cache area included in each of the plurality of first storage components and the second cache area included in each of the plurality of second storage components, and controls the sending and receiving of the target data in the storage component including the interface controller.

16. The semiconductor device according to claim 14, wherein: The interface controller is included in each of the first processing unit and the second processing unit, and controls transmission and reception of the target data in a storage section connected to the processing unit including the interface controller.

Images