A display panel including a non-display area within the display area

Abstract

A display panel is provided. The display panel includes a substrate, the substrate having a first area, a second area at least partially surrounding the first area, and a third area arranged between the first area and the second area. A plurality of display elements are arranged in the second area. A plurality of wirings are arranged around the edge of the first area in the third area. A first electrode layer covers at least a portion of the plurality of wirings. A second electrode layer is arranged above the first electrode layer and contacts at least a portion of the first electrode layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0153025 filed on November 30, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present application relates to a display panel, and more particularly, to a display panel including a non-display area inside a display area. Background Art

[0003] Display devices are widely used in a variety of electronic devices. Display devices have been designed to have a larger functional area and a smaller area in which no image is displayed. As the size of the functional area of ​​the display device increases, various other elements have been incorporated into the display device. For example, cameras, sensors, etc. have been incorporated into the functional area of ​​the display device, such as in a notch or cutout. Summary of the invention

[0004] A display panel includes a substrate, the substrate having a first area, a second area at least partially surrounding the first area, and a third area arranged between the first area and the second area. A plurality of display elements are arranged in the second area. A plurality of wirings are arranged around the edge of the first area in the third area. A first electrode layer covers at least a portion of the plurality of wirings. A second electrode layer is arranged above the first electrode layer and contacts at least a portion of the first electrode layer.

[0005] A display panel includes a substrate having a first area, a second area at least partially surrounding the first area, and a third area arranged between the first area and the second area. Each of a plurality of display elements is arranged in the second area and includes a pixel electrode, a counter electrode, and an emission layer arranged between the pixel electrode and the counter electrode. A plurality of wirings are arranged around the edge of the first area in the third area. At least one groove is arranged in the third area. A first electrode layer covers at least a portion of the plurality of wirings. A second electrode layer is arranged above the first electrode layer and contacts at least a portion of the first electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] These and / or other aspects will become clear and more easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is a perspective view showing a display device according to an exemplary embodiment of the present disclosure;

[0008] Figure 2 is a cross-sectional view showing a display device according to an exemplary embodiment of the present disclosure;

[0009] Figure 3 is a cross-sectional view showing a display device according to an exemplary embodiment of the present disclosure;

[0010] FIG. 4A to FIG. 4E is a cross-sectional view showing a display panel according to an exemplary embodiment of the present disclosure;

[0011] FIG. 5A to FIG. 5D is a cross-sectional view showing a display panel according to an exemplary embodiment of the present disclosure;

[0012] Figure 6 is a plan view showing a display panel according to an exemplary embodiment of the present disclosure;

[0013] Figure 7 is an equivalent circuit diagram showing one of the pixels of a display panel according to an exemplary embodiment of the present disclosure;

[0014] Figure 8 is a plan view showing elements arranged in a first area and a middle area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0015] Fig. 9 is along Figure 8 A sectional view taken along line IX-IX';

[0016] Fig.10 It is shown Fig. 9 an enlarged cross-sectional view of a region of a display panel;

[0017] Fig.11A and Fig. 11B It is shown Fig. 9 An enlarged cross-sectional view of region XI;

[0018] Fig. 12A It is shown Figure 8 An enlarged plan view of an example of a region W;

[0019] Fig. 12B is along Fig. 12A A cross-sectional view taken along line AA';

[0020] Fig.13A It is shown Figure 8 An enlarged plan view of an example of a region W;

[0021] Fig. 13B is along Fig.13A A cross-sectional view taken along line BB';

[0022] Fig.14A It is shown Figure 8 an enlarged plan view of an example of a region W of; and

[0023] Fig. 14B is along Fig.14A A cross-sectional view taken along line CC'. DETAILED DESCRIPTION

[0024] Because the present disclosure allows for various changes and many embodiments, exemplary embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to a specific mode of practice, and it is understood that all changes, equivalents, and substitutes that do not depart from the spirit and technical scope of the present disclosure are included in the present disclosure. In the description of the present disclosure, some detailed explanations of related technologies are omitted when it is considered that some detailed explanations of related technologies may unnecessarily obscure the essence of the present disclosure.

[0025] Although terms such as "first", "second", etc. may be used to describe various components, such components should not be limited to the above terms. The above terms are only used to distinguish one component from another.

[0026] It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, the layer, region or component may be directly or indirectly formed on the other layer, region or component. For example, there may be intervening layers, regions or components.

[0027] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of the Cartesian coordinate system, but can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0028] Hereinafter, embodiments are described with reference to the accompanying drawings. When describing with reference to the accompanying drawings, the same reference numerals may be used for substantially the same or corresponding elements, and repeated descriptions of these elements are omitted. In the accompanying drawings, the thicknesses of various layers and elements may be exaggerated for ease of explanation.

[0029] Figure 1 is a perspective view showing a display device 1 according to an exemplary embodiment of the present disclosure.

[0030] Reference Figure 1 , the display device 1 includes a first area OA and a second area DA, the second area DA being a display area at least partially surrounding the first area OA. The display device 1 may display a predetermined image by using light emitted from a plurality of pixels arranged in the second area DA. Figure 1 1 and 2 show that a first area OA is arranged inside the second area DA, and the first area OA may be completely surrounded by the second area DA. The first area OA may be arranged with Figure 2 The region of the component being described.

[0031] The third area MA may be arranged as an intermediate area between the first area OA and the second area DA as a display area. The second area DA may be surrounded by an outer area PA, which is a fourth area. The third area MA and the outer area PA may be a non-display area or a frame in which no pixels are arranged. The third area MA may be completely surrounded by the second area DA, and the second area DA may be completely surrounded by the outer area PA.

[0032] Although an organic light emitting display device is exemplarily described as the display device 1 according to the embodiment described below, the display device 1 is not limited thereto. For example, various types of display devices such as an inorganic light emitting display and a quantum dot light emitting display may be used.

[0033] Despite Figure 1 , one first area OA is provided and the first area OA is approximately circular, but the present disclosure is not limited thereto. The number of first areas OA may be two or more, and the shape of each of the first areas OA may be circular, elliptical, polygonal, star-shaped, or diamond-shaped, and various modifications may be made.

[0034] Figure 2 is along Figure 1 A cross-sectional view showing a display device 1 according to an exemplary embodiment of the present disclosure, taken along line II-II′, Figure 3 is a cross-sectional view of a display device 1 according to an exemplary embodiment of the present disclosure.

[0035] Reference Figure 2 , the display device 1 may include a display panel 10, an input sensing layer 40, and an optical functional layer 50 disposed on the display panel 10. These layers may be covered by a window 60. The display device 1 may be one of various types of electronic devices such as a mobile phone, a notebook computer, and a smart watch.

[0036] The display panel 10 may display an image. The display panel 10 includes pixels arranged in the second area DA (ie, the display area). Each pixel may include a display element and a pixel circuit connected to the display element. The display element may include an organic light emitting diode, an inorganic light emitting diode, or a quantum dot light emitting diode.

[0037] The input sensing layer 40 obtains coordinate information corresponding to an external input (e.g., a touch event). The input sensing layer 40 may include a sensing electrode (or a touch electrode) and a signal line connected to the sensing electrode. The input sensing layer 40 may be arranged on the display panel 10. The input sensing layer 40 may sense an external input using a mutual capacitance method and / or a self capacitance method.

[0038] The input sensing layer 40 may be directly formed on the display panel 10, or may be separately formed and then bonded to the display panel 10 using an adhesive layer such as an optically clear adhesive (OCA). For example, the input sensing layer 40 may be formed after a process of forming the display panel 10. In this case, the adhesive layer may not be disposed between the input sensing layer 40 and the display panel 10. Although Figure 2 It is shown that the input sensing layer 40 is disposed between the display panel 10 and the optical functional layer 50 , but the input sensing layer 40 may alternatively be disposed on the optical functional layer 50 .

[0039] The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (e.g., external light) incident from the outside toward the display panel 10 through the window 60. The anti-reflection layer may include a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal retarder. The retarder may include a λ / 2 retarder (e.g., a half-wave plate) and / or a λ / 4 retarder (e.g., a quarter-wave plate). The polarizer may include a film-type polarizer or a liquid crystal polarizer. The film-type polarizer may include a stretchable synthetic resin film, and the liquid crystal polarizer may include liquid crystals arranged in a predetermined arrangement. Each of the retarder and the polarizer may also include a protective film. The retarder and the polarizer themselves or their protective films may be defined as a substrate layer of the anti-reflection layer.

[0040] In an exemplary embodiment of the present disclosure, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged by considering the color of the light emitted from the pixels of the display panel 10, respectively. In an exemplary embodiment of the present disclosure, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer respectively arranged in different layers. The first reflected light and the second reflected light respectively reflected by the first reflective layer and the second reflective layer may cause destructive interference, and thus the reflectivity of the external light may be reduced.

[0041] The optical function layer 50 may include a lens layer. The lens layer may increase the emission efficiency of light emitted from the display panel 10 or reduce the color deviation of the light. The lens layer may include a layer having a concave lens or a convex lens shape and / or may include a plurality of layers having different refractive indices, respectively. The optical function layer 50 may include both an anti-reflection layer and a lens layer, or may include one of the anti-reflection layer and the lens layer.

[0042] The display panel 10 , the input sensing layer 40 , and / or the optical function layer 50 may each include an opening. Figure 2The display panel 10, the input sensing layer 40, and the optical function layer 50 are shown to include a first opening 10H, a second opening 40H, and a third opening 50H, respectively, and their first opening 10H, second opening 40H, and third opening 50H overlap each other and correspond to each other to form a single opening. The first opening 10H, the second opening 40H, and the third opening 50H are positioned to correspond to the first area OA. According to an exemplary embodiment of the present disclosure, at least one of the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening. For example, one or two of the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening. Optionally, as Figure 3 As shown, the display panel 10 , the input sensing layer 40 and the optical function layer 50 do not include openings.

[0043] As described above, the first area OA may be a component area (eg, a sensor area, a camera area, a speaker area, etc.) in which the component 20 for adding various functions to the display device 1 is positioned. Figure 2 As shown, the component 20 can be located in the first opening 10H, the second opening 40H and the third opening 50H. Figure 3 As shown, the component 20 may be disposed below the display panel 10 .

[0044] Component 20 may include electronic components. For example, component 20 may include electronic components that utilize light and / or sound. For example, component 20 may be a sensor, such as an infrared sensor that emits and / or receives light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure distance or recognize fingerprints, a small lamp that outputs light, or a speaker that outputs sound. Electronic components that use light can use light of various bands, such as visible light, infrared light, and ultraviolet light. In an exemplary embodiment of the present disclosure, the first area OA may be understood as a transmission area, and light and / or sound output from component 20 to the outside or propagated from the outside toward the electronic component may pass through the transmission area.

[0045] According to an exemplary embodiment of the present disclosure, in the case where the display device 1 is used as a smart watch or an instrument panel for a car, the component 20 may be a member including a pointer of a clock or a pointer indicating predetermined information (e.g., the speed of a vehicle, etc.). In the case where the display device 1 includes a pointer of a clock or an instrument panel for a car, the component 20 may be exposed to the outside through the window 60, and the window 60 may include an opening corresponding to the first area OA.

[0046] As described above, the assembly 20 may include elements related to the functions of the display panel 10 or elements such as accessories that increase the aesthetics of the display panel 10. Figure 2 and Figure 3, but a layer including OCA or the like may be located between the window 60 and the optical functional layer 50 .

[0047] FIG. 4A to FIG. 4E is a cross-sectional view of a display panel 10 according to an exemplary embodiment of the present disclosure.

[0048] Reference FIG. 4A to FIG. 4E The display panel 10 includes a display element layer 200 (also referred to as a display layer) disposed on a substrate 100. The substrate 100 may include a glass material or a polymer resin. For example, the substrate 100 may include a SiO 2 A glass material as its main component, or a resin such as reinforced plastic may be included.

[0049] The display element layer 200 is arranged to correspond to the second area DA and includes a plurality of pixels. The display element layer 200 includes a pixel circuit corresponding to each pixel and a display element electrically connected to the pixel circuit. The pixel circuit may include a thin film transistor and a storage capacitor, and the display element may include an organic light emitting diode OLED.

[0050] The display panel 10 further includes an encapsulation substrate 340 facing the substrate 100 as an encapsulation member 300 (also referred to as a thin film encapsulation layer). A sealing material 350 is arranged between the substrate 100 and the encapsulation substrate 340. The sealing material 350 surrounds the display element layer 200 between the substrate 100 and the encapsulation substrate 340. For example, the sealing material 350 may surround a first edge (also referred to as an inner edge) of the display element layer 200 in the third area MA and surround a second edge (also referred to as an outer edge) of the display element 200 in the outer area PA. When viewed in a direction perpendicular to the main surface, the first area OA may be completely surrounded by the sealing material 350, and the second edge of the display element layer 200 may also be completely surrounded by the sealing material 350.

[0051] The display panel 10 may include a first opening 10H corresponding to the first area OA. Figure 4A 2 shows that the substrate 100 and the encapsulation substrate 340 include through holes 100H and 340H corresponding to the first area OA, respectively. The display element layer 200 may also include a through hole corresponding to the first area OA.

[0052] According to an exemplary embodiment of the present disclosure, Figure 4B As shown in FIG. 3 , the encapsulation substrate 340 may include a through hole 340H corresponding to the first area OA, but the substrate 100 may not include a through hole. The display element layer 200 may include a through hole corresponding to the first area OA.

[0053] In this case, if Figure 4CAs shown in , the auxiliary display element layer 200C may be located in the first area OA. The auxiliary display element layer 200C may include a display element having a structure different from that of the display element of the display element layer 200 and / or operating in a method different from that of the display element of the display element layer 200. According to an exemplary embodiment of the present disclosure, the display element layer 200 may include pixels each including an active (or referred to as an active) organic light emitting diode, and the auxiliary display element layer 200C may include pixels each including a passive (or referred to as a passive) organic light emitting diode. In the case where the auxiliary display element layer 200C includes a display element of an active organic light emitting diode, it is impossible to be an element constituting a pixel circuit under the relevant display element. For example, it is impossible to be a transistor or a storage capacitor arranged in each pixel below the auxiliary display element layer 200C in the pixel circuit.

[0054] According to an exemplary embodiment of the present disclosure, the auxiliary display element layer 200C may include the same type of display element as the display element layer 200 (e.g., an active organic light emitting diode), but the pixel circuit below the auxiliary display element layer 200C may be different. For example, the pixel circuit below the auxiliary display element layer 200C (e.g., a pixel circuit including a light blocking layer between a substrate and a transistor, etc.) may have a structure different from that of the pixel circuit below the display element layer 200. Optionally, the display element of the auxiliary display element layer 200C may operate in response to a control signal different from the control signal of the display element of the display element layer 200.

[0055] Components that do not require relatively high transmittance (eg, infrared sensors, etc.) may be disposed in the first area OA in which the auxiliary display element layer 200C is disposed. Figure 4C and Figure 5D , the display element layer 200A / 200 can be understood as a component area and an auxiliary display area. The display element layer 200A / 200 can be covered by a thin film encapsulation layer 300. The inorganic layer 520 can cover the thin film encapsulation layer 300. The inorganic layer 520 can extend farther in the third area MA than the thin film encapsulation layer 300. The inorganic layer 520 can also cover the auxiliary display element layer 200C in the first area OA. The encapsulation layer can be arranged between the auxiliary display element layer 200C and the inorganic layer 520, and the encapsulation layer covers the auxiliary display element layer 200C. The encapsulation layer on the auxiliary display element layer 200C can have a structure that is the same as or different from the structure of the thin film encapsulation layer 300 on the display element layer 200A / 200.

[0056] According to an exemplary embodiment of the present disclosure, Figure 4DAs shown in , each of the substrate 100 and the encapsulation substrate 340 may not include a through hole corresponding to the first area OA. The display element layer 200 may include a through hole corresponding to the first area OA. According to an exemplary embodiment of the present disclosure, Figure 4D The sealing material 350 arranged in the third area MA of the display panel 10 may be omitted. In addition, the display element layer 200 may not include a through hole corresponding to the first area OA. Since a relatively high transmittance component 20 is not required (see Figure 2 ) may be arranged in the first area OA, so the first area OA may be used as a transmission area for transmitting light used by the component 20. Even when the display element layer 200 does not include a through hole corresponding to the first area OA, the portion of the display element layer 200 corresponding to the first area OA may be formed by not including a pixel circuit PC (see Fig. 9 and Fig.10 ) elements (e.g., transistors, storage capacitors, wiring, etc.) to transmit light.

[0057] In this case, if Figure 4E As shown in FIG. 1 , the auxiliary display element layer 200C may be disposed in the first area OA. Figure 4C The auxiliary display element layer 200C has been described in detail, so repeated description of the auxiliary element 200C is omitted, and it can be assumed that those features that are not described in detail here are at least similar to the corresponding elements that have been described.

[0058] FIG. 5A to FIG. 5D is a cross-sectional view of a display panel 10 according to an exemplary embodiment of the present disclosure.

[0059] Reference Figure 5A The display panel 10 includes a display layer 200 disposed on a substrate 100. The substrate 100 may include a glass material or a polymer resin. The substrate 100 may be formed of multiple layers. For example, Figure 5A As shown in the enlarged view of FIG. 1 , the substrate 100 may include a first base layer 101 , a first barrier layer 102 , a second base layer 103 , and a second barrier layer 104 .

[0060] Each of the first base layer 101 and the second base layer 103 may include a polymer resin. For example, the first base layer 101 and the second base layer 103 may each include a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC) and / or cellulose acetate propionate (CAP). The polymer resin may be transparent.

[0061] Each of the first barrier layer 102 and the second barrier layer 104 may include a barrier layer configured to prevent penetration of external foreign matter, and may include a layer including a SiN x and / or SiO x A single layer or multiple layers of inorganic materials.

[0062] The display layer 200 includes a plurality of pixels. The display layer 200 may include: a display element layer 200A including a display element disposed in each pixel; a pixel circuit layer 200B including a pixel circuit disposed in each pixel and an insulating layer. Each pixel circuit may include a thin film transistor and a storage capacitor. Each display element may include an organic light emitting diode OLED.

[0063] The display element of the display layer 200 may be covered by an encapsulation member such as a thin film encapsulation layer 300. The inorganic layer 520 is disposed on the thin film encapsulation layer 300. The inorganic layer 520 may cover an end portion of the thin film encapsulation layer 300 in the third area MA. The inorganic layer 520 may extend farther toward the first area OA than an end portion of the thin film encapsulation layer 300 in the third area MA, and may contact a layer disposed below an end portion of the thin film encapsulation layer 300. The inorganic layer 520 may include an inorganic insulating material, which may include, for example, silicon nitride, silicon oxide, and silicon oxynitride.

[0064] In the case where the display panel 10 includes a substrate 100 and a thin film encapsulation layer 300 (both of which are multi-layers), the flexibility of the display panel 10 can be increased. The display panel 10 may include a first opening 10H passing through the display panel 10. The first opening 10H may be disposed in the first area OA. In this case, the first area OA may be a kind of opening area.

[0065] exist Figure 5A 1 shows that the substrate 100, the thin film encapsulation layer 300, and the inorganic layer 520 include through holes 100H, 300H, and 520H, respectively, each of which corresponds to the first opening 10H. The display layer 200 may include a through hole 200H corresponding to the first area OA.

[0066] According to an exemplary embodiment of the present disclosure, Figure 5B As shown in , the substrate 100 may not include a through hole corresponding to the first area OA. The display element layer 200A may not be disposed in the first area OA, and the pixel circuit layer 200B may be disposed in the first area OA. The thin film encapsulation layer 300 may include a through hole 300H corresponding to the first area OA. Figure 5B As shown in FIG. 5 , the inorganic layer 520 may include a through hole 520H corresponding to the first area OA, or as shown in FIG. Figure 5C As shown in FIG. 5 , the inorganic layer 520 may cover the first area OA without including a through hole.

[0067] Despite FIG. 5A to FIG. 5C , the display element layer 200A is not disposed in the first area OA, but the present disclosure is not limited thereto. According to an exemplary embodiment of the present disclosure, Figure 5D As shown in FIG. 1 , the auxiliary display element layer 200C may be disposed in the first area OA. Figure 4C The auxiliary display element layer 200C is described in detail, so repeated description of the auxiliary display element layer 200C is omitted, and it can be assumed that those features not described in detail here are at least similar to corresponding elements that have been described.

[0068] Figure 6 is a plan view of a display panel 10 according to an exemplary embodiment of the present disclosure, Figure 7 is an equivalent circuit diagram illustrating one of the pixels of the display panel 10 according to an exemplary embodiment of the present disclosure.

[0069] Reference Figure 6 , the display panel 10 may include a second area DA, a first area OA, a third area MA, and an outer area PA. Figure 6 It may be understood as a diagram of the substrate 100 of the display panel 10. For example, the substrate 100 may be understood as including a second area DA, a first area OA, a third area MA, and an outer area PA.

[0070] The display panel 10 includes a plurality of pixels P disposed in the second area DA. Figure 7 As shown in FIG. 1 , each pixel P includes a pixel circuit PC and an organic light emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red light, green light, or blue light through the organic light emitting diode OLED, or emit red light, green light, blue light, or white light.

[0071] The second thin film transistor T2 is a switching thin film transistor and is connected to the scan line SL and the data line DL, and may transmit a data voltage input from the data line DL to the first thin film transistor T1 in response to a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage transmitted from the second thin film transistor T2 and a first power supply voltage ELVDD supplied from the driving voltage line PL.

[0072] The first thin film transistor T1 is a driving thin film transistor and can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL through the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a predetermined brightness by using the driving current. The counter electrode (e.g., cathode) of the organic light emitting diode OLED can receive the second power supply voltage ELVSS.

[0073] Despite Figure 7 2 shows that the pixel circuit PC includes two thin film transistors and one storage capacitor, but the present disclosure is not limited thereto. The number of thin film transistors and the number of storage capacitors may be variously modified according to the design of the pixel circuit PC.

[0074] Refer again Figure 6 , the third area MA may surround the first area OA. The third area MA is an area in which a display element such as an organic light emitting diode OLED is not disposed. A signal line configured to provide a signal to pixels P disposed around the first area OA may cross the third area MA. A scan driver 1100 configured to provide a scan signal to each pixel P, a data driver 1200 configured to provide a data signal to each pixel P, a main power wiring configured to provide a first power supply voltage and a second power supply voltage, etc. may be disposed in the outer area PA. Although in Figure 6 The data driver 1200 is shown to be adjacent to one side of the substrate 100, but according to an exemplary embodiment of the present disclosure, the data driver 1200 can be set on a flexible printed circuit board (FPCB) which is electrically connected to a pad (or "pad") set on one side of the display panel 10.

[0075] Figure 8 is a plan view showing elements provided in the first area OA and the middle area of ​​the display panel 10 according to an exemplary embodiment of the present disclosure, Fig. 9 is along Figure 8 A cross-sectional view taken along line IX-IX', Fig.10 yes Fig. 9 FIG. 1 is an enlarged cross-sectional view of a region of the display panel 10 .

[0076] Reference Figure 8 and Fig. 9 According to an exemplary embodiment of the present disclosure, the display panel 10 includes a first area OA, a second area DA surrounding the first area OA, and a third area MA between the first area OA and the second area DA, all of which correspond to one side of the substrate.

[0077] In this case, assuming that the edge of the first area OA is the first line E1 and the boundary between the second area DA and the third area MA is the third line E3, the third area MA can be defined as a region having a ring shape using the first line E1 and the third line E3 as the inner edge and the outer edge, respectively. In addition, the third area MA can be divided into two areas around the second line E2. The area of ​​the two areas adjacent to the first area OA is defined as the 3-1 area MA1, and the area of ​​the two areas adjacent to the second area DA is defined as the 3-2 area MA2.

[0078] The pixels P are disposed around the first area OA. The pixels P may be spaced apart from each other around the first area OA. In a plan view, the pixels P may be disposed up and down around the first area OA, and the pixels P may be disposed left and right around the first area OA.

[0079] Some lines that apply various signals and voltages to the pixels P are disposed in the 3-2nd area MA2 as a ring-shaped area using the second line E2 and the third line E3 as inner and outer edges, respectively.

[0080] For example, the signal lines of the lines adjacent to the first area OA may be arranged around the first area OA. Some data lines DL crossing the second area DA may extend in the y direction to provide data signals to pixels P respectively arranged up and down with the first area OA interposed therebetween, and detour along the first line E1 which is the edge of the first area OA in the 3-2 area MA2. Some scan lines SL crossing the second area DA may extend in the x direction to provide scan signals to pixels P respectively arranged left and right with the first area OA interposed therebetween, and detour along the first line E1 which is the edge of the first area OA in the 3-2 area MA2.

[0081] Meanwhile, one or more grooves G are provided in the 3-1st area MA1 as a ring-shaped area using the first line E1 and the second line E2 as inner and outer edges, respectively. In this case, the grooves G may be separated from each other. Figure 8 It is shown that three grooves G are provided in the 3-1th area MA1, but one, two, or four or more grooves G may be provided in the 3-1th area MA1.

[0082] Since the groove G is disposed in the 3-1th region MA1, the groove G may be more adjacent to the first region OA than portions of the data line DL and / or the scan line SL detoured along the first line E1 which is an edge of the first region OA.

[0083] In a plan view, the groove G may have a ring shape completely surrounding the first area OA in the 3-1 area MA1. In a plan view, the radius of each groove G from the center O of the first area OA may be greater than the radius of the first area OA. For example, assuming that the radius of the first area OA is the first radius R1 and the outer diameter of the 3-1 area MA1 is the second radius R2, the radius of each groove G may be greater than the first radius R1 and smaller than the second radius R2.

[0084] According to an exemplary embodiment of the present disclosure, Fig. 9 As shown in , the first area OA of the display panel 10 may be an area including the first opening 10H, and the groove G may be spaced apart from the first opening 10H and may have a concave shape in the z direction, which is a thickness direction of the substrate 100 .

[0085] Reference Fig. 9 , the display panel 10 includes a first area OA as an opening area, a second area DA as a display area, and a third area MA as a non-display area between the first area OA and the second area OA.

[0086] For example, the pixel circuit PC on the substrate 100 , the pixel electrode 221 connected to the pixel circuit PC, and the intermediate layer 222 and the counter electrode 223 sequentially stacked on the pixel electrode 221 are disposed in the second pixel area DA as a display area.

[0087] The substrate 100 may be a multi-layered layer. For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104 that are sequentially stacked.

[0088] Each of the first base layer 101 and the second base layer 103 may include a polymer resin. For example, the first base layer 101 and the second base layer 103 may each include a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC) and / or cellulose acetate propionate (CAP). The polymer resin may be transparent.

[0089] Each of the first barrier layer 102 and the second barrier layer 104 may include a barrier layer configured to prevent penetration of external foreign matter, and may include a layer including a SiN x and / or SiO x A single layer or multiple layers of inorganic materials.

[0090] The pixel circuit PC is disposed on the substrate 100 and includes a thin film transistor and a storage capacitor. The organic light emitting diode OLED including the pixel electrode 221, the emission layer of the intermediate layer 222 and the counter electrode 223 emits predetermined light and is covered by the thin film encapsulation layer 300. Fig.10 Elements disposed in the second area DA are described in detail.

[0091] Reference Fig.10 , the pixel circuit PC and the organic light emitting diode OLED electrically connected to the pixel circuit PC may be disposed in the second area DA as a display area.

[0092] A thin film transistor TFT, a storage capacitor Cst, and a pixel electrode 221 electrically connected to the thin film transistor TFT and the storage capacitor Cst are formed, and the thin film transistor TFT and the storage capacitor Cst are disposed over the substrate 100. The pixel circuit PC may be disposed on the substrate 100, and the organic light emitting diode OLED may be disposed on the pixel circuit PC.

[0093] The substrate 100 may include a polymer resin or glass. According to an exemplary embodiment of the present disclosure, the substrate 100 may include a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC) and / or cellulose acetate propionate (CAP). The substrate 100 may be flexible. The substrate 100 may include a layer containing SiO 2 The glass material as the main component may include a resin such as reinforced plastic and may be rigid. The substrate 100 may have a stacked structure including a layer including the above-mentioned polymer resin and a barrier layer disposed on the layer. In this case, the flexibility of the substrate 100 may be improved. The barrier layer may include silicon nitride (SiN x ), silicon oxynitride (SiON) and silicon oxide (SiO x ) at least one of.

[0094] The buffer layer 201 configured to prevent impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT may be disposed on the substrate 100. The buffer layer 201 may include silicon nitride (SiN x ), silicon oxynitride (SiON) and silicon oxide (SiO x ) and may include a single layer or multiple layers containing the above-mentioned inorganic insulating material.

[0095] The pixel circuit PC may be disposed on the buffer layer 201. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Fig.10 The thin film transistor TFT shown in FIG. Figure 7 Although the present embodiment shows a top-gate thin film transistor in which the gate electrode GE is disposed above the semiconductor layer Act and the gate insulating layer 203 is between the semiconductor layer Act and the gate electrode GE, according to an exemplary embodiment of the present disclosure, the thin film transistor TFT may be a bottom-gate thin film transistor.

[0096] The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including at least one of Mo, Al, Cu, and Ti, and may include a single layer or multiple layers including the above materials.

[0097] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The gate insulating layer 203 may include a single layer or multiple layers including the above materials.

[0098] The source electrode SE and the drain electrode DE may include a material having excellent electrical conductivity. The source electrode SE and the drain electrode DE may include a conductive material including at least one of Mo, Al, Cu, and Ti, and may include a single layer or a multilayer including the above materials. According to an exemplary embodiment of the present disclosure, the source electrode SE and the drain electrode DE may include a multilayer of Ti / Al / Ti. As used herein, the phrase "excellent electrical conductivity" may refer to any material having a conductivity within the range of the conductivity set by the above conductive material.

[0099] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 which are overlapped with each other with the first interlayer insulating layer 205 therebetween. The storage capacitor Cst may overlap with the thin film transistor TFT. Fig.10 2 shows that the gate electrode GE of the thin film transistor TFT is used as the lower electrode CE1 of the storage capacitor Cst. According to an exemplary embodiment of the present disclosure, the storage capacitor Cst may not overlap with the thin film transistor TFT. The storage capacitor Cst may be covered by the second interlayer insulating layer 207.

[0100] The first and second interlayer insulating layers 205 and 207 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The first and second interlayer insulating layers 205 and 207 may include a single layer or multiple layers including the above materials.

[0101] The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered by the planarization insulating layer 209. The planarization insulating layer 209 may include an approximately flat top surface. The planarization insulating layer 209 may include an organic insulating material, which includes a general polymer such as polymethyl methacrylate (PMMA) and polystyrene (PS), a polymer derivative with a phenolic group, an acryl polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a mixture thereof. According to an exemplary embodiment of the present disclosure, the planarization insulating layer 209 may include polyimide. Alternatively, the planarization insulating layer 209 may include an inorganic insulating material or include an inorganic insulating material and an organic insulating material.

[0102] The pixel electrode 221 may be formed on the planarization insulating layer 209. The pixel electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). According to an exemplary embodiment of the present disclosure, the pixel electrode 221 may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and / or compounds thereof. According to an exemplary embodiment of the present disclosure, the pixel electrode 221 may also include a reflective layer including ITO, IZO, ZnO or In on / under the reflective layer. 2 O 3 layer.

[0103] The pixel defining layer 211 may be formed on the pixel electrode 221. The pixel defining layer 211 may include an opening exposing the top surface of the pixel electrode 221 and may cover the edge of the pixel electrode 221. Alternatively, the pixel defining layer 211 may include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxynitride (SiON) and silicon oxide (SiO x ). Optionally, the pixel defining layer 211 may include an organic insulating material and an inorganic insulating material.

[0104] The intermediate layer 222 includes an emission layer 222b. The intermediate layer 222 may include a first functional layer 222a disposed under the emission layer 222b and / or a second functional layer 222c disposed on the emission layer 222b. The emission layer 222b may include a low molecular weight organic material or a polymer organic material that emits light of a predetermined color.

[0105] The first functional layer 222a may include an organic layer. The first functional layer 222a may include a single layer or multiple layers. For example, in the case where the first functional layer 222a includes a polymer material, the first functional layer 222a includes a hole transport layer (HTL) having a single layer structure, and may include poly-(3,4)-ethylene-dihydroxythiophene (PEDOT) or polyaniline (PANI). In the case where the first functional layer 222a includes a low molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and the HTL.

[0106] The second functional layer 222c may be omitted. For example, in the case where the first functional layer 222a and the emission layer 222b include a polymer material, it is preferred to provide the second functional layer 222c. The second functional layer 222c may include a single layer or multiple layers. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0107] The emission layer 222 b of the intermediate layer 222 may be disposed in each pixel in the display area DA. The emission layer 222 b may contact at least a portion of the top surface of the pixel electrode 221 exposed through the opening of the pixel defining layer 211 .

[0108] The counter electrode 223 may include a conductive material having a low work function. For example, the counter electrode 223 may include a transparent layer or a semi-transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. Optionally, the counter electrode 223 may also include a conductive material including ITO, IZO, ZnO, or In on the transparent / semi-transparent layer including the above materials. 2 O 3 The counter electrode 223 may be disposed not only in the second area DA but also in the third area MA. The intermediate layer 222 and the counter electrode 223 may be formed by a thermal deposition method.

[0109] The capping layer 230 may be disposed on the counter electrode 223. For example, the capping layer 230 may include LiF and may be formed by a thermal deposition method. Alternatively, the capping layer 230 may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. Alternatively, the capping layer 230 may be omitted.

[0110] The spacer 213 may be disposed on the pixel defining layer 211. The spacer 213 may include an organic insulating material such as polyimide. Alternatively, the spacer 213 may include an inorganic insulating material such as silicon nitride or silicon oxide, or may include an organic insulating material and an inorganic insulating material.

[0111] The spacer 213 may include a material different from that of the pixel defining layer 211. Alternatively, the spacer 213 may include the same material as that of the pixel defining layer 211. In this case, the pixel defining layer 211 and the spacer 213 may be simultaneously formed during a mask process using a half-tone mask or the like. According to an exemplary embodiment of the present disclosure, the pixel defining layer 211 and the spacer 213 may include polyimide.

[0112] The organic light emitting diode OLED is covered by a thin film encapsulation layer 300. The thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Figure 7 3 shows that the thin film encapsulation layer 300 includes first and second inorganic encapsulation layers 310 and 330 and an organic encapsulation layer 320 between the first and second inorganic encapsulation layers 310 and 330. According to an exemplary embodiment of the present disclosure, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and a stacking order may be modified.

[0113] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each include one or more inorganic insulating materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, or silicon oxynitride, and may be formed by chemical vapor deposition (CVD). The organic encapsulation layer 320 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide, and polyethylene.

[0114] The input sensing layer 40 may be disposed on the display panel 10. Fig.10 , it is shown that the input sensing layer 40 is directly formed on the display panel 10 and contacts the thin film encapsulation layer 300 .

[0115] Refer again Fig. 9 The third area MA as a non-display area of ​​the display panel 10 may include a 3-1 area MA1 adjacent to the first area OA or the first opening 10H and a 3-2 area MA2 adjacent to the second area DA, the first area OA being an opening area and the second area DA being a related display area.

[0116] The 3-2 area MA2 may be a signal line (for example, see Figure 8 The area where the data line DL) described above crosses. Fig. 9The data line DL shown in FIG. 5 may correspond to the data line that is routed around the first area OA. The 3-2 area MA2 may be a wiring area or a detour area through which the data line DL traverses.

[0117] like Fig. 9 As shown in , the data lines DL may be alternately arranged and an insulating layer may be arranged between the data lines DL. Alternatively, the data lines DL may be arranged on the same insulating layer (e.g., the second interlayer insulating layer 207). In the case where adjacent data lines DL are arranged above and below, respectively, and an insulating layer (e.g., the second interlayer insulating layer 207) is located therebetween, the gap (spacing) between the adjacent data lines DL may be reduced, and thus the width of the third area MA may be reduced.

[0118] In addition, refer to Figure 8 The scan line SL described as being arranged around the first area OA may also be disposed in the 3-2 area MA2. The scan line SL may be disposed on a layer different from the layer on which the data line DL is disposed. For example, the scan line SL may be disposed on a layer lower than the layer on which the data line DL is disposed.

[0119] The first electrode layer 221M is disposed over the detour portions of the data lines DL and the scan lines SL disposed in the 3-2 area MA2. In this case, the first electrode layer 221M covers the detour portions of the lines DL and SL. At least one insulating layer 205, 207, and 209 may be disposed between the first electrode layer 221M and the lines DL and SL.

[0120] Refer again Figure 8 , the first electrode layer 221M may correspond to the entire 3-2 area MA2. In this case, the first electrode layer 221M may define the 3-2 area MA2. For example, the area of ​​the substrate 100 in which the first electrode layer 221M is disposed may be defined as the 3-2 area MA2.

[0121] According to an exemplary embodiment of the present disclosure, the first electrode layer 221M may include a hole corresponding to the first area OA, and the hole may be larger than the first radius R1. For example, the first electrode layer 221M may be a ring-shaped pattern whose inner and outer edges correspond to the second and third lines E2 and E3, respectively.

[0122] Therefore, the first electrode layer 221M may cover the detour portions of the lines DL and SL disposed in the 3-2 area MA2 , and may not cover the groove G disposed in the 3-1 area MA1 .

[0123] Refer again Figure 8 and Fig. 9, the first insulating layer 211PR is disposed on the first electrode layer 221M. In this case, the first insulating layer 211PR may cover edges of the first electrode layer 221M corresponding to the second line E2 and the third line E3.

[0124] The first insulating layer 211PR includes an opening that exposes at least a portion of the first electrode layer 221M. The opening may have a planar shape or an island shape. In the former case, the first insulating layer 211PR may include a plurality of protrusions spaced apart from each other.

[0125] The second electrode layer 223M is disposed on the first electrode layer 221M. For example, the second electrode layer 223M contacts a portion of the first electrode layer 221M exposed by the opening.

[0126] A constant voltage may be applied to the second electrode layer 223M. Therefore, since the second electrode layer 223M and the first electrode layer 221M in contact with the second electrode layer 223M float at the same potential, the lines DL and SL disposed under the first electrode layer 221M may be shielded.

[0127] According to an exemplary embodiment of the present disclosure, the first electrode layer 221M may include the same material as that of the pixel electrode 221 included in the pixel circuit PC. In addition, the first electrode layer 221M may be disposed on the same layer on which the pixel electrode 221 is disposed.

[0128] According to an exemplary embodiment of the present disclosure, the second electrode layer 223M may include the same material as that of the counter electrode 223 included in the pixel circuit PC. In addition, the second electrode layer 223M may be disposed on the same layer on which the counter electrode 223 is disposed, and may be a part of the counter electrode 223.

[0129] According to an exemplary embodiment of the present disclosure, the first insulating layer 211PR may include the same material as that of the pixel defining layer 211 included in the pixel circuit PC. In addition, the first insulating layer 211PR may be disposed on the same layer on which the pixel defining layer 211 is disposed.

[0130] The 3-1 area MA1 is a groove area in which grooves are provided. Figure 8 and Fig. 9 It is shown in FIG. 2 that three grooves G are provided in the 3-1th area MA1 , but the number of the grooves G may be variously modified as described above.

[0131] Each groove G may be formed as a multilayer including a first layer and a second layer including different materials, respectively. Fig. 9 , it is shown that a groove G is formed in a sub-layer disposed in the substrate 100 .

[0132] The groove G may be formed by removing a portion of the second barrier layer 104 and a portion of the second base layer 103. In this case, the groove G may be formed before the process of forming the intermediate layer 222.

[0133] According to an exemplary embodiment of the present disclosure, a portion of the intermediate layer 222 (eg, the first functional layer 222a and / or the second functional layer 222c (see FIG. 21 ) extending to the third area MA Fig.10 )) may be disconnected around the groove G. Therefore, external moisture having penetrated through the first opening 10H may be prevented from traveling to the organic light emitting diode OLED of the second area DA as a display area through the organic encapsulation layer 320 .

[0134] In the first functional layer 222a and the second functional layer 222c (see Fig.10 ) is disconnected around the groove G, and the emission layer 222b (see Fig.10 ) is different, it can be used not only in Fig. 9 The first functional layer 222a and the second functional layer 222c exist in the second area DA as the display area (see Fig.10 ) Furthermore, the first functional layer 222a and the second functional layer 222c may exist in the third area MA which is a non-display area.

[0135] According to an exemplary embodiment of the present disclosure, the first functional layer 222a and the second functional layer 222c (see Fig.10 ) may be removed from the third area MA as a non-display area, or the first and second functional layers 222a and 222c may be originally disposed exclusively in the second area DA as a display area. In this case, the groove G configured to prevent moisture penetration may be omitted.

[0136] In the following, reference is made to Fig.11A and Fig. 11B The first functional layer 222a and the second functional layer 222c are described in more detail (see Fig.10 ) in the third region MA and the first functional layer 222a and the second functional layer 222c (see Fig.10 ) is not in the third area MA.

[0137] Fig.11A and Fig. 11B yes Fig. 9 An enlarged cross-sectional view of region XI.

[0138] first, Fig.11A As shown in the middle layer 222 (see Fig. 9 ) a portion of the first functional layer 222a and the second functional layer 222c are not in the third area MA.

[0139] Reference Fig.11A The first electrode layer 221M is disposed on a portion of the line disposed in the third area MA (eg, a detour portion of the data line DL (see Figure 8 In this case, the first insulating layer 211PR having the opening 211OP exposing a portion of the first electrode layer 221M may be disposed on the first electrode layer 221M, and the second electrode layer 223M may be disposed on the first insulating layer 211PR.

[0140] In this case, since the second electrode layer 223M (disposed thereon) Fig. 9 The counter electrode 223 is disposed on the same layer as the first electrode layer 221M (disposed on which the Fig. 9 There is no intermediate layer such as the first functional layer 222a and the second functional layer 222c between the pixel electrodes 221 (on the same layer of the pixel electrodes 221), so the second electrode layer 223M can directly contact the first electrode layer 221M.

[0141] Next, Fig. 11B It is shown that there is an intermediate layer 222 (see Fig. 9 ) of a portion of the first functional layer 222a and the second functional layer 222c.

[0142] Reference Fig. 11B ,and Fig.11A Similarly, the first electrode layer 221M is disposed on a portion of the line disposed in the third area MA (eg, a detour portion of the data line DL (see FIG. Figure 8 In this case, a first insulating layer 211PR having an opening 211OP exposing a portion of the first electrode layer 221M may be disposed on the first electrode layer 221M.

[0143] At the same time, Fig.11A Different, as the middle layer 222 (see Fig. 9 ) of a portion of the first functional layer 222a and the second functional layer 222c are disposed on the first insulating layer 211PR, and the second electrode layer 223M may be disposed on the first functional layer 222a and the second functional layer 222c.

[0144] In this case, since there are intervening layers such as the first functional layer 222 a and the second functional layer 222 c between the second electrode layer 223M and the first electrode layer 221M, the second electrode layer 223M cannot directly contact the first electrode layer 221M.

[0145] Therefore, after selectively removing portions of the first functional layer 222a and the second functional layer 222c by using a laser beam or the like and exposing a portion of the first electrode layer 221M to the outside within the opening 211OP of the first insulating layer 211PR, the second electrode layer 223M can be enabled to directly contact the first electrode layer 221M.

[0146] In the following, reference is made to FIG. 12A to FIG. 14B The planar structures of the display panels 10A, 10B, and 10C including the first electrode layer 221M, the first insulating layer 211PR, and the second electrode layer 223M are described in more detail.

[0147] Fig. 12A yes Figure 8 An enlarged plan view of an example of a region W, Fig. 12B is along Fig. 12A A cross-sectional view taken along line AA'.

[0148] Reference Fig. 12A and Fig. 12B , the first electrode layer 221M may include a plurality of holes 221H. Since the planarization insulating layer 209 as an organic insulating layer is disposed below the first electrode layer 221M, a vent hole is formed in the first electrode layer 221M as a layer disposed on the planarization insulating layer 209 to perform exhaust of the planarization insulating layer 209.

[0149] However, since the cross section of the first electrode layer 221M is exposed to the outside through the plurality of holes 221H of the first electrode layer 221M, a metal such as Ag may be precipitated on the first electrode layer 221M during the process. Therefore, the plurality of holes 221H may be covered by the first insulating layer 211PR so that the cross section of the first electrode layer 221M is not exposed.

[0150] The plurality of holes 221H of the first electrode layer 221M may be spaced apart from each other, and thus the first insulating layer 211PR covering each of the plurality of holes 221H may further include protrusions spaced apart from each other.

[0151] According to an exemplary embodiment of the present disclosure, the plurality of holes 221H may be arranged alternately. Here, the alternate arrangement means that when the plurality of holes 221H include a first hole arranged in a row, a second hole arranged in another row, and a third hole adjacent to the first hole and the second hole and arranged in a row different from the above row, the third hole is arranged between the first hole and the second hole.

[0152] In addition, the edge of the first electrode layer 221M corresponding to the second line E2 and the third line E3 may be a portion through which the cross section of the first electrode layer 221M is exposed. Therefore, the edge of the first electrode layer 221M may be covered by a cover member 211E including the same material as the first insulating layer 211PR.

[0153] Unlike the first electrode layer 221M including the protrusion, the cover member 211E may have a longitudinally extending strip shape, so that the edge of the cover member 211E facing the first area OA is disposed closer to the first area OA than the second line E2 corresponding to the edge of the first electrode layer 221M. Similarly, the edge of the cover member 211E facing the second area DA is closer to the second area DA than the third line E3 corresponding to the edge of the first electrode layer 221M.

[0154] Meanwhile, in order to cover each of the plurality of holes 221H of the first electrode layer 221M, the first insulating layer 211PR may include Fig. 12B The plurality of protrusions shown in FIG. 2 respectively correspond to the plurality of holes 221H.

[0155] According to an exemplary embodiment of the present disclosure, a cross-section of the protrusions of the first insulating layer 211PR respectively covering the plurality of holes 221H may have the same shape as that of the plurality of holes 221H.

[0156] At the same time, despite Fig. 12A 2 shows that the plurality of holes 221H are quadrangular holes, but the shapes of the plurality of holes 221H may be a circular shape, an elliptical shape, or a triangular shape, and may be variously modified.

[0157] The second electrode layer 223M is disposed on the protrusion and contacts a portion of the first electrode layer 221M not covered by the protrusion. Therefore, the first electrode layer 221M may have the same voltage level as that of the second electrode layer 223M and may shield the data line DL, etc. disposed under the first electrode layer 221M.

[0158] Fig.13A yes Figure 8 An enlarged plan view of an example of a region W, Fig. 13B is along Fig.13A A cross-sectional view taken along line BB'.

[0159] In the following, the main description and reference Fig. 12A and Fig. 12B The arrangements described differ and it may be assumed that features not now discussed may be at least similar to corresponding features already described.

[0160] Reference Fig.13A and Fig. 13B, the first insulating layers 211PR-1 and 211PR-2 may cover at least two adjacent holes 221H as a group among the plurality of holes 221H of the first electrode layer 221M.

[0161] In this case, the first insulating layers 211PR-1 and 211PR-2 may include protrusions spaced apart from each other, but the protrusions may be larger than Fig. 12A and Fig. 12B The protrusion shown is large.

[0162] Since the first insulating layers 211PR-1 and 211PR-2 cover at least two holes 221H and include protrusions spaced apart from each other, Fig. 13B As shown in FIG. 2 , a contact area or a contact frequency between the second electrode layer 223M and the first electrode layer 221M may be reduced, but a time taken for a process of covering the plurality of holes 221H by using the first insulating layers 211PR- 1 and 211PR- 2 may be reduced.

[0163] Fig.14A yes Figure 8 An enlarged plan view of an example of a region W, Fig. 14B is along Fig.14A A cross-sectional view taken along line CC'.

[0164] In the following, the main description and reference Fig. 12A and Fig. 12B The arrangements described differ and it may be assumed that features not now discussed may be at least similar to corresponding features already described.

[0165] Reference Fig.14A and Fig. 14B , the first insulating layer 211PR may include a plurality of protrusions respectively covering the plurality of holes 221H of the first electrode layer 221M.

[0166] However, the cross-section of the protrusion of the first insulating layer 211PR may have a shape different from that of the plurality of holes 221H. According to an exemplary embodiment of the present disclosure, the plurality of holes 221H may be quadrangular holes, but the cross-section of the protrusion may be circular.

[0167] Since the first insulating layer 211PR includes the protrusion having a shape different from that of the plurality of holes 221H as described above, Fig.14A As shown in , an overlapping area between the protrusion of the first insulating layer 211PR and the hole 221H of the first electrode layer 221M is reduced, and a contact area between the second electrode layer 223M and the first electrode layer 221M may be increased.

[0168] As described above, the display panel according to the exemplary embodiments of the present disclosure can easily shield the wiring around the first area corresponding to the electronic element such as a sensor or a camera, and can simplify the arrangement of the wiring.

[0169] However, the scope of the present disclosure is not limited to this effect.

[0170] Although the disclosure has been described with reference to the exemplary embodiments of the present disclosure shown in the drawings, this is provided by way of example only, and those skilled in the art will understand that various changes in form and details may be made herein without departing from the spirit and scope of the disclosure as defined by the claims and their equivalents.

Claims

1. A display panel, comprising: A substrate comprising a first region, a second region at least partially surrounding the first region, and a third region disposed between the first region and the second region; A plurality of display elements are arranged in the second area; a plurality of wirings arranged in the third region around an edge of the first region; a first electrode layer covering at least a portion of the plurality of wirings; as well as a second electrode layer disposed above the first electrode layer and contacting at least a portion of the first electrode layer, The first area is inside the second area.

2. The display panel according to claim 1, further comprising: a first insulating layer disposed between the first electrode layer and the second electrode layer and including an opening exposing at least a portion of the first electrode layer, The second electrode layer contacts the first electrode layer through the opening of the first insulating layer.

3. The display panel according to claim 2, wherein: The first electrode layer includes a plurality of holes spaced apart from each other.

4. The display panel according to claim 3, further comprising: A plurality of protrusions respectively cover the plurality of holes and are spaced apart from each other.

5. The display panel according to claim 4, wherein: The plurality of protrusions include a same material as the first insulating layer.

6. The display panel according to claim 1, wherein: The first electrode layer includes a hole corresponding to the first region.

7. The display panel according to claim 1, wherein: The first electrode layer has a constant voltage.

8. The display panel according to claim 1, wherein: Each of the plurality of display elements includes a pixel electrode, a counter electrode, and an emission layer disposed between the pixel electrode and the counter electrode.

9. The display panel according to claim 8, wherein: The first electrode layer includes the same material as that of the pixel electrode.

10. The display panel according to claim 8, wherein: The first electrode layer and the pixel electrode are arranged on the same layer.

11. The display panel according to claim 10, further comprising: The second insulating layer is disposed under both the first electrode layer and the pixel electrode and includes an organic insulating material.

12. The display panel according to claim 8, wherein: The second electrode layer includes the same material as the counter electrode.

13. The display panel according to claim 1, wherein: The plurality of wirings include: a plurality of data lines extending in a first direction and configured to apply data signals to the plurality of display elements; and A plurality of scan lines extend along a second direction intersecting the first direction and are configured to apply scan signals to the plurality of display elements.

14. A display panel, comprising: A substrate comprising a first region, a second region at least partially surrounding the first region, and a third region disposed between the first region and the second region; A plurality of display elements are arranged in the second region and include a pixel electrode, a counter electrode and an emission layer arranged between the pixel electrode and the counter electrode; a plurality of wirings arranged in the third region around an edge of the first region; at least one groove disposed in the third region; a first electrode layer covering at least a portion of the plurality of wirings; as well as The second electrode layer is disposed above the first electrode layer and contacts at least a portion of the first electrode layer.

15. The display panel according to claim 14, wherein: The at least one groove is closer to the first region than the plurality of wirings.

16. The display panel according to claim 14, wherein: The at least one groove is disposed between the first region and a first edge of the first electrode layer, and the first edge is adjacent to the first region.

17. The display panel according to claim 14, wherein: The first electrode layer has the same voltage level as the counter electrode.

18. The display panel according to claim 14, wherein: The first electrode layer includes the same material as the pixel electrode, and The second electrode layer includes the same material as the counter electrode.

19. The display panel according to claim 14, further comprising: an organic insulating layer, disposed below the first electrode layer, Wherein, the first electrode layer includes a plurality of holes.

20. The display panel according to claim 19, further comprising: A plurality of protrusions respectively cover the plurality of holes.

21. The display panel according to claim 14, further comprising: The encapsulation layer covers the plurality of display elements and includes an inorganic encapsulation layer and an organic encapsulation layer.

Images