Semiconductor device and method for manufacturing semiconductor device

Abstract

In one example, a semiconductor package includes a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a housing surrounding the periphery of the cover, and an encapsulation between the cover and the housing and the substrate.

Description

Technical Field

[0001] The present invention relates generally to electronic devices, and more particularly to semiconductor devices and methods of fabricating semiconductor devices. Background Art

[0002] Previous semiconductor packages and methods of forming semiconductor packages are inadequate, for example, resulting in excessive cost, reduced reliability, relatively low performance, or excessive package size. Other limitations and disadvantages of conventional and traditional methods will be apparent to those skilled in the art by comparing such methods with the present invention and referring to the drawings. Summary of the invention

[0003] In a first example, a semiconductor package includes a substrate having a top surface and a bottom surface; an electronic device on the top surface of the substrate and connected to one or more interconnects on the bottom surface of the substrate; a cover above the electronic device; a housing surrounding the periphery of the cover; and an encapsulation between the cover and the substrate and between the housing and the substrate.

[0004] In a first example, the cap is over a majority of the substrate.

[0005] In a first example, the cover has four sides and the housing covers all four sides.

[0006] In a first example, the cover has four sides and the housing covers nearly all four sides.

[0007] In a first example, a surface of the encapsulation is coplanar with a surface of the substrate and one or more surfaces of the housing.

[0008] The first example further includes an adhesive material between the cover and the electronic device.

[0009] The first example further includes a thermal interface material between the cover and the electronic device.

[0010] In a first example, the cover includes a substantially planar heat radiating member.

[0011] In a first example, the cover comprises a thermally conductive metal.

[0012] In a first example, a top surface of the cover is coplanar with a top surface of the housing, wherein the top surface of the cover is exposed.

[0013] In a first example, the housing is above the cover, wherein the cover is not exposed.

[0014] In a second example, a method of forming a semiconductor package includes: placing two or more semiconductor dies on a top surface of a substrate; forming an encapsulation between the semiconductor dies on the top surface of the substrate; attaching a cap array over the two or more semiconductor dies, wherein a cap in the cap array is over one of the semiconductor dies, wherein the cap array includes a shell surrounding the periphery of each of the cap arrays; attaching two or more interconnects to a bottom surface of the substrate to electrically connect the semiconductor dies to the interconnects via the substrate to form a subassembly of the two or more semiconductor dies; and singulating the subassembly into individual semiconductor packages, wherein the cap is over the semiconductor die and a majority of the substrate, and one or more surfaces of the encapsulation are coplanar with one or more surfaces of the substrate and one or more surfaces of the shell.

[0015] In a second example, attaching the cap array over the two or more semiconductor dies includes applying a thermal interface material between the cap array and the corresponding semiconductor dies.

[0016] In a second example, the singulating includes sawing through the housing between the caps in the array of caps.

[0017] In a second example, the forming is performed prior to attaching the capping array over the two or more semiconductor dies.

[0018] In a second example, the forming is performed after attaching the capping array over the two or more semiconductor dies.

[0019] In a third example, a method of forming a semiconductor package includes attaching a cap array to a substrate strip having two or more semiconductor dies, wherein caps in the cap array are above the semiconductor dies of the substrate strip, and wherein the cap array includes a shell surrounding the periphery of each of the caps; forming an encapsulation between the two or more semiconductor dies; and singulating the substrate strip into two or more semiconductor packages, wherein the caps of the semiconductor packages are above the semiconductor dies of the semiconductor packages and a majority of the substrate, and wherein one or more surfaces of the encapsulation are coplanar with one or more surfaces of the substrate and one or more surfaces of the shell.

[0020] In a third example, the singulating includes sawing through the housing between the caps in the array of caps.

[0021] The third example further includes forming the array of closures by pouring a shell material into a region between the two or more closures and curing the shell material to form the shell into an array of blocks.

[0022] The third example further includes forming the array of covers by placing a resin sheet on the two or more covers, and applying pressure and curing the resin sheet into areas between the two or more covers to form the housing. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A cross-sectional view of an example semiconductor device is shown.

[0024] Figures 2A to 2L A cross-sectional view illustrating an example method of manufacturing an example semiconductor device.

[0025] Figures 3A to 3D A cross-sectional view showing another example method of manufacturing a semiconductor device.

[0026] Figure 4 A cross-sectional view showing another example of a semiconductor device.

[0027] Figures 5A to 5L A cross-sectional view showing another example method of manufacturing a semiconductor device.

[0028] Figures 6A to 6D A cross-sectional view showing another example method of manufacturing a semiconductor device. DETAILED DESCRIPTION

[0029] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0030] The figures illustrate the general construction mode, and descriptions and details of well-known features and technologies may be omitted so as not to unnecessarily confuse the present invention. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the size of some elements in the figures may be enlarged relative to other elements to help improve the understanding of the examples discussed in the present invention. The same reference numerals in different figures represent the same elements. However, it should be noted that the scope of the present invention and / or the claimed subject matter is not limited in this respect.

[0031] The term "and / or" includes any single item or any combination of items in the list connected by "and / or". As used in the present invention, the singular form is also intended to include the plural form unless the context clearly indicates otherwise. However, it should be noted that the scope of the present invention and / or claimed subject matter is not limited in this regard.

[0032] The terms "include" and / or "comprising" are "open" terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features. However, it should be noted that the scope of the invention and / or claimed subject matter is not limited in this regard.

[0033] The terms "first", "second", etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element discussed in the present invention may be referred to as a second element without departing from the teachings of the present invention. It should be noted that the scope of the present invention and / or the claimed subject matter is not limited in this respect.

[0034] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected by one or more other elements. For example, if element A is coupled to element B, element A may directly contact element B or be indirectly connected to element B by an intervening element C. Similarly, the terms "above" or "on" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected by one or more other elements. However, it should be noted that the scope of the present invention and / or the claimed subject matter is not limited in this respect.

[0035] The terms "top" and "bottom" generally refer to opposite sides or surfaces of a device, feature, or structure, which correspond to the orientation of the device, feature, or structure as shown in one or more of the drawings. In general, a top side or surface may refer to a first side surface and a bottom side or surface, and a bottom side or surface may refer to a second side or surface positioned opposite the first surface. However, it should be noted that the scope of the invention and / or claimed subject matter is not limited in this regard.

[0036] The term "coplanar" may refer to two objects, sides of an object, surfaces of an object, and / or other features that are located in the same plane or are generally located at least partially in the same plane. In geometric terms, if there is a geometric plane containing all the points, then the set of points is coplanar. In general, two objects or structures can be said to be "coplanar" when the surface, end, side, or feature of each of the two objects or structures is at least partially in a single plane. In addition, the term "flat" may refer to a surface that is flat or nearly flat within an acceptable tolerance. However, it should be noted that the scope of the present invention and / or claimed subject matter is not limited in this regard.

[0037] The term "substantially" may refer to a portion greater than or equal to half, and / or may further refer to other portions such as sixty percent or greater, seventy percent or greater, eighty percent or greater, or ninety percent or greater. In some embodiments, substantially may also refer to 100% or greater, such as if the first structure is larger in size and / or volume than the second structure, the first structure may be above the second structure and may be considered to cover a substantial portion of the second structure by virtue of the first structure covering more area and / or volume than the second structure, and / or wherein the first structure at least partially extends beyond the edge or boundary of the second structure. In addition, in some embodiments, substantially may also refer to a portion less than 50%, such as when the portion has sufficient quality and / or quantity. In yet other embodiments, substantially may refer to all or nearly all. However, it should be noted that the scope of the present invention and / or claimed subject matter is not limited in this respect.

[0038] The present invention describes examples of semiconductor packages, including, among other things, flip chip scale packages (fcCSPs), and example methods of forming flip chip scale packages. In a first example, a semiconductor package includes: a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, and a housing surrounding the periphery of the cover. An encapsulation may be between the cover and the substrate and / or between the housing and the substrate.

[0039] In a second example, a method of forming a semiconductor package includes: placing two or more semiconductor dies on a top surface of a substrate; forming an encapsulation between the semiconductor dies on the top surface of the substrate; attaching an array of caps over the two or more semiconductor dies, wherein one of the caps in the array of caps may be over one of the semiconductor dies, wherein the array of caps includes a housing surrounding a periphery of each of the caps; and attaching two or more interconnects to a bottom surface of the substrate to electrically couple the semiconductor dies to the interconnects via the substrate to form a subassembly of the two or more semiconductor dies. The subassembly of the two or more semiconductor dies may be singulated into individual semiconductor packages by a singulation operation of cutting the encapsulation between the dies, wherein each of the individual semiconductor packages includes a cap over a semiconductor die and a substantial portion of the substrate, and one or more surfaces of the encapsulation may be coplanar with one or more surfaces of the substrate and one or more surfaces of the housing.

[0040] In a third example, a method of forming a semiconductor package includes: coupling two or more semiconductor dies to a substrate strip; placing an array of blocks over the two or more semiconductor dies, wherein a cap in the array of blocks is over one of the semiconductor dies; and forming an encapsulant between a first semiconductor die and a second semiconductor die in the two or more semiconductor dies. The substrate strip may be singulated into two or more semiconductor packages, wherein one cap may be over a substantial portion of the semiconductor die and the substrate, and wherein one or more surfaces of the encapsulant are coplanar with one or more surfaces of the substrate and one or more surfaces of the housing.

[0041] Other examples are included in the present invention. Such examples can be found in the figures, claims and / or description of the present invention.

[0042] Figure 1 1 shows a cross-sectional view of an example semiconductor device 100. Figure 1 In the example shown in , the semiconductor device 100 may include a substrate 110 , an electronic device 120 , an encapsulation 130 , a cover 140 , a housing 150 , and an interconnect 160 .

[0043] The substrate 110 may include a conductive structure 111 having one or more conductive layers and a dielectric structure 112 having one or more dielectric layers. The electronic device 120 may include an interconnect 121 .

[0044] Substrate 110, encapsulant 130, cover 140, housing 150, and interconnect 160 may be referred to as semiconductor package 190, and package 190 may provide protection for electronic device 120 from external elements and / or environmental exposure. In addition, semiconductor package 190 may provide electrical connections between external electrical components (not shown) and interconnect 160. Figure 1As shown in, in addition to various other figures below, in one or more embodiments, the cap 140 is above a substantial portion of the substrate 110. The term "substantially" may refer to a portion greater than or equal to half, and / or may further refer to other portions such as sixty percent or greater, seventy percent or greater, eighty percent or greater, or ninety percent or greater. In some embodiments, substantially may also refer to 100% or greater, such as if the first structure is larger in size and / or volume than the second structure, then the first structure may be above the second structure and may be considered to cover a substantial portion of the second structure by covering more area and / or volume than the second structure, and / or wherein the first structure at least partially exceeds the essence of the edge or boundary of the second structure. In addition, in some embodiments, substantially may also refer to a portion less than 50%, such as when the portion has sufficient quality and / or quantity. In yet other embodiments, substantially may refer to all or nearly all. However, it should be noted that the scope of the present invention and / or the claimed subject matter is not limited in this respect.

[0045] Figures 2A to 2L A cross-sectional view illustrating an example method of manufacturing the semiconductor device 100 . Figure 2A A cross-sectional view of a semiconductor device 100 is shown at an early stage of fabrication.

[0046] exist Figure 2A In the example shown in , the substrate 110 may include one or more conductive layers of the conductive structure 111 and one or more dielectric layers of the conductive structure 112. The substrate 110 may include, for example, a printed circuit board (e.g., a pre-built laminated circuit structure with a core) or a lead frame. In other examples, the substrate 110 may include a high-density fan-out structure (HDFO) or a stacked redistribution structure, such as a SLIM (silicon-free integrated module) or SWIFT (silicon wafer integrated fan-out technology) structure. In some examples, the substrate 110 may include a dielectric layer of the dielectric structure 112 for electrically isolating adjacent conductive layers of the conductive structure 111 from each other. The substrate 110 may be formed as a stacked structure having corresponding layers of the conductive structure 111 and the dielectric structure 112 formed sequentially and / or repeatedly.

[0047] The conductive structure 111 may be exposed to the outside through the top and bottom surfaces of the substrate 110. The electronic device 120 may be electrically connected to the conductive layer of the conductive structure 111 exposed to the top surface of the substrate 110, and the interconnect 160 may be electrically connected to the conductive layer of the conductive structure 111 exposed to the bottom surface of the substrate 110.

[0048] In some examples, the conductive structure 111 may be referred to as or may include a metal layer, a metal wiring layer, or a circuit pattern. The conductive structure 111 may include a conductive material such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), or palladium (Pd). Examples of forming the conductive layer 111 include using an electroplating process or a physical vapor deposition (PVD) process. The thickness of one or more layers of the conductive structure 111 may range from about 10 microns to about 20 microns. The conductive layer 111 may provide a conductive path between the electronic device 120 and the interconnect 160.

[0049] In some instances, the dielectric structure 112 may be referred to as an insulator or a passivation layer. The dielectric structure 112 may include an electrically insulating material such as an oxide, a nitride, a polyimide, a benzocyclobutene, a polybenzoxazole, a bismaleimide triazine (BT), a phenolic resin, or an epoxy resin. Examples of forming the dielectric layer 112 may include thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), sheet lamination, or evaporation. The thickness of the dielectric structure 112 may range from about 25 microns to about 100 microns. In some instances, the dielectric structure 112 may protect the conductive structure 111 from environmental exposure, and the dielectric structure 112 may provide electrical isolation between conductive elements in the substrate 110.

[0050] Figure 2B 1 shows a cross-sectional view of a semiconductor device 100 at a later stage of manufacture. Figure 2B In the example shown in , the electronic device 120 can be attached to the top portion of the substrate 110. In some examples, the electronic device 120 can include a semiconductor die. In some examples, the semiconductor die 120 can include a semiconductor material such as silicon (Si). The semiconductor die 120 can include a passive electronic circuit element (not shown) or an active electronic circuit element (not shown) such as a transistor. The semiconductor die 120 can include an interconnect 121. In some examples, the interconnect 121 can be referred to as a conductive bump, a conductive ball such as a solder ball, a conductive post such as a copper post, or a conductive post such as a copper post. The thickness of the interconnect 121 can range from about 40 microns to about 100 microns.

[0051] In addition, although Figure 2BOnly one semiconductor die 120 is shown in the figure, but this is not a limitation of the present invention. In other examples, more than one semiconductor die 120 can be attached to the top portion of the substrate 110. In some examples, the semiconductor die 120 may include a circuit, such as a digital signal processor (DSP), a microprocessor, a network processor, a power management processor, an audio processor, a radio frequency (RF) circuit, a wireless baseband chip system (SoC) processor, a sensor, or an application-specific integrated circuit. The semiconductor die 120 can be attached to the top portion of the substrate 110 by electrically connecting the conductive bump 121 to the conductive structure 111 exposed at the top surface of the substrate 110. In some examples, the semiconductor die 120 can be electrically connected to the conductive structure 111 by a large-scale reflow process, a hot pressing process, or a laser bonding process.

[0052] Figure 2C 1 shows a cross-sectional view of a semiconductor device 100 at a later stage of manufacture. Figure 2C In the example shown in FIG. 1 , the array 20 and the corresponding cap 140 can be attached to the top portion of the semiconductor die 120 using an adhesive material 21. The adhesive material 21 can thus act as an interface between the cap 140 and the top of the semiconductor die 120, and as seen in the example of the present invention, the adhesive material can also cover at least a portion of the sidewall of the semiconductor die 120. In some examples, the adhesive material 21 can include a thermal interface material (TIM). The TIM 21 can be formed between the semiconductor die 120 and the array 20. The TIM 21 can include a high thermal conductivity filler (e.g., aluminum nitride (AlN), boron nitride (BN), aluminum oxide (Al2O3), silicon carbide (SiC), etc.), an adhesive or adhesive (e.g., a polymer resin) and / or an additive. The TIM 21 can have a thermal conductivity in the range of about 5 w / m·k to about 100 w / m·k. The TIM 21 can be formed or applied by a variety of methods, including spraying, dipping, injection, or silk-screen coating. The thickness of TIM 21 may range from about 30 microns to about 50 microns. In some examples, TIM 21 may transfer heat generated from semiconductor die 120 to array 20. Figure 2CIn some embodiments shown in and various other figures, TIM 21 can extend to one or more ends of semiconductor die 120, and in other embodiments, it can extend beyond and / or extend to one or more ends, edges or corners of semiconductor die 120, and the scope of the present invention and / or claims is not limited in this respect. In some instances, array 20 may include a cover 140 and a housing 150. In some instances, cover 140 may be referred to as a heat radiating member. In some embodiments, cover 140 may include a substantially flat heat radiating member. It should be noted that the term "flat" may refer to a flat or nearly flat surface within an acceptable tolerance. However, it should be noted that the scope of the present invention and / or the claimed subject matter is not limited in this respect.

[0053] In some instances, the shell 150 may be referred to as a resin portion. In one or more embodiments, as will be discussed in further detail below, the shell 150 may be disposed around the periphery of the cover 140. In some embodiments, the cover 140 may have four sides, and the shell 150 may cover all four sides of the cover 140 in a continuous manner, or may cover nearly all four sides of the cover 140 in a continuous or discontinuous manner, for example, wherein the shell 150 may have one or more of notches, grooves or grooves or other structures that may prevent the shell 150 from completely covering all four sides of the cover 140 and / or the entire periphery of the cover 140, and the scope of the present invention and / or the claimed subject matter is not limited in this regard. Prior to describing the attachment array 20, the formation process of the array 20 will first be described.

[0054] exist Figure 2D In the example shown in , multiple caps 140 can be arranged on the mold or carrier 10, leaving grooves or spacings with constant spacing between the caps 140. In some examples, the caps 140 can be attached to the mold or carrier 10 using an adhesive material (not shown). In some examples, the caps 140 may include a thermally conductive metal with good thermal conductivity, such as copper (Cu), aluminum (Al), gold (Au), or silver (Ag). In some embodiments, the caps 140 may include a substantially flat thermally conductive metal. It should be noted that the term "flat" may refer to a surface that is flat or almost flat within an acceptable tolerance. However, it should be noted that the scope of the present invention and / or claimed subject matter is not limited in this respect. The thickness of the cap 140 may range from about 200 microns to about 400 microns. Next, in Figure 2E In the example shown in , a gel-type resin may be poured into a region between each of the plurality of caps 140 and may be cured through an annealing process, thereby forming the housing 150. Figure 2FIn other examples shown in FIG. 1 , the resin sheet 150 ′ may be positioned on the plurality of covers 140 . The resin sheet 150 ′ may be in a semi-cured state. Figure 2G In the example shown in , a resin sheet 150' can be positioned between each of the plurality of caps 140 by pressure, and the sheet can be cured by an annealing process, thereby forming a shell 150. In some examples, the shell 150 can include epoxy resin, phenolic resin, glass epoxy resin, polymer, polyimide, polyester, silicone, or ceramic. The thickness of the shell 150 can range from about 200 microns to about 400 microns. Therefore, the shell 150 connects the caps 140 to each other. Then, in Figure 2H In the example shown in FIG. 1 , a plurality of covers 140 and housings 150 are separated from the mold or carrier 10 , thereby completing the array 20 .

[0055] Array 20, in Fig.2I In the example shown in , a plurality of caps 140 may be arranged to be spaced apart from each other by a constant interval, and a housing 150 may be formed between each of the plurality of caps 140, so that the array 20 may be configured in a plate form. Since the array 20 allows skipping of individual steps of arranging the corresponding caps 140 on the semiconductor die 120, productivity may be improved. In some examples, in a state where the plurality of semiconductor die 120 are attached to the top portion of the substrate 110, the corresponding caps 140 may be attached to the plurality of semiconductor die 120 by attaching a single array 20, thereby improving productivity. A plurality of arrays 20 may be attached according to the size of the substrate 110 and the number of semiconductor die 120. In some embodiments, one or more covers 140 may have four sides, and the shell 150 may cover all four sides of the cover 140 in a continuous manner, or may cover nearly all four sides of the cover 140 in a continuous or discontinuous manner, for example, wherein the shell 150 may have one or more of notches, grooves or grooves or other structures that prevent the shell 150 from completely covering all four sides of the cover 140 and / or the entire periphery of the cover 140, and the scope of the present invention and / or claimed subject matter is not limited in this respect.

[0056] Return to Figure 2C, a portion of the cap 140 in the array 20 may be coupled to the top surface of the semiconductor die 120. In some instances, the area of ​​the cap 140 may be larger than the area of ​​the semiconductor die 120 and smaller than the area of ​​the substrate 110. In some instances, the cap 140 may be formed to cover the semiconductor die 120, and a portion of the substrate 110 may be exposed to the outside of the cap 140. Therefore, it is not necessary to form the adhesive material 21 on the entire bottom surface of the array 20. In fact, the adhesive material 21 may be formed only on a portion of the cap 140 corresponding to the semiconductor die 120, thereby saving the cost associated with the formation of the adhesive material 21. In addition, since the cap 140 has a larger area than the semiconductor die 120, the heat generated from the semiconductor die 120 can be quickly radiated to the outside. In some instances, the housing 150 may be formed to surround the side surface of the cap 140. Therefore, the top surface of the cap 140 can be exposed to the outside, and the heat generated from the semiconductor die 120 can be quickly radiated to the outside.

[0057] Now move to Figure 2J , shows a cross-sectional view of semiconductor device 100 at a later stage of fabrication. Figure 2J In the example shown in , the encapsulant 130 can be formed between the substrate 110 and the array 20. The encapsulant 130 encapsulates the semiconductor die 120 and the top portion of the substrate 110. In some examples, the encapsulant 130 can contact the side surface and the bottom surface of the semiconductor die 120 without contacting the top surface of the semiconductor die 120. In some examples, the encapsulant 130 can include any of various encapsulation or molding materials, such as resins, polymer compounds, polymers with fillers, epoxy resins, epoxy resins with fillers, epoxy acrylates with fillers, silicone materials, combinations thereof, or equivalents thereof. In some examples, the encapsulant 130 can be formed by one of various methods, such as a compression molding process, a liquid phase encapsulant molding process, a vacuum lamination process, a paste printing process, or a film assisted molding process. The thickness of the encapsulant 130 can range from about 120 microns to about 200 microns. In some examples, encapsulant 130 may be injected into a region between substrate 110 and array 20 and cured, thereby encapsulating semiconductor die 120 .

[0058] In some instances, such as Figure 2KAs shown in , the substrate 110, the semiconductor die 120, and the array 20 can be placed in a mold, and the encapsulant 130 can be injected into the mold through the molding inlet 30, thereby encapsulating the semiconductor die 120. In some examples, the encapsulant 130 can protect the semiconductor die 120 from the external environment. There may be examples where the housing 150 can include one or more materials similar to those described with respect to the encapsulant 130, and / or can be formed by a process similar to the description.

[0059] Figure 2L 1 shows a cross-sectional view of a semiconductor device 100 at a later stage of manufacture. Figure 2L In the example shown in , the substrate 110, the array 20, and the encapsulation 130 can be subjected to a singulation operation to separate each of the plurality of semiconductor dies 120 and each of the plurality of caps 140. In some examples, the substrate 110, the housing 150, and the encapsulation 130 can be separated with the aid of a singulation tool. In some examples, before singulating the substrate 110, the array 20, and the encapsulation 130, the interconnect 160 can be attached to the conductive structure 111 exposed at the bottom surface of the substrate 110. In other examples, the interconnect 160 can be attached to the conductive structure 111 exposed at the bottom surface of the substrate 110 after singulation. For example, the interconnect 160 can be formed as a ball grid array, a pad grid array, or a pin grid array. In addition, the interconnect 160 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, ... 37 -Pb, Sn 95 The interconnect 160 may be formed of Sn-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. Examples of forming the interconnect 160 include using a ball drop process, a screen printing process, or an electroplating process. The thickness of the interconnect 160 may range from about 150 microns to about 300 microns. The interconnect 160 may serve as an electrical contact for providing electrical signals between the substrate 110 and an external electrical component (not shown).

[0060] The completed semiconductor device 100 may include a substrate 110, a semiconductor die 120 mounted on the substrate 110, an encapsulation 130 encapsulating the semiconductor die 120, a cover 140 attached to a top portion of the semiconductor die 120, a housing 150 surrounding a side surface of the cover 140, and an interconnect 160 attached to a bottom surface of the substrate 110.

[0061] Figures 3A to 3D A cross-sectional view showing another example method of manufacturing the semiconductor device 100 is shown. Figure 3AIn the example shown in , the electronic device 120 can be attached to the top portion of the substrate 110. In some examples, the electronic device 120 can include a semiconductor die. In some examples, the semiconductor die 120 can include a semiconductor material such as silicon (Si). The semiconductor die 120 can include a passive electronic circuit element (not shown) or an active electronic circuit element (not shown) such as a transistor. The semiconductor die 120 can include an interconnect 121. In some examples, the interconnect 121 can be referred to as a conductive bump, a conductive ball such as a solder ball, a conductive post such as a copper post, or a conductive post such as a copper post.

[0062] In addition, although Figure 3A Only one semiconductor die 120 is shown in the figure, but this is not a limitation of the present invention. In other examples, more than one semiconductor die 120 can be attached to the top portion of the substrate 110. The semiconductor die 120 can be attached to the top portion of the substrate 110 by electrically connecting the conductive bumps 121 to the conductive structure 111 exposed at the top surface of the substrate 110. In some examples, the semiconductor die 120 can be electrically connected to the conductive structure 111 through a large-scale reflow process, a thermal compression process, or a laser bonding process.

[0063] Figure 3B 1 shows a cross-sectional view of a semiconductor device 100 at a later stage of manufacture. Figure 3B In the example shown in , the encapsulant 130 may be formed at the side surface of the semiconductor die 120. The encapsulant 130 encapsulates the semiconductor die 120 and the top portion of the substrate 110. In addition, the encapsulant 130 may expose the top surface of the semiconductor die 120 to the outside. In some examples, the encapsulant 130 may contact the side surface and the bottom surface of the semiconductor die 120 without contacting the top surface of the semiconductor die 120. In some examples, the encapsulant 130 may include any of various encapsulation or molding materials, such as resins, polymer compounds, polymers with fillers, epoxy resins, epoxy resins with fillers, epoxy acrylates with fillers, silicone resins, combinations thereof, or equivalents thereof. In some examples, the encapsulant 130 may be formed by one of various methods, such as a compression molding process, a liquid phase encapsulant molding process, a vacuum lamination process, a paste printing process, or a film assisted molding process.

[0064] Figure 3C 1 shows a cross-sectional view of a semiconductor device 100 at a later stage of manufacture. Figure 3CIn the example shown in , the array 20 and the corresponding cap 140 can be attached to the top portion of the semiconductor die 120 and the encapsulation 130 using adhesive materials 21, 22. The adhesive materials 21, 22 can therefore serve as an interface between the cap 140 and the top of the semiconductor die 120. In some examples, the adhesive materials 21, 22 can include a thermal interface material (TIM) 21 and an adhesive 22. Whether it is TIM 21 or adhesive 22, the adhesive material can also extend to cover at least a portion of the sidewall of the semiconductor die 120 in some examples. TIM 21 can be formed between the semiconductor die 120 and the array 20. TIM 21 can include a high thermal conductivity filler (e.g., aluminum nitride (AlN), boron nitride (BN), aluminum oxide (Al2O3), silicon carbide (SiC), etc.), an adhesive or adhesive (e.g., a polymer resin) and / or an additive. The TIM 21 may have a thermal conductivity in the range of about 5 w / m·k to about 100 w / m·k. The TIM 21 may be formed or applied by a variety of methods, including spraying, dipping, injection, or silk-screen coating. The thickness of the TIM 21 may range from about 30 microns to about 50 microns. In some instances, the TIM 21 may transfer heat generated from the semiconductor die 120 to the array 20. The adhesive 22 may be formed between the encapsulation 130 and the array 20. The thickness of the adhesive 22 may range from about 30 microns to about 50 microns. The adhesive 22 may contact the encapsulation 130 and the array 20. In addition, the thermal conductivity of the TIM 21 may be greater than the thermal conductivity of the adhesive 22. There may be instances where the TIM 21 and the adhesive 22 may include the same and / or continuous material. In some instances, the array 20 may include a cover 140 and a housing 150. In some instances, the cover 140 may be referred to as a heat radiation component. In some examples, the housing 150 may be referred to as a resin portion. Figures 2D to 2I The process of forming the array 20 is shown in FIG.

[0065] exist Figure 3C In the example shown in , a portion of the cap 140 in the array 20 may be coupled to the top surface of the semiconductor die 120. In some examples, the area of ​​the cap 140 may be larger than the area of ​​the semiconductor die 120 and smaller than the area of ​​the substrate 110. In addition, since the cap 140 has a larger area than the semiconductor die 120, the heat generated from the semiconductor die 120 may be quickly radiated to the outside. In some examples, the housing 150 may be formed to surround the side surface of the cap 140. Therefore, the top surface of the cap 140 may be exposed to the outside, and the heat generated from the semiconductor die 120 may be quickly radiated to the outside.

[0066] Figure 3D 1 shows a cross-sectional view of a semiconductor device 100 at a later stage of manufacture. Figure 3DIn the example shown in , the substrate 110, the array 20, and the encapsulation 130 can be subjected to a sawing operation to separate each of the plurality of semiconductor dies 120 and each of the plurality of caps 140. In some examples, the substrate 110, the housing 150, and the encapsulation 130 can be separated with the aid of a sawing tool. In some examples, before sawing the substrate 110, the array 20, and the encapsulation 130, the interconnect 160 can be attached to the conductive structure 111 exposed at the bottom surface of the substrate 110. In other examples, the interconnect 160 can be attached to the conductive structure 111 exposed at the bottom surface of the substrate 110 after sawing. For example, the interconnect 160 can be formed as a ball grid array, a pad grid array, or a pin grid array. In addition, the interconnect 160 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, ... 37 -Pb, Sn 95 -Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. Examples of forming the interconnect 160 include using a ball drop process, a screen printing process, or an electroplating process.

[0067] The completed semiconductor device 100 may include a substrate 110, a semiconductor die 120 mounted on the substrate 110, an encapsulation 130 encapsulating the semiconductor die 120, a cover 140 attached to a top portion of the semiconductor die 120, a housing 150 surrounding a side surface of the cover 140, and an interconnect 160 attached to a bottom surface of the substrate 110.

[0068] Figure 4 A cross-sectional view of another example of a semiconductor device 200 is shown. The semiconductor device 200 may be similar to the semiconductor device 100. The semiconductor device 200 may include a housing 250 formed on a top surface of the cover 140. The housing 250 may protect the top surface of the cover 140.

[0069] Figures 5A to 5L A cross-sectional view illustrating another example method of manufacturing a semiconductor device 200 . Figure 5A A cross-sectional view of a semiconductor device 200 is shown at an early stage of fabrication.

[0070] exist Figure 5AIn the example shown in , the substrate 110 may include one or more conductive layers of the conductive structure 111 and one or more dielectric layers of the dielectric structure 112. The substrate 110 may include, for example, a printed circuit board (e.g., a pre-built laminated circuit structure with a core) or a lead frame. In other examples, the substrate 110 may include a high-density fan-out structure (HDFO) or a stacked redistribution structure, such as a SLIM (silicon-free integrated module) or SWIFT (silicon wafer integrated fan-out technology) structure. In some examples, the substrate 110 may include a dielectric layer of the dielectric structure 112 for electrically isolating adjacent conductive layers of the conductive structure 111 from each other. The substrate 110 may be formed as a stacked structure having respective layers of the conductive structure 111 and the dielectric structure 112 formed repeatedly or sequentially.

[0071] The conductive structure 111 may be exposed to the outside through the top and bottom surfaces of the substrate 110. The electronic device 120 may be electrically connected to the conductive layer of the conductive structure 111 exposed to the top surface of the substrate 110, and the interconnect 160 may be electrically connected to the conductive layer of the conductive structure 111 exposed to the bottom surface of the substrate 110.

[0072] In some examples, the conductive structure 111 may be referred to as or may include a metal layer, a metal wiring layer, or a circuit pattern. The conductive structure 111 may include a conductive material such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), or palladium (Pd). Examples of forming the conductive structure 111 include using an electroplating process or a physical vapor deposition (PVD) process. The conductive structure 111 may be connected to the substrate 110 and the electronic device 120. In addition, the conductive structure 111 may be connected to the substrate 110 and the interconnect 160.

[0073] In some instances, the dielectric structure 112 may be referred to as an insulator or a passivation layer. The dielectric structure 112 may include an electrically insulating material such as an oxide, a nitride, a polyimide, a benzocyclobutene, a polybenzoxazole, a bismaleimide triazine (BT), a phenolic resin, or an epoxy resin. Examples of forming the dielectric structure 112 may include thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), sheet lamination, or evaporation. In some instances, the dielectric structure 112 may protect the conductive structure 111 from environmental exposure, and the dielectric structure 112 may provide electrical isolation between conductive elements in the substrate 110.

[0074] Figure 5B 2 shows a cross-sectional view of a semiconductor device 200 at a later stage of manufacture. Figure 5BIn the example shown in , the electronic device 120 can be attached to the top portion of the substrate 110. In some examples, the electronic device 120 can include a semiconductor die. In some examples, the semiconductor die 120 can include a semiconductor material such as silicon (Si). The semiconductor die 120 can include a passive electronic circuit element (not shown) or an active electronic circuit element (not shown) such as a transistor. The semiconductor die 120 can include an interconnect 121. In some examples, the interconnect 121 can be referred to as a conductive bump, a conductive ball such as a solder ball, a conductive post such as a copper post, or a conductive post such as a copper post.

[0075] In addition, although Figure 5B Only one semiconductor die 120 is shown in the figure, but this is not a limitation of the present invention. In other examples, more than one semiconductor die 120 can be attached to the top portion of the substrate 110. In some examples, the semiconductor die 120 can include a circuit, such as a digital signal processor (DSP), a microprocessor, a network processor, a power management processor, an audio processor, a radio frequency (RF) circuit, a wireless baseband chip system (SoC) processor, a sensor, or an application-specific integrated circuit. The semiconductor die 120 can be attached to the top portion of the substrate 110 by electrically connecting the conductive bump 121 to the conductive structure 111 exposed to the top surface of the substrate 110. In some examples, the semiconductor die 120 can be electrically connected to the conductive structure 111 by a large-scale reflow process, a hot pressing process, or a laser bonding process.

[0076] Figure 5C 2 shows a cross-sectional view of a semiconductor device 200 at a later stage of manufacture. Figure 5C In the example shown in , array 20 ′ may be attached to a top portion of semiconductor die 120 using adhesive material 21 .

[0077] In some examples, the adhesive material 21 may include a thermal interface material (TIM). The TIM 21 may be formed between the semiconductor die 120 and the array 20'. The TIM 21 may include a high thermal conductivity filler (e.g., aluminum nitride (AlN), boron nitride (BN), aluminum oxide (Al2O3), silicon carbide (SiC), etc.), an adhesive or adhesive (e.g., a polymer resin) and / or an additive. The TIM 21 may have a thermal conductivity in the range of about 5 w / m·k to about 100 w / m·k. The TIM 21 may be formed or applied by a variety of methods, including spraying, dipping, injection, or silk-screen coating. The thickness of the TIM 21 may range from about 30 microns to about 50 microns. In some examples, the TIM 21 may transfer heat generated from the semiconductor die 120 to the array 20'. In some examples, the array 20' may include a cover 140 and a housing 250. In some examples, the cover 140 may be referred to as a heat radiation component. In some examples, the housing 250 may be referred to as a resin portion. Before describing the attachment of the array 20', a formation process of the array 20' will first be described.

[0078] exist Figure 5D In the example shown in , a plurality of caps 140 may be arranged on a carrier 40 at constant intervals. In some examples, an adhesive material (not shown) may be used to attach the caps 140 to the carrier 40. In some examples, the carrier 40 may include metal, silicon (Si), or glass. In some examples, the caps 140 may include a thermally conductive metal with good thermal conductivity, such as copper (Cu), aluminum (Al), gold (Au), or silver (Ag). The thickness of the caps 140 may range from about 200 microns to about 400 microns. Next, in Figure 5E In the example shown in FIG. 2 , the housing 250 may be formed by placing the carrier 40 disposed with the cover 140 on a mold (not shown) and injecting an epoxy molding compound (EMC) into the mold. Fig. 5F In other examples shown in FIG. 1 , the resin sheet 250 ′ may be positioned on the plurality of covers 140 . The resin sheet 250 ′ may be in a semi-cured state. Figure 5G In the example shown in , a resin sheet 250' can be positioned between each of the plurality of caps 140 by pressure, and the sheet can be cured by an annealing process, thereby forming a shell 250. In some examples, the shell 250 can include epoxy resin, phenolic resin, glass epoxy resin, polymer, polyimide, polyester, silicon, or ceramic. The thickness of the shell 250 can range from about 300 microns to about 500 microns. Therefore, the shell 250 connects the caps 140 to each other. Next, in Figure 5HIn the example shown in , the carrier 40 can be removed, thereby completing the array 20' including a plurality of covers 140 and a housing 250. Since the side surfaces and top surfaces of the covers 140 of the array 20' can be covered by the housing 250, unnecessary electrical contact between the array 20' and an external circuit can be prevented.

[0079] Array 20', in Fig.5I In the example shown in , a plurality of caps 140 may be arranged to be spaced apart from each other by a constant interval, and a housing 250 may be formed between each of the plurality of caps 140, so that the array 20' may be configured in a plate form. Since the array 20' allows skipping of individual steps of arranging the corresponding caps 140 on the semiconductor die 120, productivity may be improved. In some examples, in a state where a plurality of semiconductor die 120 are attached to a top portion of a substrate 110, the corresponding caps 140 may be attached to the plurality of semiconductor die 120 by attaching a single array 20', thereby improving productivity. A plurality of arrays 20' may be attached according to the size of the substrate 110 and the number of semiconductor die 120.

[0080] exist Figure 5C In the example shown in , a portion of the cap 140 in the array 20' may be in contact with the top surface of the semiconductor die 120. In some examples, the area of ​​the cap 140 may be larger than the area of ​​the semiconductor die 120 and smaller than the area of ​​the substrate 110. In some examples, the cap 140 may be formed to cover the semiconductor die 120, and a portion of the substrate 110 may be exposed to the outside of the cap 140. Therefore, it is not necessary to form the adhesive material 21 on the entire bottom surface of the array 20'. In fact, the adhesive material 21 may be formed only on a portion of the cap 140 corresponding to the semiconductor die 120, thereby saving the cost associated with the formation of the adhesive material 21. In addition, since the cap 140 has a larger area than the semiconductor die 120, the heat generated from the semiconductor die 120 can be quickly radiated to the outside. In some examples, the housing 250 may be formed to surround the side surface and the top surface of the cap 140. Therefore, the housing 250 can prevent electrical contact between the array 20' and the external circuit.

[0081] Figure 5J 2 shows a cross-sectional view of a semiconductor device 200 at a later stage of manufacture. Figure 5JIn the example shown in , the encapsulant 130 can be formed between the substrate 110 and the array 20'. The encapsulant 130 encapsulates the semiconductor die 120 from the top portion of the substrate 110. In some examples, the encapsulant 130 can contact the side surface and the bottom surface of the semiconductor die 120 without contacting the top surface of the semiconductor die 120. In some examples, the encapsulant 130 can include any of various encapsulation or molding materials, such as resins, polymer compounds, polymers with fillers, epoxy resins, epoxy resins with fillers, epoxy acrylates with fillers, silicone resins, combinations thereof, or equivalents thereof. In some examples, the encapsulant 130 can be formed by one of various methods, such as a compression molding process, a liquid phase encapsulant molding process, a vacuum lamination process, a paste printing process, or a film assisted molding process. In some examples, the encapsulant 130 can be injected into the area between the substrate 110 and the array 20' and cured, thereby encapsulating the semiconductor die 120.

[0082] For example, Figure 5K As shown in FIG. 1 , substrate 110, semiconductor die 120, and array 20′ may be placed in a mold, and encapsulant 130 may be injected into the mold through molding inlet 30, thereby encapsulating semiconductor die 120. In some examples, encapsulant 130 may protect semiconductor die 120 from external environment.

[0083] Figure 5L 2 shows a cross-sectional view of a semiconductor device 200 at a later stage of manufacture. Figure 5L In the example shown in , the substrate 110, the array 20', and the encapsulation 130 can be subjected to a sawing operation to separate each of the plurality of semiconductor dies 120 and each of the plurality of caps 140. In some examples, the substrate 110, the housing 250, and the encapsulation 130 can be separated with the aid of a sawing tool. In some examples, before sawing the substrate 110, the array 20', and the encapsulation 130, the interconnect 160 can be attached to the conductive structure 111 exposed to the bottom surface of the substrate 110. In other examples, the interconnect 160 can be attached to the conductive structure 111 exposed to the bottom surface of the substrate 110 after sawing. For example, the interconnect 160 can be formed into a ball grid array, a pad grid array, or a pin grid array. In addition, the interconnect 160 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, ... 37 -Pb, Sn 95 -Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. Examples of forming the interconnect 160 include using a ball drop process, a screen printing process, or an electroplating process.

[0084] The completed semiconductor device 200 may include a substrate 110, a semiconductor die 120 mounted on the substrate 110, an encapsulation 130 encapsulating the semiconductor die 120, a cover 140 attached to the top portion of the semiconductor die 120, a housing 250 surrounding the side surfaces and top surfaces of the cover 140, and an interconnect 160 attached to the bottom surface of the substrate 110.

[0085] Figures 6A to 6D FIG. 2 is a cross-sectional view showing another example method of manufacturing a semiconductor device 200. Fig. 6A In the example shown in , the electronic device 120 can be attached to the top portion of the substrate 110. In some examples, the electronic device 120 can include a semiconductor die. In some examples, the semiconductor die 120 can include a semiconductor material such as silicon (Si). The semiconductor die 120 can include a passive electronic circuit element (not shown) or an active electronic circuit element (not shown) such as a transistor. The semiconductor die 120 can include an interconnect 121. In some examples, the interconnect 121 can be referred to as a conductive bump, a conductive ball such as a solder ball, a conductive post such as a copper post, or a conductive post such as a copper post.

[0086] In addition, although Fig. 6A Only one semiconductor die 120 is shown in the figure, but this is not a limitation of the present invention. In other examples, more than one semiconductor die 120 can be attached to the top portion of the substrate 110. The semiconductor die 120 can be attached to the top portion of the substrate 110 by electrically connecting the conductive bumps 121 to the conductive structure 111 exposed to the top surface of the substrate 110. In some examples, the semiconductor die 120 can be electrically connected to the conductive structure 111 through a large-scale reflow process, a thermal compression process, or a laser bonding process.

[0087] Figure 6B 2 shows a cross-sectional view of a semiconductor device 200 at a later stage of manufacture. Figure 6BIn the example shown in , the encapsulant 130 may be formed at the side surface of the semiconductor die 120. The encapsulant 130 encapsulates the semiconductor die 120 from the top portion of the substrate 110. In addition, the encapsulant 130 may expose the top surface of the semiconductor die 120 to the outside. In some examples, the encapsulant 130 may contact the side surface and the bottom surface of the semiconductor die 120 without contacting the top surface of the semiconductor die 120. In some examples, the encapsulant 130 may include any of various encapsulation or molding materials, such as resins, polymer compounds, polymers with fillers, epoxy resins, epoxy resins with fillers, epoxy acrylates with fillers, silicone resins, combinations thereof, or equivalents thereof. In some examples, the encapsulant 130 may be formed by one of various methods, such as a compression molding process, a liquid phase encapsulant molding process, a vacuum lamination process, a paste printing process, or a film assisted molding process.

[0088] Figure 6C 2 shows a cross-sectional view of a semiconductor device 200 at a later stage of manufacture. Figure 6C In the example shown in , the array 20' can be attached to the top portion of the semiconductor die 120 and the encapsulation 130 using adhesive materials 21, 22. In some examples, the adhesive materials 21, 22 may include a thermal interface material (TIM) and an adhesive 22. The TIM 21 may be formed between the semiconductor die 120 and the array 20'. The TIM 21 may include a high thermal conductivity filler (e.g., aluminum nitride (AlN), boron nitride (BN), aluminum oxide (Al2O3), silicon carbide (SiC), etc.), an adhesive or adhesive (e.g., a polymer resin) and / or an additive. The TIM 21 may have a thermal conductivity in the range of about 5 w / m·k to about 100 w / m·k. The TIM 21 may be formed or applied by a variety of methods, including spraying, dipping, injection, or silk-screen coating. The thickness of the TIM 21 may range from about 30 microns to about 50 microns. In some examples, TIM 21 may transfer heat generated from semiconductor die 120 to array 20 ′. Adhesive 22 may be formed between encapsulant 130 and array 20 .

[0089] The thickness of adhesive 22 may range from about 30 microns to about 50 microns. Adhesive 22 may contact encapsulation 130 and array 20. In addition, the thermal conductivity of TIM 21 may be greater than the thermal conductivity of adhesive 22. There may be instances where TIM 21 and adhesive 22 may include the same and / or continuous material. In some instances, array 20' may include cover 140 and housing 150. In some instances, cover 140 may be referred to as a heat radiating member. In some instances, housing 150 may be referred to as a resin portion. Figure 5D to 5G The process of forming the array 20' is shown in FIG. Figure 6CIn the example shown in , a portion of the cap 140 in the array 20' may be coupled to the top surface of the semiconductor die 120. In some examples, the area of ​​the cap 140 may be larger than the area of ​​the semiconductor die 120 and smaller than the area of ​​the substrate 110. In addition, since the cap 140 has a larger area than the semiconductor die 120, the heat generated from the semiconductor die 120 may be quickly radiated to the outside. In some examples, the housing 250 may be formed to surround the side surface and the top surface of the cap 140. Therefore, the housing 250 may prevent electrical contact between the array 20' and the external circuit.

[0090] Fig.6D 2 shows a cross-sectional view of a semiconductor device 200 at a later stage of manufacture. Fig.6D In the example shown in , the substrate 110, the array 20', and the encapsulation 130 can be subjected to a sawing operation to separate each of the plurality of semiconductor dies 120 and each of the plurality of caps 140. In some examples, the substrate 110, the housing 250, and the encapsulation 130 can be separated with the aid of a sawing tool. In some examples, before sawing the substrate 110, the array 20', and the encapsulation 130, the interconnect 160 can be attached to the conductive structure 111 exposed at the bottom surface of the substrate 110. In other examples, the interconnect 160 can be attached to the conductive structure 111 exposed at the bottom surface of the substrate 110 after sawing. For example, the interconnect 160 can be formed as a ball grid array, a pad grid array, or a pin grid array. In addition, the interconnect 160 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, ... 37 -Pb, Sn 95 -Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. Examples of forming the interconnect 160 include using a ball drop process, a screen printing process, or an electroplating process.

[0091] The completed semiconductor device 200 may include a substrate 110, a semiconductor die 120 mounted on the substrate 110, an encapsulation 130 encapsulating the semiconductor die 120, a cover 140 attached to the top portion of the semiconductor die 120, a housing 250 surrounding the side surfaces and top surfaces of the cover 140, and an interconnect 160 attached to the bottom surface of the substrate 110.

[0092] In general, a semiconductor package such as a flip chip scale package (fcCSP) includes: a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and connected to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device and a substantial portion of the substrate, a housing surrounding the periphery of the cover, and an enclosure between the cover and the housing and the substrate, wherein the enclosure is coplanar with one or more ends of the substrate and the housing.

[0093] The method of forming such a semiconductor package includes attaching a plurality of caps or covers to respective electronic devices or semiconductor dies of the package by first forming the caps or covers array into a block array, wherein the block array includes a housing that holds the caps or covers in the block array. The block array may then be attached to a substrate with a plurality of electronic devices attached to the substrate, wherein one cap or cover in the block array covers the respective electronic device. An encapsulation may be molded between the electronic devices and the caps or covers before attaching the block array or after attaching the block array.

[0094] Individual semiconductor packages can be singulated from the resulting structure, for example, by sawing through the encapsulation between the caps. The singulated semiconductor packages can have a resulting structure with the cap or lid covering a substantial portion of the electronic device and the substrate, and the housing covering the remainder of the substrate around the periphery of the cap or lid.

[0095] In some embodiments, the housing and the cover or lid are coplanar, wherein the surface of the cover or lid is exposed to the surrounding environment. In other embodiments, the housing completely or substantially covers the cover or lid, wherein the cover or lid is not exposed to the surrounding environment. The cover or lid can act as a heat radiating device and can include a thermally conductive metal to dissipate heat from the electronic device. In some embodiments, a thermal interface material can be between the electronic device and the cover or lid.

[0096] The above example method of forming a semiconductor package allows for attaching multiple caps to multiple electronic devices at a higher rate than a pick-in-place method or a one-by-one method to achieve a higher unit manufacturing throughput per hour. In addition, the resulting semiconductor package allows the semiconductor device to have a cap or lid that includes a larger portion of the semiconductor device to enhance thermal dissipation of heat from the electronic device of the semiconductor package. Forming the cap in an array of blocks allows singulation of individual semiconductor packages using a standard sawing process, thereby achieving a smaller form factor of the individual semiconductor packages.

[0097] The present invention includes references to certain examples. However, it will be appreciated by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, modifications may be made to the disclosed examples without departing from the scope of the present invention. Therefore, it is contemplated that the present invention is not limited to the disclosed examples, but rather that the present invention will include all examples within the scope of the appended claims.

Claims

1. A semiconductor package, comprising: a substrate having a top surface and a bottom surface; an electronic device on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate; a cover over the electronic device; an adhesive material between the cover and the electronic device, wherein the adhesive material covers a side of the electronic device; a housing surrounding the periphery of the cover; as well as An encapsulation is between the cover and the substrate and between the housing and the substrate. 2 . The semiconductor package of claim 1 , wherein the cap is over more than half of the substrate. 3 . The semiconductor package according to claim 1 , wherein the cover has four sides and the housing covers all four sides. 4 . The semiconductor package of claim 1 , wherein the cover has four sides and the housing covers more than half of all four sides. 5 . The semiconductor package of claim 1 , wherein a surface of the encapsulant is coplanar with a surface of the substrate and one or more surfaces of the housing. 6 . The semiconductor package of claim 1 , further comprising a thermal interface material between the lid and the electronic device. The semiconductor package according to claim 1 , wherein the cover comprises a substantially planar heat radiation member. The semiconductor package according to claim 1 , wherein the cover comprises a thermally conductive metal. 9 . The semiconductor package of claim 1 , wherein a top surface of the cover is coplanar with a top surface of the housing, wherein the top surface of the cover is exposed.

10. The semiconductor package of claim 1, wherein the housing is above the cover, wherein the cover is not exposed.

11. A method of forming a semiconductor package, the method comprising: placing two or more semiconductor dies on the top surface of the substrate; forming an encapsulation between the semiconductor dies on the top surface of the substrate; attaching an array of caps over the two or more semiconductor dies, wherein a cap in the array of caps is over one of the semiconductor dies, wherein the array of caps comprises a casing material surrounding a periphery of each cap in the array of caps; attaching two or more interconnects to a bottom surface of the substrate to electrically couple the semiconductor die to the interconnects via the substrate to form a subassembly of the two or more semiconductor dies; as well as The subassembly is singulated into individual semiconductor packages, wherein a single semiconductor package includes a cap over the semiconductor die and over more than half of the substrate, the casing material surrounds the cap, and one or more surfaces of the encapsulation are coplanar with one or more surfaces of the substrate and one or more surfaces of the casing material.

12. The method of claim 11, wherein said attaching said capping array over said two or more semiconductor dies comprises applying a thermal interface material between said capping array and said semiconductor dies corresponding to said capping array.

13. The method of claim 11, wherein the singulating comprises sawing through the housing between the covers in the array of covers.

14. The method of claim 11, wherein the forming is performed before attaching the capping array over the two or more semiconductor dies.

15. The method of claim 11, wherein the forming is performed after attaching the capping array over the two or more semiconductor dies.

16. A method of forming a semiconductor package, the method comprising: attaching an array of caps to a substrate strip having two or more semiconductor dies, wherein the caps in the array of caps are over the semiconductor dies of the substrate strip, and wherein the array of caps includes a casing material surrounding a periphery of each cap in the array of caps; forming an encapsulation between the two or more semiconductor dies; as well as The substrate strip is singulated into two or more semiconductor packages, wherein a lid of the semiconductor package is over a semiconductor die of the semiconductor package and over more than half of the substrate, wherein the casing material surrounds the lid, and wherein one or more surfaces of the encapsulation are coplanar with one or more surfaces of the substrate and one or more surfaces of the casing.

17. The method of claim 16, wherein the singulating comprises sawing through the casing material between the caps in the array of caps.

18. The method of claim 16, further comprising forming the array of closures by pouring the casing material into the regions between the closures and curing the casing material to form the casing material into an array of nuggets.

19. The method of claim 16, further comprising forming the array of covers by disposing a resin sheet on the covers and applying pressure and curing the resin sheet into areas between the covers to form the casing material.

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