Semiconductor device and power conversion device

Abstract

The object is to provide a semiconductor device with high insulation reliability. In addition, the present invention also relates to a power conversion device. The semiconductor device (202) comprises: a semiconductor element (2a, 2b); a lead frame (3) having a mounting portion (10) on which the semiconductor element (2a, 2b) is mounted on the upper surface; a packaging resin (1) that packages the lead frame (3) and the semiconductor element (2a, 2b) in a manner that the external leads (12, 14) of the lead frame (3) protrude to the outside; and a resin wall (6) that is provided on the internal lead (13) between the external lead (14) in the lead frame (3) and the mounting portion (10). The thickness of the resin wall (6) in the vertical direction is thicker than the thickness in the vertical direction from the lower surface of the packaging resin (1) to the lower end of the lead frame (3).

Description

Technical Field

[0001] The present invention relates to a technology for improving the reliability of power semiconductor devices such as IGBTs and diodes. Background Art

[0002] With the development of civil equipment, electric railways, and automobiles, the operating temperature of semiconductor elements used in them has also increased. In recent years, the development of semiconductor elements that can also work at high temperatures has been actively carried out, and the miniaturization, high voltage resistance, and high current density of semiconductor elements are developing. In particular, wide bandgap semiconductors such as SiC and GaN have a larger band gap than Si semiconductors, and semiconductor devices are expected to have high voltage resistance, miniaturization, high current density, and high temperature operation. In order to make semiconductor elements with such characteristics into devices, it is necessary to improve the insulation reliability of the semiconductor device and improve the resistance to temperature changes in harsh use environments, thereby ensuring the stable operation of the semiconductor device.

[0003] For example, Patent Document 1 discloses a technique for improving both the thermal fatigue life and moisture resistance of the solder joints of the semiconductor device by pre-coating the semiconductor device with a polyamide resin having excellent heat resistance and moisture resistance before encapsulating the semiconductor device with an epoxy resin.

[0004] Patent Document 2 discloses a technique for suppressing warping of a semiconductor device by providing a block member having a lower linear expansion coefficient than a sealing resin, facing a circuit board.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2008-270455

[0006] Patent Document 2: Japanese Patent Application Publication No. 2018-67655

[0007] Although the components mounted on the semiconductor device include components with low linear expansion coefficients such as semiconductor elements, this does not become a problem in the case of existing silicone gel packaging. However, for semiconductor devices formed by molded packages composed of epoxy resins, etc., the peeling of the components from the molded resin becomes a problem due to the thermal cycle of the semiconductor device. Therefore, in recent years, there is a tendency to use molded resins with low linear expansion coefficients that are highly filled with fillers composed of ceramics in epoxy resins.

[0008] On the other hand, in contrast to the low linear expansion of the molding resin, the high filling of the filler increases the elastic modulus and resin viscosity of the molding resin. In order to miniaturize semiconductor devices, the molding resin also needs to encapsulate the semiconductor element, lead frame, and various wirings without holes.

[0009] However, in the case of a high-viscosity resin, the phenomenon that voids are mixed in the narrow gap region becomes a problem.

[0010] For example, in the technology described in Patent Document 1, since stress relaxation resin is applied to narrow gap portions such as the lower end of wiring or wire, the narrow gap region becomes narrower, and the encapsulation resin does not flow in this region, and voids remain. Furthermore, the fluidity of the high-viscosity encapsulation resin cannot be controlled, and there is a concern that the insulation reliability may be reduced due to the incorporation of voids into the insulation layer in the narrow gap region on the lower surface side of the lead frame.

[0011] Furthermore, the technique described in Patent Document 2 has no effect on the reduction in insulation reliability caused by voids mixed into the insulation layer in the narrow gap region on the lower surface side of the lead frame. Summary of the invention

[0012] Therefore, an object of the present invention is to provide a semiconductor device having high insulation reliability.

[0013] The semiconductor device involved in the present invention comprises: a semiconductor element; a lead frame having a mounting portion on the upper surface for mounting the semiconductor element; a packaging resin for packaging the lead frame and the semiconductor element in a manner that the external leads of the lead frame protrude to the outside; and a resin wall, which is arranged above the external leads in the lead frame and the internal leads between the mounting portion, and the thickness of the resin wall in the up-down direction is thicker than the thickness in the up-down direction from the lower surface of the packaging resin to the lower end of the lead frame.

[0014] Effects of the Invention

[0015] According to the present invention, the thickness of the resin wall in the vertical direction is thicker than the thickness in the vertical direction from the lower surface of the encapsulation resin to the lower end of the lead frame. Therefore, when filling the encapsulation resin, the inflow of the encapsulation resin to the upper surface side of the lead frame can be restricted, so that the encapsulation resin can be restrained from detouring from the upper surface side of the lead frame to the lower surface side. As a result, the voids generated on the lower surface side of the lead frame can be restrained, so that the insulation reliability of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a cross-sectional view of a main part of the semiconductor device according to the first embodiment.

[0017] Figure 2 This is a perspective view of a semiconductor element and a resin wall arranged on the upper surface of a lead frame included in the semiconductor device according to the first embodiment.

[0018] Figure 3 This is a cross-sectional view showing an inflow path of the sealing resin of the semiconductor device according to the first embodiment.

[0019] Figure 4 This is a cross-sectional view of a main part of a semiconductor device according to a second embodiment.

[0020] Figure 5 This is a cross-sectional view of a main part of a semiconductor device according to a third embodiment.

[0021] Figure 6 This is a cross-sectional view of a main part of a semiconductor device according to a fourth embodiment.

[0022] Figure 7 : is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the fifth embodiment is applied.

[0023] Figure 8 It is a cross-sectional view showing an inflow path of a sealing resin of a semiconductor device according to the related art.

[0024] Description of the label

[0025] 1 packaging resin, 2a, 2b semiconductor element, 3 lead frame, 5a, 5b wire wiring, 6 resin wall, 7 insulating sheet, 8 resin plate, 9 ceramic plate, 10 mounting portion, 11, 13 internal leads, 12, 14 external leads, 200 power conversion device, 202, 202A, 202B, 202C semiconductor device, 201 main conversion circuit, 203 control circuit. DETAILED DESCRIPTION

[0026] <Implementation Method 1>

[0027] Next, Embodiment 1 of the present invention will be described with reference to the drawings. Figure 1 This is a cross-sectional view of a main part of the semiconductor device 202 according to the first embodiment. Figure 2 It is a perspective view of a semiconductor element 2 b and a resin wall 6 arranged on the upper surface of a lead frame 3 included in a semiconductor device 202 .

[0028] like Figure 1 As shown, the semiconductor device 202 is a semiconductor power module widely used in home appliances, industrial applications, automobile applications, electric vehicles, etc. The semiconductor device 202 includes a sealing resin 1, semiconductor elements 2a, 2b, a lead frame 3, a bonding material 4, wire wirings 5a, 5b, and a resin wall 6.

[0029] The semiconductor elements 2a and 2b are, for example, power semiconductor elements that operate at 150°C or higher, and are mounted on the upper surface of the mounting portion 10 of the lead frame 3 via the bonding material 4. The semiconductor elements 2a and 2b may also include so-called wide bandgap semiconductors formed of materials such as silicon carbide (SiC), gallium nitride (GaN), or diamond, which have a larger bandgap than silicon (Si). Figure 1 In the embodiment, only two semiconductor elements 2a and 2b are mounted on the upper surface of the lead frame 3, but the present invention is not limited to this, and a required number of semiconductor elements can be mounted according to the application.

[0030] The lead frame 3 has a mounting portion 10, inner leads 11, 13, and outer leads 12, 14. The mounting portion 10 mounts semiconductor elements 2a, 2b on the upper surface. The inner leads 11, 13 are connected to the left and right ends of the mounting portion 10, respectively. The outer leads 12, 14 are connected to the inner leads 11, 13, respectively.

[0031] The lead frame 3 is usually formed of copper, but it is not limited to this. As long as it has the required heat dissipation characteristics, it is not particularly limited. For example, aluminum or iron can also be used, and materials obtained by compounding them can also be used. In addition, composite materials such as copper / invar / copper can also be used, and alloys such as SiCal or CuMo can also be used. In addition, the surface of the lead frame 3 is usually nickel-plated, but it is not limited to this. It can also be gold-plated or tin-plated, as long as it is a structure that can supply the required current and voltage to the semiconductor elements 2a, 2b. In addition, with respect to at least a portion of the lead frame 3 and the electrode pattern, in order to improve the adhesion with the resin, tiny bumps can also be provided on the surface, or a primer treatment or other adhesion enhancer can also be provided.

[0032] The bonding material 4 may be not only ordinary solder but also a sintered material composed of silver, and is not particularly limited as long as it has both required thermal conductivity and bonding properties.

[0033] The lead wire 5a connects the semiconductor element 2a and the inner lead 11. The lead wire 5b connects the semiconductor element 2b and the inner lead 13. As the lead wires 5a and 5b, a wire body having a circular cross section made of aluminum, silver, or gold is used, but it is not limited to this. For example, a lead wire obtained by forming a copper plate having a square cross section into a strip shape may also be used.

[0034] In addition, Figure 1In the embodiment, two lead wires 5a and 5b are connected to the semiconductor elements 2a and 2b, but the present invention is not limited thereto, and a required number of wires can be connected according to the current density of the semiconductor elements 2a and 2b, etc. In addition, the lead wires 5a and 5b can be joined by melting or ultrasonic joining with respect to metal sheets such as copper or tin, but the method and structure are not particularly limited as long as the required current and voltage can be supplied to the semiconductor elements 2a and 2b.

[0035] The encapsulating resin 1 encapsulates the lead frame 3 and the semiconductor elements 2a and 2b in such a manner that the external leads 12 and 14 of the lead frame 3 protrude to the outside. Specifically, the encapsulating resin 1 encapsulates the mounting portion 10 and the internal leads 11 and 13 in the lead frame 3 and the semiconductor elements 2a and 2b. The encapsulating resin 1 is formed using, for example, epoxy resin, but is not limited thereto, and any resin having a desired elastic modulus and heat resistance may be used.

[0036] The resin wall 6 is provided perpendicularly to the internal lead 13 on the upper surface of the internal lead 13 between the external lead 14 in the lead frame 3 and the mounting portion 10, and is encapsulated by the encapsulation resin 1. The thickness B of the resin wall 6 in the vertical direction is thicker than the thickness A in the vertical direction from the lower surface of the encapsulation resin 1 to the lower end of the lead frame 3. Here, the lower end of the lead frame 3 refers to the lower end of the mounting portion 10. In addition, the resin wall 6 is formed using epoxy resin, silicone resin, polyurethane resin, polyimide resin, polyamide resin, polyamideimide resin, or acrylic resin, but is not limited thereto, and any material having both insulation and adhesiveness may be used.

[0037] like Figure 1 and Figure 2 As shown in FIG. 1 , the height position of the upper end of the resin wall 6 is formed higher than the height position of the upper end of the lead wiring 5b. Here, the upper end of the lead wiring 5b refers to the highest position of the lead wiring 5b. In addition, the resin wall 6 is provided within 10 mm from the connection portion between the lead wiring 5b and the lead frame 3, and is closer to the external lead 14 side of the lead frame 3 than the connection portion. In this way, by providing the resin wall 6 on the external lead 14 side near the connection portion, the deformation of the lead wiring 5a, 5b can be effectively suppressed when the encapsulation resin 1 is filled.

[0038] In addition, the resin wall 6 is provided in only one direction relative to the lead wiring 5b, but is not limited thereto, and may be provided in two to four directions relative to the lead wiring 5b. In addition, it is preferred that at least one of the resin walls 6 is provided perpendicularly to the flow direction of the encapsulating resin 1 when the encapsulating resin 1 is filled.

[0039] As a method for forming the resin wall 6 on the lead frame 3, the resin is usually applied by a dispenser. The semiconductor elements 2a and 2b are bonded to the lead frame 3 via the bonding material 4, and the resin wall 6 is formed after the lead wirings 5a and 5b are formed, that is, before the encapsulation resin 1 is filled. In addition, if the height position of the upper end of the lead wiring 5a and 5b is high and the thickness of the resin wall 6 in the vertical direction cannot meet the desired thickness only by applying the resin by the dispenser, the resin wall 6 made as a block may be provided on the lead frame 3.

[0040] In the semiconductor device 202 on which the lead frame 3 is mounted, a narrow gap region is generated on the lower surface side of the mounting portion 10 . The narrow gap region is an important region for ensuring the insulation performance of the semiconductor device 202 .

[0041] The semiconductor elements 2a and 2b are generally components with a low linear expansion coefficient. For the encapsulation resin 1 composed of a highly elastic resin represented by epoxy resin, the linear expansion coefficient of the encapsulation resin 1 is set low in order to suppress the peeling of the semiconductor elements 2a and 2b and the encapsulation resin 1 associated with the thermal cycle. However, since the encapsulation resin 1 is highly filled with fillers for the purpose of reducing the linear expansion coefficient, there is a tendency for the viscosity to increase as the elastic modulus of the encapsulation resin 1 increases. Therefore, the fluidity of the encapsulation resin 1 becomes lower, so it is feared that filling into the narrow gap area becomes difficult, and holes are generated on the lower surface side of the mounting portion 10, and the insulation reliability of the semiconductor device 202 is reduced.

[0042] Next, the operation and effects of the semiconductor device 202 according to the first embodiment will be described in comparison with the related art. First, the related art will be described. Figure 8 It is a cross-sectional view showing an inflow path of the sealing resin 1 of the semiconductor device 102 according to the related art.

[0043] like Figure 8 As shown in FIG. 1 , in general, a method of filling the sealing resin 1 is to inject the sealing resin 1 from a predetermined point of the mold 50 and fill the inside of the mold 50. Figure 8 In the process, the encapsulating resin 1 is injected into the mold 50 from the injection port 51 .

[0044] In the case of the molded semiconductor device 102 equipped with the lead frame 3, the encapsulating resin 1 is injected from the side of the lead frame 3 indicated by R1. The encapsulating resin 1 injected from R1 is filled along two paths, namely, a path R2 passing through the upper surface side of the lead frame 3 and a path R3 passing through the lower surface side of the lead frame 3, to encapsulate the semiconductor device 102 set in the mold 50. At this time, since the path R3 passes through the narrow gap area, it takes more time to complete the filling of the encapsulating resin 1 compared with the path R2 injected at the same time.

[0045] As a result, the encapsulating resin 1 filled through the path R2 starts filling the region on the lower surface side of the lead frame 3 in a circuitous manner from the path R4 in a direction opposite to the path R3 after the filling is completed to the end of the mold 50. In the encapsulating resin 1 sandwiched between the path R3 and the path R4 on the lower surface side of the lead frame 3, air cannot escape, and voids are generated in the encapsulating resin 1, which significantly reduces the insulation reliability of the semiconductor device 102.

[0046] Next, the inflow path of the sealing resin 1 of the semiconductor device 202 according to the first embodiment will be described. Figure 3 It is a cross-sectional view showing an inflow path of the sealing resin 1 of the semiconductor device 202 .

[0047] like Figure 3 As shown, since the resin wall 6 is formed on the upper surface of the inner lead 13, the encapsulation resin 1 flowing in from the upper surface side of the lead frame 3 is restricted by the resin wall 6. In this way, by extending the time required until the encapsulation resin 1 flowing in from the path R2 fills the upper surface side of the lead frame 3, the filling of the upper surface side of the lead frame 3 is completed in a time substantially the same as the time required for filling the lower surface side of the lead frame 3 flowing in from the path R3.

[0048] As a result, the inflow of the sealing resin 1 from the path R4 can be suppressed, and the voids generated on the lower surface side of the lead frame 3 can be suppressed. The thicker the resin wall 6 in the vertical direction is, the longer the flow distance of the sealing resin 1 can be, and thus the greater the effect.

[0049] In the related art, the sealing resin 1 filled from the path R2 to the upper surface side of the lead frame 3 tends to deform the lead wires 5a and 5b due to the stress generated during the filling. The contact between the lead wires 5a and 5b and the semiconductor elements 2a and 2b and the contact between the lead wires 5a and 5b caused by the deformation of the lead wires 5a and 5b causes the electrical function of the semiconductor device 102 to be unable to be realized, resulting in characteristic defects.

[0050] In the semiconductor device 202 according to the first embodiment, the resin wall 6 reduces stress when the lead wirings 5a and 5b come into contact with the sealing resin 1, thereby suppressing deformation of the lead wirings 5a and 5b that occurs when the sealing resin 1 is filled.

[0051] As described above, in the semiconductor device 202 according to the first embodiment, the thickness of the resin wall 6 in the vertical direction is thicker than the thickness in the vertical direction from the lower surface of the encapsulating resin 1 to the lower end of the lead frame 3. Therefore, when the encapsulating resin 1 is filled, the inflow of the encapsulating resin 1 to the upper surface side of the lead frame 3 can be restricted, so that the encapsulating resin 1 can be prevented from detouring from the upper surface side to the lower surface side of the lead frame 3. As a result, the voids generated on the lower surface side of the lead frame 3 can be prevented, so that the insulation reliability of the semiconductor device 202 can be improved.

[0052] Furthermore, it is possible to suppress deformation of the lead wires 5a and 5b that occurs when filling the sealing resin 1. This can improve the durability of the semiconductor device 202 and improve the yield.

[0053] The resin wall 6 is provided within 10 mm of the connection portion between the lead wire 5b and the lead frame 3 and is located closer to the external lead 14 of the lead frame 3 than the connection portion. Thus, by providing the resin wall 6 on the external lead 14 side near the connection portion, deformation of the lead wires 5a and 5b can be effectively suppressed when the encapsulation resin 1 is filled.

[0054] The semiconductor elements 2a and 2b include wide bandgap semiconductors. Although cracks may occur in the encapsulation resin 1 due to differences in linear expansion coefficients of components when the semiconductor device 202 is used in a higher temperature region, cracks in the encapsulation resin 1 can be suppressed in the case of the semiconductor device 202. Therefore, when the semiconductor elements 2a and 2b including wide bandgap semiconductors such as SiC or GaN are mounted, the crack suppression effect becomes higher.

[0055] <Implementation Method 2>

[0056] Next, a semiconductor device according to Embodiment 2 will be described. Figure 4 It is a cross-sectional view of a main part of a semiconductor device according to Embodiment 2. In Embodiment 2, the same components as those described in Embodiment 1 are denoted by the same reference numerals, and the description thereof is omitted.

[0057] like Figure 4 As shown, in the second embodiment, the semiconductor device 202A further includes an insulating sheet 7 disposed at the lower end of the lead frame 3 .

[0058] The insulating sheet 7 is provided to be bonded to the lower end of the lead frame 3, i.e., the lower surface of the mounting portion 10 of the lead frame 3, and is used to ensure high insulation and heat dissipation of the mounting portion 10 of the lead frame 3. The insulating sheet 7 has a sheet layer 7a and a metal plate 7b, and the sheet layer 7a has insulation. The sheet layer 7a is formed by a resin cured product in which ceramic powder is dispersed, or a resin cured product in which a ceramic plate is embedded. The sheet layer 7a is bonded to the upper surface of the metal plate 7b, and the thickness of each component can be freely set. In addition, a metal foil can be used instead of the metal plate 7b.

[0059] As the sheet layer 7a, epoxy resin is generally used, but the material is not limited thereto and polyimide resin, silicone resin, acrylic resin or the like may be used as long as the material has both insulating properties and adhesive properties.

[0060] In addition, as the ceramic powder dispersed in the sheet layer 7a, Al2O3, SiO2, AlN, BN, or Si3N4, etc. are used, and the shape is mostly spherical, but not limited to this, and crushed, granular, flaky, or agglomerated, etc. can also be used. The ceramic powder can be filled in an amount that obtains the required insulation and heat dissipation properties.

[0061] In addition, as the metal plate 7b or the metal foil, copper foil or aluminum foil is generally used, but other materials may be used as long as they are metals having heat dissipation properties.

[0062] As described above, the semiconductor device 202A according to the second embodiment further includes the insulating sheet 7 disposed at the lower end of the lead frame 3. Therefore, the mounting portion 10 of the lead frame 3 and the insulating sheet 7 are in surface contact, and there is no region filled with the encapsulating resin 1 at the lower end of the lead frame 3, so that voids generated on the lower surface side of the lead frame 3 can be suppressed, thereby improving the insulation reliability of the semiconductor device 202A.

[0063] Furthermore, the resin wall 6 can suppress deformation of the lead wirings 5 ​​a and 5 b that occurs when the sealing resin 1 is filled.

[0064] In addition, when the insulating sheet 7 is not disposed on the entire lower end of the lead frame 3, that is, when the insulating sheet 7 is disposed only on a portion of the lower end of the lead frame 3, or when the lower end of the lead frame 3 and the insulating sheet 7 are not in contact, the filling area of ​​the encapsulating resin 1 on the lower surface side of the lead frame 3 is reduced due to the arrangement of the insulating sheet 7. Therefore, the flow of the encapsulating resin 1 to the lower surface side of the lead frame 3 is completed earlier than that to the upper surface side of the lead frame 3, and the generation of voids caused by the encapsulating resin 1 being rolled in on the lower surface side of the lead frame 3 can be suppressed.

[0065] <Implementation Method 3>

[0066] Next, a semiconductor device according to Embodiment 3 will be described. Figure 5It is a cross-sectional view of a main part of a semiconductor device 202B according to Embodiment 3. In Embodiment 3, the same components as those described in Embodiments 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.

[0067] like Figure 5 As shown, in the third embodiment, the semiconductor device 202B has two resin walls 6, one resin wall 6 is provided on one internal lead 13 between one external lead 14 in the lead frame 3 and the mounting portion 10, and the other resin wall 6 is provided on another internal lead 11 between another external lead 12 in the lead frame 3 and the mounting portion 10. The semiconductor device 202B further has a resin plate 8 connecting the upper ends of the two resin walls 6 to each other. The two resin walls 6 and the resin plate 8 are encapsulated by the encapsulation resin 1.

[0068] exist Figure 8 The related art shown has a problem that the stress generated by the difference in linear expansion coefficient between the semiconductor elements 2a, 2b and the lead frame 3 built into the semiconductor device 102 and the sealing resin 1 causes separation from various components due to the thermal history, thereby reducing reliability. In addition to separation from various components caused by the thermal cycle test based on the thermal history, there is also a problem that, if the linear expansion coefficients of various components are not coordinated, the entire semiconductor device 102 is warped, thereby reducing long-term reliability.

[0069] In contrast, the semiconductor device 202B according to the third embodiment includes two resin walls 6, one of which is provided on one internal lead 13 between one external lead 14 in the lead frame 3 and the mounting portion 10, and the other of which is provided on another internal lead 11 between another external lead 12 in the lead frame 3 and the mounting portion 10. The semiconductor device 202B further includes a resin plate 8 that connects the upper ends of the two resin walls 6 to each other.

[0070] Therefore, the stress caused by the difference in linear expansion coefficient between the semiconductor elements 2a, 2b, the lead frame 3, the insulating sheet 7 and the sealing resin 1 can be relieved by the resin plate 8, and the warping of the entire semiconductor device 202B can be suppressed. As a result, the long-term reliability of the semiconductor device 202B is improved.

[0071] The resin plate 8 does not need to be formed of the same material as the resin wall 6, and the material can be changed in accordance with the warpage amount required for the final product of the semiconductor device 202B. When the material is changed, the resin plate 8 after pre-curing can be easily manufactured by placing it on the resin wall 6 before curing, but the manufacturing method is not limited.

[0072] In addition, by selecting a material having a larger linear expansion coefficient than the linear expansion coefficient of the encapsulating resin 1 as the material of the resin plate 8, the linear expansion coefficients of the lead frame 3 and the insulating sheet 7, which are the built-in components, are close to each other, and the effect of reducing the amount of warpage generated in the semiconductor device 202B as a whole can be increased. Here, the shape and thickness of the resin plate 8 are not particularly limited, but the thicker the thickness, the larger the shape, and the larger the volume, the greater the effect.

[0073] In addition, similarly to the other embodiments, in the third embodiment, the formation of voids on the lower surface side of the lead frame 3 is suppressed, and deformation of the lead wires 5a and 5b is suppressed, thereby obtaining a semiconductor device with high insulation reliability.

[0074] <Implementation Method 4>

[0075] Next, a semiconductor device according to a fourth embodiment will be described. Figure 6 It is a cross-sectional view of a main part of a semiconductor device 202C according to Embodiment 4. In Embodiment 4, the same components as those described in Embodiments 1 to 3 are denoted by the same reference numerals, and description thereof is omitted.

[0076] like Figure 6 As shown, the semiconductor device 202C according to the fourth embodiment includes a ceramic plate 9 instead of the resin plate 8 , compared to the semiconductor device 202B according to the third embodiment.

[0077] As the ceramic material forming the ceramic plate 9, Al2O3, SiO2, AlN, BN, Si3N4, etc. are used, but there is no particular limitation as long as it has the required insulation properties.

[0078] As described above, the semiconductor device 202C according to the fourth embodiment includes two resin walls 6, one of which is provided on one internal lead 13 between one external lead 14 in the lead frame 3 and the mounting portion 10, and the other of which is provided on another internal lead 11 between another external lead 12 in the lead frame 3 and the mounting portion 10. The semiconductor device 202C further includes a ceramic plate 9 that connects the upper ends of the two resin walls 6 to each other.

[0079] The ceramic material forming the ceramic plate 9 absorbs less moisture than resin and can suppress expansion due to moisture absorption. Therefore, it can suppress moisture absorption into the semiconductor elements 2a and 2b mounted on the semiconductor device 202B, thereby improving the reliability of the semiconductor device 202C against moisture absorption.

[0080] In addition, similarly to the other embodiments, the semiconductor device 202C according to the fourth embodiment can also suppress the voids generated on the lower surface side of the lead frame 3 and suppress the deformation of the lead wirings 5a and 5b, thereby obtaining a semiconductor device 202C with high insulation reliability.

[0081] <Implementation method 5>

[0082] This embodiment applies the semiconductor device 202 according to the first embodiment to a power converter. The present invention is not limited to a specific power converter, but the case where the present invention is applied to a three-phase inverter will be described below as a fifth embodiment.

[0083] Figure 7 : is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the fifth embodiment is applied.

[0084] Figure 7 The power conversion system shown is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various power supplies, for example, it can be composed of a DC system, a solar cell, and a storage battery, and can also be composed of a rectifier circuit or an AC / DC converter connected to an AC system. In addition, the power supply 100 can also be composed of a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

[0085] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. Figure 7 As shown, the power conversion device 200 includes: a main conversion circuit 201 that converts DC power into AC power and outputs the AC power; and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201 .

[0086] Load 300 is a three-phase motor driven by AC power supplied from power converter 200. Load 300 is not limited to a specific use, and is a motor mounted on various electrical devices, for example, a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, and air conditioners.

[0087] The details of the power conversion device 200 are described below. The main conversion circuit 201 has a switching element and a freewheeling diode (not shown), and converts the DC power supplied from the power supply 100 into AC power by turning the switching element on and off, and supplies it to the load 300. The specific circuit structure of the main conversion circuit 201 is various, but the main conversion circuit 201 involved in this embodiment is a 2-level three-phase full-bridge circuit, which can be composed of 6 switching elements and 6 freewheeling diodes connected in reverse parallel to each switching element. Each switching element and each freewheeling diode of the main conversion circuit 201 is composed of a semiconductor device corresponding to any of the above-mentioned embodiments 1 to 3. In addition, the case where it is composed of the semiconductor device 202 involved in embodiment 1 is described here. The 6 switching elements are connected in series two by two to form upper and lower bridge arms, and each upper and lower bridge arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Moreover, the output terminals of each upper and lower bridge arm, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0088] In addition, the main conversion circuit 201 has a driving circuit (not shown) for driving each switching element, but the driving circuit can be built into the semiconductor device 202, or it can be a structure that is independent of the semiconductor device 202 and has a driving circuit. The driving circuit generates a driving signal for driving the switching element of the main conversion circuit 201, and supplies it to the control electrode of the switching element of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 described later, the driving signal for turning the switching element into the on state and the driving signal for turning the switching element into the off state are output to the control electrode of each switching element. When the switching element is maintained in the on state, the driving signal is a voltage signal (on signal) greater than or equal to the threshold voltage of the switching element, and when the switching element is maintained in the off state, the driving signal is a voltage signal (off signal) less than or equal to the threshold voltage of the switching element.

[0089] The control circuit 203 controls the switch elements of the main conversion circuit 201 to supply the desired power to the load 300. Specifically, the time (on time) at which each switch element of the main conversion circuit 201 should be in the on state is calculated based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on time of the switch element according to the voltage to be output. In addition, a control instruction (control signal) is output to a drive circuit of the main conversion circuit 201 so that an on signal is output to the switch element that should be in the on state and an off signal is output to the switch element that should be in the off state at each moment. The drive circuit outputs the on signal or the off signal as a drive signal to the control electrode of each switch element according to the control signal.

[0090] In the power conversion device according to the present embodiment, since the semiconductor device 202 according to the first embodiment is used as a switching element and a freewheeling diode of the main conversion circuit 201, it is possible to improve reliability.

[0091] In this embodiment, an example of applying the present invention to a 2-level three-phase inverter is described, but the present invention is not limited thereto and can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is used, but a 3-level or multi-level power conversion device may also be used. When power is supplied to a single-phase load, the present invention may also be applied to a single-phase inverter. In addition, when power is supplied to a DC load, the present invention may be applied to a DC / DC converter or an AC / DC converter.

[0092] In addition, the power conversion device to which the present invention is applied is not limited to the case where the above-mentioned load is an electric motor. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, and a contactless power supply system, and can also be used as a power conditioner for a solar power generation system and a power storage system.

[0093] Furthermore, the present invention can freely combine the various embodiments within the scope of the invention, and can appropriately modify or omit the various embodiments.

Claims

1. A semiconductor device comprising: Semiconductor components; a lead frame having a mounting portion on an upper surface of which the semiconductor element is mounted; an encapsulation resin for encapsulating the lead frame and the semiconductor element in such a manner that the external leads of the lead frame protrude to the outside; a resin wall provided on the inner leads between the outer leads and the mounting portion in the lead frame; as well as an insulating sheet disposed at the lower end of the lead frame, The thickness of the resin wall in the vertical direction is thicker than the thickness in the vertical direction from the lower surface of the encapsulating resin to the lower end of the lead frame. having two resin walls, The lead frame has two outer leads and two inner leads. One of the resin walls is provided on one of the inner leads between one of the outer leads and the mounting portion in the lead frame, The other resin wall is provided on the other inner lead between the other outer lead and the mounting portion in the lead frame, The semiconductor device further comprises a resin plate or a ceramic plate connecting the upper ends of the two resin walls to each other. The resin wall is provided within 10 mm from a connection portion between a wire wiring and the lead frame and is located closer to the outer lead side of the lead frame than the connection portion. The wire wiring connects the semiconductor element and the inner lead of the lead frame. The height position of the upper end of the resin wall is higher than the height position of the upper end of the lead wiring.

2. The semiconductor device according to claim 1, wherein The linear expansion coefficient of the resin plate is larger than the linear expansion coefficient of the encapsulating resin.

3. The semiconductor device according to claim 1 or 2, wherein: The semiconductor device includes a wide bandgap semiconductor.

4. A power conversion device, comprising: A main conversion circuit comprising the semiconductor device according to any one of claims 1 to 3, the main conversion circuit converting input power and outputting the converted power; and A control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

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