Monolithic microwave integrated circuit with backside interconnect for fan-out packaging

Abstract

A monolithic microwave integrated circuit (MMIC) with backside interconnects for fan-out packaging is disclosed. Fan-out packaging, such as fan-out wafer-level packaging (FOWLP) or fan-out panel-level packaging (FOPLP), facilitates high-density packaging of MMICs. However, the fan-out packaging may generate undesirable electromagnetic (EM) coupling between the MMIC die and metal features in a redistribution layer (RDL) of a FOW / PLP package and / or a next-level assembly (NHA). In an exemplary aspect, a circuit package according to the present disclosure includes the MMIC die and an RDL. The MMIC includes a chip side having components that may be undesirably coupled to metal signal lines (e.g., package metal interconnects) in the RDL. The chip side of the MMIC is oriented away from the RDL to reduce such EM coupling.

Description

Technical Field

[0001] The present application relates to packaging of radio frequency (RF) integrated circuits (ICs). Background Art

[0002] Mobile devices such as mobile phones require increasingly smaller integrated circuits (ICs), including radio frequency (RF) circuits. The performance of high-frequency RF circuits, especially monolithic microwave integrated circuits (MMICs), is often very sensitive to the coupling of electromagnetic (EM) energy to nearby structures. As IC packages and modules decrease in size, nearby metal features in the package or in the next-level assembly (NHA) can couple to these RF circuits and affect their performance. This coupling becomes increasingly a problem, especially for RF frequencies above 2 gigahertz (GHz). Summary of the invention

[0003] A monolithic microwave integrated circuit (MMIC) with backside interconnects for fan-out packaging is disclosed. Fan-out packaging, such as fan-out wafer-level packaging (FOWLP) or fan-out panel-level packaging (FOPLP), facilitates high-density packaging of the MMIC. However, fan-out packaging may generate undesirable electromagnetic (EM) coupling between the MMIC die and metal features in the redistribution layer (RDL) of the FOW / PLP package and / or the next-level assembly (NHA). In an exemplary aspect, a circuit package according to the present disclosure includes an MMIC die and an RDL. The MMIC includes a chip side having components that may be undesirably coupled to metal signal lines (e.g., package metal interconnects) in the RDL. The chip side of the MMIC is oriented away from the RDL to reduce such EM coupling.

[0004] The MMIC further includes backside interconnects, also known as thermal vias, so that the interface to the package metal interconnects in the RDL is from the backside of the die rather than the frontside. In this configuration, the MMIC die is less susceptible to interference from the underlying RDL itself or the substrate used in the NHA. This can also facilitate improved heat dissipation paths, such as through the RDL or through the overmolding layers of the circuit package.

[0005] Exemplary embodiments relate to a circuit package. The circuit package includes a first MMIC die and a secondary injection molding layer at least partially surrounding the first MMIC die. The circuit package further includes an RDL attached to a surface of the first MMIC die, the RDL including a plurality of signal lines connected to the conductors of the first MMIC die. The circuit package further includes an interconnect layer attached to the RDL and configured to electrically connect the plurality of signal lines in the RDL to a next level component.

[0006] Another exemplary embodiment relates to a method for packaging an MMIC die. The method includes overmolding a first MMIC die and forming an RDL over a surface of the first MMIC die. Forming the RDL includes coating a first signal line on a first conductive element in the first MMIC die, coating a second signal line on a second conductive element in the first MMIC die, and coating an insulating material to isolate the first signal line from the second signal line. The method further includes coating a ball grid array over the RDL such that a first ball is electrically connected to the first signal line and a second ball is electrically connected to the second signal line.

[0007] Those skilled in the art will understand the scope of the present disclosure and recognize other aspects of the present disclosure after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0009] Figure 1 is a cross-sectional view of an exemplary embodiment of a circuit package for a monolithic microwave integrated circuit (MMIC) die.

[0010] Figure 2 yes Figure 1 0014] A cross-sectional view of another exemplary embodiment of a circuit package having an MMIC die with the chip side facing up.

[0011] Figure 3 yes Figure 2 A cross-sectional view of another exemplary embodiment of a circuit package having a thermal path through a redistribution layer (RDL).

[0012] Figure 4A yes Figure 2 A cross-sectional view of another exemplary embodiment of a circuit package having a thermally conductive column extending through a secondary injection molded layer.

[0013] Figure 4B yes Figure 4A A cross-sectional view of another example of an embodiment in which a heat exchanger is attached to a thermally conductive post.

[0014] Figure 4C yes Figure 4A A cross-sectional view of another example of an embodiment in which a circuit layer is attached to a thermally conductive post.

[0015] Figure 5A yes Figure 2 A cross-sectional view of another exemplary embodiment of a circuit package wherein a second MMIC die is positioned laterally adjacent to a first MMIC die.

[0016] Figure 5B yes Figure 5A A cross-sectional view of another example of an embodiment in which a second RDL is attached to the overmold layer.

[0017] Fig. 6A yes Figure 2 0026] A cross-sectional view of another exemplary embodiment of a circuit package in which a second MMIC die is vertically stacked above a first MMIC die.

[0018] Figure 6B yes Fig. 6A A cross-sectional view of another example of an embodiment wherein a second MMIC die is flipped over a first MMIC die. DETAILED DESCRIPTION

[0019] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments, and show the best mode of practicing the embodiments. When reading the following description according to the accompanying drawings, those skilled in the art will understand the conception of the present disclosure, and will recognize the application of these concepts not particularly proposed herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0020] It will be understood that, although the terms first, second, etc. can be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0021] It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending" on another element, it can be directly on or directly on another element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly on" or "directly extending on another element", there is no intermediate element. Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "above" or "extending" on another element, it can be directly above or directly above another element, or there can also be an intermediate element. On the contrary, when an element is referred to as being "directly above" or "directly extending above another element", there is no intermediate element. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intermediate element. On the contrary, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0022] Relative terms, such as "below" or "above" or "above" or "horizontally" or "vertically", may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms, as well as those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0023] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used herein, the terms "comprises, comprising" and / or "includes, including" specify the presence of the features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined herein, the terms used herein should be interpreted as having a meaning consistent with that in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0025] A monolithic microwave integrated circuit (MMIC) with backside interconnects for fan-out packaging is disclosed. Fan-out packaging, such as fan-out wafer-level packaging (FOWLP) or fan-out panel-level packaging (FOPLP), facilitates high-density packaging of the MMIC. However, fan-out packaging may generate undesirable electromagnetic (EM) coupling between the MMIC die and metal features in the redistribution layer (RDL) of the FOW / PLP package and / or the next-level assembly (NHA). In an exemplary aspect, a circuit package according to the present disclosure includes an MMIC die and an RDL. The MMIC includes a chip side having components that may be undesirably coupled to metal signal lines (e.g., package metal interconnects) in the RDL. The chip side of the MMIC is oriented away from the RDL to reduce such EM coupling.

[0026] The MMIC further includes backside interconnects, also known as thermal vias, so that the interface to the package metal interconnects in the RDL is from the backside of the die rather than the frontside. In this configuration, the MMIC die is less susceptible to interference from the underlying RDL itself or the substrate used in the NHA. This can also facilitate improved heat dissipation paths, such as through the RDL or through the overmolding layers of the circuit package.

[0027] Figure 1 is a cross-sectional view of an exemplary embodiment of a circuit package 10 for an MMIC die 12. The circuit package 10 includes the MMIC die 12 surrounded by an overmold layer 14 and attached to an RDL 16. An interconnect layer 18 attaches the RDL 16 to an NHA 20, which may be a printed circuit board (PCB) or another component that supports the circuit package 10 and / or electrically connects the MMIC die 12 to other components in an RF device (e.g., a mobile device).

[0028] In this regard, the circuit package 10 may form a radio frequency (RF) module in which the MMIC die 12 is packaged using FOWLP, also known as wafer-level fan-out (WLFO) packaging. Other examples use FOPLP or similar packaging methods for packaging. FOWLP and FOPLP are thin-film processes that allow semiconductor-like processes (e.g., high-resolution photolithographic patterns, physical vapor deposition (PVD) metallization, and chemical vapor deposition (CVD) dielectrics) to be used to spread out (e.g., fan out) the dense input / output (I / O) connections on the MMIC die 12 to accommodate larger sizes on NHAs, such as PCBs, interposers, or chip-scale packages (CSPs).

[0029] For example, in one embodiment of the FOWLP process, a known good die (KGD) (e.g., the MMIC die 12 and a plurality of additional MMIC dies) and sometimes other passive components are precisely placed on a temporary carrier (not shown), often referred to as a reconstituted wafer, and epoxy overmolded to form an overmolded layer 14. The KGD may be formed from one or more MMIC wafers that are cut to form the MMIC die 12 and a plurality of additional MMIC dies, and then overmolded into an overmolded MMIC array. A portion of the overmolded layer 14 may be removed to expose a top surface and / or a bottom surface of the MMIC die 12, such that the overmolded layer 14 partially surrounds the MMIC die 12 (e.g., surrounds only a side of the MMIC die 12 or one of a side and a top or bottom of the MMIC die 12). One or more RDLs 16 and dielectric layers are formed over the exposed surface of the MMIC die 12, and semiconductor-like processes and tools are used to define vias to route metal traces from tightly spaced input / output (I / O) pads 22 on the MMIC die 12 to the periphery of the circuit package 10 (or, in the case of a multi-chip module, to other components within the same package, such as described below with respect to Figure 5A and 5B ). Thus, the RDL 16 includes a plurality of signal lines 24, 26, 28 connected to the I / O pads 22 (e.g., conductors of the MMIC die 12) and an insulating material 30 that isolates at least some of the signal lines 24 from each other. For example, the first signal line 24 may be isolated from the second signal line 26 and the third signal line 28.

[0030] Depending on whether a chip-first or chip-last approach is used, the RDL 16 interconnects (e.g., signal lines 24, 26, 28) are formed directly on top of the overmolded MMIC die 12, or on a carrier before the MMIC die 12 (and other components) are attached and overmolded. In some examples, the RDL 16 is formed as a multi-layer laminate. With the I / O pads 22 now redistributed (i.e., fanned out), the circuit package 10 can be attached to the NHA pads 32, which are arranged at a wider pitch on the NHA 20 (shown herein as a multi-layer PCB, although other configurations may be used). The circuit package 10 is attached to the NHA 20 using an interconnect layer 18 (e.g., a ball grid array, a land grid array, or other suitable interconnects) and the signal lines 24, 25, 28 in the RDL 16 are connected to the NHA pads 32. After the RDL layer 16 or interconnect layer 18 is formed, the overmolded MMIC array can be cut into circuit packages 10.

[0031] The MMIC die 12 includes an MMIC substrate 34 on which an active layer 36 is formed, which may be referred to as the chip side of the MMIC die 12. Figure 1 In the exemplary embodiment depicted, the MMIC die 12 is oriented with the chip side facing down, i.e., with the chip side facing the RDL 16. One or more components 38 that are sensitive to EM coupling may be part of or coupled to the active layer 36. For example, passive components 38 may be coupled to the active layer 36, such as RF transmission lines, tuning networks, interconnect conductors, etc. In some instances, one or more of these passive components 38 may be particularly sensitive to EM coupling with structures near the MMIC die 12. In some instances, the active layer 36 may further include EM-sensitive active elements, such as transistors and diodes.

[0032] The MMIC die 12 may also include a ground plane 40 on a surface of the MMIC die 12 opposite the active layer 36 (eg, a backside of the MMIC die 12). The ground plane 40 may be electrically connected to the RDL 16 by one or more grounded thermal vias 42 through the MMIC substrate 34.

[0033] For high frequency RF circuits such as MMIC die 12, the proximity of signal lines 24, 26, 28 in RDL 16 can cause undesirable coupling with EM sensitive components 38, thereby interfering with the normal operation and performance of the circuit in circuit package 10. To design high frequency circuits for use in such environments, especially those extending into the millimeter wave (mmW) frequency band, the effects of these adjacent metal features need to be carefully simulated and modeled. Such simulations may still not take into account all interference factors, and the resulting RF circuit or system performance may be affected.

[0034] Through careful design, the RDL 16 layer immediately adjacent to the MMIC die 12 can be used as a ground plane, which can effectively protect the circuit from other nearby metal traces. The impact of such a ground plane in the RDL 16 needs to be considered in the design of the MMIC die 12, as it will have a significant impact on the characteristics of the transmission line. This means that the unpackaged MMIC die 12 without a ground plane will behave very differently from the circuit package 10, which can complicate KGD testing and module troubleshooting at the wafer level.

[0035] Figure 21 is a cross-sectional view of another exemplary embodiment of a circuit package 10 having an MMIC die 12 with its chip side facing upward. To reduce or eliminate EM coupling between signal lines 24, 26, 28 in the RDL 16 and EM sensitive components 38 (e.g., passive components such as RF transmission lines for impedance matching, tuning networks, interconnect conductors, etc.) of the MMIC die 12, the chip side of the MMIC die 12 is oriented upward. That is, the chip side of the MMIC die 12 (e.g., the side having the active layer 36) is oriented away from the RDL 16.

[0036] In this regard, the surface of the MMIC die 12 attached to the RDL 16 includes a ground plane 40 (covering a portion or a majority of the backside) and I / O pads 22. The MMIC die 12 also includes backside interconnects, such as a plurality of thermal vias 42, 44, 46 to connect with corresponding signal lines 24, 26, 28 in the RDL 16. For example, a first signal thermal via 44 connects a first signal line 24 to a component 38 on the chip side of the MMIC die 12 (through an I / O pad 22), and a second signal thermal via 46 connects a second signal line 26 to another component 38 on the chip side (through another I / O pad 22). One or more ground thermal vias 42 connect the ground plane 40 (and the third signal line 28) to an element or component 38 on the chip side of the MMIC die 12.

[0037] In this configuration, the backside ground plane 40 of the MMIC die 12 serves to shield the components 38 in the MMIC die 12 with the chip side facing up from the signal lines 24, 26, 28 in the RDL 16 and the NHA 20. The active layer 36 of the MMIC die 12 is covered by the secondary injection molding layer 14. In addition, the RDL 16 is designed according to good RF design practices to properly shield the controlled impedance RF transmission lines using the appropriate topology for mmW circuits (e.g., microwave transmission strip, stripline, etc.). Conventional FOWLP packaging requires additional ground layers in the RDL 16, and the ground plane 40 can further define the ground reference for the signal lines 24, 26 in the RDL 16 to reduce or eliminate such ground layers in the RDL 16.

[0038] Figure 2An advantage of the embodiment of the circuit package 10 is that design optimization of the package routing in the RDL 16 and NHA 20 can be performed extensively without affecting the performance of the MMIC die 12, since it is effectively shielded by its own backside ground plane 40 and decoupled from package design issues. In addition, the backside of the MMIC die 12 is much flatter than the side of the chip, which may have thicker plated transmission lines and air bridge crossings. The planarity of the backside is also advantageous in the FOWLP packaging process, facilitating better sealing at the edges of the MMIC die 12, preventing composite mold creep during the secondary injection molding process, and providing better pattern uniformity during the molding process of the interconnect lines of the RDL 16.

[0039] Figure 3 is a cross-sectional view of another exemplary embodiment of a circuit package 10 having a thermal path through the RDL 16 . Figure 3 The circuit package 10 has the above Figure 2 The MMIC die 12 is depicted with the chip side facing up. Inverting the MMIC die 12 in the circuit package 10 in this manner has an impact on the direction of heat flow from the package to the NHA 20. In planar packaging technologies like FOWLP, there are two heat transfer paths: 1) through the bottom of the package (e.g., through the interconnect layer 18) into the NHA 20; and 2) through the top of the package (e.g., the sides of the overmold layer 14) into a heat exchanger (e.g., a heat sink or cooling plate).

[0040] In the latter case, for a conventional chip-side down configuration, thermal conductivity can be improved by exposing the back side of the MMIC die 12 (or exposing a heat spreader attached to the back side of the MMIC die 12) from within the overmolded layer 14 through a subtractive grinding / etching process or a selective molding process. Figure 3 In the exemplary circuit package 10 of FIG. 1 , the top of the MMIC die 12 is embedded in the overmold layer 14, rather than the backside. In this configuration, the most natural heat conduction path from the MMIC die 12 is through the interconnect layer 18 into the NHA 20. The ground plane 40 covers most of the backside of the MMIC die 12, so the thermal conductivity to the NHA 20 can be improved by contacting the backside with a dense array of grounded RDL vias 48 (or a large area via, which may be referred to as an embedded heat sink (EHS)) through the RDL 16 to spread and better transfer the heat. The grounded RDL vias 48 may be formed by the same metallization as the signal lines 24, 26, 28 in the RDL 16, such as copper. In this way, the RDL 16 provides a heat conduction path from the ground plane 40 to the NHA 20. The NHA 20 may similarly contain thermal vias 50 or a solid embedded heat sink to improve the conductivity to the NHA 20.

[0041] Figure 4A is a cross-sectional view of another exemplary embodiment of a circuit package 10 having a thermally conductive pillar 52 passing through the overmold layer 14 . Figure 4A The circuit package 10 has the above Figure 2 The MMIC die 12 is depicted with the chip side facing up. With this orientation, a highly thermally conductive path can also be created through the top of the circuit package 10 if a heat spreader is formed directly over a hot spot on the active layer 36 of the MMIC die 12. For example, a thermally conductive pillar 52 or other thermally conductive structure is formed over and near a heat source on the die (e.g., a transistor or other active element in the active layer).

[0042] The thermally conductive pillars 52 may be formed using currently practiced semiconductor processes, similar to the formation of copper bumps for flip chips with semiconductor dies attached. If the thermally conductive pillars 52 are appropriately exposed from the secondary injection molding layer 14, the thermally conductive pillars 52 may be used to conduct heat away from the top of the MMIC die 12 on the molded side of the circuit package 10. In this regard, the thermally conductive pillars 52 may be formed before or after the secondary injection molding layer 14 is applied. If formed before, the secondary injection molding layer 14 may be partially removed to expose the thermally conductive pillars 52.

[0043] Figure 4B yes Figure 4A 5 , wherein a heat exchanger 54 is attached to a thermally conductive post 52. The heat exchanger 54 may be attached to the thermally conductive post 52 and / or the overmolded layer 14 by suitable techniques, such as welding or brazing to the thermally conductive post 52 or by an adhesive (e.g., a thermally conductive adhesive). In this manner, the thermally conductive post 52 provides thermal conduction to the heat exchanger 54. The heat exchanger 54 may be a heat sink or cold plate, and may appropriately exchange heat by liquid, air, conduction, convection, etc.

[0044] Figure 4C yes Figure 4A 5 is a cross-sectional view of another example of an embodiment of the present invention, in which a circuit layer 56 is attached to a thermally conductive pillar 52. In addition to conducting heat, the thermally conductive pillar 52 can also provide electrical conduction to the functional parts of the MMIC die 12. For example, the circuit layer 56 can provide interconnections between the functional parts of the MMIC die 12, an RF antenna connected to the MMIC die 12, connections to external circuits, etc.

[0045] In other embodiments, the circuit package 10 may include multiple MMIC dies 12. The thermally conductive pillars 52 may provide connections between these MMIC dies 12. In some embodiments, the circuit package 10 may include multiple MMIC dies 12 arranged laterally in a common overmolding layer 14, as described below with respect to Figure 5A and 5BIn other embodiments, the circuit package 10 may include a plurality of MMIC dies 12 stacked vertically, as described below with respect to Fig. 6A and 6B as further described.

[0046] Figure 5A 1 is a cross-sectional view of another exemplary embodiment of the circuit package 10, wherein the second MMIC die 58 is positioned laterally adjacent to the first MMIC die 12. In this regard, the first MMIC die 12 and the second MMIC die 58 are surrounded by the overmolding layer 14 and attached to the RDL 16 in the above-described FOWLP process. The first MMIC die 12 includes a first MMIC substrate 34 having a first active layer 36 formed thereon, and the second MMIC die 58 includes a second MMIC substrate 60 having a second active layer 62 formed thereon, as described above with respect to Figure 1 Each of the first MMIC die 12 and the second MMIC die 58 is oriented with the chip side facing up—the first active layer 36 and the second active layer 62 are oriented away from the RDL 16 .

[0047] Each of the first MMIC die 12 and the second MMIC die 58 is connected to the NHA 20 through the RDL 16 and the interconnect layer 18. In addition, the first MMIC die 12 and the second MMIC die 58 can be interconnected. For example, the interconnection can be provided by one or more conductors 64 in the NHA 20 or the RDL 16. Additionally or alternatively, the first thermally conductive pillar 52 (as described above with respect to the first active layer 36) attached to the first active layer 36 can be connected to the NHA 20. Figure 4A The front side interconnection line 66 is connected to the second thermally conductive pillar 68 attached to the second active layer 62 to provide interconnection.

[0048] Figure 5B yes Figure 5A 1 is a cross-sectional view of another example of an embodiment of the present invention, wherein a second RDL 70 is attached to the overmold layer. The second RDL 70 is attached to the overmold layer 14, the first thermally conductive pillar 52, and the second thermally conductive pillar 68. The second RDL 70 can be formed in a manner similar to the first RDL 16 attached to the bottom side of the overmold layer 14, the first MMIC die 12, and the second MMIC die 58, and provides interconnections between the functional parts of the first MMIC die 12 and the functional parts of the second MMIC die 58.

[0049] Fig. 6A 1 is a cross-sectional view of another exemplary embodiment of the circuit package 10, wherein the second MMIC die 58 is vertically stacked on the first MMIC die 12. In this regard, the first MMIC die 12 is surrounded by the overmolding layer 14 and has a first thermally conductive pillar 52 passing through the overmolding layer 14, as described above with respect to Figure 4A The second MMIC die 58 is similarly oriented with the chip side facing up and is vertically stacked on the first MMIC die 12. A second thermally conductive pillar 68 is attached to the bottom side of the second MMIC die 58 to interconnect the first MMIC die 12 with the second MMIC die 58.

[0050] The second interconnect layer 72 attaches and connects the first thermally conductive pillar 52 and the second thermally conductive pillar 68. The second interconnect layer 72 may be a ball grid array, a land grid array, or another suitable interconnect similar to the first interconnect layer 18 that attaches the circuit package 10 to the NHA 20. The underfill layer 74 surrounds the second thermally conductive pillar 68 and fills the space between the first MMIC die 12 and the overmold layer 14.

[0051] Figure 6B yes Fig. 6A FIG. 1 is a cross-sectional view of another example of an embodiment of the present invention, wherein the second MMIC die 58 is flipped over the first MMIC die 12. In this example, the second MMIC die 58 is flipped over the first MMIC die 12, wherein the second thermally conductive pillars 68 are attached to the top side of the second MMIC die 58 to interconnect the first MMIC die 12 with the second MMIC die 58. The second interconnect layer 72 is attached to and connects the first thermally conductive pillars 52 and the second thermally conductive pillars 68.

[0052] In some examples, the second MMIC die 58 is also surrounded by the second overmold layer 76. The second MMIC die 58 can be further attached to the second RDL 70. In other examples, the second RDL 70 can connect the second MMIC die 58 to the second NHA 78 through the third interconnect layer 80. It should be understood that further embodiments may include additional MMIC dies arranged vertically, horizontally, or as described above with respect to Figures 5A-6B A combination of the arrangements described.

[0053] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A circuit package, comprising: a first monolithic microwave integrated circuit die having a chip side including one or more active elements of the first monolithic microwave integrated circuit die, the component susceptible to electromagnetic coupling being part of or coupled to the chip side; an overmolded layer at least partially surrounding the first MMIC die and covering the chip side; a redistribution layer attached to a surface of the first MMIC die opposite the chip side, wherein the redistribution layer includes a plurality of signal lines connected to the one or more active components on the chip side of the first MMIC die, wherein a length of the redistribution layer is equal to a length of the overmold layer; an interconnect layer attached to the redistribution layer and configured to electrically connect the plurality of signal lines in the redistribution layer to a next level component; as well as a plurality of thermal vias passing through the first MMIC die; in: A chip side of the first monolithic microwave integrated circuit die is oriented away from the redistribution layer to reduce electromagnetic coupling between the plurality of signal lines of the redistribution layer and the component sensitive to electromagnetic coupling; The surface of the first monolithic microwave integrated circuit die opposite to the chip side is the back side of the first monolithic microwave integrated circuit die; The circuit package further includes a ground plane on a portion of the backside of the first monolithic microwave integrated circuit die to shield the component from electromagnetic coupling with the plurality of signal lines of the redistribution layer; and At least one respective thermal via of the plurality of thermal vias is operable to connect the ground plane to at least one active element of the one or more active elements of the first monolithic microwave integrated circuit die.

2. The circuit package of claim 1 , wherein one or more, but not all, of the plurality of thermal vias passing through the first MMIC die are operatively connected to corresponding ones of the plurality of signal lines of the redistribution layer.

3. The circuit package of claim 1, wherein the redistribution layer provides a thermal conduction path from the back side of the first MMIC die to the next level components. 4 . The circuit package of claim 2 , further comprising a plurality of thermally conductive pillars passing through the overmolded layer.

5. The circuit package of claim 4, further comprising a heat exchanger attached to the overmolded layer; The plurality of thermally conductive pillars provide heat conduction to the heat exchanger.

6. The circuit package of claim 4, wherein the plurality of thermally conductive pillars are electrically connected to a second monolithic microwave integrated circuit die.

7. The circuit package of claim 6, wherein the second monolithic microwave integrated circuit die is attached to the circuit package over the first monolithic microwave integrated circuit die.

8. The circuit package of claim 6, wherein: the second monolithic microwave integrated circuit die is positioned laterally adjacent to the first monolithic microwave integrated circuit die; and The overmold layer at least partially surrounds the second monolithic microwave integrated circuit die.

9. The circuit package of claim 1, wherein the redistribution layer comprises a multi-layer laminate.

10. A method for packaging a monolithic microwave integrated circuit die, comprising: overmolding a first monolithic microwave integrated circuit die having a chip side including one or more active elements of the first monolithic microwave integrated circuit die, a first component and a second component sensitive to electromagnetic coupling as part of or coupled to the chip side; forming a redistribution layer over a surface of the first monolithic microwave integrated circuit die opposite the chip side, comprising: depositing a first signal line on a first input / output pad in the first MMIC die; depositing a second signal line on a second input / output pad in the first MMIC die; and depositing an insulating material to isolate the first signal line from the second signal line; depositing an interconnect layer over the redistribution layer to electrically connect to the first signal line and the second signal line; forming a first thermal via through the substrate of the first MMIC die to connect the first input / output pad to a first component on the chip side; forming a second thermal via through the substrate of the first MMIC die to connect the second input / output pad to a second component on the chip side; and forming a ground plane over a portion of the surface of the first MMIC die to shield at least one of the first component and the second component from electromagnetic coupling with the first signal line and the second signal line of the redistribution layer, The chip side of the first MMIC die is oriented away from the redistribution layer to reduce electromagnetic coupling between the first and second signal lines of the redistribution layer and the at least one of the first and second components sensitive to electromagnetic coupling.

11. The method according to claim 10, wherein: The surface of the first monolithic microwave integrated circuit die is a back side of the first monolithic microwave integrated circuit die opposite the chip side.

12. The method of claim 10, further comprising dicing the MMIC wafer to form the first MMIC die and a plurality of additional MMIC dies.

13. The method of claim 12, wherein overmolding the first MMIC die comprises overmolding the first MMIC die and the plurality of additional MMIC dies into an overmolded MMIC array.

14. The method of claim 13, further comprising dicing the overmolded MMIC array after depositing the interconnect layer.

15. The method of claim 13, further comprising interconnecting the first monolithic microwave integrated circuit die with a second monolithic microwave integrated circuit die of the plurality of additional monolithic microwave integrated circuit dies.

16. The method of claim 10, further comprising: Prior to forming the redistribution layer, a portion of the overmold is removed from the surface of the first monolithic microwave integrated circuit die.

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