Circuit and method for secondary-side rectified voltage sensing in a power converter

Abstract

The present disclosure relates to circuits and methods for secondary-side rectified voltage sensing in a power converter. An isolated switch-mode power converter converts power from an input source into power for an output load. A digital controller senses a secondary-side voltage, such as a rectified voltage, of the power converter. The secondary-side voltage is divided using a high-impedance voltage divider. The resulting divided voltage is provided to a voltage sensor within the digital controller. The voltage sensor level-shifts the provided voltage and buffers the resulting level-shifted voltage. The buffered level-shifted voltage is provided to a tracking analog-to-digital converter (ADC) for digitization. The buffered signal provided to the tracking ADC has a high current capability so that the voltage input to the tracking ADC can converge quickly before the tracking ADC outputs a digital value for the sensed secondary-side voltage.

Description

Technical Field

[0001] The present application relates to isolated switch-mode power converters, and in particular to circuits and related methods for sensing a voltage, such as a rectified voltage, on a secondary side of an isolated switch-mode power converter. Background Art

[0002] An isolated switch-mode direct current (DC) to DC power converter uses a transformer to convert power from an input source to power for an output load. Such a power converter includes a power switch that converts the DC input power into alternating current (AC) power, which is fed to the primary side of the transformer. The AC power supplied on the secondary side of the transformer is rectified and filtered to provide DC power to the output load. The primary side power switch is typically controlled by a pulse width modulation (PWM) control signal. A controller generates a PWM control signal having a frequency and duty cycle suitable for meeting the power requirements of the output load.

[0003] The controller typically uses a linear closed-loop feedback technique to keep the output voltage near the desired target. The controller can be implemented using analog or digital circuits and can be located on the primary or secondary side of the power converter. In order to maintain the integrity of the isolation barrier of the power converter, any signals that cross between the primary and secondary sides must pass through an isolator (e.g., transformer, optocoupler). Isolated switch-mode power converters increasingly use digital controllers located on the secondary side to avoid passing the output voltage, which must be sensed by the controller for linear closed-loop feedback control, through an analog isolator at the primary-secondary boundary. In addition, locating the controller on the secondary side allows for convenient communication between the controller and components of the output load, for example, for load management, without the need for an isolator.

[0004] However, some techniques used by the controller may require information about the input voltage or current on the primary side of the power converter. For example, linear feedback control techniques can be enhanced with feedforward control techniques to quickly compensate for input voltage transients. However, feedforward control techniques require the use of the input voltage or an estimate thereof from the primary side. Similarly, the controller may need to detect a primary side fault condition, which also requires information about the input voltage or current. The input voltage or current can be sensed directly by the secondary side controller, but this requires an analog isolator, which is preferably avoided. Alternatively, the input voltage or current can be estimated based on the output voltage or current, which can be sensed on the secondary side of the power converter. However, typically, the output voltage is low-pass filtered by an output capacitor and a load resistor. The delay caused by the low-pass output filter means that changes in the input voltage can only be detected in the output voltage after a considerable time lag. Such a hysteresis may make it impossible to use the output voltage for the purpose of feedforward control and / or primary side fault detection.

[0005] Typically, a rectified voltage is available on the secondary side of an isolated power converter, before the output filter, i.e., between the transformer and the output filter. Input voltage transients can be detected in the rectified voltage without incurring delays in the output filter. Therefore, the rectified voltage can be used to estimate the input voltage with only minimal delay. The rectified voltage can also be used for other purposes, including estimating the magnetic flux of the transformer and measuring the time delay between the issuance of a PWM control signal and the corresponding pulse in the rectified voltage.

[0006] To achieve such goals, circuits and methods are needed that can accurately sense the secondary side voltage, including the rectified voltage, which may be changing rapidly. Such sensing should be energy-efficient, and the associated circuits should be feasible to implement in a digital controller on the secondary side of an isolated power converter. Summary of the invention

[0007] According to one embodiment of a voltage sensor for tracking a secondary side voltage of an isolated switch mode power converter, the voltage sensor includes a first sensing terminal, a first level shifter, a first input buffer, and a tracking analog-to-digital converter (ADC). The first sensing terminal is used to connect to a node of the secondary side voltage being tracked and has a first sensing voltage. The first level shifter is configured to shift the first sensing voltage to provide a first level shifted voltage. The first level shifted voltage is provided to a first input buffer, which outputs a first buffered output having a voltage corresponding to the first level shifted voltage and having a first buffered current higher than the current input to the first input buffer. The tracking ADC digitizes the first buffered output to provide a digital value corresponding to the secondary side voltage being tracked.

[0008] According to one embodiment of a method for sensing a secondary side voltage within an isolated switch mode power converter, the method includes sensing a first sense voltage at a first sense terminal, wherein the first sense voltage corresponds to the secondary side voltage. The first sense voltage is shifted to provide a first level shifted voltage. The first level shifted voltage is buffered to provide a first buffered output having a voltage corresponding to the first level shifted voltage. An available current driven from the first buffered output is higher than an input current of a first input buffer. An output of the first buffer is digitized using a tracking analog-to-digital converter (ADC) to provide a digital value corresponding to the secondary side voltage.

[0009] According to an embodiment of a switch mode power converter using an isolated topology to convert power from an input source into power for an output load, the switch mode power converter includes a primary side, a transformer, and a secondary side. The primary side includes a power stage coupled to an input source, the power stage including one or more power switches. The transformer includes a primary winding coupled to the power stage, and a secondary winding. The secondary side includes a rectifier circuit, a filter circuit, and a voltage sensor. The rectifier circuit is coupled to the secondary winding and provides a first rectified voltage at a first rectified voltage node. The filter circuit is inserted between the first rectified voltage node and the output of the switch mode power converter. The filter circuit is configured to filter the first rectified voltage and provide a filtered voltage at the output. The voltage sensor includes a circuit that is largely the same as the above-mentioned voltage sensor, but additionally includes a resistor divider that couples the secondary side voltage node being sensed to the sensing terminal of the voltage sensor.

[0010] According to an embodiment of an alternative switch-mode power converter using an isolated topology to convert power from an input source into power for an output load, the switch-mode power converter includes a primary side, a transformer, and a secondary side. Except for a voltage sensor on the secondary side, these circuits are largely the same as the corresponding circuits of the switch-mode power converter described above. The voltage sensor of the alternative power converter is configured to estimate the voltage of the input source based on a first rectified voltage. The voltage sensor includes a first sensing terminal, a front end, and a tracking analog-to-digital converter (ADC).

[0011] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The elements of the drawings are not necessarily to scale with respect to each other. The same reference numerals represent corresponding similar parts. The features of the various illustrated embodiments may be combined unless they are mutually exclusive. The embodiments are depicted in the drawings and described in detail in the subsequent description.

[0013] Figure 1 A circuit diagram of an isolated switch-mode power converter including a controller having a voltage sensor for sensing a secondary-side voltage is shown.

[0014] Figure 2 shows a method for a voltage sensor such as Figure 1 A circuit for a voltage sensor) including a tracking analog-to-digital converter (ADC) and an ADC front end.

[0015] Figure 3 A circuit is shown for a level shifter that is part of an ADC front end and compensates for variations in input and supply voltages.

[0016] Figure 4 A circuit for an ADC front end is shown that corrects errors due to various stress effects, where the correction uses digital compensation.

[0017] Figure 5 A circuit for an ADC front end is shown that corrects errors due to various stress effects, where the correction uses a charge pump.

[0018] Figure 6 The corresponding waveforms of voltages and other signals within an isolated voltage converter utilizing the voltage sensors described herein are shown.

[0019] Figure 7 A circuit for an alternative ADC front end using a current amplifier is shown.

[0020] Figure 8 A method for sensing the secondary side voltage is shown. DETAILED DESCRIPTION

[0021] Embodiments described herein provide circuits and related methods for sensing the voltage on the secondary side of an isolated switch-mode power converter. Although the voltage sensor circuit described herein can be used to sense the output voltage of a power converter, the circuit provides special benefits when used to sense the rectified voltage of an isolated switch-mode power converter, and the circuit will be described primarily in the context of sensing the rectified voltage. Such a rectified voltage can be sensed at one or more rectified voltage nodes located at the output of the secondary-side rectifier, where the rectified voltage node typically provides the rectified voltage to the output filter of the power converter. The rectified voltage typically consists of a series of approximately square pulses (i.e., square waves). Sensing and digitizing such a rectified voltage requires a voltage sensing circuit with a high bandwidth, i.e., the voltage sensing circuit can detect and track the steep rising edge or falling edge of the square wave, and can accurately track the rectified voltage during its active pulse. In a typical application, the voltage sensing circuit provides at least a digital voltage sample corresponding to each rectified voltage pulse. Depending on the rectifier circuit topology, one or two such rectified voltage pulses may be generated for each switching cycle of the power converter, which means that the voltage sensor typically provides a voltage sample once or twice per switching cycle.

[0022] In addition to providing digitized voltage samples, the voltage sensor also provides timing signals corresponding to the rising and falling edges of the rectified voltage pulses. Such timing signals can be used to measure pulse widths for purposes such as calculating volt-second metrics for transformer flux, detecting primary-side fault conditions, and determining the delay from when the digital controller sets the PWM signal until the corresponding rectified voltage pulse appears on the secondary side.

[0023] The voltage sensor circuit is preferably integrated in the secondary side digital controller, in which case such a circuit must be feasible to implement using the same processing technology used in manufacturing the digital controller. Typically, the secondary side voltage to be sensed must be shifted to a voltage range feasible for the input of the digital controller. This can be achieved using a resistor divider. For example, the rectified voltage can alternate between 0V and 12V, while the input of the digital controller may only be able to handle voltages up to about 3V, so a 4:1 voltage divider is required. In order to minimize the power loss in the voltage divider, the resistance of the voltage divider should be large. However, the large resistance of such a voltage divider limits the current that can be used to drive the analog-to-digital converter (ADC) in the digital controller. In other words, the large resistance forms a low-pass filter together with the input capacitance of the ADC in the digital controller, which limits the speed at which the ADC can track the secondary side voltage being sensed.

[0024] The circuit and method described below solve these problems by introducing a front-end circuit for tracking the ADC. The front end is used to level shift and buffer the secondary side voltage as provided by the voltage divider. The resulting level-shifted and buffered voltage is provided to the tracking ADC. The voltage sensor circuit can track the secondary side voltage with minimal delay without significantly affecting the rise or fall time of the pulse of the secondary side voltage. In addition, the described circuit is feasible for implementation using digital or mixed signal processing techniques, which are commonly used to manufacture power converter controllers.

[0025] The following detailed description and associated drawings provide embodiments of voltage sensor circuits and related methods for sensing secondary side voltage within a power converter. The described embodiments provide specific examples for the purpose of explanation and are not intended to be limiting. Otherwise, features and aspects from the example embodiments may be combined or rearranged unless the context does not allow this.

[0026] The described voltage sensor circuit can be used to sense the secondary side rectified voltage, which in turn can be used to estimate the input voltage of an isolated power converter. The accuracy and minimal delay of the voltage sensing allows a digital controller to use the estimated input voltage for purposes such as feed-forward control to address input voltage transients, and to detect primary side fault conditions.

[0027] First, a voltage sensor circuit is described within an embodiment of an isolated switch-mode power converter using a full-bridge power stage on the primary side and a center-tapped secondary winding. This is followed by a more detailed circuit for the voltage sensor, which includes a level shifter, a buffer stage, and a tracking analog-to-digital converter (ADC). Next, an alternative level shifter is described that includes various error compensation circuits to improve accuracy, followed by a front-end circuit that corrects for long-term drift errors. Next, waveforms corresponding to voltages and other signals within the voltage converter are described. This is followed by another alternative ADC front end that uses a current amplifier instead of the level shifter and buffer of the previous ADC front end. Finally, a method for voltage sensing is described.

[0028] Voltage Sensing in Isolated Switch-Mode Power Converters

[0029] Figure 1 An isolated switch mode power converter 100 is shown, which includes, among other things, voltage sensors 180, 190 for sensing the secondary side voltage. The power converter 100 also includes an input 102, an output 104, a rectified voltage node 106, a power stage 110, a transformer 120, an isolator 130, a rectifier 140, an output filter 150, and a digital controller 170. The input 102 is for coupling to an input power source and is supplied with an input voltage V INThe output 104 is coupled to an output load (eg, a microprocessor) and provides an output voltage V OUT .like Figure 1 As shown, electrical (galvanic) isolation is provided by a transformer 120 and an isolator 130 , which together divide the power converter 100 into a primary side and a secondary side.

[0030] The input voltage V from the input power supply IN is provided to the power stage 110, which couples the voltage to the transformer 120 using power switches. The power stage 110 shown includes four power switches Q1, Q2, Q3, Q4 oriented in a full-bridge configuration. The power switches are controlled via a driver 112, which is connected to a switch control signal output from the isolator 130. During an active interval within a positive half-cycle of the power converter 100, switches Q1 and Q3 are set to conduct, thereby connecting the input V across the transformer 120. AB A positive voltage is provided to transformer 120. During an active interval in the negative half cycle of power converter 100, switches Q2 and Q4 are set to conduct, thereby providing a positive voltage across the input V of transformer 120. AB A negative voltage is provided to the transformer 120. In addition, there may be an idle interval during which the switches Q1, Q2, Q3, Q4 are not conducting and no voltage is applied across V AB The voltage is supplied to the transformer 120 .

[0031] Figure 1 The power switches Q1, Q2, Q3, Q4 shown are metal oxide semiconductor field effect transistors (MOSFETs), such as enhancement mode MOSFETs, but other switch types may be used. For example, in some applications, junction field effect transistors (JFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), or other types of power transistors may be preferred.

[0032] The transformer 120 includes a primary winding 122 having N1 turns, secondary windings 124a, 124b each having N2 turns, and a core 126. The secondary windings 124a, 124b are connected together at a center tap. RECT The rectified voltage node 106 is coupled to the center tap. Ignoring practical effects such as the resistive losses and leakage inductance of the transformer 120, the turns ratio N2 / N1 determines the rectified voltage V RECT The input voltage V of the transformer 120 AB The ratio of the amplitude.

[0033] The rectifier circuit 140 is configured to rectify the voltage output from the secondary windings 124a, 124b to provide a rectified voltage V at the rectified voltage node 106. RECT .like Figure 1 As shown, the rectifier circuit 140 includes rectifier switches SR1 and SR2, each of which has an associated driver. The rectifier switches SR1, SR2 are controlled by a rectifier controller 172 (preferably located within the controller 170). Other rectifier circuits or techniques may be used. For example, a diode may couple each external terminal of the secondary windings 124a, 124b to a rectified voltage node, with the center tap coupled to the ground of the load. In another alternative configuration, four diodes in a bridge configuration may be used with a secondary winding without a center tap. In general, as with Figure 1 Compared to the active rectification using power switches SR1, SR2 shown, diode-based rectification is not preferred due to the power losses associated with diodes, especially for low secondary side voltages. The rectification switches SR1, SR2 shown are enhancement mode MOSFETs, but as with the power switches Q1, Q2, Q3, Q4, other switch types may be preferred in some applications.

[0034] The output filter 150 uses an output inductor L O and output capacitor C O Rectified voltage V RECT (In some applications, other filter types (including high-order filters and / or active filters) may be preferred.) The resulting filtered output voltage V OUT is provided to output 104 to be coupled to a load (not shown) of power converter 100. Note that the rectified voltage V RECT The frequency of the pulse train corresponding to the switching frequency of the power stage 110 is composed, and the filtered output voltage V OUT Also, note that filter 150 produces a significant delay between voltage changes at its input (rectified voltage node 106 ) and output node 104 , and that this delay depends on the amount of current drawn by the load coupled to output 104 .

[0035] The controller 170 and its components may be implemented using a combination of analog hardware components (such as transistors, amplifiers, diodes, and resistors), and a processor circuit that primarily includes digital components. The processor circuit may include one or more of a digital signal processor (DSP), a general-purpose processor, and an application-specific integrated circuit (ASIC). The controller 170 may also include a memory and one or more timers, the memory including instructions or data for use by the processor circuit, the memory being, for example, a non-volatile memory such as flash memory. The controller 170 inputs a sensor signal, such as a signal that corresponds to the output voltage VOUT and the rectified voltage V RECT The corresponding signal.

[0036] The controller 170 is responsible for controlling the power converter 100 so as to supply necessary power to the load. The controller 170 senses the rectified voltage V RECT and output voltage V OUT , and uses the sensed voltage to generate a control signal V for controlling the rectifier circuit 140 and the power switch of the power stage 110 PWM_SR1 、V PWM_SR2 、V PWM_Q1 、V PWM_Q2 、V PWM_Q3 、V PWM_Q4 .

[0037] The rectifier controller 172 generates a control signal V for the rectifier switches SR1 and SR2. PWM_SR1 、V PWM_SR2 , so as to provide a (non-negative) rectified voltage V at the rectified voltage node 106 RECT These control signals V PWM_SR1 、V PWM_SR2 Based on the rectified voltage V RECT , a sensed version of , a signal provided by PWM generator 174, and / or a sensed current flowing through rectifier switches SR1, SR2. (For ease of illustration, such current sensing is not shown.) Since such rectification techniques are well known in the art, further details about rectifier controller 172 are not provided.

[0038] The controller 170 further includes a PWM generator 174 that generates a switch control signal V for controlling the power switch of the power stage 110. PWM_Q1 、V PWM_Q2 、V PWM_Q3 、V PWM_Q4 The switch control signal V output from the controller 170 PWM_Q1 、V PWM_Q2 、V PWM_Q3 、V PWM_Q4 is provided to the secondary side of the isolator 130, which in turn provides the primary side control signal to the driver 112. The PWM generator 174 typically comprises a linear feedback controller, such as a proportional integral derivative (PID) controller. The PWM generator 174 inputs the output voltage V provided by the voltage sensor 190. OUT Sensing version, such as V OUT_DIG , and compare this voltage with the reference (target) voltage V TARGET The comparison is performed to determine a control parameter for generating a switch control signal.

[0039] There are several control techniques that can be used by the PWM generator 174. For example, the PWM generator 174 can generate a control signal with a fixed switching frequency and a variable duty cycle, in which case the determined control parameter is the duty cycle. Alternatively, the PWM generator 174 can generate a control signal with a fixed pulse width and a variable frequency, in which case the control parameter is the switching frequency. In another alternative, the PWM generator 174 can generate a phase shift modulation (PSM) signal, in which case the control parameter is the phase shift. These and other techniques are well known in the field of feedback control. Because such techniques are well known and are not critical to understanding the unique aspects of the voltage sensing circuit described herein, no further details about such control techniques are provided.

[0040] The conditioning circuit 107 regulates the rectified voltage V RECT , to provide voltages VSENP and VSENN suitable for being sensed by the voltage sensor 180 in the controller 170. For example, the conditioning circuit 107 can convert the rectified voltage V RECT to a certain range that is within the voltage input limits of the controller 170 and the voltage sensor 180. Figure 1 The conditioning circuit 107 is shown as a resistor divider in FIG. 1 , but in some implementations, the conditioning circuit 107 may additionally or alternatively include a filter, an amplifier, etc. Similarly, the conditioning circuit 105 conditions the output voltage V OUT , to provide a voltage suitable for sensing by the second voltage sensor 190. The conditioning circuit 105 is also shown as a resistor divider, but may include other components in some applications. In a preferred implementation, regardless of their specific topology, the conditioning circuits 107, 105 provide a voltage suitable for sensing by the secondary side voltage being sensed (e.g., V RECT 、V OUT ) provides high impedance to minimize power losses caused by voltage sensing.

[0041] The voltage sensor 180 includes a tracking ADC 184 and an ADC front end 182. Because the conditioning circuit 107 has a high impedance, it is generally unable to provide the high current levels required for rapid digitization of the voltages VSENP, VSENN to the voltage sensor 180. As explained in detail in the embodiments described below, the ADC front end 182 provides voltage level shifting and / or buffering to provide the tracking ADC 184 with high current levels that enable rapid voltage stabilization and subsequent digitization. The ADC front end 182 may additionally include an edge detector (not shown for ease of illustration) for detecting the rising edge of the rectified voltage pulse, which may be used, for example, to help the tracking ADC 184 quickly return to the steady-state value of the rectified voltage pulse. In addition, the edge detector may be used to determine the width of the rectified voltage pulse. In addition, the controller 170 may use the timing signals from the PWM generator 174 and the edge detector to determine the timing of the rectified voltage pulse from the PWM control signal (e.g., V PWM_Q1 、V PWM_Q3 ) until the time delay of the corresponding rectified voltage pulse at the rectified voltage node 106.

[0042] Digital voltage V RECT_DIG is output from the voltage sensor 180 and can be provided to V IN Estimator 176, V IN Estimator 176 is shown as optional. IN The estimator 176 inputs the digitized voltage V corresponding to the rectified voltage pulse. RECT_DIG , and for example based on the digitized voltage V RECT_DIG and the turns ratio N2 / N1 of the transformer 120 to estimate the input voltage V IN The controller 170 can use the digitized voltage V RECT_DIG or (similarly) the estimated input voltage V IN , for feedforward control, fault detection, transformer flux estimation, etc. Since the input voltage V IN This usage of is generally known and is not necessary for understanding the unique aspects of the present invention involving voltage sensing circuits and methods, and therefore is not described in further detail.

[0043] A second voltage sensor 190 is shown for sensing the output voltage V OUT , and outputs the digital sensing output voltage V OUT_DIG The second voltage sensor 190 may be configured like the voltage sensor 180 .

[0044] Voltage sensor circuit with level shifting and buffering

[0045] Figure 2 It shows that it can be Figure 1The voltage sensor 200 is an embodiment of a voltage sensor 200 used in the power converter 100 of the embodiment of the present invention. The voltage sensor 200 includes a tracking ADC 280 and an ADC front end 210. The voltage sensor 200 inputs a first voltage VSENP and a second voltage VSENN, and outputs a digitized value V corresponding to the difference between these voltages VSENP and VSENN. RECT_DIG .

[0046] The ADC front end 210 is configured to connect the Figure 1 The conditioning circuit 107 shown in the figure inputs a secondary side voltage (such as a rectified voltage V RECT ). Assuming the rectified voltage V RECT The voltage pulse has a sufficient duration, and the voltage sensor 200 provides a voltage pulse at least once (which corresponds to at least once or twice per switching cycle of the power converter) with the rectified voltage V RECT The corresponding measurement result V RECT_DIG (A full-bridge or similar rectifier produces two rectified voltage pulses per switching cycle, while a half-bridge or similar rectifier produces only one rectified voltage pulse per switching cycle.) The rectified voltage measurement V RECT_DIG Can be used to estimate the input voltage V IN The ADC front end 210 supports tracking fast transients (e.g., fast transients with a slope of up to 7V / μs for V IN transients), and tracking relatively narrow rectified voltage pulses (e.g., down to 350ns). In addition, the voltage sensor 200 detects rising and falling edges, which can be used to determine the width of the rectified voltage pulse, and / or the time delay between when an active interval is commanded by the PWM generator 174 and when a corresponding rectified voltage pulse is sensed on the secondary side, for example. The voltage sensor 200 senses voltages as low as 0V.

[0047] Tracking ADC 280 digitizes the differential input voltage (VBUFP-VBUFN) by matching the input voltage to a voltage VTRK generated within tracking ADC 280. A low input impedance differential amplifier 286 generates an input voltage VSEN from the differential input voltage (VBUFP-VBUFN) provided to tracking ADC 280. (The amplifier 286 shown provides unity gain, i.e., VSEN=VBUFP-VBUFN. In other embodiments, a variant amplifier may provide non-unity gain to match the voltage range of VSEN to that of VTRK.) Because differential amplifier 286 has a low input impedance, the voltage level at its input quickly swings back to a new level after a voltage transient as long as sufficient current is provided to its input. A digital-to-analog converter (DAC) register 284 provides the digital code to DAC 285, which in turn generates an approximate voltage VTRK. The approximate voltage VTRK is compared to the input voltage VSEN by comparator 288. The comparator 288 outputs a high signal to indicate that the internally generated approximate voltage VTRK is greater than the input voltage VSEN, and outputs a low signal otherwise.

[0048] The up / down indicator output from the comparator 288 is provided to the ADC controller 282. The ADC controller 282 uses the up / down indicator from the comparator 288 to manipulate the approximate voltage VTRK to be higher or lower. If the up / down indicator indicates that the approximate voltage VTRK is higher than the input voltage VSEN, the ADC controller 282 decreases the value in the DAC register 284. If the up / down indicator indicates that the approximate voltage VTRK is lower than the input voltage VSEN, the ADC controller 282 increases the value in the DAC register 284. The ADC controller 282 adjusts the value of the DAC register 284 until the up / down indicator switches between its two states, indicating that the approximate voltage VTRK has converged to the input voltage VSEN. Upon reaching this state or reaching the end of the sampling period, the ADC controller 282 latches the final value provided to the DAC register 284 and outputs the value as the digitized voltage V RECT_DIG .

[0049] The rate at which the tracking ADC 280 can provide digital samples is determined by the speed at which the ADC controller 282 can adjust the value used for the DAC register 284, the number of iterations required for the approximate voltage VTRK to converge to the input voltage VSEN, and the time required for the input voltages VBUFP, VBUFN to settle to steady-state values ​​after a voltage transient. Figure 6 As discussed in the waveform of FIG. 1 , the DAC register 284 is preloaded with the last digitized voltage V stored from the previous rectified voltage pulse at the rising edge of the rectified voltage pulse. RECT_DIG, the number of iterations can be reduced. Because the previous voltage pulse provides a good voltage estimate for the current voltage pulse, the tracking ADC 280 can converge more quickly. (The ADC front end 210 provides an edge indicator, which the ADC controller 282 can use as a trigger to load the previous DAC value into the DAC register 284.) In addition, the step size used in adjusting the DAC register value can be dynamically set so that a large step is used immediately when a rectified voltage pulse is detected, and a smaller step is used after a certain number of iterations, or after a switch of the up / down indicator is detected. For example, after preloading the DAC register 284 after detecting the rectified voltage pulse, and after waiting for a stable period, the ADC controller 282 can begin to adjust the DAC register value with 7 code steps per iteration. Once the ADC controller 282 detects a change in the up / down indicator from the comparator 288, the ADC controller 282 can reduce the step size to 3 code steps for the next iteration. Once the up / down indicator from comparator 288 changes polarity again, ADC controller 282 may reduce the step size to 1 code step.

[0050] Fast settling of the input voltage to the tracking ADC 280 requires low impedance (high current) which cannot be directly supplied by the high impedance conditioning circuit 107. This problem is solved by a high bandwidth ADC front end 210.

[0051] The ADC front end 210 includes an edge detector 250, unity gain buffers 260p, 260n, and a level shifter 220. The unity gain buffers 260p, 260n provide buffered outputs VBUFP, VBUFN to the tracking ADC 280. The buffers 260p, 260n provide low impedance to the tracking ADC 280 and provide the high current levels required for fast voltage settling times. Since depletion mode MOSFETs are generally not available in small channel length technologies (such as those used to manufacture the (largely digital) controller 170, e.g., 65nm), the unity gain buffers 260p, 260n use a push-pull output stage including N- and P-channel enhancement mode MOSFETs to source / sink current to / from the tracking ADC 280.

[0052] However, it is of great significance to use an enhancement mode MOSFET rather than a depletion mode MOSFET in the push-pull output stage. The n-channel MOSFET of the output stage (which draws current to ground) requires a gate-to-source control voltage of at least several hundred millivolts (e.g., >600mV) to be applied to turn on and provide the necessary buffering (unity gain amplification). An output stage based on such an enhancement mode MOSFET has no ability to buffer voltages below these levels, and relatedly, no ability to provide these low voltage levels at its output. To address this problem, the level shifter 220 shifts the input voltages VSENN, VSENP upward by, for example, 0.6V, thereby providing the shifted voltages VSHFTN, VSHFTP to the buffers 260n, 260p. The combination of the level shifter 220 and the buffers 260n, 260p allows input voltages as low as 0V to be digitized. For example, the input voltage between 0V and 2.1V can be level shifted and buffered by the ADC front end 210 so that the voltage range can be accurately digitized by the tracking ADC 280. By using the same level shifter and buffer circuits for both the first input VSENP and the second input VSENN, the voltage sensor 200 achieves good common-mode rejection to mitigate inaccuracies that may be generated by noise in the power or ground supplies.

[0053] The level shifter 220 includes a first level shifter stage and a second level shifter stage. The first level shifter stage performs level shifting on a first input voltage VSENP (also referred to as a signal voltage), and the second level shifter stage performs level shifting on a second input voltage VSENN (also referred to as a reference voltage). The first level shifter stage includes a current source 222p, which provides a reference current I to the first p-channel MOSFET P1. REF . Constant reference current I REF Establishing a positive and constant source-to-gate voltage V SG1 (In other words, the gate-to-source voltage of MOSFET P1 is negative.) This in turn provides a level-shifted output voltage VSHFTP=VSENP+V SG1 The second level shifter stage is similarly configured so that VSHFTN = VSENN + V SG2 The same reference current level I is provided by current sources 222p and 222n. REF In the case of MOSFET P1, P2, the source-to-gate voltage V SG1 、V SG2 Nominally identical, resulting in identical voltage shifts to the signal and reference input voltages (VSENP, VSENN).

[0054] The edge detector 250 compares the signal voltage input (VSENP) to a reference voltage VREF and provides an output indicating, for example, whether the input voltage (VSENP) is within an active pulse. For example, VREF may be set to 1 V when the signal voltage VSENP is expected to switch between 0 V and 2 V. The output of the edge detector 250 may be used, for example, by components within the digital controller 170 to determine the duration of a rectified voltage pulse, determine the hysteresis between when the PWM generator 174 commands the generation of an active pulse on the primary side and when a corresponding rectified voltage pulse occurs on the secondary side, and the like.

[0055] Level shifter with error compensation feedback circuit

[0056] As the input signal voltage VSENP varies within its range, as the supply voltage driving the current sources 222p, 222n varies from a nominal value, and / or as temperature varies, Figure 2 The level shifter 220 may produce slight to moderate inaccuracies. In order to provide accurate voltages VBUFP, VBUFN to the tracking ADC 280, the input voltages VSENP, VSENN should be shifted by the same voltage offset. This implies that the source-to-gate voltage V SG1 、V SG2 Although these voltages (such as Figure 2 ) are nominally the same, but the voltage range applied to the source signal input VSENP results in a Figure 2 The channel length modulation of the source follower topology shown, and the source to gate voltage V SG1 For example, an active rectifier pulse of 2V supplied to the input VSENP results in a source-to-drain voltage V of about 2.6V for the first MOSFET P1. SD1 , and a source-to-drain voltage V of about 0.6V for the second MOSFET P2 SD2 For the same current I through MOSFET P1 and P2 REF , this difference in their respective source terminal voltages relative to their respective drain terminal voltages results in a source-to-gate voltage V for MOSFETs P1, P2 GS Although the resulting source-to-gate voltage difference is relatively small, e.g., about 10 mV, and may be considered negligible in some contexts, the voltage difference is large enough to prevent accuracy levels as low as 1%, which is desirable for a voltage sensor.

[0057] Figure 3 A detailed circuit 300 for a level shifter is shown, which is similar to Figure 2The invention is a level shifter of the type shown in FIG. 1 , but it includes an error compensation loop to provide the same source-to-drain voltage level to the MOSFETs P1, P2 in order to further improve the consistency of the level shifting provided by the source follower level shifter circuit to the two signal inputs VSENP, VSENN. By maintaining the same source-to-drain voltage for the MOSFETs P1, P2, the source-to-gate voltage V SG The value is controlled to be smaller than that used for Figure 2 The corresponding voltage of the level shifter 220 is closer.

[0058] The level shifter 300 includes a current mirror for providing a reference current I to both the first MOSFET P1 and the second MOSFET P2. REF The power supply VDD33 provides a nominal voltage of 3.3V to the current mirror, but as shown in the figure, this voltage can vary by up to 10%. The current source 322 sets the reference current level I REF The current mirror further includes a reference p-channel MOSFET P REF and the first mirror MOSFET P MIR1 and the second mirror MOSFET P MIR2 . Mirror MOSFET P REF , P MIR1 , P MIR2 The gate terminals of each mirror in are connected together, and each of the source terminals in is connected to the power supply VDD33. Therefore, the gate-to-source control voltage V for each mirror MOSFET in the mirror MOSFET is GS same, thus forcing the same current I REF Flows through a first level shifter stage including MOSFET P1 and a second level shifter stage including MOSFET P2.

[0059] The first compensation loop 310 is configured to force the drain voltage of the first MOSFET P1 to be the same as the gate voltage of the first MOSFET P1. The compensation loop 310 includes a first amplifier 312, the differential input of which is connected to the gate terminal and the drain terminal of the first MOSFET P1. The first amplifier 312 sources or sinks an additional current to the compensation resistor R1, thereby enhancing the reference current I REF , so that the voltage drop across R1 is driven to be the same as the signal input voltage VSENP, i.e., the gate-to-drain voltage V for the first MOSFET P1 GD1=0. The gate terminal and drain terminal of the second MOSFET P2 are connected to a reference voltage (e.g., ground), so that no compensation loop is required. In the case where the gate terminal and drain terminal of each MOSFET in MOSFET P1, P2 have the same voltage, and the two MOSFETs have the same current I REF In this case, the channel modulation effect is eliminated, which means that both MOSFETs have the same source-to-drain voltage V SD This in turn forces the gate-to-source voltage V GS Almost the same.

[0060] The channel modulation effect can also affect the mirror MOSFET P REF , P MIR1 , P MIR2 By including cascaded MOSFETP MIR_CAS , P CAS1 , P CAS2 The second compensation loop 320 mitigates or eliminates this effect. The second compensation loop 320 includes a second amplifier 322, the differential input of which is connected to the mirror MOSFET P REF , P MIR1 The output of the second amplifier 322 is connected to the drain terminals of the first cascade MOSFET P CAS1 and the second cascode MOSFET P CAS2 The gate (control) terminal of the REF , these cascade MOSFETs P CAS1 , P CAS2 The gate-to-source voltage V GS are the same, i.e. they have the same voltage at their respective source terminals. This in turn means that the mirror MOSFET P MIR1 , P MIR2 The drain terminals of the mirror MOSFET P are at the same potential. REF , P MIR1 , P MIR2 Each of the drain terminal, the source terminal and the gate terminal of each mirror MOSFET in the circuit is at the same respective voltage, thereby ensuring that the reference current I is accurately replicated in the first level shifter stage including the MOSFET P1 and the second level shifter stage including the MOSFET P2. REF . (For the first cascade MOSFET P CAS1 and the second cascode MOSFET P CAS2 The source to drain voltage V SDmay differ significantly, but this has an important effect on the level shifter voltage V SG1 、V SG2 No substantive impact.)

[0061] The combination of the current mirror, cascode MOSFETs and compensation loops 310, 320 of the level shifter 300 drives the source-to-gate voltages of the MOSFETs P1, P2 to nearly the same value, thereby ensuring that the signal input voltage VSENP and the reference signal input voltage VSENN are shifted by the same amount, for example 600 mV.

[0062] Over the expected range of input voltage (e.g., VSENP-VSENN = 0 to 2.1V), over the variation of the power supply (e.g., + / -10% of VDD33), and over a large temperature range (e.g., -40°C to 125°C), Figure 3 The level shifter circuit 300 typically provides a highly accurate level shift, e.g., 1% or better. This good accuracy is maintained assuming that the level shift MOSFETs are well matched with respect to offset and drift. For example, by matching the biases for the body, gate, and drain nodes, and by laying out the MOSFET devices together but in separate wells, offset and drift can be minimized. However, even with these precautions, stress-related drift may cause inaccuracies to develop over time. P-channel MOSFET devices are particularly susceptible to stress-related drift, and in particular, are more susceptible to such drift than corresponding N-channel MOSFET devices. P-channel MOSFETs with small channel lengths have a significant problem with positive bias temperature instability.

[0063] Error compensation for stress-related drift

[0064] As described above, stress effects cause the gain and / or offset of the MOSFETs (particularly P-channel MOSFETs) of the level shifter circuit and / or buffer to drift over time. Stress due to temperature, pressure, and aging can cause this drift. In order to maintain good voltage sensor accuracy, this drift must be mitigated, for example, by compensating for the drift. This can be achieved by measuring the voltage difference across the input voltages VSENP, VSENN, measuring the voltage difference across the buffer output voltages VBUFP, VBUFN, and applying compensation that forces these voltage differences to be the same. This compensation mitigates the effects of ADC front ends (such as Figure 2 and Figure 3 Figure 2 shows stress-related gain and offset drift of the level shifter circuit and buffer circuit within the ADC front end (shown in Figure 2).

[0065] Figure 4A voltage sensing circuit 400 is shown, which includes a compensation circuit for mitigating stress-related drift. The voltage sensor 400 includes an ADC front end 410 and a tracking ADC 280, the ADC front end 410 including a level shifter 300 and buffers 260n, 260p. Each of these circuits is similar to Figure 2 or Figure 3 The corresponding circuits in are similarly configured and therefore will not be described in further detail. Figure 2 In the circuit 200, the buffers 260n and 260p include feedback resistors R1 and R2. The current DAC 464 and the current source 462 are combined to source or sink the compensation current I CMP Through the first feedback resistor R1. Compensation current I CMP A compensation voltage V is generated across the first resistor R1. CMP , the compensation voltage V CMP Can be used to compensate for gain and / or offset drift in the level shifter 300 and buffers 260n, 260p. The current DAC and current source can be similarly coupled to the positive side buffer 260p, rather than to the negative side buffer 260n. However, the illustrated embodiment is preferred because providing compensation at the negative side buffer 260n avoids channel length modulation issues that may complicate compensation applied to the positive side buffer 260p.

[0066] The current source 462 shown sources a current of 10 μA, while the current DAC 464 sinks a current between 0 and 20 μA, resulting in a compensation current I CMP The range is ±10μA, and the compensation voltage V CMP The range is ±20mV. The current DAC 464 preferably has a 6-bit digital input (64 levels), which means that each DAC step corresponds to a current change of 0.3125μA and a compensation voltage change of 0.625mV. Figure 4 denoted as 'compensation count' in the figure) to achieve the compensation voltage V CMP , so that the voltage input difference is equal to the buffer output difference, that is, VSENP-VSENN=VBUFP-VBUFN. The current DAC 464 should be set to its midpoint (e.g., 32 for the 6-bit DAC shown as an initial default) and can be left there if stress-related compensation is not required. This setting corresponds to a 10 μA current drawn by the DAC 464 and a zero compensation voltage V across the feedback resistor R1. CMP The resolution of DAC 464 is preferably 1 / 2 the resolution of DAC 285 of tracking ADC 280 in order to mitigate the impact of any noise introduced by stress effect compensation on tracking ADC 280 .

[0067] The digital input of the DAC 464 is generated by a stress effect compensator 470, which samples the input voltages VSENP, VSENN and the buffer voltages VBUFP, VBUFN, and adjusts the output of the DAC 464 until the input voltage difference and the buffer voltage difference are the same, i.e., VSENP-VSENN=VBUFP-VBUFN. While stress-related compensation is being performed, the compensation enable signal CMP_EN is input to the compensator 470 and enables its components. Since stress-related effects typically occur slowly over time, the compensation enable signal CMP_EN can only be activated at a relatively low rate. If the DAC input (compensation count) is relatively stable, the compensation enable signal CMP_EN can disable the stress effect compensator 470, thereby avoiding unnecessary adjustments to the DAC 464, and the associated noise and power consumption. When the compensator 470 is enabled, the compensation clock signal CLK_FE_CMP drives the rate at which compensation updates are provided. As described with respect to Figure 6 As explained more fully in the waveform of FIG. 1 , for the case where the rectified voltage is being sensed, the compensation provided by the stress effect compensator 470 is preferably for the rectified voltage V RECT is updated once for each pulse in.

[0068] The stress effect compensator 470 includes a switched capacitor network 472, a comparator 474, a D flip-flop 476, and an up / down counter 478. The switched capacitor network 472 samples the input and buffer voltages VSENN, VSENP, VBUFN, VBUFP using capacitors C1, C2, C3, C4. When the compensation clock CLK_FE_CMP is high (this is in Figure 4 1), the switches in the first group are closed so that C1 is charged with voltage VSENP, C2 is charged with voltage VBUFP, C3 is charged with voltage VBUFN, and C4 is charged with voltage VSENN. During the second phase, when the compensation clock CLK_FE_CMP is low (at Figure 4 During this second phase (denoted as Φ2), the switches of the first group are opened and the switches within the second group are closed to connect capacitors C1 and C2, and capacitors C3 and C4. During this second phase (Φ2), the input voltage of comparator 474 is given by:

[0069]

[0070] From equation (1), we can see that the comparator input V IP -V IN Driving to zero is equivalent to driving VSENP-VSENN=VBUFP-VBUFN.

[0071] During the second phase (Φ2) of the clock CLK_FE_CMP, the comparator 474 is enabled so that it amplifies and compares its input signal V IP 、V IN Once the preamplifier of comparator 474 has stabilized, when V IP >V IN Comparator 474 generates a digital high signal when CLK_FE_CMP is low, and generates a digital low signal otherwise. The comparator output is latched by D flip-flop 476 in response to latch signal CLK_FE_LATCH. The latch signal is activated at a stable time after the start of the second phase (Φ2) of clock CLK_FE_CMP. For example, comparator 474 is enabled when CLK_FE_CMP goes low, and is known to be stable within 100ns. Therefore, 100ns after the falling edge of CLK_FE_CMP, CLK_FE_LATCH is asserted, which causes D flip-flop 476 to latch the (stable) output from comparator 474.

[0072] The output Q of the D flip-flop 476 is input to the up / down selector of the counter 478. For each cycle of the compensator, the count in the counter 478 is updated according to the up / down selector input. The counter 478 can be updated with a small delay after the input of the D flip-flop 476 has been latched by the latch signal CLK_FE_LATCH. As shown, the counter 478 is enabled by the enable signal CLK_DAC_EN and is clocked by the clock count signal CLK_CNT. The clock count CLK_CNT runs at a fairly fast rate, such as 100MHz, and the enable signal CLK_DAC_EN provides an active pulse so that the counter is updated once in each cycle of the compensator. For example, a 50ns delay after the latch signal CLK_FE_LATCH rises can assert an active pulse of 10ns on the enable signal CLK_DAC_EN. The 50ns delay is included to allow time for the D flip-flop 476 to stabilize after it is latched, and the pulse width of 10ns provides an update to the 100MHz counter clock CLK_CNT. As long as V IP >V IN , the counter 478 increases its count, otherwise it decreases its count. Once the counter 478 starts switching between two adjacent counts, the compensation voltage V CMP has converged to a voltage that compensates for stress-related drift.

[0073] As shown, the output of the counter 478 is provided to the current DAC 464. In an alternative embodiment (not shown), a latch may be inserted between the counter 478 and the DAC 464. The latch is enabled so that the latch inputs a new value from the counter 478 only after the counter has been increased or decreased for several consecutive clock cycles, or only after the count has changed a certain threshold. In contrast, repeated switching of the comparator output, and the associated switching between two count values ​​of the counter 478 indicate convergence. Detection of convergence can be used to stop latching (updating) the "compensation count" provided to the current DAC 464, thereby avoiding unnecessary noise. Relatedly, the stress effect compensator 470 can be enabled, for example, by setting the compensation enable signal CMP_EN to inactive, which also saves power. After a certain period of time, or after detecting some other event that may cause stress-related drift (e.g., temperature, voltage, or time changes above a certain threshold), the compensator 470 and / or the above-mentioned latch can be re-enabled.

[0074] Alternative error compensation for stress-related drift

[0075] Figure 4 The description thereof provides a stress-dependent compensator 470 that utilizes a digital counter 478 and a current DAC 464. Other techniques may be preferred in some applications. Figure 5 One such alternative embodiment of a voltage sensing circuit for compensating for stress-related drift is shown. The circuit utilizes an analog charge pump to compensate for stress-related drift instead of Figure 4 Digital counter 478. Figure 5 Many circuits in the voltage sensing circuit 500 are related to Figure 4 The corresponding circuits in the figures are the same or similar, and only the circuits that are obviously different are described below.

[0076] Figure 5 5 shows a voltage sensing circuit 500, which includes an ADC front end 510 and a stress-related compensator 570. The ADC front end 510 and the stress-related compensator 570 are shown in FIG. Figure 4 The ADC front end shown is largely the same, except that there is no current DAC for providing a compensation current to the feedback resistor R1 of the buffer 260n. Instead, the ADC front end 510 inputs an offset current I OFF_P ,I OFF_N , offset current I OFF_P ,I OFF_N is applied to the feedback resistors R2, R1 of the buffers 260p, 260n, thereby generating an offset voltage across the feedback resistors R2, R1, which can be used to compensate for stress-related drift. OFF_P ,I OFF_N Provided by stress-dependent compensator 570.

[0077] The stress-dependent compensator 570 includes a switched capacitor network 472, a comparator 474, and a D flip-flop 476, each of which is configured as Figure 4 . And Figure 4 As in the example, the compensation enable signal CMP_EN can disable the stress effect compensator 570, thereby preventing the offset current I OFF_P ,I OFF_N The stress-related compensator 570 further includes a charge pump 577, a negative offset generator 578n, and a positive offset generator 578p. The positive offset generator 578p and the negative offset generator 578n provide an offset current I to the ADC front end 510. OFF_P ,I OFF_N .like Figure 4 As in the compensator 470, when V IP >V IN , that is, VBUFP-VBUFN>VSENP-VSENN, the D flip-flop 476 provides a high output, otherwise it provides a low output. However, the output of the D flip-flop 476 is provided to the charge pump 577 instead of being provided to the counter.

[0078] The charge pump 577 includes: a push-pull output stage based on MOSFET, a reference current I CP The charge pump current source and the MOSFET driver shown as an AND gate. The charge pump clock signal CP_CLK is input to the AND gate and determines whether the charge pump is active (sourcing / sinking current). When the charge pump is active and the output of the D flip-flop 476 is high, the low-side MOSFET Q CPL turns on, thereby drawing the charge pump voltage from node V CP Discharge current I CP , and from the charge pump capacitor C CP This reduces the charge pump voltage V CP When the charge pump is active and the output of D flip-flop 476 is low, the high-side MOSFET Q CPH turns on, thereby feeding the charge pump voltage node V CP Source current I CP , and increase the node V CP The voltage at .

[0079] The negative offset generator 578n inputs the charge pump voltage V CP , and based on this voltage and the bias resistor R B Generates negative offset current I OFF_N More specifically, buffer 579n is biased by resistor R B The charge pump voltage V is copied at one endCP , thus generating a current (V CP / R B ). This current is replicated via the current mirror shown to provide an offset current I to the feedback resistor R1 within the ADC front end 510. OFF_N =(V CP / R B ). When the buffer voltage difference increases to a value higher than the input voltage difference, that is, VBUFP-VBUFN>VSENP-VSENN, the charge pump voltage V CP reduces and offsets the current level I OFF_N This increases the buffer voltage VBUFN, thereby forcing the buffer voltage difference VBUFP-VBUFN to converge towards the input voltage difference VSENP-VSENN.

[0080] Positive offset generator 578p provides bias current I to feedback resistor R2 of buffer 260p. OFF_P The bias current I OFF_P Corresponding to the nominal offset current I OFF_N , if the output of D flip-flop 476 (and comparator 474) switches between high and low, a nominal offset current I OFF_N , that is, when (VBUFP-VBUFN)≈(VSENP-VSENN), the nominal offset current I OFF_N By setting the input of buffer 579p to the reference voltage V REF To determine the bias current I OFF_P , the reference voltage V REF The midpoint between the charge pump supply voltage VDD and ground, V REF = VDD / 2. Buffer 579p across bias resistor R B The reference voltage is copied. The resulting current I OFF_P =(V REF / R B ) is replicated by a current mirror and provided to the feedback resistor R2 of the buffer 260p so as to generate a bias voltage across the feedback resistor R2.

[0081] When the buffer voltage difference VBUFP-VBUFN deviates from the input voltage difference VSENP-VSENN, the offset current I OFF_N from its nominal bias value (equivalent to I OFF_P ) is adjusted so that a compensation voltage is generated across the feedback resistor R1, which forces the buffer voltage difference and the input voltage difference to be the same or nearly the same.

[0082] Voltage waveform of voltage sensor

[0083] Figure 6 Shown with Figure 1 The waveform 600 corresponding to the power converter 100 includes Figure 4 The voltage sensing circuit 400. The first waveform 610 corresponds to the primary side gate drive signal. Figure 1 The power converter 100 generates an active signal V PWM_Q1 、V PWM_Q3 To enable the power switches Q1 and Q3, and when the active signal V PWM_Q2 、V PWM_Q4 The first waveform 610 is high when the power switches Q2 and Q4 are enabled. The pulses of the first waveform 610 correspond to the input V across the transformer 120, except for the delays through the isolator, driver, and power switches. AB The second waveform 620 corresponds to the rectified voltage V RECT , for example, as in Figure 1 The rectified voltage V appears at the rectified voltage node 106 RECT .exist Figure 6 The rising edge of the first waveform 610 produces a rising edge in the rectified voltage waveform 620 after a delay indicated as 'rising delay' in FIG. 1 . This delay includes delays through the isolator 130, the driver 112, the power switches Q1, Q2, Q3, Q4, and the transformer 120. After the falling edge of the first waveform 610, a corresponding 'falling delay' occurs.

[0084] exist Figure 6 Indicated as V RECT_BUF The third waveform 630 corresponds to Figure 4 The differential output of the ADC front end 410, namely V RECT_BUF =VBUFP-VBUFN. The impedance of the level shifter 300 and the buffer 260p, 260n circuits causes V RECT_BUF The rising and falling edges of the rectified voltage V RECT This is indicated by the 'buffer stable < 250ns' in the third waveform 630. Figure 2 and Figure 4 The tracking ADC 280 shown should not be enabled until the differential output V RECT_BUF has settled to a steady-state value. This is achieved by: RECT After the rising edge of , the programmable time threshold (VRS_TRACK_THRS) is waited until the tracking ADC is enabled. This is shown in the fourth waveform 640, which shows the enable signal V for the tracking ADC. ADC_EN Once the enable signal V ADC_ENWhen activated, the tracking ADC 280 adjusts its tracking voltage VTRK via DAC285 to converge to the digital rectified voltage V RECT_DIG . Rectified voltage V RECT The rising and falling edges of Figure 2 The edge detector 250 in the circuit generates an edge detection signal VRS_COMP. Figure 6 The fifth waveform 650 is shown in FIG.

[0085] The sixth waveform 660 shows the DAC value VS_DAC, which is provided to the DAC 285 and determines the tracking voltage VTRK of the tracking ADC 280. RECT At the rising edge of , the DAC register 284 is loaded with a value representing the DAC value of the rectified voltage pulse from the previous track. After a waiting time interval VRS_TRACK_THRS, the tracking ADC 280 begins operation and adjusts the value VS_DAC output from the DAC register 284. As shown by pulse 662, the DAC value VS_DAC converges before the end of the pulse. In contrast, the second rectified voltage pulse 624 is so short that the buffered voltage pulse 634 does not have time to safely stabilize. The tracking ADC 280 loads the previous DAC value VS_DAC during pulse 664. However, during this short pulse, the tracking ADC 280 is not enabled and the DAC value VS_DAC is not updated. Nevertheless, the tracking ADC 280 is able to provide a rectified voltage V corresponding to the previous value. RECT_DIG The rectified voltage V RECT At the falling edge of the pulse of , the DAC register 284 is preferably cleared (loaded with zeros) so that during the interval when there is no active rectifier pulse, the rectified voltage V RECT The effective digital value V RECT_DIG Still available.

[0086] The seventh waveform 670 shows the Figure 4 The compensating clock signal CLK_FE_CMP used by the stress effect compensator 470 of FIG. 4 corresponds to the phase 1 interval (Φ1), during which the switches of the switched capacitor network 472 are set to the sampling mode. The low level of the clock signal corresponds to the phase 2 interval (Φ2), during which the comparator 474 is set to its amplification mode (in the phase 2 interval). Figure 6476). The eighth waveform 680 shows the latch signal CLK_FE_LATCH, which latches the output of the comparator 474 into the D flip-flop 476. After the amplification mode is completed, the latch signal CLK_FE_LATCH pulse is high, which is shown as a 100ns delay after the falling edge of the compensation clock signal CLK_FE_CMP. This delay provides sufficient time for the output of the comparator 474 to stabilize. The ninth waveform 690 shows the enable signal CLK_DAC_EN that enables the counter 478. At a certain delay after the pulse of the latch signal CLK_FE_LATCH, the signal pulse is high, and as shown, the signal has a pulse width of 10ns. The delay between the rising edge of the latch signal CLK_FE_LATCH and the rising edge of the enable signal CLK_DAC_EN allows time for the output of the D flip-flop 476 to stabilize. The 10 ns pulse width enables the counter 478 long enough for its count to be updated, for example, one cycle of the 100 MHz counter clock CLK_CNT.

[0087] Note that the buffer rectified voltage V RECT_BUF The second pulse 634 is also too narrow to allow iterations of stress effect compensation. The voltages provided to the stress effect compensator 470 are not available long enough for the switched capacitor network 474 to sample these voltages. This is shown by the waveform 650 of the edge indicator VRS_COMP, which indicates that the second pulse 634 does not last for the duration of 250ns required for adequate sampling. Therefore, the latch signal CLK_FE_LATCH is not activated for the second pulse 634, and there is no corresponding triggering of iterations of the compensator 470.

[0088] Tracking ADC Replacement

[0089] The ADC front-end circuit described previously includes a level shifter and a buffer. This ADC front-end circuit inputs a secondary side voltage from a high impedance source (e.g. Figure 1 V RECT ), and for example in Figure 2 The ADC is connected to VBUFP and VBUFN to generate a high current output suitable for inputting to a low impedance tracking ADC. Figure 7 An alternative to this ADC front end circuit is shown that does not use a rail-to-rail buffer. Instead, current amplification is built into the tracking ADC circuit by using a push-pull output stage 720 and an amplifier-based driver 730.

[0090] Tracking ADCs that utilize current steering DACs can use resistors to connect the positive and negative inputs (e.g., VSENP, VSENN) to positive and negative current summing nodes within the tracking ADC. These summing nodes are regulated to have a constant voltage, such as 700mV. This regulated voltage (at Figure 7 Internally called V ADC_REF ) can be set, for example, by tracking the gate-to-source voltage of the MOSFET of the ADC. Instead of directly digitizing the input voltage VSENP, VSENN, the input voltage is converted into an input current I SIG_P ,I SIG_N , using digital tracking logic and a current steering DAC to match the internally generated current to the input current, SIG_P ,I SIG_N In such a tracking ADC, the positive side source voltage input VSENP and the regulated voltage V ADC_REF and input resistance Rt to determine the positive input current I SIG_P . Positive side input current I SIG_P Therefore, I SIG_P =(VSENP-V ADC_REF ) / Rt. Similarly, the negative input current I SIG_N Can be I SIG_N =(VSENN-V ADC_REF ) / Rt. (The resistance Rt between the positive and negative inputs VSENP, VSENN and the summing node is usually the same.) To achieve fast ADC conversion, the resistance Rt of the input resistor is preferably small so that the input current I SIG_P ,I SIG_N is high, and the current steering DAC can slew quickly to match the input current.

[0091] Figure 7 The tracking ADC 700 inputs the voltages VSENP and VSENN from the conditioning circuit, which has high impedance and cannot supply the input current I SIG_P The desired high current level. For example, the input voltages VSENP and VSENN can be Figure 1 The conditioning circuit 107 supplies the rectified voltage V RECT The tracking ADC 700 includes a current amplifier, which inputs a current I SIG_P The positive current I supplied by the positive input terminal 712p is SENP Due to its source (e.g. Figure 1 The high impedance of the conditioning circuit 107) has a low current level.

[0092] Tracking ADC 700 has input terminals 712p, 712n for connecting to positive and negative source voltages VSENP, VSENN. Tracking ADC 700 has positive and negative summing nodes 714p, 714n, which are part of the back-end tracking ADC circuitry. Positive input current I SIG_P and the negative input current I SIG_N Typically flows from input terminals 712p, 712n to summing nodes 714p, 714n. The back-end ADC circuit typically includes a current steering DAC and digital tracking logic for determining a digital value corresponding to the differential input source voltage VSENP-VSENN. Because such ADC back-end circuits are well known in the art, Figure 7 Instead, the following detailed description relates to providing a positive side input current I SIG_P Unique aspects of the present invention.

[0093] For example, the rectified voltage V RECT At the beginning of the pulse in, as the positive side input voltage VSENP rises, the voltage VSENP increases to a level higher than the reference voltage V of the positive side summing node 714p. ADC_REF The current flows from the positive side input terminal 712p through the resistors R1, R2 to the positive side summing node 714p. This current induces a positive voltage drop V2 across the resistor R2, which corresponds to the negative differential input of the amplifier-based driver 730. The negative differential input voltage of the driver 730 activates the output gate drive signal V for the high-side MOSFET QH of the push-pull output stage 720. GH , where the voltage level of the gate drive signal is based on the voltage drop V2, for example, V GH =f(Gm, V2), where Gm is the gain of the amplifier-based driver 730. (gate drive signal V GH Level shifting may also be required to generate the appropriate gate-to-source voltage, which is typical for transistor drive circuits. ) The high-side MOSFET QH turns on, causing the push-pull output stage 720 to supply the amplifier current I AMP , where the amplifier current I AMP The level of the amplifier current I AMP Enhanced input current I SENP , so that a very small current I is required from the input 712p SENP When the positive-side input voltage VSENP reaches a steady state after such an increase, the positive-side current I provided to the positive-side summing node 714p is SIG_P The amplifier current I AMP The source is sent, so that no current from the positive side input terminal 712p is required, that is, I SENP=0 and I AMP =I SIG_P =(VSENP-V ADC_REF ) / (R1+R2). Thus, a high current may be provided to the (low impedance) positive side summing node 714p of the tracking ADC 700 without requiring a high current level from the positive side input source VSENP (which is typically provided by a high impedance source).

[0094] When the positive input voltage VSENP drops (for example, when the rectified voltage V RECT At the end of the pulse in ), the tracking ADC 700 acts in a complementary manner. As the positive side input voltage VSENP decreases, the voltage V2 across the resistor R2 decreases, and the amplified current I AMP Once the voltage VSENP decreases below the reference voltage V ADC_REF , current flows from the positive side summing node 714p through resistors R2, R1 to the positive side input terminal 712p. For the polarity shown, this current induces a negative voltage V2 across resistor R2. The positive differential input voltage is provided to the amplifier-based driver 730. This positive differential input voltage of the driver 730 activates the output gate drive signal V for the low-side MOSFET QL of the push-pull output stage 720. GL , where the gate drive signal V GL The voltage level is based on the voltage drop V2, for example, V GL =Gm*V2, where Gm is the gain of the amplifier-based driver 730. The low-side MOSFET QL is turned on, causing the push-pull output stage 720 to draw the amplifier current (-I AMP ), where the amplifier current I AMP The level of is based on the voltage drop V2. Therefore, although a high impedance may be provided at the positive input VSENP, the positive input current I SIG_P It can react quickly to a falling voltage at the input.

[0095] The negative side resistor Rt is inserted between the negative side input 712n and the negative side summing node 714n so that the positive side input 712p and the negative side input 712n have the same impedance.

[0096] In some implementations, the tracking ADC 700 has the advantage of providing a simpler design. The push-pull output stage 720 and the amplifier 730 must be designed to be fast enough to respond adequately to changes in the input source voltage VSENP. A disadvantage of the tracking ADC 700 relative to the previously described ADC front-end circuit is that the tracking ADC 700 cannot draw sufficient current when the positive-side input voltage VSENP drops to a value close to 0V. This is because at such a low voltage level of the positive-side input voltage VSENP, the low-side MOSFET QL of the push-pull circuit cannot turn on (and draw current).

[0097] A method for detecting primary-side faults based on rectified voltage

[0098] Figure 8 A method 800 for sensing a secondary side voltage within an isolated switch mode power converter is shown. The method may be used in a Figure 1 The method 800 is implemented in a power converter shown in FIG. 800 begins by sensing 810 a first sense voltage at a first sense terminal. The first sense voltage corresponds to a secondary side voltage, such as a rectified voltage or an output voltage of the power converter. The first sense voltage is level shifted 820 to generate a first level shifted voltage. The first level shifted voltage is then buffered 830 to provide a first buffered output. The level of current corresponding to the first buffered output may be higher than the current provided at the buffer input. The voltage at the first buffered output is then digitized 840 using a tracking ADC.

[0099] In a typical application, the first sensing signal will correspond to the source voltage. The above method can be repeated for the second sensing signal, which corresponds to a reference voltage (eg, ground).

[0100] According to one embodiment of a voltage sensor for tracking a secondary side voltage of an isolated switch mode power converter, the voltage sensor includes a first sensing terminal, a first level shifter, a first input buffer, and a tracking analog-to-digital converter (ADC). The first sensing terminal is used to connect to a node of the secondary side voltage being tracked and has a first sensing voltage. The first level shifter is configured to shift the first sensing voltage to provide a first level shifted voltage. The first level shifted voltage is provided to a first input buffer, which outputs a first buffered output having a voltage corresponding to the first level shifted voltage and having a first buffered current higher than the current input to the first input buffer. The tracking ADC digitizes the first buffered output to provide a digital value corresponding to the secondary side voltage being tracked.

[0101] According to any embodiment of the voltage sensor, the voltage sensor further includes an edge detection comparator connected to the first sensing terminal and configured to detect a voltage pulse of the secondary side voltage and activate the tracking ADC in response to the pulse detection. According to any embodiment of the voltage sensor, its tracking ADC includes: a digital-to-analog converter (DAC) having a DAC output; and a DAC register, the stored value of which determines the voltage at the DAC output. The tracking ADC also includes a DAC comparator configured to compare the voltage at the ADC input with the voltage at the DAC output and provide a DAC comparator output indicating which of these voltages is higher. The ADC controller also within the tracking ADC is configured to update the stored value of the DAC register based on the DAC comparator output. Activation of the tracking ADC includes preloading the DAC register with a value from a previous active interval of the tracking ADC. In some embodiments, the edge detection comparator is further configured to detect a falling edge of the voltage pulse, and the tracking ADC is configured to preload zeros to the DAC register in response to receiving an indication of a detected falling edge from the edge detection comparator. In some embodiments, the ADC controller is configured to change the stored value of the DAC register in multiple steps (multiple codes) when the ADC controller is initially activated, i.e., at the beginning of a pulse. For subsequent iterations of the tracking ADC, the step size is reduced. In another sub-embodiment, the step size is reduced once the comparator output switches.

[0102] According to any embodiment of the voltage sensor, the voltage sensor further includes a second sensing terminal, a second level shifter, and a second input buffer. The second sensing terminal is used to connect to a reference node having a second sensing voltage corresponding to the secondary side reference voltage. The second level shifter shifts the second sensing voltage to provide a second level shifted voltage. The second input buffer inputs the second level shifted voltage and provides a second buffered output having a voltage corresponding to the second level shifted voltage. The current capability provided by the second buffered output is higher than the input current of the second input buffer. The tracking ADC is configured to output a digital value based on a voltage difference between the first buffered output and the second buffered output.

[0103] According to any embodiment of the voltage sensor having a first sensing terminal and a second sensing terminal and a first level shifter and a second level shifter, the first level shifter and the second level shifter are part of a level shifter circuit, which includes a first MOSFET, a second MOSFET, a current source, and a current mirror. Each of the first MOSFET and the second MOSFET includes a first terminal, a second terminal, and a gate terminal, wherein the gate terminal controls conduction between the first terminal and the second terminal. The gate terminal of the first MOSFET is coupled to the first sensing terminal, and a first level shift voltage is provided at the first terminal of the first MOSFET. The gate terminal of the second MOSFET is coupled to the second sensing terminal, and a second level shift voltage is provided at the first terminal of the second MOSFET. The current source provides a reference current to the current mirror. The current mirror includes three MOSFETs, which are configured to provide a reference current to the first MOSFET and the second MOSFET.

[0104] According to any embodiment of the voltage sensor having such a level shifter circuit, the level shifter circuit further includes a first feedback correction loop, the first feedback correction loop being configured to drive the voltage at the second terminal of the first MOSFET to the voltage at the gate terminal of the first MOSFET. The first feedback correction loop includes a first amplifier having a first input coupled to the gate terminal of the first MOSFET, a second input, and an output coupled to the second input and the second terminal of the first MOSFET. A feedback correction loop resistor is coupled to the output of the first amplifier so that the first amplifier can source / sink current through the resistor to keep the voltage at the gate terminal and the second terminal of the first MOSFET at a common level.

[0105] According to any embodiment of the voltage sensor having such a level shifter circuit, with or without the first feedback correction loop, the level shifter circuit further includes a second feedback correction loop, the second feedback correction loop being configured to maintain a common voltage at the second terminal of the first mirror MOSFET and the second terminal of the second mirror MOSFET. The second feedback correction loop includes a second amplifier having a first input coupled to the second terminal of the first mirror MOSFET, a second input coupled to the second terminal of the second mirror MOSFET, and an output. In other embodiments of the voltage sensor, the level shifter circuit also includes a first cascade MOSFET and a second cascade MOSFET. The first cascade MOSFET is inserted between the second mirror MOSFET and the first MOSFET and has a gate terminal coupled to the output of the second amplifier. The second cascade MOSFET is inserted between the third mirror MOSFET and the second MOSFET and has a gate terminal coupled to the output of the second amplifier.

[0106] According to any embodiment of the voltage sensor having a first sensing terminal and a second sensing terminal and a first level shifter and a second level shifter, the voltage sensor further comprises a drift compensation circuit. The drift compensation current or voltage source is configured to compensate for the difference between the buffer voltage difference and the sensing voltage difference, wherein the first buffer voltage difference is the difference between the first buffer output and the second buffer output, and the sensing voltage difference is the difference between the first sensing voltage and the second sensing voltage. The capacitor and the switch network are configured such that: during a first phase interval, the capacitor stores a voltage corresponding to each of the first sensing voltage, the first buffer output, the second sensing voltage, and the second buffer output. During a second phase interval, the capacitor and the switch network provide a first difference between the first buffer output and the first sensing voltage, and a second difference between the second buffer output and the second sensing voltage. The drift compensation comparator is coupled to the capacitor and the switch network, and generates a drift compensation output based on a comparison of the first difference and the second difference. The drift compensation current or voltage source is based on the drift compensation output.

[0107] According to any embodiment of the voltage sensor, the voltage sensor provides a digital output for each switching cycle or each switching half-cycle of the isolated switch mode power converter. The digital output corresponds to the digital value output from the tracking ADC.

[0108] According to one embodiment of a method for sensing a secondary side voltage within an isolated switch mode power converter, the method includes sensing a first sense voltage at a first sense terminal, wherein the first sense voltage corresponds to the secondary side voltage. The first sense voltage is shifted to provide a first level shifted voltage. The first level shifted voltage is buffered to provide a first buffered output having a voltage corresponding to the first level shifted voltage. An available current driven from the first buffered output is higher than an input current of a first input buffer. An output of the first buffer is digitized using a tracking analog-to-digital converter (ADC) to provide a digital value corresponding to the secondary side voltage.

[0109] According to an embodiment of a switch mode power converter using an isolated topology to convert power from an input source into power for an output load, the switch mode power converter includes a primary side, a transformer, and a secondary side. The primary side includes a power stage coupled to an input source, the power stage including one or more power switches. The transformer includes a primary winding coupled to the power stage, and a secondary winding. The secondary side includes a rectifier circuit, a filter circuit, and a voltage sensor. The rectifier circuit is coupled to the secondary winding and provides a first rectified voltage at a first rectified voltage node. The filter circuit is inserted between the first rectified voltage node and the output of the switch mode power converter. The filter circuit is configured to filter the first rectified voltage and provide a filtered voltage at the output. The voltage sensor includes a circuit that is largely the same as the above-mentioned voltage sensor, but additionally includes a resistor divider that couples the secondary side voltage node being sensed to the sensing terminal of the divider.

[0110] According to any embodiment of the switch-mode power converter, the secondary-side voltage node coupled to the resistor divider is a first rectified voltage node. According to another embodiment of the switch-mode power converter, a digital value corresponding to the rectified voltage node is used to estimate an input current and / or voltage of an input source. According to yet another embodiment of the switch-mode power converter, the voltage sensor further includes an edge detection comparator configured to determine a width of a rectified voltage pulse at the rectified voltage node. According to yet another embodiment of the switch-mode power converter, the voltage sensor further includes an edge detection comparator configured to detect an edge of a rectified voltage pulse at the rectified voltage node, and the switch-mode power converter further includes a controller configured to generate a control signal for a power switch on the primary side and determine a time delay between the generated control signal and a detected edge of the rectified voltage pulse.

[0111] According to any embodiment of the switch mode power converter, the secondary side voltage node coupled to the resistor divider is an output of the switch mode power converter.

[0112] According to an embodiment of an alternative switch mode power converter using an isolated topology to convert power from an input source to power for an output load, the switch mode power converter includes a primary side, a transformer, and a secondary side. Except for a voltage sensor on the secondary side, these circuits are largely the same as the corresponding circuits of the switch mode power converter described above. The voltage sensor of the alternative power converter is configured to estimate the voltage of the input source based on a first rectified voltage. The voltage sensor includes a first sensing terminal, a front end, and a tracking analog-to-digital converter (ADC).

[0113] According to any embodiment of the alternative switch mode power converter, the front end includes a current amplifier, the current amplifier is coupled to a first sensing terminal and is configured to amplify a first input current of the first sensing terminal and provide a first amplified current to the tracking ADC. According to another embodiment of the alternative switch mode power converter, the current amplifier includes a push-pull output stage, a first resistor and a second resistor, and an amplifier-based driver. The push-pull output stage includes a first transistor and a second transistor coupled in series and inserted between a voltage sensor power supply and a reference voltage node. The second terminal of the first transistor and the first terminal of the second transistor are coupled to a first sensing terminal of the voltage sensor. The first resistor and the second resistor are coupled in series and inserted between the first sensing terminal and the input of the tracking ADC. The first amplifier-based driver has an input coupled to a terminal of the second resistor. The first output of the driver is coupled to a control terminal of the first transistor, and the second output of the driver is coupled to a control terminal of the second transistor.

[0114] According to any embodiment of the alternative switch-mode power converter, the front end comprises a first level shifter, and the first level shifter is inserted between the first sense terminal and the input of the tracking ADC.

[0115] As used herein, the terms "having", "comprising", "including", "including", etc. are open terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" are intended to include the plural as well as the singular.

[0116] It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0117] Although specific embodiments have been shown and described herein, it will be appreciated by those of ordinary skill in the art that various alternative and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention is limited only by the claims and their equivalents.

Claims

1. A voltage sensor for tracking a secondary side voltage of an isolated switch mode power converter, the voltage sensor comprising: a first sensing terminal, connected to an input node, the input node having a first sensing voltage corresponding to the secondary side voltage; a first level shifter, configured to shift the first sensing voltage to provide a first level shift voltage; a first input buffer configured to input the first level-shifted voltage and provide a first buffer output having a voltage corresponding to the first level-shifted voltage and having a first buffer current higher than a current at an input of the first input buffer; a tracking ADC (analog-to-digital converter) having an ADC input coupled to the first buffered output and configured to output a digital value corresponding to the secondary-side voltage at a current sample instant; an edge detection comparator connected to the first sense terminal and configured to detect a voltage pulse of the secondary side voltage and to activate the tracking ADC in response to the pulse detection, The tracking ADC includes: A digital-to-analog converter (DAC) having a DAC output; A DAC register, wherein a storage value of the DAC register determines a voltage output by the DAC; a DAC comparator configured to compare the voltage at the ADC input to the voltage at the DAC output and to provide a DAC comparator output indicating which of the voltages is higher; and an ADC controller configured to update the stored value of the DAC register based on the DAC comparator output, Wherein activating the tracking ADC comprises preloading the DAC register with values ​​from a previous active interval of the tracking ADC.

2. The voltage sensor of claim 1 , wherein the edge detection comparator is further configured to detect a falling edge of the voltage pulse, and the tracking ADC is configured to preload zeros into the DAC register in response to receiving an indication of the detected falling edge from the edge detection comparator.

3. The voltage sensor of claim 1 , wherein the ADC controller is configured to, when the tracking ADC is activated, change the stored value of the DAC register by a step size of multiple steps for each tracking iteration, and to reduce the step size during subsequent iterations of the tracking ADC.

4. The voltage sensor according to claim 1, further comprising: a second sensing terminal for connecting to a reference node having a second sensing voltage corresponding to the secondary-side reference voltage; a second level shifter, configured to shift the second sensing voltage to provide a second level shift voltage; as well as a second input buffer configured to input the second level shift voltage and provide a second buffer output having a voltage corresponding to the second level shift voltage and having a second buffer current higher than a current at an input of the second input buffer, Wherein the tracking ADC is configured to output a digital value based on a voltage difference between the first buffered output and the second buffered output.

5. The voltage sensor of claim 4, wherein the first level shifter and the second level shifter are part of a level shifter circuit, and the level shifter circuit comprises: a first pMOSFET (p-channel metal oxide semiconductor field effect transistor) having a first terminal, a second terminal and a gate terminal, wherein the gate terminal is coupled to the first sensing terminal, the gate terminal controls conduction between the first terminal and the second terminal, and provides the first level-shifted voltage at the first terminal of the first pMOSFET; a second pMOSFET having a first terminal, a second terminal, and a gate terminal, wherein the gate terminal is coupled to the second sensing terminal, the gate terminal controls conduction between the first terminal and the second terminal, and provides the second level-shifted voltage at the first terminal of the second pMOSFET; a level shifter current source, providing a reference current level; A current mirror comprises a first mirror MOSFET, a second mirror MOSFET and a third mirror MOSFET, wherein the first mirror MOSFET, the second mirror MOSFET and the third mirror MOSFET are configured to set the current for the first pMOSFET and the second pMOSFET to the reference current level, wherein each of the first mirror MOSFET, the second mirror MOSFET and the third mirror MOSFET has a gate terminal, a first terminal and a second terminal.

6. The voltage sensor of claim 5 , wherein the level shifter circuit further comprises a first feedback correction loop, the first feedback correction loop being configured to drive the voltage at the second terminal of the first pMOSFET to the voltage at the gate terminal of the first pMOSFET, the first feedback correction loop comprising: a first amplifier having a first input coupled to the gate terminal of the first pMOSFET, a second input, and an output coupled to the second input and the second terminal of the first pMOSFET; as well as A feedback correction loop resistor is coupled to the output of the first amplifier.

7. The voltage sensor of claim 5, wherein the level shifter circuit further comprises a second feedback correction loop, the second feedback correction loop being configured to maintain a common voltage at the second terminal of the first mirror MOSFET and the second terminal of the second mirror MOSFET, the second feedback correction loop comprising: A second amplifier has a first input coupled to the second terminal of the first mirror MOSFET, a second input coupled to the second terminal of the second mirror MOSFET, and an output.

8. The voltage sensor according to claim 7, further comprising: a first cascode MOSFET inserted between the second mirror MOSFET and the first pMOSFET and having a gate terminal coupled to the output of the second amplifier; as well as A second cascode MOSFET is inserted between the third mirror MOSFET and the second pMOSFET and has a gate terminal coupled to the output of the second amplifier.

9. The voltage sensor according to claim 4, further comprising a drift compensation circuit, the drift compensation circuit comprising: a drift compensation current or voltage source configured to compensate for a difference between a buffer voltage difference and a sense voltage difference, wherein the buffer voltage difference is a difference between the first buffer output and the second buffer output, and the sense voltage difference is a difference between the first sense voltage and the second sense voltage; a capacitor and a switch network configured such that during a first phase interval, the capacitor stores a voltage corresponding to each of the first sense voltage, the first buffer output, the second sense voltage, and the second buffer output, and during a second phase interval, the capacitor provides a first difference between the first buffer output and the first sense voltage, and a second difference between the second buffer output and the second sense voltage; as well as a drift compensation comparator coupled to the capacitor and the switch network and configured to generate a drift compensation output based on a comparison of the first difference and the second difference, Wherein the drift compensation current or voltage source is based on the drift compensation output.

10. The voltage sensor of claim 1, wherein the voltage sensor provides a digital output for each switching cycle or each switching half-cycle of the isolated switch-mode power converter, the digital output comprising the digital value output from the tracking ADC.

11. A method for sensing a secondary side voltage in an isolated switch mode power converter, the method comprising: sensing a first sensing voltage at a first sensing terminal, the first sensing voltage corresponding to the secondary-side voltage; shifting the first sensing voltage to provide a first level-shifted voltage; buffering the first level shifted voltage to provide a first buffered output having a voltage corresponding to the first level shifted voltage and having a first buffered current that is higher than a current at an input of a first input buffer; digitizing the first buffered output using a tracking ADC (analog-to-digital converter) to provide a digital value corresponding to the secondary side voltage at a current sample time; detecting a voltage pulse of the secondary side voltage by an edge detection comparator, the edge detection comparator being connected to the first sensing terminal; and In response to the pulse detection, activating the tracking ADC, The tracking ADC includes: A digital-to-analog converter (DAC) having a DAC output; A DAC register, wherein a storage value of the DAC register determines a voltage output by the DAC; a DAC comparator configured to compare the voltage at the ADC input to the voltage at the DAC output and to provide a DAC comparator output indicating which of the voltages is higher; and an ADC controller configured to update the stored value of the DAC register based on the DAC comparator output, Wherein activating the tracking ADC comprises preloading the DAC register with values ​​from a previous active interval of the tracking ADC.

12. A switch mode power converter, the switch mode power converter using an isolated topology to convert power from an input source to power for an output load, the switch mode power converter comprising: a primary side including a power stage coupled to the input source and including one or more power switches; a transformer including a primary winding coupled to the power stage, and a secondary winding; as well as The secondary side includes: a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node, a filter circuit interposed between the first rectified voltage node and an output of the switch mode power converter, the filter circuit being configured to filter the first rectified voltage to provide a filtered voltage at the output; a resistor divider coupled to the secondary side voltage node and configured to provide a first sensing voltage; and A voltage sensor according to any one of claims 1 to 10.

13. The switch mode power converter of claim 12 wherein the secondary side voltage node coupled to the resistor divider is the rectified voltage node.

14. The switch-mode power converter of claim 13, wherein the digital value corresponding to the rectified voltage node is used to estimate an input current and / or voltage of the input source. 15 . The switch-mode power converter of claim 13 , wherein the voltage sensor further comprises an edge detection comparator configured to determine a width of a rectified voltage pulse at the rectified voltage node.

16. The switch-mode power converter of claim 13, wherein the voltage sensor further comprises an edge detection comparator configured to detect edges of rectified voltage pulses at the rectified voltage node, and the switch-mode power converter further comprises: A controller is configured to generate a control signal for the power switch of the primary side and determine a time delay between the generated control signal and the detected edge of the rectified voltage pulse.

17. The switch mode power converter of claim 12, wherein the secondary side voltage node coupled to the resistor divider is the output of the switch mode power converter.

18. A switch mode power converter using an isolated topology to convert power from an input source to power for an output load, the switch mode power converter comprising: a primary side including a power stage coupled to the input source and including one or more power switches; a transformer including a primary winding coupled to the power stage, and a secondary winding; as well as The secondary side includes: a rectifier circuit coupled to the secondary winding and configured to provide a first rectified voltage at a first rectified voltage node, a filter circuit interposed between the first rectified voltage node and an output of the switch mode power converter, the filter circuit being configured to filter the first rectified voltage to provide a filtered voltage at the output; and a voltage sensor configured to estimate the voltage of the input source based on the first rectified voltage, the voltage sensor comprising a first sensing terminal, a front end, a first level shifter, a first input buffer and a tracking ADC (analog-to-digital converter), wherein the first level shifter is configured to shift a first sense voltage at the first sense terminal to provide a first level shifted voltage, the first input buffer is configured to input the first level shifted voltage and provide a first buffered output, the first buffered output having a voltage corresponding to the first level shifted voltage and having a first buffered current higher than the current at the input of the first input buffer, and the tracking ADC (analog-to-digital converter) has an ADC input coupled to the first buffered output and is configured to output a digital value corresponding to the secondary side voltage of the switch mode power converter at a current sample time, wherein the voltage sensor further comprises an edge detection comparator connected to the first sensing terminal and configured to detect a voltage pulse of the secondary side voltage and activate the tracking ADC in response to the pulse detection, and The tracking ADC includes: A digital-to-analog converter (DAC) having a DAC output; A DAC register, wherein a storage value of the DAC register determines a voltage output by the DAC; a DAC comparator configured to compare the voltage at the ADC input to the voltage at the DAC output and to provide a DAC comparator output indicating which of the voltages is higher; and an ADC controller configured to update the stored value of the DAC register based on the DAC comparator output, Wherein activating the tracking ADC comprises preloading the DAC register with values ​​from a previous active interval of the tracking ADC.

19. The switch-mode power converter of claim 18, wherein the front end comprises: A current amplifier is coupled to the first sensing terminal and is configured to amplify a first input current of the first sensing terminal and provide a first amplified current to the tracking ADC.

20. The switch-mode power converter of claim 19, wherein the current amplifier comprises: a first transistor and a second transistor coupled in series between a voltage sensor power supply and a reference voltage node, wherein a second terminal of the first transistor and a first terminal of the second transistor are coupled to the first sense terminal; a first resistor and a second resistor coupled in series between the first sensing terminal and an input of the tracking ADC; as well as A first amplifier-based driver has a first input coupled to the first terminal of the second resistor and a second input coupled to the second terminal of the second resistor, and has a first output coupled to the control terminal of the first transistor and a second output coupled to the control terminal of the second transistor.

21. The switch-mode power converter of claim 18, wherein the first level shifter is inserted between the first sense terminal and an input of the tracking ADC.

Images