A charging acceleration unit, a charging circuit and a non-volatile memory

Abstract

The embodiment of the present invention provides a charging acceleration unit, a charging circuit and a non-volatile memory, wherein the charging acceleration unit comprises: a first charging module, a second charging module, a shut-off module and a charging output terminal, wherein the shut-off module is connected to the first charging module and the second charging module respectively. The charging acceleration unit of the embodiment of the present invention can provide accelerated charging for a device to be charged through the charging output terminal, thereby greatly improving the charging speed of the device to be charged. When the acceleration is completed, the charging acceleration unit can also shut down automatically without causing other effects on the circuit where the device to be charged is located.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a charging acceleration unit, a charging circuit and a non-volatile memory. Background Art

[0002] A non-volatile memory such as NAND FLASH usually requires a sense amplifier SA to implement functions such as data programming and data reading. During the data programming and data reading process, the bit line BL needs to be charged through the charging transistor of SA.

[0003] In the prior art, an operational amplifier is usually used to pull up the gate voltage of the charging transistor in SA and clamp it to the input reference voltage of the operational amplifier, so that the charging transistor is turned on to charge the bit line BL.

[0004] However, the inventors found in the process of studying the above technical solution that the above technical solution has the following defects: when the existing technology is used to charge the BL, the speed of data programming and data reading of the NAND FLASH is slow. Summary of the invention

[0005] In view of the above problems, a charging acceleration unit, a charging circuit and a non-volatile memory according to an embodiment of the present invention are proposed to increase the charging speed.

[0006] According to a first aspect of the present invention, there is provided a charging acceleration unit, comprising:

[0007] A first charging module, a second charging module, a shut-off module, and a charging output terminal;

[0008] The first charging module comprises: a first power connection terminal connected to the first power source, a first signal receiving terminal for receiving a first signal, and a first charging terminal connected to the shutdown module;

[0009] The second charging module comprises: a second power connection terminal connected to the first power supply, a second signal receiving terminal for receiving a second signal, a second charging terminal connected to the shutdown module, and a shutdown signal receiving terminal for receiving a shutdown signal from the shutdown module; wherein the second signal and the first signal are inverse phase signals to each other;

[0010] The shutdown module includes: a first charging receiving end connected to the first charging end, and configured to receive charging from the first power source when the first charging module is in a conducting state according to the first signal;

[0011] The shut-off module further includes: a second charging receiving end connected to the second charging end, configured to receive charging from the first power source when the second charging module is in a conducting state according to the second signal;

[0012] The shutdown module further includes: a shutdown signal output terminal connected to the shutdown signal receiving terminal, configured to shut down the second charging module through the shutdown signal receiving terminal when the voltage of the second charging receiving terminal is greater than the conduction threshold of the shutdown module;

[0013] The charging output terminal is connected to the second charging terminal, and the charging output terminal is used to connect to the acceleration device to be charged.

[0014] Preferably, the first charging module comprises: a first P-type field effect transistor;

[0015] The gate terminal of the first P-type field effect transistor serves as the first signal receiving terminal;

[0016] The source end of the first P-type field effect transistor serves as the first power connection end;

[0017] The drain terminal of the first P-type field effect transistor serves as the first charging terminal.

[0018] Preferably, the second charging module comprises: a second P-type field effect transistor and a third P-type field effect transistor;

[0019] The gate terminal of the second P-type field effect transistor serves as the second signal receiving terminal;

[0020] The source end of the second P-type field effect transistor serves as the second power supply connection end;

[0021] The drain terminal of the second P-type field effect transistor is connected to the source terminal of the third P-type field effect transistor;

[0022] The gate terminal of the third P-type field effect transistor serves as the shutdown signal receiving terminal;

[0023] The drain terminal of the third P-type field effect transistor serves as the second charging terminal.

[0024] Preferably, the shutdown module comprises: a first N-type field effect transistor, an inverter;

[0025] The gate terminal of the first N-type field effect transistor serves as the second charging receiving terminal;

[0026] The source terminal of the first N-type field effect transistor is grounded;

[0027] The drain end of the first N-type field effect transistor serves as the first charging receiving end and is connected to the input end of the inverter;

[0028] The output end of the inverter serves as the shutdown signal output end.

[0029] An embodiment of the present invention further provides a charging circuit, comprising any of the charging acceleration units described above.

[0030] Preferably, the charging circuit further comprises: a third charging module;

[0031] The third charging module includes: an amplifier, a fourth P-type field effect transistor, a resistor, and a capacitor;

[0032] The amplifier comprises a reference voltage input terminal for receiving a reference voltage signal, a third signal input terminal for receiving a third signal, a comparison voltage input terminal, and an amplifier output terminal; wherein the third signal and the second signal are mutually inverted signals;

[0033] The amplifier output terminal is connected to the gate terminal of the fourth P-type field effect transistor;

[0034] The comparison voltage input terminal is connected to the drain terminal of the fourth P-type field effect transistor;

[0035] The drain end of the fourth P-type field effect transistor is also connected to one end of the resistor, one end of the capacitor, and the charging output end respectively;

[0036] The source end of the fourth P-type field effect transistor is connected to the second power supply;

[0037] The other end of the resistor and the other end of the capacitor are grounded.

[0038] An embodiment of the present invention further provides a non-volatile memory, comprising the charging circuit.

[0039] Preferably, the non-volatile memory further comprises a sense amplifier.

[0040] Preferably, the sense amplifier comprises:

[0041] A second N-type field effect transistor, a third N-type field effect transistor, a fourth N-type field effect transistor, a fifth N-type field effect transistor, a sixth N-type field effect transistor, a second capacitor, and a latch;

[0042] The drain terminal of the second N-type field effect transistor is connected to a third power supply;

[0043] The source end of the second N-type field effect transistor is respectively connected to the drain end of the third N-type field effect transistor, the gate end of the fourth N-type field effect transistor, and one end of the second capacitor;

[0044] The gate terminal of the third N-type field effect transistor is connected to the charging output terminal;

[0045] The source end of the third N-type field effect transistor is connected to the drain end of the fifth N-type field effect transistor and the drain end of the sixth N-type field effect transistor respectively;

[0046] The source end of the fifth N-type field effect transistor is connected to the bit line of the non-volatile memory;

[0047] The drain terminal of the fourth N-type field effect transistor is connected to the latch;

[0048] A source end of the fourth N-type field effect transistor and the other end of the second capacitor are grounded respectively.

[0049] The charging acceleration unit in the embodiment of the present invention can provide accelerated charging for the device to be charged and accelerated through the charging output terminal, which greatly improves the charging speed of the device to be charged and accelerated. When the device to be charged and accelerated is a non-volatile memory, the speed of data programming and data reading of NAND FLASH can be greatly improved. When the acceleration is completed, the charging acceleration unit can also shut down by itself without causing other impacts on the circuit where the device to be charged and accelerated is located. Specifically, the charging acceleration unit includes a first charging module, a second charging module, a shutdown module, and a charging output terminal; the first charging module includes: a first power connection terminal connected to the first power supply, a first signal receiving terminal for receiving a first signal, and a first charging terminal connected to the shutdown module; the second charging module includes: a second power connection terminal connected to the first power supply, a second signal receiving terminal for receiving a second signal, a second charging terminal connected to the shutdown module, and a shutdown signal receiving terminal for receiving a shutdown signal of the shutdown module; wherein the second signal and the first signal are inverted signals to each other; the charging output terminal is connected to the second charging terminal, and the charging output terminal is used to connect the device to be charged and accelerated; the shutdown module includes: The shutdown module also includes: a first charging receiving end connected to the first charging end, used for receiving the charge of the first power source at the first charging receiving end when the first charging module is in a conductive state according to the first signal; the shutdown module also includes: a second charging receiving end connected to the second charging end, used for receiving the charge of the first power source at the second charging receiving end when the second charging module is in a conductive state according to the second signal, so as to improve the charging speed of the charging acceleration device; the shutdown module also includes: a shutdown signal output end connected to the shutdown signal receiving end, used for shutting down the second charging module through the shutdown signal receiving end when the voltage at the second charging receiving end is greater than the conductive threshold of the shutdown module, so as to avoid interference of the charging acceleration unit to the circuit.

[0050] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0052] Figure 1 This is a schematic diagram of a charging acceleration unit circuit provided by an embodiment of the present invention;

[0053] Figure 2 is a schematic diagram of a third charging module circuit provided by an embodiment of the present invention;

[0054] Figure 3 It is a schematic diagram of BL_PREC waveform comparison provided by an embodiment of the present invention;

[0055] Figure 4 It is a simplified circuit diagram of a sensitive amplifier provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0056] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, are only part of the embodiments of the present invention, not all of the embodiments, and are not used to limit the present invention.

[0057] Reference Figure 1 , shows a charging acceleration unit, which may specifically include:

[0058] A first charging module 10, a second charging module 20, a shut-off module 30, and a charging output terminal BL_PREC;

[0059] The first charging module 10 includes: a first power connection terminal 12 connected to a first power source VCC, a first signal receiving terminal 11 for receiving a first signal, and a first charging terminal 13 connected to the shutdown module 30; the second charging module 20 includes: a second power connection terminal 22 connected to the first power source VCC, a second signal receiving terminal 21 for receiving a second signal, a second charging terminal 23 connected to the shutdown module 30, and a shutdown signal receiving terminal 24 for receiving a shutdown signal of the shutdown module 30; wherein the second signal and the first signal are mutually inverted signals; the shutdown module 30 includes: a first charging receiving terminal 31 connected to the first charging terminal 13, which is used to, when the first charging module 10 is in a conducting state according to the first signal, The first charging receiving terminal 31 receives the charge of the first power supply VCC; the shutdown module 30 also includes: a second charging receiving terminal 33 connected to the second charging terminal 23, which is used for the second charging receiving terminal 33 to receive the charge of the first power supply VCC when the second charging module 20 is in the on state according to the second signal; the shutdown module 30 also includes: a shutdown signal output terminal 32 connected to the shutdown signal receiving terminal 24, which is used for shutting down the second charging module 20 through the shutdown signal receiving terminal 32 when the voltage of the second charging receiving terminal 33 is greater than the on threshold of the shutdown module 30; the charging output terminal BL_PREC is connected to the second charging terminal 23, and the charging output terminal BL_PREC is used to connect the acceleration device to be charged.

[0060] In the embodiment of the present invention, when the charging acceleration unit is working, the first charging module 10 can be turned on according to the received first signal, and the first power supply VCC can charge the first charging receiving terminal 31 of the shutdown module 30; when the second charging module 20 is turned on according to the second signal, because the first signal and the second signal are inverted signals, the first charging module 10 is turned off and no longer works, and the first voltage VCC can charge the charging output terminal BL_PREC, thereby realizing the charging acceleration of the device to be accelerated. When the voltage of the charging output terminal BL_PREC is higher than the turn-on threshold of the shutdown module 30, the shutdown signal output terminal 32 of the shutdown module can output a shutdown signal, so that the second charging module 20 is turned off and no longer interferes with the circuit where the device to be accelerated is located.

[0061] As a preferred solution of the embodiment of the present invention, refer to Figure 1 The first charging module 10 includes: a first P-type field effect transistor MP1; the gate end of the first P-type field effect transistor MP1 serves as the first signal receiving end 11; the source end of the first P-type field effect transistor MP1 serves as the first power connection end 12; and the drain end of the first P-type field effect transistor MP1 serves as the first charging end 13.

[0062] The second charging module 20 includes: a second P-type field effect transistor MP2 and a third P-type field effect transistor MP3; the gate end of the second P-type field effect transistor MP2 serves as the second signal receiving end 21; the source end of the second P-type field effect transistor MP2 serves as the second power supply connection end 22; the drain end of the second P-type field effect transistor MP2 is connected to the source end of the third P-type field effect transistor MP3; the gate end of the third P-type field effect transistor MP3 serves as the shutdown signal receiving end 24; and the drain end of the third P-type field effect transistor MP3 serves as the second charging end 23.

[0063] The shutdown module 30 includes: a first N-type field effect transistor MN1 and an inverter; the gate end of the first N-type field effect transistor MN1 serves as the second charging receiving end 33; the source end of the first N-type field effect transistor MN1 is grounded; the drain end of the first N-type field effect transistor MN1 serves as the first charging receiving end 31 and is connected to the input end of the inverter; the output end of the inverter serves as the shutdown signal output end 32.

[0064] In a specific application, the first signal may be END, the second signal may be ENB, and the first signal and the second signal are inverted signals.

[0065] The working principle of the charging acceleration unit of the embodiment of the present invention is: when ENB is high, MP2 and MP3 are not turned on, END is low, and MP1 is turned on. In theory, the first charging receiving terminal 31 can be charged to the power supply voltage VCC, and the voltage at the output terminal of the inverter is low; when ENB is low, MP1 is not turned on. Since the voltage at the output terminal of the inverter is low at this time, MP2 and MP3 are turned on, and the charging output terminal BL_PREC starts to charge. When BL_PREC reaches the threshold voltage Vt of MN1, MN1 is turned on, and the inverter input terminal is discharged to the ground through MN1, then the voltage at the output terminal of the inverter turns high, MP3 is turned off, and the entire charging acceleration unit no longer works.

[0066] The embodiment of the present invention further provides a charging circuit, comprising any of the above-mentioned charging acceleration units. Preferably, the charging circuit further comprises: a third charging module 30; specifically, the charging output terminal BL_PREC of the charging acceleration unit is connected to the third charging module 30, referring to Figure 2 The third charging module 30 includes: an amplifier EA, a fourth P-type field effect transistor MP4, a resistor R1, and a capacitor C1.

[0067] The amplifier EA includes a reference voltage input terminal Vref for receiving a reference voltage signal, a third signal input terminal for receiving a third signal EN, a comparison voltage input terminal, and an amplifier output terminal; wherein the third signal EN and the second signal ENB are inverted signals to each other; the amplifier output terminal is connected to the gate terminal of the fourth P-type field effect transistor MP4; the comparison voltage input terminal is connected to the drain terminal of the fourth P-type field effect transistor MP4; the drain terminal of the fourth P-type field effect transistor MP4 is also respectively connected to one end of the resistor R1, one end of the capacitor C1, and the charging output terminal BL_PREC; the source terminal of the fourth P-type field effect transistor MP4 is connected to the second power supply V4V; the other end of the resistor R1 and the other end of the capacitor C1 are grounded.

[0068] In the embodiment of the present invention, the working principle of the third charging module 30 is: when EN is high, V1 is low, MP4 is turned on, and the current source I1 charges the capacitor C1. When BL_PREC reaches Vref, V1 is high, MP1 is turned off, and BL_PREC is maintained at Vref; and, ENB is the reverse signal of EN. When EN is high and the third charging module 30 is working, ENB is low, MP1 is not turned on, and since the voltage at the output of the inverter is low at this time, MP2 and MP3 are turned on, and the charging output terminal BL_PREC starts to charge. When BL_PREC reaches the threshold voltage Vt of MN1, MN1 is turned on, and the inverter input terminal discharges to the ground through MN1, then the voltage at the output of the inverter turns high, MP3 is turned off, and the entire charging acceleration unit no longer works and consumes no current. The third charging module 30 has the following defects: BL_PREC is sometimes set at a higher gear, so Figure 2 The power supply voltage of the circuit needs to be a higher voltage, generally the output voltage V4V of the pump is used. However, due to area limitations, the pump cannot provide too much output current, so the size of the current source I1 is limited.

[0069] Compared with the charging method using only the third charging module 30, the charging method of connecting the charging output terminal BL_PREC of the charging acceleration unit to the third charging module 30 in the embodiment of the present invention can greatly improve the charging speed of BL_PREC from 0 to Vt. Figure 3As shown, Line 1 is a waveform diagram of BL_PREC established by only using the third charging module 30 for charging, and Line 2 is a waveform diagram of adding a charging acceleration unit proposed in an embodiment of the present invention. Before BL_PREC reaches Vt, the charging acceleration unit works, and after BL_PREC is greater than Vt, the charging acceleration unit does not work. In practical applications, the time when BL_PREC in the non-volatile memory reaches Vref can be used as the BL establishment time, so the BL establishment in the embodiment of the present invention can save time t2-t1. The reason why the charging acceleration unit is turned off when BL_PREC is greater than Vt is that when BL_PREC is greater than Vt, Figure 4 The third power supply VDD in the circuit charges BL. Since there are a large number of SAs and the circuit for VDD to charge BL is very large, VDD will have a large voltage drop, which will affect the performance of the SA circuit.

[0070] The embodiment of the present invention further provides a non-volatile memory, comprising any of the above-mentioned charging circuits. Preferably, the non-volatile memory further comprises a sensitive amplifier. Specifically, Figure 4 As shown, the sense amplifier comprises:

[0071] The second N-type field effect transistor MN2, the third N-type field effect transistor MN3, the fourth N-type field effect transistor MN4, the fifth N-type field effect transistor MN5, the sixth N-type field effect transistor MN6, the second capacitor C2, and the latch LATCH; the drain end of the second N-type field effect transistor MN2 is connected to the third power supply VDD; the source end of the second N-type field effect transistor MN2 is respectively connected to the drain end of the third N-type field effect transistor, the gate end of the fourth N-type field effect transistor MN4, and one end of the second capacitor C2; the third N-type field effect transistor The gate end of the transistor MN3 is connected to the charging output end BL_PREC; the source end of the third N-type field effect transistor MN3 is respectively connected to the drain end of the fifth N-type field effect transistor MN5 and the drain end of the sixth N-type field effect transistor MN6; the source end of the fifth N-type field effect transistor MN5 is connected to the bit line BL of the non-volatile memory; the drain end of the fourth N-type field effect transistor MN4 is connected to the latch; the source end of the fourth N-type field effect transistor MN4 and the other end of the second capacitor C2 are respectively grounded.

[0072] It can be understood that the embodiment of the present invention only provides a simplified circuit of a sense amplifier. The parameters in the sense amplifier and the setting of the input signal can be set by those skilled in the art according to the specific situation of the non-volatile memory, so that the sense amplifier can charge the bit line in the non-volatile memory, thereby supporting the reading read and programming pgm of the non-volatile memory. The embodiment of the present invention does not limit the specific circuit structure of the sense amplifier.

[0073] In specific applications, the field effect tubes (including P-type field effect tubes and N-type field effect tubes) of the embodiments of the present invention can be single MOS transistors, which makes the circuit construction simple and low-cost; or they can be constructed by multiple MOS transistors, with a source terminal, a gate terminal and a drain terminal. For example, a structure in which multiple MOS tubes are connected in parallel is used. When multiple MOS tubes are connected in parallel, the source terminal, the gate terminal and the drain terminal of each MOS tube are connected separately to provide a larger current for the circuit in a parallel manner. The embodiments of the present invention do not specifically limit this.

[0074] The charging circuit in the embodiment of the present invention can quickly charge the gate voltage of MN3 to Vref and clamp it, and then charge the bit line BL through MN3, thereby accelerating the read and pgm processes of the non-volatile memory. In practical applications, the storage capacity of the non-volatile memory is large, and the number of SA and BL can reach tens of thousands or even hundreds of thousands. Therefore, the parasitic capacitance on BL is tens of nF. By reducing the charging time of BL, the time of read and pgm operations can be greatly shortened.

[0075] In summary, the charging acceleration unit in the embodiment of the present invention can provide accelerated charging for the device to be charged and accelerated through the charging output terminal, which greatly improves the charging speed of the device to be charged and accelerated. When the device to be charged and accelerated is a non-volatile memory, the speed of data programming and data reading of NAND FLASH can be greatly improved. When the acceleration is completed, the charging acceleration unit can also shut down by itself without causing other impacts on the circuit where the device to be charged and accelerated is located. Specifically, the charging acceleration unit includes a first charging module, a second charging module, a shutdown module, and a charging output terminal; the first charging module includes: a first power connection terminal connected to the first power supply, a first signal receiving terminal for receiving a first signal, and a first charging terminal connected to the shutdown module; the second charging module includes: a second power connection terminal connected to the first power supply, a second signal receiving terminal for receiving a second signal, a second charging terminal connected to the shutdown module, and a shutdown signal receiving terminal for receiving the shutdown signal of the shutdown module; wherein the second signal and the first signal are inverted signals to each other; the charging output terminal is connected to the second charging terminal, and the charging output terminal is used to connect the device to be charged and accelerated; the shutdown module includes: The shutdown module also includes: a first charging receiving end connected to the first charging end, used for receiving the charge of the first power source at the first charging receiving end when the first charging module is in a conductive state according to the first signal; the shutdown module also includes: a second charging receiving end connected to the second charging end, used for receiving the charge of the first power source at the second charging receiving end when the second charging module is in a conductive state according to the second signal, so as to improve the charging speed of the charging acceleration device; the shutdown module also includes: a shutdown signal output end connected to the shutdown signal receiving end, used for shutting down the second charging module through the shutdown signal receiving end when the voltage at the second charging receiving end is greater than the conductive threshold of the shutdown module, so as to avoid interference of the charging acceleration unit to the circuit.

[0076] It should be noted that, for the sake of simplicity, each embodiment is described as a series of circuit combinations, but those skilled in the art should know that the embodiments of the present invention are not limited to the description. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the circuit connections involved are not necessarily required for the embodiments of the present invention.

[0077] The present invention is shown and described in detail above through the accompanying drawings and preferred embodiments. However, the present invention is not limited to these disclosed embodiments, and other solutions derived therefrom by those skilled in the art are also within the protection scope of the present invention.

[0078] It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention, and these improvements and modifications should also be regarded as within the scope of protection of the present invention.

[0079] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0080] The charging acceleration unit, charging circuit and non-volatile memory provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A charging acceleration unit, characterized in that: The charging acceleration unit comprises: A first charging module, a second charging module, a shut-off module, and a charging output terminal; The first charging module comprises: a first power connection terminal connected to the first power source, a first signal receiving terminal for receiving a first signal, and a first charging terminal connected to the shutdown module; The second charging module comprises: a second power connection terminal connected to the first power supply, a second signal receiving terminal for receiving a second signal, a second charging terminal connected to the shutdown module, and a shutdown signal receiving terminal for receiving a shutdown signal from the shutdown module; wherein the second signal and the first signal are inverse phase signals to each other; The shutdown module includes: a first charging receiving end connected to the first charging end, and configured to receive charging from the first power source when the first charging module is in a conducting state according to the first signal; The shut-off module further includes: a second charging receiving end connected to the second charging end, configured to receive charging from the first power source when the second charging module is in a conducting state according to the second signal; The shutdown module further includes: a shutdown signal output terminal connected to the shutdown signal receiving terminal, configured to shut down the second charging module through the shutdown signal receiving terminal when the voltage of the second charging receiving terminal is greater than the conduction threshold of the shutdown module; The charging output terminal is connected to the second charging terminal, and the charging output terminal is used to connect to the acceleration device to be charged.

2. The charging acceleration unit according to claim 1, characterized in that: The first charging module includes: a first P-type field effect transistor; The gate terminal of the first P-type field effect transistor serves as the first signal receiving terminal; The source end of the first P-type field effect transistor serves as the first power connection end; The drain terminal of the first P-type field effect transistor serves as the first charging terminal.

3. The charging acceleration unit according to claim 1, characterized in that: The second charging module includes: a second P-type field effect transistor and a third P-type field effect transistor; The gate terminal of the second P-type field effect transistor serves as the second signal receiving terminal; The source end of the second P-type field effect transistor serves as the second power supply connection end; The drain terminal of the second P-type field effect transistor is connected to the source terminal of the third P-type field effect transistor; The gate terminal of the third P-type field effect transistor serves as the shutdown signal receiving terminal; The drain terminal of the third P-type field effect transistor serves as the second charging terminal.

4. The charging acceleration unit according to claim 1, characterized in that: The shutdown module includes: a first N-type field effect transistor, an inverter; The gate terminal of the first N-type field effect transistor serves as the second charging receiving terminal; The source terminal of the first N-type field effect transistor is grounded; The drain end of the first N-type field effect transistor serves as the first charging receiving end and is connected to the input end of the inverter; The output end of the inverter serves as the shutdown signal output end.

5. A charging circuit, characterized in that: The invention comprises the charging acceleration unit as described in any one of claims 1 to 4.

6. The charging circuit according to claim 5, characterized in that: The charging circuit further includes: a third charging module; The third charging module includes: an amplifier, a fourth P-type field effect transistor, a resistor, and a capacitor; The amplifier comprises a reference voltage input terminal for receiving a reference voltage signal, a third signal input terminal for receiving a third signal, a comparison voltage input terminal, and an amplifier output terminal; wherein the third signal and the second signal are mutually inverted signals; The amplifier output terminal is connected to the gate terminal of the fourth P-type field effect transistor; The comparison voltage input terminal is connected to the drain terminal of the fourth P-type field effect transistor; The drain end of the fourth P-type field effect transistor is also connected to one end of the resistor, one end of the capacitor, and the charging output end respectively; The source end of the fourth P-type field effect transistor is connected to the second power supply; The other end of the resistor and the other end of the capacitor are grounded.

7. A non-volatile memory, characterized in that: Includes the charging circuit as claimed in claim 5.

8. The nonvolatile memory according to claim 7, characterized in that: The nonvolatile memory also includes a sense amplifier.

9. The nonvolatile memory according to claim 8, characterized in that: The sense amplifier comprises: A second N-type field effect transistor, a third N-type field effect transistor, a fourth N-type field effect transistor, a fifth N-type field effect transistor, a sixth N-type field effect transistor, a second capacitor, and a latch; The drain terminal of the second N-type field effect transistor is connected to a third power supply; The source end of the second N-type field effect transistor is respectively connected to the drain end of the third N-type field effect transistor, the gate end of the fourth N-type field effect transistor, and one end of the second capacitor; The gate terminal of the third N-type field effect transistor is connected to the charging output terminal; The source end of the third N-type field effect transistor is connected to the drain end of the fifth N-type field effect transistor and the drain end of the sixth N-type field effect transistor respectively; The source end of the fifth N-type field effect transistor is connected to the bit line of the non-volatile memory; The drain terminal of the fourth N-type field effect transistor is connected to the latch; A source end of the fourth N-type field effect transistor and the other end of the second capacitor are grounded respectively.

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