Power semiconductor devices

Abstract

The power semiconductor device includes a semiconductor body having a front side and a back side, which includes a drift region of a first conductivity type; a field stop region of the first conductivity type, arranged between the drift region and the back side and having a dopant with a higher dopant concentration than the drift region, created by proton implantation via the back side; and an emitter adjustment region of the first conductivity type, arranged between the field stop region and the back side and having a dopant with a higher dopant concentration than the field stop region. The field stop region includes a dopant concentration profile presenting a first local maximum and a first local minimum, the first local minimum being arranged between the first local maximum and another local maximum of the dopant concentration profile of the field stop region and / or between the first local maximum and the maximum of the dopant concentration profile of the emitter adjustment region, the dopant concentration at the first local maximum being at most three times as high as the dopant concentration at the first local minimum, and the semiconductor body is or includes a semiconductor substrate having an interstitial oxygen concentration of at least 1E17 cm<supgt;‑3< / supgt>.

Description

Technical Field

[0001] The present description relates to embodiments of a power semiconductor device. In particular, the present description relates to embodiments of a power semiconductor device including a field stop zone, and to embodiments of processing and / or manufacturing such a power semiconductor device. Background Art

[0002] Modern devices in automotive, consumer and industrial applications rely on power semiconductor devices for many functions, such as converting electrical energy and driving electric motors or motors. For example, insulated gate bipolar transistors (IGBTs) and metal oxide semiconductor field effect transistors (MOSFETs), to name a few, have been used in a variety of applications, including but not limited to switches in power supplies and power converters, for example, in traction applications.

[0003] A power semiconductor device typically includes a semiconductor body configured to conduct a load current along a load current path between two load terminals of the device. For example, in a vertical arrangement of such a power semiconductor device, a first load terminal may be coupled to a front side of the semiconductor body, and a second load terminal may be coupled to a back side of the semiconductor body. The load current path typically passes through a drift region of a first conductivity type (e.g., n-type).

[0004] Furthermore, in some cases, the load current path can be controlled by an insulated electrode, sometimes referred to as a gate electrode. For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can selectively set the power semiconductor device to one of a conducting state and a blocking state.

[0005] Typically, the semiconductor body comprises a field stop zone of the first conductivity type (sometimes also referred to as a buffer zone), wherein the field stop zone can be arranged, for example, between the drift zone and the back side. The field stop zone can be configured to influence the course of the electric field during the blocking state of the power semiconductor device. The field stop zone can present dopants of the first conductivity type at a higher concentration than the drift zone. For example, the drop of the electric field in the blocking state along the direction pointing from the front side to the back side can thereby be increased. The field stop zone of the semiconductor transistor can be formed, for example, by the implantation of protons through the back side of the semiconductor body.

[0006] The field stop zone may have an influence on a number of other characteristics of the power semiconductor device.It is often desirable to provide a power semiconductor device that is optimized with respect to certain electrical characteristics such as conduction and / or switching losses, short circuit ruggedness and / or turn-off softness. Summary of the invention

[0007] According to one embodiment, a power semiconductor device comprises a semiconductor body having a front side and a back side, wherein the semiconductor body comprises: a drift zone of a first conductivity type; a field stop zone of the first conductivity type, the field stop zone being arranged between the drift zone and the back side and having dopants of the first conductivity type at a higher dopant concentration than the drift zone, wherein the field stop zone is at least partially created by proton implantation via the back side; and an emitter adjustment zone of the first conductivity type, the emitter adjustment zone being arranged between the field stop zone and the back side and having dopants of the first conductivity type at a higher dopant concentration than the field stop zone; wherein the field stop zone comprises, in a cross section along a vertical direction pointing from the back side to the front side, a dopant concentration distribution of the dopant of the first conductivity type exhibiting a first local maximum and a first local minimum, the first local minimum being arranged between the first local maximum and another local maximum of the dopant concentration distribution of the field stop zone and / or between the first local maximum and a maximum of the dopant concentration distribution of the emitter adjustment zone; and wherein the dopant concentration at the first local maximum is at most three times higher than the dopant concentration at the first local minimum.

[0008] According to another embodiment, a power semiconductor device comprises a semiconductor body having a front side and a back side, wherein the semiconductor body comprises: a drift zone of a first conductivity type; a field stop zone of the first conductivity type, the field stop zone being arranged between the drift zone and the back side and having dopants of the first conductivity type at a higher dopant concentration than the drift zone, wherein the field stop zone is at least partially created by proton implantation via the back side; and an emitter adjustment zone of the first conductivity type, the emitter adjustment zone being arranged between the field stop zone and the back side and having dopants of the first conductivity type at a higher dopant concentration than the field stop zone; wherein the field stop zone comprises, in a cross section along a vertical direction pointing from the back side to the front side, a dopant concentration profile of the dopant of the first conductivity type exhibiting a first local maximum and a first local minimum, the first local minimum being arranged between the first local maximum and another local maximum of the dopant concentration profile of the field stop zone and / or between the first local maximum and a maximum of the dopant concentration profile of the emitter adjustment zone; wherein the dopant concentration at the first local maximum is at most three times higher than the dopant concentration at the first local minimum; and wherein the semiconductor body is or comprises a dopant concentration profile having at least 1E17 cm -3 The interstitial oxygen concentration of the semiconductor substrate.

[0009] According to another embodiment, a power semiconductor device includes a semiconductor body having a front side and a back side, wherein the semiconductor body includes: a drift zone of a first conductivity type; a field stop zone of the first conductivity type, the field stop zone being arranged between the drift zone and the back side and having dopants of the first conductivity type with a higher dopant concentration than the drift zone, wherein the field stop zone is at least partially created by proton implantation via the back side; and an emitter adjustment zone of the first conductivity type, the emitter adjustment zone being arranged between the field stop zone and the back side and having dopants of the first conductivity type with a higher dopant concentration than the field stop zone; wherein the field stop zone includes a zone in which the dopant concentration is at least three times as high as the dopant concentration in the drift zone, and wherein at least 20% of the dopants of the first conductivity type in the zone are oxygen-induced thermal donors.

[0010] According to another embodiment, a power semiconductor device comprises a semiconductor body having a front side and a back side, wherein the semiconductor body comprises: a drift zone of a first conductivity type; a field stop zone of the first conductivity type, the field stop zone being arranged between the drift zone and the back side and having dopants of the first conductivity type at a higher dopant concentration than the drift zone, wherein the field stop zone is at least partially created by proton implantation via the back side; and an emitter adjustment zone of the first conductivity type, the emitter adjustment zone being arranged between the field stop zone and the back side and having dopants of the first conductivity type at a higher dopant concentration than the field stop zone; wherein the semiconductor body is or comprises a first conductivity type having a first conductivity type of at least 1E17 cm -3 A semiconductor substrate having an interstitial oxygen concentration of ; wherein the field stop zone includes a region in which the dopant concentration is at least three times as high as the dopant concentration in the drift region, and wherein at least 20% of the dopants of the first conductivity type in the region are oxygen-induced thermal donors.

[0011] According to another embodiment, a method for processing a power semiconductor device includes: providing a semiconductor body having a front side and a back side; creating or providing a drift zone of a first conductivity type inside the semiconductor body; creating a field stop zone of the first conductivity type inside the semiconductor body by at least one proton implantation via the back side, the field stop zone being arranged between the drift zone and the back side and having a dopant of the first conductivity type with a higher dopant concentration than the drift zone; and creating an emitter adjustment zone of the first conductivity type inside the semiconductor body, the emitter adjustment zone being arranged between the field stop zone and the back side and having a dopant of the first conductivity type with a higher dopant concentration than the field stop zone; wherein the field stop zone includes, in a cross section along a vertical direction pointing from the back side to the front side, a dopant concentration distribution of the dopant of the first conductivity type presenting a first local maximum and a first local minimum, the first local minimum being arranged between the first local maximum and another local maximum of the dopant concentration distribution of the field stop zone and / or between the first local maximum and a maximum of the dopant concentration distribution of the emitter adjustment zone; and wherein the dopant concentration at the first local maximum is at most three times as high as the dopant concentration at the first local minimum.

[0012] According to another embodiment, a method for processing a power semiconductor device comprises: providing a semiconductor body having a front side and a back side; creating or providing a drift zone of a first conductivity type inside the semiconductor body; creating a field stop zone of the first conductivity type inside the semiconductor body by at least one proton implantation via the back side, the field stop zone being arranged between the drift zone and the back side and having a dopant of the first conductivity type with a higher dopant concentration than the drift zone; and creating an emitter adjustment zone of the first conductivity type inside the semiconductor body, the emitter adjustment zone being arranged between the field stop zone and the back side and having a dopant of the first conductivity type with a higher dopant concentration than the field stop zone. a dopant of a first conductivity type; wherein the field stop zone comprises, in a cross section along a vertical direction pointing from the back side to the front side, a dopant concentration distribution of the dopant of the first conductivity type exhibiting a first local maximum and a first local minimum, the first local minimum being arranged between the first local maximum and another local maximum of the dopant concentration distribution of the field stop zone and / or between the first local maximum and the maximum of the dopant concentration distribution of the emitter adjustment zone; wherein the dopant concentration at the first local maximum is at most three times higher than the dopant concentration at the first local minimum; and wherein the semiconductor body is or comprises a dopant concentration having a thickness of at least 1E17 cm -3 The interstitial oxygen concentration of the semiconductor substrate.

[0013] According to another embodiment, a method for processing a power semiconductor device includes: providing a semiconductor body having a front side and a back side; creating or providing a drift zone of a first conductivity type inside the semiconductor body; creating a field stop zone of the first conductivity type inside the semiconductor body by at least one proton implantation through the back side, the field stop zone being arranged between the drift zone and the back side and having a dopant of the first conductivity type with a higher dopant concentration than the drift zone; and creating an emitter adjustment zone of the first conductivity type inside the semiconductor body, the emitter adjustment zone being arranged between the field stop zone and the back side and having a dopant of the first conductivity type with a higher dopant concentration than the field stop zone; wherein the field stop zone includes a zone in which the dopant concentration is as high as at least three times the dopant concentration in the drift zone; and wherein at least 20% of the dopant of the first conductivity type in the zone is oxygen-induced thermal donors.

[0014] According to another embodiment, a method for processing a power semiconductor device comprises: providing a semiconductor body having a front side and a back side; creating or providing a drift zone of a first conductivity type inside the semiconductor body; creating a field stop zone of the first conductivity type inside the semiconductor body by at least one proton implantation via the back side, the field stop zone being arranged between the drift zone and the back side and having a dopant of the first conductivity type with a higher dopant concentration than the drift zone; and creating an emitter adjustment zone of the first conductivity type inside the semiconductor body, the emitter adjustment zone being arranged between the field stop zone and the back side and having a dopant of the first conductivity type with a higher dopant concentration than the field stop zone; wherein the semiconductor body is or comprises a first conductivity type having at least 1E17 cm -3 A semiconductor substrate having an interstitial oxygen concentration of ; wherein the field stop zone includes a region in which the dopant concentration is at least three times as high as the dopant concentration in the drift region; and wherein at least 20% of the dopants of the first conductivity type in the region are oxygen-induced thermal donors.

[0015] Those skilled in the art will recognize additional features and advantages after reading the following detailed description and viewing the accompanying drawings. It should be noted that the features of the present invention described above and to be described below for power semiconductor devices can be similarly applied to processing and / or manufacturing methods, and vice versa. In addition, unless otherwise explicitly stated, the features of different embodiments can be combined with each other to form another embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The parts in the drawings are not necessarily to scale, instead, the emphasis is on illustrating the principles of the present invention. In addition, in the drawings, the same reference numerals represent corresponding parts. In the drawings:

[0017] Figure 1 schematically and exemplarily illustrates a portion of a vertical cross section of a power semiconductor device according to one or more embodiments;

[0018] Figure 2A - B each schematically and exemplarily illustrates a dopant concentration profile within an emitter tuning region and a field stop region according to one or more embodiments;

[0019] Figure 3 schematically and exemplarily illustrate dopant concentration profiles within an emitter tuning region and a field stop region according to one or more embodiments;

[0020] Figure 4 schematically and exemplarily illustrates a dopant concentration profile within a field stop zone according to one or more embodiments;

[0021] Figure 5 schematically and exemplarily illustrates a portion of a vertical cross section of a power semiconductor device according to one or more embodiments;

[0022] Fig. 6A -B each schematically and exemplarily illustrates a dopant concentration profile according to one or more embodiments;

[0023] Figure 7 schematically and exemplarily illustrates a portion of a vertical cross section of a power semiconductor device according to one or more embodiments (left figure) and the course of dopant concentration and corresponding electric field within the power semiconductor device (right figure); and

[0024] Fig. 8A -D each schematically and exemplarily show a portion of a vertical cross section of a power semiconductor device according to one or more embodiments. DETAILED DESCRIPTION

[0025] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0026] In this regard, directional terms such as "top", "bottom", "below", "front", "back", "back", "head", "tail", "below", "above", etc. may be used with reference to the orientation of the accompanying drawings being described. Since the parts of the embodiments may be positioned in a plurality of different orientations, directional terms are for illustrative purposes and are by no means limiting. It should be understood that other embodiments may also be utilized and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following detailed description should not be considered restrictive, and the scope of the present invention is defined by the appended claims.

[0027] Reference will now be made in detail to various embodiments, one or more examples of which are shown in the accompanying drawings. Each example is provided by way of explanation and is not intended to limit the invention. For example, a feature shown or described as part of one embodiment may also be used on other embodiments or in combination with other embodiments to produce yet another embodiment. The invention is intended to include such modifications and variations. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing steps are represented by the same reference numerals in different drawings unless otherwise specified.

[0028] The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, a surface of a semiconductor wafer or die. For example, the first lateral direction X and the second lateral direction Y mentioned below may both be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0029] The term "vertical" used in this specification is intended to describe an orientation that is substantially perpendicular to a horizontal surface arrangement, i.e., parallel to the normal direction of the surface of the semiconductor wafer. For example, the vertical direction Z mentioned below can be a vertical direction perpendicular to both the first lateral direction X and the second lateral direction Y.

[0030] In this specification, n-doping is referred to as the "first conductivity type" and p-doping is referred to as the "second conductivity type." Alternatively, the opposite doping relationship can be adopted, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

[0031] Furthermore, within the present specification, the terms "charge carrier concentration", "dopant concentration" and "donor concentration" may refer to an average charge carrier / dopant / donor concentration of a particular semiconductor region or semiconductor area or to a mean charge carrier / dopant / donor concentration or a sheet charge carrier / dopant / donor concentration, respectively. Thus, for example, a statement that a particular semiconductor region exhibits a higher or lower specific dopant concentration compared to the dopant concentration of another semiconductor region may indicate that the respective average dopant concentrations of the semiconductor regions are different from each other.

[0032] In the context of this specification, the terms "ohmic contact", "electrical contact", "ohmic connection" and "electrical connection" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, regions, parts or portions of a semiconductor device or between different terminals of one or more devices or between a terminal or metallization or electrode and a portion or part of a semiconductor device. In addition, in the context of this specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of a respective semiconductor device; for example, a transition between two elements that are in contact with each other may not include additional intermediate elements, etc.

[0033] Additionally, in the context of this specification, if not otherwise specified, the term "electrically insulated" is used in its generally validly understood context, and is therefore intended to describe that two or more components are located separately from each other and there is no ohmic connection connecting these components. However, components that are electrically insulated from each other can still be coupled to each other, such as mechanically and / or capacitively and / or inductively. For example, two electrodes of a capacitor can be electrically insulated from each other while being mechanically and capacitively coupled to each other through, for example, an insulator (e.g., a dielectric).

[0034] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices, such as power semiconductor transistors, that present a strip-shaped unit or a pin-shaped unit configuration, which can be used in a power converter or a power supply. Therefore, in one embodiment, the semiconductor device is configured to carry a load current to be fed to a load and / or provided by a power source. For example, the semiconductor device may include one or more active power semiconductor units, such as a monolithic integrated diode unit, and / or a monolithic integrated transistor unit, and / or a monolithic integrated IGBT unit, and / or a monolithic integrated RC-IGBT unit, and / or a monolithic integrated MOS gate-controlled diode (MGD) unit, and / or a monolithic integrated MOSFET unit and / or its derivatives. Such a diode unit and / or such a transistor unit can be integrated in a power semiconductor module. A plurality of such units can constitute a unit field arranged together with the active area of ​​the power semiconductor device.

[0035] The term "power semiconductor device" as used in this specification is intended to describe a semiconductor device on a single chip having high voltage blocking and / or high current carrying capability. In other words, such a power semiconductor device is intended for high current (typically in the ampere range, e.g., up to tens or hundreds of amperes) and / or high voltage (typically above 100V, more typically 500V and higher, e.g., up to at least 1 kV, up to at least 6 kV). For example, the process semiconductor device described below may be a semiconductor device exhibiting a stripe cell configuration or a pin cell configuration, and may be configured for use as a power component in low, medium and / or high voltage applications.

[0036] For example, the term “power semiconductor device” as used in this specification does not refer to a logic semiconductor device that is used, for example, to store data, calculate data, and / or other types of semiconductor-based data processing.

[0037] Figure 1 Schematically and exemplarily, a portion of a vertical cross section of a power semiconductor transistor 1 according to one or more embodiments is shown. The vertical cross section shown extends in a plane defined by a first lateral direction X and a vertical direction Z, and is orthogonal to a second lateral direction Y. Each of the shown components may also extend along the second lateral direction Y.

[0038] The semiconductor device 1 comprises a semiconductor body 10 having a front side 10-1 and a back side 10-2. For example, the semiconductor body 10 may be coupled to each of a first load terminal structure and a second load terminal structure (not shown). The first load terminal structure may be, for example, an anode terminal, an emitter terminal or a source terminal (depending on the type of power semiconductor device), which is, for example, coupled to the front side 10-1 of the semiconductor body 10. The second load terminal structure may be, for example, a cathode terminal, a collector terminal or a drain terminal, which may be coupled to the back side 10-2 of the semiconductor body 10. For example, the first load terminal structure and / or the second load terminal may include respective front side or back side metallizations.

[0039] In one embodiment, the semiconductor body 10 is or includes a semiconductor body having a thickness of at least 1E17 cm -3 For example, the semiconductor substrate may be produced by a Czochralski (Cz) or a Magnetic Czochralski (MCz) process.

[0040] The semiconductor body 10 includes a drift region 100, which may be configured, for example, to conduct a load current between the first load terminal structure and the second load terminal structure described above. The drift region 100 may include dopants of a first conductivity type (eg, n-type). In one embodiment, the drift region 100 is n-type. - Doped semiconductor region.

[0041] Furthermore, the power semiconductor device 1 may include one or more power cells 14, each of which extends at least partially into the semiconductor body 10 at the front side 10-1. One or more power cells 14 may be configured to control the load current depending on the flow direction of the load current and / or depending on the switching state of the power semiconductor device 1. For example, in the case where the power semiconductor device 1 has a diode configuration, a large power cell 14 may be provided, wherein the power cell 14 may include an anode region of the second conductivity type. The transition between the anode region and the drift region 100 may form a pn junction configured to block a blocking voltage. In another embodiment in which the power semiconductor device has a transistor configuration, a plurality of power cells 14 ( Figure 1 ), which may be configured to selectively switch the power semiconductor transistor 1 to one of an on state and a blocking state. In other words, one or more power cells 14 may be configured to selectively conduct a load current or block a blocking voltage depending on the switching state of the power semiconductor device 1. For example, in one embodiment, the power semiconductor device 1 is an IGBT or includes an IGBT. Correspondingly, a plurality of power cells 14 in the form of IGBT cells (such as IGBT cells having gate electrodes arranged in vertical trenches) may be provided. Those skilled in the art are familiar with the principles and variations of such configurations of power cells 14, and therefore will not be explained in more detail.

[0042] The semiconductor body 10 further comprises a field stop zone 105 of the first conductivity type, which is arranged between the drift region 100 and the back side 10-2. It should be noted that in this context, the relationship "between" should be understood in a broad sense, that is, other elements may be arranged between the field stop zone 105 and the back side 10-2, such as the emitter adjustment zone 106 mentioned below, see Figure 1 As is known in principle to a person skilled in the art, such a field stop zone 105 may be provided for influencing the course of the electric field, in particular during the blocking state of the power semiconductor device 1 .

[0043] The field stop zone 105 may include dopants of the first conductivity type at a higher concentration than the drift zone 100. Figure 2A and 2B , which schematically and exemplarily depicts a dopant concentration profile extending from the back side 10-2 to the inside of the semiconductor body 10 along the vertical direction Z. For example, due to the presence of the field stop zone 105, a drop in the electric field in the blocking state along the direction pointing from the front side 10-1 to the back side 10-2 (i.e., along the direction opposite to the vertical direction Z) can be increased in the field stop zone 105.

[0044] For example, the field stop zone 105 may have been formed by implantation of protons through the back side 10-2 of the semiconductor body 10. Such an implantation process may be followed by a subsequent annealing step, which may be performed, for example, at a temperature in the range of 380° C. to 420° C. and for a duration in the range of 30 minutes to 10 hours or for a duration between 1 hour and 5 hours. Thus, in the context of the present specification, the term "dopant" may, for example, denote charge centers that have been created inside the semiconductor body 10 by proton implantation and subsequent thermal annealing.

[0045] In one embodiment, the dose of the dopant of the first conductivity type in the field stop zone 105 corresponds to at most 50% of the material-specific breakdown charge for the semiconductor body 10. For example, the dose may be in the range of 15% to 70% or one quarter to one half of the material-specific breakdown charge for the semiconductor body 10, e.g. in the case of a silicon semiconductor body 10, at 2E11 cm -2 To 8E11cm -2 Or at 2.5E11 cm -2 to 5E11 cm -2 within the range.

[0046] In addition to the field stop zone 105 , the semiconductor body 1 may include an emitter adjustment zone 106 of the first conductivity type, such as Figure 1 As schematically shown in Figure 2A and 2B The emitter adjustment region 106 is arranged between the field stop region 105 and the back side 10-2 and has a dopant of the first conductivity type at a higher dopant concentration than the field stop region 105. Also in this context, the relationship "between" should be understood broadly, i.e., other elements such as the back side emitter region 107 mentioned below may be arranged between the emitter adjustment region 106 and the back side 10-2. For example, the vertical extension d1 of the emitter adjustment region may be equal to or less than 1 μm or even less than 0.5 μm.

[0047] In one embodiment, the emitter adjustment region 106 mainly includes another type of dopant other than the dopant created by proton implantation (possibly followed by thermal annealing). For example, the emitter adjustment region 106 can mainly include phosphorus and / or arsenic and / or antimony and / or selenium and / or sulfur dopants, which can be implanted through the back side 10-2. In other words, creating the emitter adjustment region 106 can include implanting dopants such as phosphorus and / or arsenic and / or antimony and / or selenium and / or sulfur dopants through the back side 10-2.

[0048] For example, in one embodiment, the dose of the dopant of the first conductivity type in the emitter adjustment region 106 corresponds to at least 50% of the material-specific breakdown charge for the semiconductor body 10. For example, the dose may be in the range of ½ to 2 of the material-specific breakdown charge for the semiconductor body 10, e.g., in the case of a silicon semiconductor body 10, in the range of 6E11 cm -2 to 2.4E12 cm -2 within the range.

[0049] In accordance with Figure 2A and Figure 3 In each of the embodiments, the field stop zone 105 includes a dopant concentration distribution of a dopant of the first conductivity type exhibiting a first local maximum 1051 and a first local minimum 1052 in a cross section along the vertical direction Z. The first local minimum 1052 may be arranged between the first local maximum 1051 and the maximum of the dopant concentration distribution of the emitter adjustment region 106, such as Figure 2A and 3 Each of the shown.

[0050] Also in this context, the relation “between” should be understood broadly, i.e. the statement that the first local minimum 1052 may be arranged between the first local maximum 1051 and the maximum of the dopant concentration distribution of the emitter adjustment region 106 does not generally exclude embodiments in which, for example, further local maxima 1053, 1055 and local minima 1054, 1056 are arranged between the first local minimum 1052 and said maximum of the dopant concentration distribution of the emitter adjustment region 106. Figure 3 exemplarily shown in FIG. 1 and explained in further detail below.

[0051] However, in some embodiments, the first local minimum 1052 may be arranged directly between the first local maximum 1051 and the maximum of the dopant concentration distribution of the emitter adjustment region 106, in the sense that, apart from the first local minimum 1052, no other local maximum or local minimum is provided between the first local maximum 1051 and the maximum of the dopant concentration distribution of the emitter adjustment region 106. Figure 2AIn the exemplary embodiment shown, the dopant concentration exhibits a single first local maximum 1051 and a single first local minimum 1052 located between the first local maximum and the maximum of the emitter adjustment region 106. In other words, the dopant concentration distribution within the field stop zone 105 exhibits only one deep local maximum, namely the first local maximum 1051. The relatively low-doped portion between the first local maximum 1051 and the emitter adjustment region 106 may include a thermal donor (i.e., an oxygen-induced thermal donor). A thermal donor (oxygen donor) is a class of several electrically active oxygen complexes consisting of small aggregates of several oxygen atoms. Specifically, a thermal donor in silicon is a silicon-oxygen complex containing three or more oxygen atoms, which serves as the main thermal donor species in the thermally treated oxygen-containing silicon. In another embodiment (not shown), the dopant concentration distribution within the field stop zone 105 may exhibit, for example, a relatively shallow local maximum (i.e., a local maximum located relatively close to the back side 10-2) and a relatively deep local maximum (i.e., a local maximum that may be located, for example, close to the back side 10-2). Figure 2A The relatively lower doped portion between the relatively shallower local maximum and the relatively deeper local maximum may include a thermal donor.

[0052] On the contrary, Figure 3 In an exemplary embodiment of the present invention, the dopant concentration distribution of the field stop zone 105 exhibits three local maxima 1051, 1053, 1055 and three local minima 1052, 1054, 1056 formed therebetween and / or formed between the local maxima 1055 and the maximum of the emitter adjustment zone 106. Generally, a plurality (e.g., 2 to 5) of such local maxima 1051, 1053, 1055 and corresponding local minima 1052, 1054, 1056 may be provided. Therefore, as Figure 3 As exemplarily shown in FIG. 1 , the first local minimum 1052 may also be arranged between the first local maximum 1051 and another local maximum 1053, 1055 of the dopant concentration distribution of the field stop zone 105. At the same time, Figure 3 An embodiment is shown by way of example, in which the first local minimum 1052 is arranged directly between the first local maximum 1051 and the further local maximum 1053 , in the sense that, apart from the first local minimum 1052 , no further local maxima or local minima are provided between the first local maximum 1051 and the further local maximum 1053 .

[0053] According to one embodiment, the dopant concentration at the first local maximum 1051 is at most three times higher than the dopant concentration at the first local minimum 1052, such as for example at most two times higher. Furthermore, in a variant embodiment, at least 20%, such as at least 30%, such as at least 50%, or even at least 70% of the dopant at the first local minimum 1052 is a thermal donor. Figure 3 In the case where multiple local minima 1052, 1054, 1056 are provided in the field stop zone 105 as exemplarily depicted, also at other local minima 1054, 1056, at least 20%, such as at least 30%, or such as at least 50% or at least 70% of the dopants may be thermal donors.

[0054] Furthermore, in embodiments where multiple local maxima are provided in the field stop zone 105 , the dopant concentration at the local maximum located closest to the emitter adjustment region 106 may be as small as at least ⅓ of the maximum dopant concentration of the emitter adjustment region 106 .

[0055] In accordance with Figure 2B In one embodiment of the present invention, the field stop zone 105 does not necessarily include the first local maximum 1051 and the first local minimum 1052 as described above. In this embodiment, the field stop zone 105 includes a region R, wherein the dopant concentration is at least three times, such as at least 5 times or even 10 times, higher than the dopant concentration in the drift zone 100. Furthermore, at least 20%, such as at least 30% or even at least 40% of the dopants of the first conductivity type in the region R are thermal donors.

[0056] exist Figure 4 , the solid curve shows another exemplary dopant concentration profile according to one or more embodiments, wherein the field stop zone 105 exhibits a plurality of (four in this example) local maxima 1051, 1053, 1055, 1057 and corresponding local minima 1052, 1054, 1056 formed therebetween. Figure 4 For example, such a dopant concentration profile may be achieved by several proton implantation steps, which may be performed at different implantation energies and / or at different implantation angles relative to the backside surface. For example, at least three, such as at least 4, different implantation energies may be used. Figure 4 The solid curve in FIG. 1 corresponds to a case where the semiconductor body 10 exhibits a relatively high interstitial oxygen concentration (such as at least 1E17 cm -3 As described above, the semiconductor substrate may be produced by a Czochralski (Cz) or a Magnetic Czochralski (MCz) process, which may result in such an interstitial oxygen concentration.

[0057] For comparison, Figure 4The dashed curve in shows the dopant concentration profile created by proton implantation in a floating zone (FZ) substrate having a rather low interstitial oxygen concentration. A comparison shows that the local minima 1052, 1054, 1056 of the solid curve are less pronounced than the corresponding local minima of the dashed curve, i.e., in case of a relatively high interstitial oxygen concentration in the substrate, the corresponding minimum dopant concentration is higher. Furthermore, in case of the solid curve, the proton implantation(s) may be performed at a relatively low dose, resulting in lower local maxima 1051, 1053, 1055, 1057 compared to the dashed reference curve.

[0058] In accordance with Figure 3 and Figure 4 In each of the embodiments, the dopant concentration at the local maximum 1051, 1053, 1055, 1057 decreases when going from one local maximum 1057, 1055, 1053 to another local maximum 1055, 1053, 1051 along the vertical direction Z. In other words, the dopant concentration may decrease each time when going from one local maximum 1057, 1055, 1053 to another local maximum 1055, 1053, 1051 located further away from the back side 10-2 (i.e., deeper in the semiconductor body as viewed from the back side 10-2). In addition, as Figure 4 As shown exemplarily, it can be considered that when moving from one local maximum 1055, 1053 to another local maximum 1053, 1051 along the vertical direction Z, the ratio of the dopant concentration at the local maximum 1051, 1053, 1055 to the dopant concentration at the local minimum 1052, 1054, 1056 decreases, and the local minimum 1052, 1054, 1056 is positioned close to the local maximum 1051, 1053, 1055 and is closer to the back side 10-2 than the local maximum 1051, 1053, 1055.

[0059] In one embodiment, the semiconductor body 10 may further include a backside emitter region 107 of a second conductivity type (eg, p-type), which may be arranged between the emitter adjustment region 106 and the backside 10 - 2 , for example Figure 5 , 6A and 6B. Figure 5 , 6A 6B in each case show a semiconductor component 1 having a back-side emitter region 107 and otherwise correspond to the semiconductor components already described above. Figure 1 , 2AIn the case where the power semiconductor device 1 includes such a back emitter region 107, it may be configured as an IGBT, for example. In another variation in which the power semiconductor device 1 is configured as, for example, a MOSFET or a diode, such a back emitter region 107 of the second conductivity type may not be present, and a highly doped n-type region may be provided instead.

[0060] In one embodiment (not shown in the figures), the emitter adjustment region 106 may be arranged at a certain vertical distance from the back side emitter region 107, wherein, for example, the maximum distance between the region of the back side emitter region 107 exhibiting the maximum doping level and the region of the emitter adjustment region 106 exhibiting the maximum doping level may be less than 1 μm or even less than 500 nm. For example, a region with at least 20%, such as at least 30% or even at least 40% thermal donor may be arranged between the emitter adjustment region 106 and the back side emitter region 107.

[0061] In one embodiment, the concentration of the dopant of the second conductivity in the back emitter region 107 corresponds to at least 1E17 cm -3 Furthermore, in one embodiment, the concentration of the dopant of the second conductivity in the backside emitter region 107 may be at least three times the concentration of the dopant of the first conductivity in the emitter adjustment region 106 .

[0062] For example, the backside emitter region 107 may be formed by implanting a dopant of the second conductivity type, such as, for example, a boron dopant. In one embodiment, the backside emitter region 107 and the emitter adjustment region 106 are created by subsequent implantation steps without an intermediate thermal annealing step. In other words, for example, a phosphorus implant for creating the emitter adjustment region 106 may be directly followed by a boron implant for creating the backside emitter region 107. Then, a suitable annealing step may be performed, for example, by an ultrashort melting laser process.

[0063] In one embodiment, the backside emitter efficiency of the power semiconductor device 1 may be substantially determined by the emitter adjustment region 106. For example, due to the emitter adjustment region, the backside emitter efficiency at the rated current of the power semiconductor device 1 may be reduced by at least 10% or even at least 30%. In other words, in the presence of the emitter adjustment region 106, the emitter efficiency at the rated current may be 10% or even at least 30% lower than in the case where the emitter adjustment region 106 would not be present.

[0064] Figure 7 A portion of a vertical cross section of a semiconductor body 10 is shown schematically and exemplarily (left figure). Figure 7 (right) schematically shows the dopant concentration N in the semiconductor body 10 D(Expressed in logarithm, log N D ) and the corresponding course of the electric field E. The depicted course of the electric field E may correspond to a blocking state at a rated blocking voltage of the power semiconductor device 1. In the illustrated embodiment, in the blocking state at the rated blocking voltage, the absolute value of the electric field E within the semiconductor body 1 decreases along a direction pointing from the front side 10-1 to the back side 10-2 (i.e., along a direction −Z opposite to the vertical direction Z) and cannot penetrate to reach the emitter adjustment region 106. For example, the respective doses in the field stop region 105 and the emitter adjustment region 106 may be adapted such that the space charge region does not reach into the emitter adjustment region 106 during normal operation, but only in the case of a short circuit, i.e., when a high current flows and a high voltage is simultaneously applied. In an alternative embodiment (not shown), the electric field within the semiconductor body 1 may reach into the emitter adjustment region 106 even during normal blocking operation. In the latter case, the emitter adjustment region 106 may therefore also serve as a field stop.

[0065] According to some embodiments, the emitter adjustment region 106 may exhibit a lateral variation of the dopant concentration of the first conductivity type, for example along the first lateral direction X, such as in Fig. 8A In other words, the emitter adjustment region 106 may be laterally structured in that it includes a plurality of emitter adjustment regions 106-1 having a relatively high dopant concentration and a plurality of intermediate regions 106-2 laterally arranged between the emitter adjustment regions 106-1, wherein the intermediate regions 106-2 have a relatively low dopant concentration. For example, the emitter adjustment region 106-1 may be n ++ The doped semiconductor region, and / or the intermediate region 106 - 2 may be n-doped or n- - For example, such a structured emitter adjustment region 106 can be formed by placing a laterally uniform n-doped semiconductor region. + Doping layer and structured n + The doped layers are combined additively to obtain n + Doping the middle region 106-2 and n ++ Doping the Emitter Tuning Region 106 - 1 In one embodiment, the relatively high dopant concentration inside the emitter tuning region 106 - 1 may exceed the dopant concentration of the backside emitter region 107 .

[0066] In combination with the backside emitter region 107, a corresponding lateral variation of the backside emitter efficiency may thus be provided, wherein (as a whole) at least one first emitter efficiency region 107-1 having a relatively high backside emitter efficiency is laterally arranged adjacent to at least one second region emitter efficiency region 107-2 having a relatively low emitter efficiency. For example, the second emitter efficiency region 107-2 may be positioned closer to a lateral chip edge of the semiconductor body 10 than the first emitter efficiency region 107-1. In other words, the first emitter efficiency region 107-1 may, for example, be located in an active region (including one or more power cells 14) of the semiconductor device 1, while the second emitter efficiency region 107-2 may, for example, be positioned at least partially below an edge termination structure 18, as shown. Fig.8D As schematically shown in Fig.8D In an exemplary embodiment of the present invention, the second emitter efficiency region 107-2 also includes a wide emitter adjustment region 106-11 extending continuously under the edge termination structure 18. For example, the dopant concentration in the wide emitter adjustment region 106-11 can be equal to or even greater than the dopant concentration of the emitter adjustment region 106-1. As a result, for example, the emitter efficiency under the edge termination structure can be significantly reduced in order to ensure high dynamic robustness ("HDR") of the power semiconductor device by reducing the current flow in this region during the turn-off of the device.

[0067] In one embodiment, Figure 8B As exemplarily shown in FIG. 1 , a smaller emitter adjustment region 106-1 may be provided in the first region 107-1 compared to the second region 107-2. That is, the lateral extension L1 of the emitter adjustment region 106-1 in the first region 107-1 may be smaller than the lateral extension of the emitter adjustment region 106-1 in the second region 107-2. Additionally or alternatively, as Figure 8C As exemplarily shown in FIG. 1 , in the first region 107-1, the lateral extension G1 of the middle region 106-2, i.e., the lateral gap G1 between the emitter adjustment regions 106-1, can be smaller than the lateral extension G2 of the middle region 106-2 in the second region 107-2. By this measure, a defined area with higher emitter efficiency can be achieved in the chip, which can lead to soft turn-off of the device and in which it is at a lower overshoot voltage.

[0068] In accordance with Fig. 8AIn some embodiments of each of the first emitter efficiency regions 107-1 to 107-D, the total lateral extension of the one or more first emitter efficiency regions 107-1 exhibiting relatively high emitter efficiency may correspond to at least 50% of the vertical thickness T (i.e., chip thickness T) of the semiconductor body 10. For example, the total lateral extension of the one or more first emitter efficiency regions 107-1 may be in the range of 50% to 90% of the vertical thickness T of the semiconductor body 10. Furthermore, in some embodiments, the ratio between the total area of ​​the one or more first emitter efficiency regions 107-1 and the total active area of ​​the power semiconductor device 1 may be in the range of 8% to 50%.

[0069] Embodiments of the method of processing and / or manufacturing a power semiconductor transistor correspond to the embodiments of the power semiconductor transistor described above with reference to the accompanying drawings. Thus, for example, the features of the embodiments of the power semiconductor device described above with reference to the accompanying drawings can be implemented by performing corresponding processing method steps. Thus, embodiments of the method of processing a power semiconductor device may include providing a semiconductor body 10 and forming corresponding structures arranged in / on the semiconductor body 10 by processes such as masked or non-masked implantation and / or deposition of semiconductor layers and / or oxide layers.

[0070] Features of further embodiments are defined in the dependent claims. Features of further embodiments and features of the above-described embodiments can be combined with one another to form further embodiments, as long as the features are not explicitly described as alternatives to one another.

[0071] In the above, embodiments of semiconductor devices are described. For example, these semiconductor devices are based on silicon (Si). Therefore, a single crystal semiconductor region or layer (such as the semiconductor body 10 of the exemplary embodiment) may be a single crystal Si region or Si layer. In other embodiments, polycrystalline silicon or amorphous silicon may be used.

[0072] However, it should be understood that the semiconductor body 10 and components (e.g., regions 100, 105, 106, and 107) may be made of any semiconductor material suitable for fabricating semiconductor devices. Examples of such materials include, but are not limited to, basic semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name just a few. The above semiconductor materials are also referred to as "homojunction semiconductor materials." When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor device applications, Si, SiC, GaAs, and GaN materials are currently used.

[0073] Spatially relative terms such as "lower", "below", "above", "lower", "upper", "upper", etc. are used to explain the positioning of one element relative to a second element for ease of description. These terms are intended to include different orientations of the corresponding devices other than those shown in the figures. In addition, terms such as "first", "second", etc. are also used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the specification, the same terms refer to the same elements.

[0074] As used herein, the terms "having," "containing," "including," "comprising," "presenting," and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0075] In view of the above range of variations and applications, it should be understood that the present invention is not limited by the foregoing description, nor by the accompanying drawings. Instead, the present invention is limited only by the appended claims and their legal equivalents.

Claims

1. A power semiconductor device (1), comprising a semiconductor body (10) having a front side (10-1) and a back side (10-2), wherein: The semiconductor body (10) comprises: - a drift region (100) of a first conductivity type; a field stop zone (105) of a first conductivity type, the field stop zone (105) being arranged between the drift zone (100) and the back side (10-2) and having a dopant of the first conductivity type at a higher dopant concentration than the drift zone (100), wherein the field stop zone (105) is at least partially created by implantation of protons via the back side (10-2); and an emitter adjustment zone (106) of the first conductivity type, the emitter adjustment zone (106) being arranged between the field stop zone (105) and the back side (10-2) and having a dopant of the first conductivity type at a higher dopant concentration than the field stop zone (105); wherein the field stop zone (105) comprises, in a cross section along a vertical direction (Z) pointing from the back side (10-2) to the front side (10-1), a dopant concentration distribution of a dopant of a first conductivity type exhibiting a first local maximum (1051) and a first local minimum (1052), the first local minimum (1052) being arranged between the first local maximum (1051) and another local maximum (1053, 1055, 1057) of the dopant concentration distribution of the field stop zone (105) and / or between the first local maximum (1051) and a maximum of the dopant concentration distribution of the emitter adjustment zone (106), wherein the dopant concentration at the first local maximum (1051) is at most three times higher than the dopant concentration at the first local minimum (1052), and The semiconductor body (10) is or includes a semiconductor body having a thickness of at least 1E17 cm -3 The interstitial oxygen concentration of the semiconductor substrate.

2. The power semiconductor device (1) according to claim 1, wherein at least 20% of the dopants at the first local minimum (1052) are thermal donors.

3. A power semiconductor device (1), comprising a semiconductor body (10) having a front side (10-1) and a back side (10-2), wherein: The semiconductor body (10) comprises: - a drift region (100) of a first conductivity type; a field stop zone (105) of a first conductivity type, the field stop zone (105) being arranged between the drift zone (100) and the back side (10-2) and having a dopant of the first conductivity type at a higher dopant concentration than the drift zone (100), wherein the field stop zone (105) is at least partially created by implantation of protons via the back side (10-2); and an emitter adjustment zone (106) of the first conductivity type, the emitter adjustment zone (106) being arranged between the field stop zone (105) and the back side (10-2) and having a dopant of the first conductivity type at a higher dopant concentration than the field stop zone (105); The semiconductor body (10) is or includes a semiconductor body having a thickness of at least 1E17 cm -3 A semiconductor substrate having an interstitial oxygen concentration of ; wherein the field stop zone (105) includes a region (R) in which the dopant concentration is at least three times higher than the dopant concentration in the drift region (100); and wherein at least 20% of the dopants of the first conductivity type in the region (R) are oxygen-induced thermal donors.

4. The power semiconductor device (1) according to any one of claims 1 to 3, wherein: The emitter adjustment region (106) mainly includes another kind of dopant other than the dopant created by proton implantation.

5. The power semiconductor device (1) according to any one of claims 1 to 3, wherein: The vertical extension (d1) of the emitter adjustment region is equal to or less than 1 μm.

6. The power semiconductor device (1) according to any one of claims 1 to 3, wherein: The dopant concentration distribution of the field stop zone (105) exhibits a plurality of local maxima (1051, 1053, 1055, 1057).

7. The power semiconductor device (1) according to claim 6, wherein: When moving from one local maximum (1057, 1055, 1053) to another local maximum (1055, 1053, 1051) along the vertical direction (Z), the dopant concentration at the local maximum (1051, 1053, 1055, 1057) decreases.

8. The power semiconductor device (1) according to claim 6, wherein: When moving from one local maximum (1055, 1053) to another local maximum (1053, 1051) along the vertical direction (Z), the ratio of the dopant concentration of the local maximum (1051, 1053, 1055) to the dopant concentration of the local minimum (1052, 1054, 1056) located adjacent to the local maximum (1051, 1053, 1055) and closer to the back side (10-2) than the local maximum (1051, 1053, 1055) decreases.

9. The power semiconductor device (1) according to any one of claims 1 to 3, wherein: The dosage of the dopant of the first conductivity type within the field stop zone (105) corresponds to at most 50% of the material-specific breakdown charge of the semiconductor body (10).

10. The power semiconductor device (1) according to any one of claims 1 to 3, wherein: The dose of the dopant of the first conductivity type within the emitter adjustment region (106) corresponds to at least 50% of the material-specific breakdown charge of the semiconductor body (10).

11. The power semiconductor device (1) according to any one of claims 1 to 3, wherein: The semiconductor body (10) is or includes a semiconductor substrate manufactured by a Czochralski method or a magnetic Czochralski method.

12. The power semiconductor device (1) according to any one of claims 1 to 3, wherein: The power semiconductor device (1) is configured to block a rated blocking voltage in a blocking state of the power semiconductor device (1), wherein, in the blocking state at the rated blocking voltage, the electric field inside the semiconductor body (1) decreases in a direction from the front side (10-1) to the back side (10-2), and wherein, in the blocking state at the rated blocking voltage, the electric field does not penetrate to reach the emitter adjustment region (106).

13. The power semiconductor device (1) according to any one of claims 1 to 3, wherein: The power semiconductor device (1) is configured to block a rated blocking voltage in a blocking state of the power semiconductor device (1), wherein, in the blocking state at the rated blocking voltage, the electric field inside the semiconductor body (1) decreases in a direction from the front side (10-1) to the back side (10-2), wherein, in the blocking state at the rated blocking voltage, the electric field reaches the emitter adjustment region (106).

14. The power semiconductor device (1) according to any one of claims 1 to 3, wherein: The emitter adjustment region (106) exhibits a lateral variation in dopant concentration of the first conductivity type.

15. The power semiconductor device (1) according to any one of claims 1 to 3, wherein: The semiconductor body (10) comprises a backside emitter region (107) of a second conductivity type complementary to the first conductivity type, the backside emitter region (107) being arranged between the emitter adjustment region (106) and the back side (10-2).

16. The power semiconductor device (1) according to claim 15, wherein: The concentration of the dopant of the second conductivity in the back side emitter region (107) is at least three times the concentration of the dopant of the first conductivity type in the emitter adjustment region (106).

17. A method for processing a power semiconductor device (1), comprising: - providing a semiconductor body (10) having a front side (10-1) and a back side (10-2); - creating or providing a drift region (100) of a first conductivity type within the semiconductor body (10); - creating a field stop zone (105) of the first conductivity type inside the semiconductor body (10) by at least one proton implantation via the back side (10-2), the field stop zone (105) being arranged between the drift zone (100) and the back side (10-2) and having a dopant of the first conductivity type at a higher dopant concentration than the drift zone (100); and - creating an emitter adjustment zone (106) of the first conductivity type inside the semiconductor body (10), the emitter adjustment zone (106) being arranged between the field stop zone (105) and the back side (10-2) and having a dopant of the first conductivity type at a higher dopant concentration than the field stop zone (105); wherein the field stop zone (105) comprises, in a cross section along a vertical direction (Z) pointing from the back side (10-2) to the front side (10-1), a dopant concentration distribution of a dopant of a first conductivity type exhibiting a first local maximum (1051) and a first local minimum (1052), the first local minimum (1052) being arranged between the first local maximum (1051) and another local maximum (1053, 1055, 1057) of the dopant concentration distribution of the field stop zone (105) and / or between the first local maximum (1051) and a maximum of the dopant concentration distribution of the emitter adjustment zone (106), wherein the dopant concentration at the first local maximum (1051) is at most three times higher than the dopant concentration at the first local minimum (1052), and The semiconductor body (10) is or includes a semiconductor body having a thickness of at least 1E17 cm -3 The interstitial oxygen concentration of the semiconductor substrate.

18. A method for processing a power semiconductor device (1), comprising: - providing a semiconductor body (10) having a front side (10-1) and a back side (10-2); - creating or providing a drift region (100) of a first conductivity type within the semiconductor body (10); - creating a field stop zone (105) of the first conductivity type inside the semiconductor body (10) by at least one proton implantation via the back side (10-2), the field stop zone (105) being arranged between the drift zone (100) and the back side (10-2) and having a dopant of the first conductivity type at a higher dopant concentration than the drift zone (100); and - creating an emitter adjustment zone (106) of the first conductivity type inside the semiconductor body (10), the emitter adjustment zone (106) being arranged between the field stop zone (105) and the back side (10-2) and having a dopant of the first conductivity type at a higher dopant concentration than the field stop zone (105); The semiconductor body (10) is or includes a semiconductor body having a thickness of at least 1E17 cm -3 A semiconductor substrate having an interstitial oxygen concentration of ; wherein the field stop zone (105) includes a region (R) in which the dopant concentration is at least three times higher than the dopant concentration in the drift region (100); and wherein at least 20% of the dopants of the first conductivity type in the region (R) are oxygen-induced thermal donors.

19. The method according to claim 17 or 18, wherein: Creating the emitter tuning region (106) includes implanting phosphorus and / or selenium dopants through the back side (10-2).

20. The method according to claim 17 or 18, further comprising creating a back side emitter region (107) of a second conductivity type complementary to the first conductivity type inside the semiconductor body (10), the back side emitter region (107) being arranged between the emitter adjustment region (106) and the back side (10-2).

21. The method according to claim 20, wherein: The backside emitter region (107) and the emitter tuning region (106) are created by subsequent implantation steps without an intermediate thermal annealing step.

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