Computing devices and computing systems

Abstract

A computing device and a computing system are provided. The computing device includes a plurality of computing modules and a serial communication path between the plurality of computing modules. Each computing module includes an internal circuit to operate on a signal received from a corresponding serial communication path and an extension circuit to receive a signal from the internal circuit as an input signal. The extension circuit includes a delay module to delay the input signal, the delay including one or more delay cells in series with each other, one or more extension selection modules to selectively level extend the input signal with the signal delayed through a corresponding one or more delay cells to produce one or more corresponding level extended signals, and an output module to output one or more of the one or more level extended signals.

Description

Technical Field

[0001] This disclosure relates to computing devices and computing systems, and in particular, to computing devices and computing systems having multiple chips or cores in series communication. Background Technology

[0002] In some multi-chip (or multi-core) systems, serial communication protocols are used. These protocols employ asynchronous transmission. As the number of chips connected in series increases, the amount of data transmitted also grows, leading to higher demands on the speed of serial communication. This often limits the performance capabilities of multi-chip serial systems.

[0003] Therefore, there is a need to provide computing devices and systems with improved performance. Summary of the Invention

[0004] According to one aspect of this disclosure, a computing device is provided, comprising: a plurality of computing modules; and a serial communication path between the plurality of computing modules; wherein each computing module includes: internal circuitry for operating on a signal received from a corresponding serial communication path; and extension circuitry for receiving a signal from the internal circuitry as an input signal, the extension circuitry including: a delay module for delaying the input signal, the delay module including one or more delay units; one or more extension selection modules for selectively level-expanding the input signal by means of a signal delayed by the corresponding one or more delay units, generating one or more corresponding level-expanded signals; and an output module for outputting one or more of the one or more level-expanded signals.

[0005] In some embodiments, the plurality of computing modules are a plurality of chips or a plurality of cores, and the internal circuitry of the plurality of computing modules performs one or more of the following operations on signals received from their respective corresponding serial communication paths: performing calculations on the received signals; and forwarding the received signals.

[0006] In some embodiments, the plurality of computing modules may be identical to each other. In some embodiments, the plurality of computing modules are capable of performing the same operation on the same received signal. In some embodiments, the internal circuitry of the plurality of computing modules performs calculations on their respective received signals based on the same algorithm. In some embodiments, the internal circuitry of the plurality of computing modules performs calculations on their respective received signals based on the same algorithm for virtual currency.

[0007] In some embodiments, the signal from the internal circuitry includes one of the following: the result of the internal circuitry's calculation of the received signal; or the received signal forwarded by the internal circuitry.

[0008] In some embodiments, each computing module may further include: an input interface circuit connected to a corresponding serial communication path and the internal circuit; and an output interface circuit connected to another corresponding serial communication path and the output module.

[0009] In some embodiments, each of the delay units includes an even number of inverters connected in series; the output module outputs one of the one or more level-expanded signals based on an enable signal.

[0010] In some embodiments, each extended selection module receives the input signal, the signal delayed by the corresponding delay unit, and a selection signal, and extends the input signal to a high or low level based on the selection signal using the signal delayed by the corresponding delay unit to generate a level-extended signal.

[0011] In some embodiments, each extended selection module includes: a first logic gate and a second logic gate, which respectively receive the input signal and a signal delayed by a corresponding delay unit, the first logic gate and the second logic gate performing different logic operations to generate a first level extended signal and a second level extended signal that have been extended at different levels relative to the input signal; and selection logic for selecting an output from the first level extended signal and the second level extended signal.

[0012] In some embodiments, the first logic gate is an AND gate, and the second logic gate is an OR gate.

[0013] In some embodiments, the one or more delay units include two or more delay units, the one or more extended selection modules include two or more extended selection modules, and the output module includes: two or more first logic gates, each first logic gate receiving an enable signal and a level extension signal from the corresponding extended selection module; and selection logic for selectively outputting the operation results of the two or more first logic gates.

[0014] In some embodiments, the one or more delay units include two or more delay units, the one or more extended selection modules include two or more extended selection modules, the extended circuit further includes an input module, the input module includes an inverter connected between the corresponding serial communication path and the internal circuit, and the output module includes: two or more first logic gates, each first logic gate receiving an enable signal and a level-expanded signal from the corresponding extended selection module; selection logic for selectively outputting the operation result of the two or more first logic gates; and an inverter for inverting the output of the selection logic.

[0015] In some embodiments, the received signal includes one or more of instructions, addresses, and data.

[0016] In some embodiments, each computing module further includes a memory storing level expansion information for level expansion of the input signal, wherein the level expansion is performed based on the level expansion information.

[0017] In some embodiments, the computing device further includes a control module configured to monitor the state of the plurality of computing modules and, based on the monitoring results, provide the plurality of computing modules with information about the level extension to be performed by each of the plurality of computing modules.

[0018] In some embodiments, the control module is configured to monitor the state as follows: a) issuing a command to the plurality of computing modules, the command causing the plurality of computing modules to feed back specified information to the control module, the command including at least information indicating the amount of level extension to be performed by the relevant computing module, wherein the relevant computing module operates based on the indicated amount of level extension to feed back the specified information; b) determining, based on the information fed back from the plurality of computing modules, whether each computing module has correctly received the command based on the amount of level extension; and c) if it is determined that a computing module has not correctly received the command, resending the command to at least the computing module that has not correctly received the command, the resent command including at least the increased amount of level extension; and d) repeating b) and c) until it is determined that all the plurality of computing modules have correctly received the command or a predetermined number of cycles has been reached.

[0019] In some embodiments, the plurality of computing modules include a first computing module and one or more second computing modules, wherein the first computing module is configured to monitor the state of the one or more second computing modules and provide information to the one or more second computing modules about the level extension to be performed by each of the one or more second computing modules based on the monitoring results.

[0020] In some embodiments, the first computing module is configured to monitor the state as follows: a) issuing a command to the one or more second computing modules, the command causing the one or more second computing modules to feed back specified information to the first computing module, the command including at least information indicating the amount of level extension to be performed by the relevant second computing module, wherein the relevant second computing module operates based on the indicated amount of level extension to feed back the specified information; b) determining, based on the information fed back from the one or more second computing modules, whether each second computing module has correctly received the command based on the amount of level extension; and c) if it is determined that a second computing module has not correctly received the command, resending the command to at least the second computing module that did not correctly receive the command, the resent command including at least the increased amount of level extension; and d) repeating b) and c) until it is determined that all one or more second computing modules have correctly received the command or a predetermined loop condition is met.

[0021] According to another aspect of this disclosure, a computing system is also provided, which includes a computing device according to any embodiment of the present invention.

[0022] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0024] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0025] Figure 1 A schematic block diagram of a computing device is shown;

[0026] Figure 2 A schematic block diagram of a computing device according to an embodiment of the present disclosure is shown;

[0027] Figure 3 A schematic block diagram of an extension circuit according to an embodiment of the present disclosure is shown;

[0028] Figure 4 A schematic block diagram of a delay unit according to an embodiment of the present disclosure is shown;

[0029] Figure 5 A schematic block diagram of an extended selection module according to an embodiment of the present disclosure is shown;

[0030] Figure 6 A schematic block diagram of an output module according to an embodiment of the present disclosure is shown;

[0031] Figure 7 and 8 Timing diagrams illustrating level spread according to one embodiment of the present disclosure are shown respectively;

[0032] Figure 9 An example configuration of the control module / first computing module and the computing module / second computing module according to an embodiment of the present disclosure is shown; and

[0033] Figure 10 Monitoring operations according to one embodiment of this disclosure are illustrated.

[0034] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0035] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other references may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other references. Detailed Implementation

[0036] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure. Furthermore, techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification.

[0037] It should be understood that the following description of at least one exemplary embodiment is merely illustrative and not intended to limit the scope of this disclosure or its application or use. It should also be understood that any implementation described herein does not necessarily represent a preferred or advantageous implementation over others. This disclosure is not limited to any expressed or implied theory given in the foregoing description of the technical field, background, summary of the invention, or detailed description.

[0038] Additionally, certain terms may be used in the following description for reference only, and are therefore not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence.

[0039] It should also be understood that when the term “including / contains” is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0040] Figure 1 A schematic block diagram of a computing device is shown. Figure 1 As shown, the computing device 100 includes a plurality of computing modules (e.g., chips) 101 that communicate using a serial communication protocol. Figure 1 The diagram shows chips CHIP[0], CHIP[1], ..., CHIP[n], which are connected to each other via serial communication links (e.g., S0 and S1).

[0041] Each chip 101 may include internal circuitry 103 and 107 for downstream (e.g., from the control board to a remote chip) and upstream (e.g., from the remote chip to the control board) communication operations, respectively. Interfaces S0_UP (to the upstream chip) and S0_DN (to the downstream chip), connected to internal circuitry 103, are respectively connected to their corresponding serial communication paths (as shown by the arrows in the figure). Similarly, interfaces S1_UP (to the upstream chip) and S1_DN (to the downstream chip), connected to internal circuitry 107, are respectively connected to their corresponding serial communication paths.

[0042] Figure 1 A control board 111 is also shown, on which control circuitry or logic or a chip 113 is formed. The control board 111 can communicate with the computing module 101 via, for example, a serial communication path (as shown by the arrows in the figure) to provide it with, for example, instructions, addresses, data, etc.

[0043] Because serial communication requires very few signals (one downlink signal and one uplink signal), it is very convenient for multi-chip cascading (signals are passed from one chip to the next) in system-board routing. The serial communication protocol uses an asynchronous transmission mode.

[0044] The inventors of this application have discovered that serial communication has low requirements for signal timeliness but high requirements for duty cycle. The duty cycle has a significant impact on communication success rate, especially in computing devices or systems integrating numerous chips (or cores) for intensive computation. The transmission of communication signals through numerous serially connected chips deteriorates the duty cycle; the more chips involved, the worse the duty cycle becomes. In low-speed modes or when the number of serially connected chips is small, the impact of the duty cycle is relatively small. However, as the number of serially connected chips increases, the amount of data transmitted also increases, and the speed requirements for serial communication become increasingly stringent. The impact of the duty cycle becomes increasingly significant in high-speed modes. The duty cycle of serial communication signals has become a key factor limiting the performance improvement of multi-chip serially connected computing systems.

[0045] Based on the inventor's above understanding, the invention disclosed herein is proposed.

[0046] Figure 2 A schematic block diagram of a computing device according to an embodiment of the present disclosure is shown. Figure 2 As shown, the computing device 200 may include: a plurality of computing modules 201, and serial communication paths between the plurality of computing modules 201 (as shown by the arrows in the figure). The computing module 201 may be, for example, a chip or a core.

[0047] Similarly, as an example of a computing module, Figure 2 The diagram shows chips CHIP[0], CHIP[1], ..., CHIP[n], which are connected to each other via a serial communication link and communicate using a serial communication protocol. Here, although... Figure 2 The diagram shows n chips as computing modules, but it should be understood that more or fewer computing modules can be used.

[0048] Each computing module includes internal circuitry for operating on signals received from the corresponding serial communication path. As shown in the figure, each chip 201 may include internal circuitry 203 and 207 for operations related to downlink (e.g., as shown by the arrows from left to right in the figure) and uplink (e.g., as shown by the arrows from right to left in the figure) communication, respectively.

[0049] In some implementations, the internal circuitry of the computing modules performs calculations on signals received from their respective corresponding serial communication paths, and / or forwards the received signals to the next computing module. Additionally, in some implementations, the multiple computing modules may be identical to each other. Alternatively, the multiple computing modules may perform the same operation on the same received signal. Alternatively, the calculations performed by the internal circuitry of the multiple computing modules on their respective received signals may be based on the same algorithm. Alternatively, the calculations performed by the internal circuitry of the multiple computing modules on their respective received signals may be based on the same algorithm used for virtual currency.

[0050] According to embodiments of this disclosure, each computing module may further include an extension circuit. The extension circuit receives signals from the internal circuits as input signals and performs level expansion on the input signals to change their duty cycle. As shown in the figures, extension circuits 205 and 209 are respectively located downstream of the corresponding internal circuits 203 and 207 (as indicated by the arrows in the computing module) to receive signals from internal circuits 203 and 207 for processing. Extension circuits 205 and 209 can selectively extend the width of the high or low level of the signals they receive, according to actual needs.

[0051] Similarly, Figure 2 The diagram also shows upstream interfaces S0_UP and S1_UP, connected to internal circuits 203 and 207 respectively, which are connected to their corresponding serial communication paths (as indicated by the arrows in the figure). It also shows downstream interfaces S0_DN and S1_DN, connected to the expansion circuit, which are also connected to their corresponding serial communication paths. For link S0, interface S0_UP serves as an input interface, while interface S0_DN serves as an output interface. For link S1, interface S1_DN serves as an input interface, while interface S1_UP serves as an output interface.

[0052] Similarly, Figure 2 A control board 211 is also shown, on which control circuitry or logic or a chip (hereinafter also referred to as a control module) 213 is formed. The control module 213 can communicate with the computing module 201 via, for example, a serial communication path (as shown by the arrows in the figure) to provide it with, for example, instructions, addresses, data, etc. However, it should be understood that this disclosure is not limited thereto.

[0053] Figure 3 A schematic block diagram of an extension circuit according to an embodiment of the present disclosure is shown.

[0054] like Figure 3 As shown, the expansion circuit 300 receives the corresponding internal circuit (see...). Figure 2The output of the internal circuitry is used as input. As previously described, the received signal from the internal circuitry may include one of the following: the result of calculations performed by the internal circuitry on the received signal; or the received signal forwarded by the internal circuitry.

[0055] here, Figure 3 The diagram also shows an optional input module 323 (CHIP_EXD_In) to receive signals as input from the corresponding internal circuitry. In some implementations, input module 323 may include an inverter connected between the corresponding serial communication path and the internal circuitry.

[0056] like Figure 3 As shown, the expansion circuit 300 may include a delay module 301 for delaying the input signal (exd_in, which may or may not pass through the input module 323). As shown, the delay module 301 may include one or more delay units. As an example, the figure shows four delay units 3011, 3013, 3015, and 3017 (CHIP_EXD_Unit 0 to CHIP_EXD_Unit 3) connected in series; however, it should be understood that more or fewer delay units may be used, and the connection relationships of the delay units may also be varied. Each delay unit 3011, 3013, 3015, and 3017 is used to delay the input signal. Figure 3 In the example shown, delay unit 3011 receives the input signal exd_in and outputs a signal exd_in0 delayed by itself. Delay unit 3013 outputs a signal exd_in1 delayed by delay units 3011 and 3013. Delay unit 3015 outputs a signal exd_in2 delayed by delay units 3011, 3013, and 3015. Delay unit 3017 outputs a signal exd_in3 delayed by delay units 3011, 3013, 3015, and 3017. (See later for further details.) Figure 4 The delay unit will be described in more detail.

[0057] The expansion circuit 300 may further include one or more expansion selection modules for selectively expanding the level of the input signal using signals delayed by one or more corresponding delay units, thereby generating one or more corresponding level-expanded signals. Figure 3 Four extended selection modules 311, 313, 315, and 317 (CHIP_EXD_Lvl 0 to CHIP_EXD_Lvl 3) are shown. These extended selection modules can be implemented using standard cells such as AN2 / OR2 / MUX2, as will be discussed below. Figure 5 Further explanation.

[0058] As shown in the figure, the extended selection module 311 receives the input signal exd_in, the output exd_in0 of the delay unit 3011, and the selection signal (chip_exd_sel from module 325 (CHIP_EXD_Sel)). The extended selection module 311 selectively extends the input signal using the signal exd_in0 delayed by the delay unit 3011, generating a level-extended signal. Here, as mentioned earlier, the input signal exd_in may or may not pass through the input module 323.

[0059] The extended selection module 313 receives the input signal exd_in, the output exd_in1 of the delay unit 3013, and the selection signal (chip_exd_sel). The extended selection module 313 selectively extends the input signal using the signal exd_in1 delayed by the delay unit 3013 to generate a level-extended signal.

[0060] The extended selection module 315 receives the input signal exd_in, the output exd_in2 of the delay unit 3015, and the selection signal (chip_exd_sel). The extended selection module 313 selectively extends the input signal using the signal exd_in2 delayed by the delay unit 3015 to generate a level-extended signal.

[0061] Similarly, the extended selection module 317 receives the input signal, the output exd_in3 of the delay unit 3017, and the selection signal (chip_exd_sel). The extended selection module 317 selectively extends the input signal using the signal exd_in3 delayed by the delay unit 3013 to generate a level-extended signal.

[0062] In some embodiments, when the selection signal (chip_exd_sel) is logic 0, an extended low level is selected, and when the selection signal (chip_exd_sel) is logic 1, an extended high level is selected. This disclosure is not limited thereto; for example, in alternative embodiments, inverse logic may also be used.

[0063] Therefore, in this example, each extended selection module receives the input signal, the signal delayed by the corresponding delay unit, and the selection signal, and extends the input signal to a high or low level based on the selection signal using the signal delayed by the corresponding delay unit to generate a level-extended signal.

[0064] Module 325 (CHIP_EXD_Sel) can be configured to generate the selection signal chip_exd_sel. However, this disclosure is not limited thereto. For example, in some embodiments, module 325 can receive the selection signal chip_exd_sel from outside the expansion module 300. Additionally, in... Figure 3 In the example shown, each extended selection module is depicted as receiving the selection signal chip_exd_sel; however, it should be understood that this is merely exemplary, and the configuration of the selection signal can vary. For example, in other embodiments, the selection signal used for different extended selection modules can be configured to be different.

[0065] The extension circuit 300 may further include an output module for outputting one or more of the one or more level-extended signals. For example... Figure 3 As shown, output module 321 (CHIP_EXD_Out) receives the outputs of each extended selection module 311 to 317 and receives the enable signal chip_exd_en[3:0], thereby selecting one of the level-expanded signals output by each extended selection module based on the enable signal. It should be understood that this is merely exemplary; for example, in other implementations, the enable signal chip_exd_en may also be provided to each extended selection module to achieve selective output.

[0066] Figure 3 Module 327 (CHIP_EXD_En) is also shown. In some embodiments, module 327 (CHIP_EXD_En) can be configured to generate an enable signal chip_exd_en. However, this disclosure is not limited thereto. For example, in some embodiments, module 327 can receive the enable signal chip_exd_en from outside the extension module 300.

[0067] Figure 4 A schematic block diagram of a delay unit according to an embodiment of the present disclosure is shown. Figure 4 As shown, the delay unit 400 may include an even number of inverters connected in series. The delay unit 400 can represent Figure 3 Any of the delay units shown. Figure 4 In the diagram, delay unit 400 is shown as comprising four inverters (INVs) 401 to 407 connected in series; however, it should be understood that more or fewer inverters may be included, such as 2, 6, 8, etc. Delay units can be implemented using buffers / inverters (BUFs / INVs) as standard units. It should also be understood that the number of inverters in each delay unit may be the same or different.

[0068] Figure 5 A schematic block diagram of an extended selection module according to one embodiment of the present disclosure is shown. Figure 5 As shown, the extended selection module 500 may include a first logic gate 501 and a second logic gate 503. The first logic gate 501 and the second logic gate 503 respectively receive an input signal exd_in and a signal exd_inx (e.g., one of exd_in0 to exd_in3) delayed by a corresponding delay unit. The first logic gate 501 and the second logic gate 503 are configured to perform different logic operations to generate a first level-extended signal and a second level-extended signal that have undergone different level extensions relative to the input signal. In some implementations, the first logic gate 501 is an AND gate, and the second logic gate is an OR gate; or vice versa.

[0069] The extended selection module 500 may include selection logic 507 for selecting one output from the first level extended signal and the second level extended signal. As shown, the selection logic is implemented as a multiplexer 507 (MUX2), which receives a selection signal exd_sel and selects one of the first level extended signal and the second level extended signal for output (exd_lvl) based on the selection signal exd_sel. Here, the selection signal exd_sel corresponds to Figure 3 The selection signal chip_exd_sel is shown below. (See below for reference.) Figure 7 and 8 In more detail, the width of the high or low level of the signal can be adjusted by operating the first and second logic gates. The amount of adjustment can be adjusted by selecting a delay unit.

[0070] Incidentally, in this document, "logic" can be implemented in hardware, software, or a combination of hardware and software. Therefore, in some embodiments, "logic" may also be referred to as a logic component, which can be implemented in hardware or a combination of hardware and software (e.g., firmware).

[0071] Figure 6 A schematic block diagram of an output module according to an embodiment of the present disclosure is shown. Figure 6 As shown, the output module 600 may include two or more first logic gates 601-607. Each first logic gate receives one of the level-expanded signals exd_lvl[0-3] from the corresponding extended selection module and one of the corresponding enable signals exd_en[0-3]. The enable signal exd_en may correspond to... Figure 3 The enable signal chip_exd_en is shown. In some embodiments, the first logic gate is an AND gate; however, it should be understood that this disclosure is not limited thereto. Figure 6As shown, logic gate 601 receives the level-extended signal exd_lvl0 and the corresponding enable signal exd_en0 from the corresponding extended selection module. Logic gate 603 receives the level-extended signal exd_lvl1 and the corresponding enable signal exd_en1 from the corresponding extended selection module. Logic gate 605 receives the level-extended signal exd_lvl2 and the corresponding enable signal exd_en2 from the corresponding extended selection module. Logic gate 607 receives the level-extended signal exd_lvl3 and the corresponding enable signal exd_en3 from the corresponding extended selection module.

[0072] The output module 600 may further include selection logic 610 for selectively outputting the operation results of the first logic gates 601-607. In some embodiments, the selection logic 610 may be implemented as a multiplexer. Figure 6 In a more specific implementation shown, selection logic 610 is implemented as including three OR gates. OR gate 611 receives the outputs of first logic gates 601 and 603 as input to perform an OR operation. OR gate 613 receives the outputs of first logic gates 605 and 607 as input to perform an OR operation. OR gate 615 receives the outputs of OR gates 611 and 613 as input to perform an OR operation.

[0073] exist Figure 6 In the illustrated embodiment, exd_en0 to exd_en3 can be used to control the width of the required level extension. For example, in some implementations (e.g., as...) Figure 3 As shown, exd_en0 being valid indicates that the level needs to be extended by the delay width of one CHIP_EXD_Unit. exd_en1 being valid indicates that the level needs to be extended by the delay width of two CHIP_EXD_Units. exd_en2 being valid indicates that the level needs to be extended by the delay width of three CHIP_EXD_Units. exd_en3 being valid indicates that the level needs to be extended by the delay width of four CHIP_EXD_Units. And so on, more CHIP_EXD_Units and extended selection modules CHIP_EXD_Lvl can be added as needed to achieve the goal of extending a wider level.

[0074] In some embodiments, the output module 600 may further include an optional inverter 620 for inverting the output of the selection logic.

[0075] Figure 7 and 8 Exemplary timing diagrams illustrating level extension according to one embodiment of the present disclosure are shown.

[0076] Figure 7 The image shows an example of the effect of extending the high level. Figure 7 In the diagram, signal waveform S0 schematically illustrates the original state of the communication signal at the initiating end. As shown in the figure, signal waveform S0 represents the original state of the communication signal at the initiating end, where the width of the low level L0 and the width of the high level H0 are approximately the same. The duty cycle at this point is approximately 50%, which is essentially perfect. If the received communication signal also maintains this original state, the communication success rate is high.

[0077] Signal waveform S1 schematically illustrates the state where the communication signal is transmitted to the Nth-level chip without being processed by the expansion module. As shown in the figure, signal waveform S1 represents the state where the communication signal is transmitted to the Nth-level chip without being processed by the expansion module. The width of the low-level L1 is significantly larger than the width of the high-level H1, with the low-level L1 accounting for a larger proportion (e.g., approximately 62.5%), while the high-level H1 accounts for a smaller proportion (e.g., approximately 37.5%). In this case, the success rate of communication at the receiving end is relatively low.

[0078] Signal waveform S2 schematically illustrates the state of the communication signal after passing through several delay units (EXD_Unit) in the Nth-level chip's internal expansion module. As shown in the figure, signal waveform S2 represents the state of the communication signal after passing through several EXD_Unit units in the Nth-level chip's internal expansion module. The width of the low-level L2 is significantly larger than the width of the high-level H2, with low-level L2 accounting for 62.5% and high-level H2 accounting for 37.5%. The widths of the high and low levels remain the same as in signal waveform S1, but after passing through several EXD_Unit units, there is a significant delay compared to signal waveform S1.

[0079] Signal waveform S3 represents the state of the communication signal after processing by the expansion module within the Nth-level chip. As shown in the figure, signal waveform S3 represents the state of the communication signal after processing by the expansion module within the Nth-level chip. After processing by the expansion module, the widths of the low-level L3 and high-level H3 are very close. Through proper configuration, the duty cycle of signal waveform S3 can be made to be equal to or close to the original state of the communication signal at the initiating end. This greatly improves the communication success rate at the receiving end (e.g., the next-level chip).

[0080] Figure 8 The image shows an example of the effect of extending the low level. For example... Figure 8 As shown, signal waveform S0 represents the original state of the communication signal at the initiating end, where the width of the low level L0 and the width of the high level H0 are approximately the same, and the duty cycle at this time is approximately 50%, which is essentially perfect. If the received communication signal also maintains this original state, the communication success rate will be high.

[0081] Signal waveform S1 represents the state of the communication signal transmitted to the Nth-level chip before being processed by the expansion module. The width of the low-level L1 is significantly smaller than the width of the high-level H1, with low-level L1 accounting for a smaller percentage (e.g., 37.5%) and high-level H1 accounting for a larger percentage (e.g., 62.5%). In this case, the success rate of communication at the receiving end is very low.

[0082] Signal waveform S2 represents the state of the communication signal transmitted to the Nth level chip expansion module after passing through several EXD_Unit units. The widths of the high and low levels H2 and L2 are still the same as the widths of the high and low levels of signal waveform S1, but after passing through several EXD_Unit units, there is a significant delay compared to signal waveform S1.

[0083] Signal waveform S3 represents the state of the communication signal after processing by the expansion module within the Nth-level chip. After the expansion module processes the low-level width, the low-level L3 width and the high-level H3 width are very close. Through proper configuration, the duty cycle of signal waveform S3 can be made to resemble or closely approximate the original state of the communication signal at the initiating end. This significantly improves the communication success rate at the receiving end (e.g., the next-level chip).

[0084] In some embodiments, each computing module further includes a memory. The memory may store level expansion information for level expansion of the input signal. For example, the level expansion information may include, for instance, information indicating whether a high-level expansion or a low-level expansion is performed for the computing module, and information indicating the amount of level expansion. The information indicating the amount of level expansion may include, for example, but not limited to, time or a number of units of inverter delay time, etc. The computing module may perform the level expansion based on the level expansion information. In this embodiment, the level expansion information may be predetermined.

[0085] In alternative embodiments, the level extension information can be adaptively adjusted. In some implementations, the status of one or more computing modules can be monitored by a separate control module, or a seat control module within the computing modules, and information regarding the level extension to be performed by each of the one or more computing modules can be provided to the latter based on the monitoring results.

[0086] Figure 9 An example configuration of a control module / first computing module and a computing module / second computing module according to an embodiment of the present disclosure is shown.

[0087] According to this embodiment, such as Figure 9As shown, the computing device may include a control module and one or more computing modules. The control module is configured to monitor the status of the plurality of computing modules and, based on the monitoring results, provide the plurality of computing modules with information regarding the level extensions that each of the plurality of computing modules should perform.

[0088] The control module is configured to monitor the status as follows:

[0089] a) Issue a command to the plurality of computing modules, the command causing the plurality of computing modules to feed back specified information to the control module, the command including at least information indicating the amount of level extension to be performed by the relevant computing module, wherein the relevant computing module operates based on the indicated amount of level extension to feed back the specified information;

[0090] b) Based on the information fed back from the plurality of computing modules, determine whether each computing module has correctly received the command based on the level extension; and

[0091] c) If it is determined that a computing module has not correctly received a command, the command shall be resent to the computing module that did not correctly receive the command, and the resent command shall contain at least the amount of increased level extension; and

[0092] d) Repeat b) and c) until it is determined that all of the plurality of computing modules have correctly received the command or reached the predetermined loop condition.

[0093] In an alternative embodiment, the computing device may include a selected first computing module (which serves as a control module) and one or more other computing modules (second computing modules). The first computing module is configured to monitor the status of the one or more second computing modules and, based on the monitoring results, provide the one or more second computing modules with information regarding the level extensions that each of the one or more second computing modules should perform.

[0094] The first computing module can be configured to monitor the state as follows:

[0095] a) Issue a command to the one or more second computing modules. The command causes the one or more second computing modules to feed back specified information to the first computing module. The command includes at least information indicating the amount of level expansion to be performed by the relevant second computing module. The relevant second computing module operates based on the indicated amount of level expansion to feed back the specified information;

[0096] b) Based on information fed back from the one or more second computing modules, determine whether each second computing module correctly received the command based on the level extension; and

[0097] c) If it is determined that a second computing module has not correctly received a command, the command is resent to the second computing module that did not correctly receive the command, and the resent command contains at least the amount of increased level extension; and

[0098] d) Repeat b) and c) until it is determined that one or more of the second computing modules have correctly received the command or reached the predetermined loop condition.

[0099] Figure 10 A monitoring operation according to an embodiment of the present disclosure is illustrated. According to this embodiment, monitoring can be performed via… Figure 10 The detection operation 1000 shown automatically retrieves the optimal extended configuration for each chip using, for example (but not limited to), system software in the control board. Figure 10 As shown, in step S1001, an identifier, CHIP_ID or other similar identifier, can be set in each chip. In step S1003, the system software issues a read CHIP_ID command to each serially connected chip using the current extended configuration. If each serially connected chip can normally receive the read CHIP_ID command, it returns the value of CHIP_ID in step S1005; otherwise, it does not return it. In step S1007, the system software counts the value or number of CHIP_IDs received from each serially connected chip to determine whether the serially connected chips can communicate normally.

[0100] If any chip fails to return a CHIP_ID or returns an incorrect CHIP_ID value, the system software will automatically adjust the configuration of the expansion modules within each chip based on statistical data. This could involve changing the expansion level or increasing / decreasing the number of CHIP_EXD_Units used. The system will then return to step S1003 to perform a new search. This cycle repeats until all connected chips return the correct CHIP_ID or the predetermined loop condition is met.

[0101] Therefore, it should also be understood that this disclosure also conceives of a computing system that includes the computing device described in any embodiment.

[0102] Those skilled in the art will recognize that the boundaries between operations (or steps) described in the above embodiments are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0103] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A computing device, comprising: Comprise: a plurality of computing modules; and a serial communication path between the plurality of computing modules; wherein each computing module comprises: an internal circuit for operating on a signal received from a corresponding serial communication path; and an extension circuit receiving a signal from the internal circuit as an input signal, the extension circuit comprising: a delay module for delaying the input signal, the delay module comprising one or more delay units; one or more extension selection modules for selectively level-extending the input signal by the signal delayed by a corresponding one or more delay units, generating one or more corresponding level-extended signals; an output module for outputting one or more of the one or more level-extended signals.

2. The computing device of claim 1, wherein, wherein the plurality of computing modules are a plurality of chips or a plurality of cores, the operations on the signal received by the internal circuit of each of the plurality of computing modules comprise one or more of: computing on the received signal; and forwarding the received signal.

3. The computing device of claim 2, wherein at least one of: the plurality of computing modules are identical to each other; the plurality of computing modules are capable of performing identical operations on identical received signals; the computing on the respective received signal by the internal circuit of the plurality of computing modules is based on identical algorithms; and / or the computing on the respective received signal by the internal circuit of the plurality of computing modules is based on identical algorithms for virtual currency.

4. The computing device of claim 1, wherein, wherein the signal from the internal circuit comprises one of: a result of the computation on the signal received by the internal circuit; or the signal received by the internal circuit forwarded.

5. The computing device of claim 1, wherein, wherein each computing module further comprises: an input interface circuit connected to the corresponding serial communication path and the internal circuit; and an output interface circuit connected to another corresponding serial communication path and the output module.

6. The computing device of claim 1, wherein, wherein each of the delay units comprises an even number of inverters in series; the output module outputs one of the one or more level-extended signals based on an enable signal.

7. The computing device of claim 1, wherein, wherein each extension selection module receives the input signal, the signal delayed by the corresponding delay unit, a selection signal, and based on the selection signal, level-extends the input signal with the signal delayed by the corresponding delay unit to generate a level-extended signal.

8. The computing device of claim 1, wherein, wherein each extension selection module comprises: a first logic gate and a second logic gate receiving the input signal and the signal delayed by the corresponding delay unit respectively, the first logic gate and the second logic gate performing different logical operations to generate a first level-extended signal and a second level-extended signal that are different level-extended relative to the input signal; and a selection logic for selecting one of the first level-extended signal and the second level-extended signal to output.

9. The computing device of claim 8, wherein, wherein the first logic gate is an AND gate and the second logic gate is an OR gate.

10. The computing device of claim 1, wherein, wherein the one or more delay units comprise two or more delay units, the one or more extension selection modules comprise two or more extension selection modules, The output module comprises: two or more first logic gates, each of which receives an enable signal and a level-extended signal from a corresponding extension selection module; and selection logic for alternatively outputting operation results of the two or more first logic gates.

11. The computing device of claim 1, wherein, In which, the one or more delay units comprise two or more delay units, the one or more extension selection modules comprise two or more extension selection modules, the extension circuit further comprises an input module, the input module comprising an inverter connected between the corresponding serial communication path and the internal circuit, The output module comprises: two or more first logic gates, each of which receives an enable signal and a level-extended signal from a corresponding extension selection module; selection logic for alternatively outputting operation results of the two or more first logic gates; and an inverter for inverting the output of the selection logic.

12. The computing device of any of claims 1-3, wherein, In which, the received signal comprises one or more of an instruction, an address, and data.

13. The computing device of claim 1, wherein, In which, each calculation module further comprises a memory in which level extension information for level extension of the input signal is stored, wherein the level extension is performed based on the level extension information.

14. The computing device of claim 1, wherein, Further comprising a control module, the control module is configured to monitor the state of the plurality of calculation modules, and based on the monitoring result, provide information to the plurality of calculation modules about the level extension to be performed by each of the plurality of calculation modules.

15. The computing device of claim 14, wherein, In which, the control module is configured to monitor the state as follows: a) issue a command to the plurality of calculation modules, the command causing the plurality of calculation modules to feed back designated information to the control module, the command containing at least information indicating the amount of level extension to be performed by the relevant calculation module, wherein the relevant calculation module operates based on the indicated amount of level extension to feed back designated information; b) according to the information fed back from the plurality of calculation modules, determine whether each calculation module correctly receives the command based on the amount of level extension; and c) in the case where it is determined that there is a calculation module that does not correctly receive the command, reissue the command to at least the calculation module that does not correctly receive the command, the reissued command containing at least an increased amount of level extension; and d) repeat b) and c) until it is determined that the plurality of calculation modules all correctly receive the command or a predetermined number of cycles is reached.

16. The computing device of claim 1, wherein, In which, the plurality of calculation modules comprise a first calculation module and one or more second calculation modules, the first calculation module is configured to monitor the state of the one or more second calculation modules, and based on the monitoring result, provide information to the one or more second calculation modules about the level extension to be performed by each of the one or more second calculation modules.

17. The computing device of claim 16, wherein, In which, the first calculation module is configured to monitor the state as follows: a) issuing a command to the one or more second computing modules, the command causing the one or more second computing modules to feedback specified information to the first computing module, the command containing at least information indicative of an amount of level expansion to be performed by the relevant second computing module, wherein the relevant second computing module operates based on the indicated amount of level expansion to feedback the specified information; b) determining, based on the information fed back from the one or more second computing modules, whether each second computing module correctly received the command based on the amount of level expansion; and c) in the event that it is determined that there is a second computing module that did not correctly receive the command, reissuing the command to at least the second computing module that did not correctly receive the command, the reissued command containing at least an increased amount of level expansion; and d) repeating b) and c) until it is determined that the one or more second computing modules all correctly received the command or a predetermined loop condition is reached.

18. A computing system, comprising: The computing device of any one of claims 1-17. The computing device of any one of claims 1-17.

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