Master / Slave Frequency Lock Loop

Abstract

A master / slave configuration of a frequency locked loop (FLL) decouples locking the loop's process, target voltage, temperature (PVT) tracking target from adapting a clock frequency in response to a voltage drop in a power supply. A master oscillator circuit receives a regulated power supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control the frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to the regulated power supply voltage and the dropout power supply voltage and supplies a slave oscillator signal having a frequency in response to a slave frequency control signal, the slave frequency control signal being based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to voltage changes in the dropout power supply voltage.

Description

Background Art

[0001] Integrated circuits utilize clock signals to synchronize the flow of data through the integrated circuit. The data flow may be subject to strict timing requirements, and the timing of the clock signal may vary with changes in the power supply voltage. Noise affects the power supply in the integrated circuit and may cause the voltage to vary above (overshoot) or below (droop) the nominal voltage level. Noise may adversely affect the timing margin associated with the clock signal. Noise may be caused by deterministic noise sources and random noise sources. Today's high-speed integrated circuits (such as graphics processor units (GPUs) or central processing units (CPUs)) compensate for noise on the power supply line by reducing the clock frequency in response to voltage droop to allow more time for the data signal to reach the destination from the source. If there is no such adaptive clock method that provides additional timing margin, failure may occur due to voltage droop.

[0002] Conventional adaptive clocking methods utilize a delay locked loop (DLL) or a frequency locked loop (FLL) to lock the frequency of the clock signal supplied to the integrated circuit components when generating the system clock. This causes the circuits in the adaptive clocking system (using a DLL or FLL) to lock the average noise voltage and the average clock frequency, resulting in uncertainty due to dependence on power transfer response and application characteristics. In particular, the adaptive clocking system may lock low-frequency noise that may occur due to temperature changes or low-frequency voltage changes. Summary of the invention

[0003] Therefore, embodiments herein utilize a master / slave configuration of a frequency locked loop (FLL) to decouple the locked loop's process, target voltage, temperature (PVT) tracking objectives from adapting the clock frequency in response to voltage droop or overshoot of the supply voltage.

[0004] Therefore, in one embodiment, a device includes a first oscillator circuit, which is coupled to a first power supply voltage and is configured to supply a first oscillator signal. The first power supply voltage is a regulated power supply voltage. A control circuit is coupled to receive the first oscillator signal and receive an indication of a target frequency, and is configured to supply a first frequency control signal to control the frequency of the first oscillator signal to the target frequency. A second oscillator circuit is coupled to receive a second power supply voltage and is configured to supply a second oscillator signal, the second oscillator signal having a frequency responsive to a second frequency control signal. The second frequency control signal is based at least in part on the first frequency control signal. The frequency of the second frequency control signal is further responsive to a voltage change of the second power supply voltage.

[0005] In another embodiment, a method for compensating a clock signal in an integrated circuit includes: supplying a first oscillator signal from a first oscillator circuit that receives a first power supply voltage. The method also includes: generating a first frequency control signal based on a target frequency and a frequency of the first oscillator signal to control the frequency of the first oscillator signal. The method also includes: supplying a second frequency control signal to a second oscillator circuit that receives a second power supply voltage and receives a third power supply voltage. The second frequency control signal is based at least in part on the first control signal. The second oscillator circuit supplies a second oscillator signal, wherein the frequency of the second oscillator signal is based on the second frequency control signal. The second oscillator circuit also adjusts the frequency of the second oscillator signal in response to a voltage change associated with the second power supply voltage.

[0006] In another embodiment, a device includes a master oscillator circuit coupled to a regulated power supply voltage. The master oscillator circuit is configured to supply a master oscillator signal. A control circuit is coupled to the master oscillator signal and is configured to supply a master frequency control signal to control the frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated power supply voltage, which may be the same as the regulated power supply voltage supplied to the master oscillator circuit or may be separately regulated. The slave oscillator circuit further receives a noise or attenuation power supply voltage and is configured to supply a slave oscillator signal having a frequency responsive to a slave frequency control signal, the slave frequency control signal being based on the master frequency control signal and an offset from the master frequency control frequency. The noise or attenuation power supply voltage has a frequency voltage attenuation or overshoot higher than the regulated power supply voltage. The frequency of the second oscillator signal is further responsive to a voltage change of the noise or attenuation power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0008] Figure 1 An exemplary system including a master oscillator and a slave oscillator is shown.

[0009] Figure 2 A high level block diagram showing an implementation of a slave oscillator.

[0010] Figure 3 A timing diagram illustrating the operation of the C element of the slave oscillator is shown.

[0011] Figure 4 A high-level block diagram showing additional details of an implementation of a slave oscillator is shown.

[0012] Figure 5 A high level block diagram showing an implementation in which a master oscillator controls multiple slave oscillators.

[0013] Figure 6 An embodiment of a control structure for generating an offset from an oscillator is shown.

[0014] Figure 7 It shows how the effective frequency can be tracked and adjusted by a control loop to bring it closer to the target frequency.

[0015] The use of the same reference symbols in different drawings indicates similar or identical items. DETAILED DESCRIPTION

[0016] refer to Figure 1 , an exemplary system includes a master oscillator 101 and a slave oscillator 103. In the illustrated embodiment, both the master oscillator and the slave oscillator are digitally controlled oscillators (DCOs). A frequency locked loop (FLL) including the master oscillator 101 and loop control logic 104 tracks frequency changes associated with the master oscillator 101 caused by voltage and temperature changes. The loop control logic 104 supplies a frequency control word (FCWM) 105 to the master oscillator. The master oscillator 101 receives a regulation voltage 112 from a regulator 107. This ensures that the voltage received by the master DCO 101 is much "cleaner" than the noisy or attenuated VDD voltage 111 received by the slave oscillator 103. The noisy / attenuated voltage can be, for example, a voltage utilized by a processor core. The slave oscillator 103 utilizes the master oscillator control signal to control the frequency and also adapts the slave oscillator output 109 to changes in the attenuated voltage 111, as further explained herein.

[0017] The slave oscillator 103 receives a slave frequency control word (FCWS) 115 based on the master frequency control word FCWM from the summing circuit 114. This allows an offset to be added to the FCWM to produce the slave frequency control word FCWS 115. The offset may have a value of zero, in which case the slave oscillator receives an unchanged FCWM. In an embodiment, the master and slave oscillators are located in close physical proximity so that PVT changes that affect the master oscillator also affect the slave oscillator. Although the master and slave oscillators may be such Figure 1 The embodiment shown is a digitally controlled oscillator, but in other embodiments, the oscillator can be a voltage or current controlled oscillator. The control signals FCWM and FCWS can be multi-bit digital signals to control the frequency of the DCO. In other embodiments, FCWM and FCWS are voltage or current signals for analog control of the oscillator. In an analog embodiment, the adder circuit 114 is implemented to add or subtract voltage or current.

[0018] The loop control logic 104 receives a reference clock 121 having a known frequency. In the illustrated embodiment, the reference clock may be down-converted in a frequency divider 123. A counter 125 counts a predetermined number of reference clock cycles to provide a sampling window for a master oscillator clock signal 127. A counter 129 counts the master oscillator clock signal (or down-converted version) during the sampling window. In the illustrated embodiment, a frequency divider 131 divides the master oscillator clock signal 127. A proportional and integral (PI) controller 133 receives a count of the number of down-converted master oscillator clock signal cycles within the sampling window and compares the sample count value with a target count value 135. The target count value represents the target frequency of the master oscillator clock signal 127. Although the illustrated embodiment utilizes a PI controller 133, other control methods may be utilized in other embodiments. The control logic 104 may be implemented in a microcontroller or other control logic. The control loop tracks low frequency variations due to voltage and temperature variations and also compensates for process variations associated with a specific chip, which allows the slave oscillator 103 to be isolated from low frequency PVT variations and respond to higher frequency voltage droops or overshoots that occur in the noise voltage of the voltage domain supplied to the integrated circuit.

[0019] Although Figure 1 Separate regulator blocks 107 and 108 are shown, but embodiments may utilize a single regulator to supply regulated voltages to both master oscillator 101 and slave oscillator 103, in which case regulated voltages 112 and 113 are the same voltage. Selector circuit 141 receives master oscillator output signal 127 and slave oscillator output signal 109. For testing purposes, the selector circuit may select the master oscillator signal to be output from selector circuit 141. If the adaptive clock generator that is supplying the voltage is turned off, but other logic still requires a clock, the clock signal from the master oscillator may be operatively selected.

[0020] Figure 2 A high-level block diagram of an exemplary slave oscillator 103 is shown, which functions as an adaptive oscillator to slow down the system clock in response to voltage droop and limit the frequency response to voltage overshoot. The adaptive slave oscillator 103 includes a reference delay line 201 operating with a regulated voltage VDD 113 and a droop delay line 203 operating with a noise / droop voltage 111. The voltage supplied to the delay line 201 is "clean", and the clock signal A should be more stable than the clock signal B. The delay line 203 outputs a clock signal B that varies in frequency with the droop voltage. When the droop voltage 111 decays, the delay line slows down, and when the droop voltage increases, the delay line speeds up. It should be noted that the inverter 207 forms a fifth inverter to ensure that each of the delay lines 201 and 203 functions as an oscillator.

[0021] like Figure 3 As shown, when both inputs A and B are high at 301, the C element logic 205 outputs an output signal C having a logic high. The C element logic 205 maintains the output signal C high until both inputs A and B are low at 303. Once the output C is a logic low, the C element maintains the output C low until both inputs become high again at 305. Figure 3 As shown, when clock signal A leads clock signal B, clock signal C is the same as clock signal B. When clock signal B leads clock signal A, clock signal C is the same as clock signal A. Therefore, when both inputs A and B are high at 307, C-element logic 205 outputs a logic high output signal C, and keeps output C high until both inputs go low at 309. Once output C is logic low, the C-element maintains output C low until both inputs go high again at 311. In other words, logic 205 selects to output the latest pulse.

[0022] Figure 4 A more detailed view of an implementation of the adaptive slave oscillator 103 is shown. The implementation includes a reference delay line 401 that receives a regulated voltage 402 and a decaying delay line 403 that receives an decaying voltage 404. Each of the delay lines has a number of rows of delay elements that can be turned on or off. The more rows that are turned on, the faster the delay elements operate. In one implementation, the delay lines 401 and 403 have 256 rows. Other implementations may have other numbers of rows. The implementations may use Figure 4 The three-state inverters, buffers or other forms of delay elements are shown. In addition, although a single-ended implementation is shown, other implementations may utilize differential delay lines.

[0023] A frequency control word (FCW) 405 selects how many rows in each of the delay lines are enabled, and therefore selects the output frequency of each of the delay lines. In the illustrated embodiment, a bias setting 407 controls a variable capacitor in each of the delay lines. In addition, an offset value 409 may be used to adjust the FCW 405 supplied to the reference delay line 401, if desired. The decay delay line 403 receives an offset value 411, which may be used to adjust the FCW 405 supplied to the decay delay line 403. For ease of illustration, the offset logic of the reference delay line and decay delay line is not shown. Figure 4 The illustrated implementation effectively addresses high frequency noise such as voltage drop, but does not work well for low frequency noise. Figure 4 The circuit can lock low frequency noise and cannot compensate for the noise. Using the master oscillator control loop (see Figure 1 ), more effectively compensate for low-frequency noise in the system.

[0024] In one embodiment, the master oscillator 101 ( Figure 1 ) include such as Figure 4 However, instead of one of the delay lines receiving a regulated voltage supply and one of the delay lines receiving an attenuated voltage supply, each of the delay lines receives a regulated voltage supply. Thus, in this embodiment, the C-element outputs reflect the two delay lines of the master oscillator.

[0025] Re-reference Figure 1 , adder circuit 114 forms slave control word FCWS 115 based on the master frequency control word FCWM and the offset value 136 generated in offset calculation logic 137. The offset calculation logic receives inputs 139 and 140, which cause the offset calculation logic to increase or decrease the offset value 136 supplied to the adder circuit 114, thereby increasing or decreasing FCWM 105 before supplying it to the slave oscillator 103. The offset value 136 may be zero, in which case the slave oscillator uses the master frequency control word 105 unchanged. In certain situations (e.g., current drift is detected, such as current overshoot or undershoot), the offset calculation logic 137 receives the force signal 139 to adjust the frequency supplied by the slave oscillator by adding an offset or subtracting an offset from the master frequency control word depending on the direction of the current drift. Other situations may result in a non-zero offset. For example, two independent clock domains may be operating in an integrated circuit, and the domain supplied by the slave DCO 103 may need to be slowed down in order to avoid a FIFO overflow in the other clock domain. In addition, the offset can be used to affect various power management results to speed up or slow down the clock frequency supplied by the slave oscillator. In the illustrated embodiment, the offset calculation logic 137 receives the master frequency control word 105 to help determine the appropriate offset. Although shown separately, the adder 114 and the offset calculation logic 137 can be combined and supply a modified FCWM as a FCWS. In one embodiment, the slave oscillator 103 has two offset calculation blocks 137 (only one is shown) and two adding circuits 114 (only one is shown). One of the offset calculation blocks and the adding circuit is for a reference delay line (e.g., Figure 2 and Figure 4 201, 401), and another offset calculation block and addition circuit are for the attenuation delay line (see, for example, Figure 2 and Figure 4 203, 403 in FIG. 2). This allows independent adjustment of the frequencies of the slave reference delay line and the attenuation delay line that were originally controlled by the master frequency control word.

[0026] Figure 5An embodiment is shown in which a master oscillator 501 controls two slave oscillators 503 and 505. The slave oscillator 503 receives a master frequency control word (FCWM) via an adder circuit 507, and the slave oscillator 505 receives a master frequency control word (FCWM) via an adder circuit 509. The slave oscillator 503 receives a degraded voltage VDD(0), and the slave oscillator 505 receives a degraded voltage VDD(1). VDD(0) and VDD(1) may be derived from a common input voltage rail, but may be used for separately controlled voltage domains and clock domains. For example, one voltage domain may be shut down while the other remains powered. The two slave oscillators may receive different reference voltages. Separate offset calculation blocks 511 and 515 independently determine any desired offsets of the two slave oscillator frequency control words FCWS0 and FCWS1.

[0027] Figure 6 and Figure 7 Provides how the amount of expansion can be determined and supplied to the offset calculation logic 137 ( Figure 1 ). In addition to the control loop 104, the clock logic may include logic for determining the effective frequency of the slave oscillator within a predetermined time period. The slave oscillator output signal 601 and the known reference clock signal 603 are supplied to the effective frequency calculation logic 605. The effective frequency calculation logic counts the number of slave oscillator clock cycles that occur within a predetermined number of reference clock cycles to determine the effective frequency. The number of reference clock cycles corresponds to a specific time period, for example, 10ms. The microcontroller 607 may operate a proportional integral derivative (PID), PI control loop, or another form of control to control the effective frequency.

[0028] refer to Figure 7 , the control logic sets the maximum frequency Fmax 701. Curve 703 represents the actual frequency. As can be seen, the actual frequency is limited by the maximum frequency. The controller uses the expansion input 140 to the offset calculation logic 137 to limit the frequency by reducing the frequency control word and slowing down the slave oscillator (see Figure 1 ), which ensures that the frequency is limited to a maximum frequency. The target frequency is shown as 705. If over time, the effective frequency 707 is far below the target frequency 705, the expansion amount input 140 can be used to increase the frequency of the slave oscillator and increase the effective frequency over time to get closer to the target frequency, such as Figure 7 When the effective frequency is higher than the target frequency, the master frequency control word can be adjusted using the offset calculation logic to reduce the slave oscillator frequency to reduce the effective frequency. In addition to controlling the frequency by applying an offset to the master frequency control word, the controller can also increase or decrease VDD in response to the effective frequency being higher or lower than the target value.

[0029] Although circuits and physical structures are generally assumed for some embodiments, it is well recognized that in modern semiconductor design and manufacturing, physical structures and circuits can be implemented in a computer-readable description form suitable for use in subsequent design, testing, or manufacturing stages. The structures and functionality presented as separate components in the exemplary configuration can be implemented as combined structures or components. It is contemplated that embodiments include circuits, circuit systems, related methods, and non-transitory computer-readable media encodings of such circuits, systems, and methods, all of which are described herein and as defined in the appended claims. As used herein, non-transitory computer-readable media include at least a disk, tape, or other magnetic, optical, semiconductor (e.g., flash memory card, ROM), or electronic media.

[0030] Thus, embodiments have been described that decouple tracking targets for target voltage and temperature from adapting clock frequency in response to high frequency voltage variations of the supply voltage. The description set forth herein is illustrative and is not intended to limit the scope of the following claims. Other changes and modifications may be made to the embodiments disclosed herein based on the description set forth herein without departing from the scope set forth in the following claims.

Claims

1. A device, wherein include: a first oscillator circuit coupled to a first supply voltage and configured to supply a first oscillator signal, the first supply voltage being a regulated supply voltage; a control circuit coupled to the first oscillator signal and to an indication of a target frequency and configured to supply a first frequency control signal to control the frequency of the first oscillator signal to the target frequency; a second oscillator circuit coupled to receive a second supply voltage and configured to supply a second oscillator signal having a frequency responsive to a second frequency control signal, the second frequency control signal being based at least in part on the first frequency control signal, and wherein the frequency of the second oscillator signal is further responsive to voltage changes of the second supply voltage.

2. The device of claim 1, wherein the second oscillator circuit further comprises include: a first delay line coupled to a third supply voltage and to the second frequency control signal, wherein the first delay line supplies a first delay line output signal; a second delay line coupled to the second supply voltage and to the second frequency control signal, wherein the second delay line supplies a second delay line output signal; as well as A logic circuit is used to supply the second oscillator signal according to a logical relationship between the first delay line output signal and the second delay line output signal.

3. The apparatus of claim 2, wherein the first oscillator circuit further comprises include: a third delay line coupled to the regulated supply voltage and to the first frequency control signal, wherein the third delay line supplies a third delay line output signal; a fourth delay line coupled to the regulated supply voltage and to the first frequency control signal, wherein the fourth delay line supplies a fourth delay line output signal; as well as A second logic circuit is configured to supply the first oscillator signal according to a logical relationship between the third delay line output signal and the fourth delay line output signal.

4. The apparatus of claim 2, wherein the third supply voltage is the regulated supply voltage.

5. The apparatus of any one of claims 1 to 4, wherein the second frequency control signal is further based on an offset from the first frequency control signal, and wherein the first frequency control signal is a first digital signal and the offset is a second digital signal, and the apparatus further comprises an adding circuit for adding the second digital signal to the first digital signal or subtracting the second digital signal from the first digital signal.

6. The apparatus of any one of claims 1 to 4, wherein the first oscillator circuit tracks temperature variations and voltage variations of the regulated supply voltage.

7. The apparatus of any one of claims 1 to 4, further comprising a selector circuit for selecting between the first oscillator signal and the second oscillator signal.

8. The device according to any one of claims 1 to 4, further comprising: include: a third oscillator circuit coupled to a fourth supply voltage and to a third frequency control signal and configured to supply a third oscillator signal having a frequency responsive to a change in the fourth supply voltage; and Wherein the frequency of the third oscillator signal is further responsive to the third frequency control signal, the third frequency control signal being based at least in part on the first frequency control signal.

9. A method for compensating a clock signal in an integrated circuit, wherein include: supplying a first oscillator signal from a first oscillator circuit receiving a first supply voltage; generating a first frequency control signal based on a target frequency and a frequency of the first oscillator signal to control the frequency of the first oscillator signal; supplying a second frequency control signal to a second oscillator circuit that receives a second supply voltage and receives a third supply voltage, the second frequency control signal being based at least in part on the first frequency control signal; supplying a second oscillator signal from the second oscillator circuit, wherein a frequency of the second oscillator signal is based at least in part on the second frequency control signal; as well as The frequency of the second oscillator signal is adjusted in response to voltage changes associated with the second supply voltage.

10. The method of claim 9, further comprising: include: supplying the second frequency control signal and the third supply voltage to a first delay line of the second oscillator circuit; supplying a first delay line output signal from said first delay line; supplying the second frequency control signal and the second supply voltage to a second delay line of the second oscillator circuit; supplying a second delay line output signal from the second delay line; supplying the first delay line output signal and the second delay line output signal to a logic circuit; as well as The second oscillator signal is supplied from the logic circuit according to a logical relationship of the first delay line output signal and the second delay line output signal.

11. The method of claim 9, wherein the first supply voltage is a regulated supply voltage, and wherein the second supply voltage is a noisy supply voltage.

12. The method according to claim 9 or 10, further comprising: include: combining the first frequency control signal and an offset signal to generate the second frequency control signal; and Wherein the third power supply voltage is a regulated power supply voltage.

13. The method of claim 11, further comprising: include: combining the first frequency control signal and an offset signal to generate the second frequency control signal; and Wherein the third power supply voltage is the regulated power supply voltage.

14. The method according to any one of claims 9 to 11, further comprising: include: the second oscillator circuit tracks voltage variation of the second power supply voltage to generate the second oscillator signal; as well as The first oscillator circuit tracks temperature variations and voltage variations of the first supply voltage.

15. The method according to any one of claims 9 to 11, further comprising: include: One of the first oscillator signal and the second oscillator signal is selected in a selector circuit.

16. The method according to any one of claims 9 to 11, further comprising: include: supplying a fourth power supply voltage and a fifth power supply voltage to a third oscillator circuit; combining the first frequency control signal and the second offset signal to generate a third frequency control signal; supplying the third frequency control signal to the third oscillator circuit to at least partially control the frequency of a third oscillator signal; and The frequency of the third oscillator signal is adjusted in response to changes in the fourth supply voltage.

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