Current limiting circuit and device of an inverter

Abstract

The present invention relates to a current limiting circuit and device for an inverter. The circuit includes: a main control module, a wave generating module, an overcurrent detection module, and a plurality of lock / unlock modules; the main control module is connected to the input end of the wave generating module, the wave generating module has a plurality of output ends, the input end of each lock / unlock module is connected to one output end of the wave generating module, the output end of each lock / unlock module is used to be connected to a control signal input end in a three-level inverter, the input end of the overcurrent detection module is used to be connected to the output end of the three-level inverter, and the output end of the overcurrent detection module is connected to the input ends of each lock / unlock module; by setting a plurality of independent lock / unlock modules, it is ensured that each switching tube in the three-level inverter can be blocked and driven cycle by cycle when current limiting occurs, so that when an interphase short circuit occurs in the three-level inverter, the switching tube state switching time can be extended, the damage to the switching tube can be reduced, and the loss of the switching tube can be lowered.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and particularly to a current limiting circuit and device for an inverter. Background Art

[0002] An inverter is a device that converts direct current into alternating current; an inverter mainly consists of an inverter bridge, control logic, and a filter circuit; it is widely used in air conditioners, home theaters, electric grinders, power tools, sewing machines, DVDs, VCDs, computers, TVs, washing machines, range hoods, refrigerators, video recorders, massagers, fans, and lighting.

[0003] Refer to Figure 1 , Figure 1 which shows a circuit schematic diagram of a three-level inverter, including four switching tubes and a freewheeling diode. The four switching tubes are switching tube T1, switching tube T2, switching tube T3, and switching tube T4. Among them, switching tube T1 and switching tube T4 are the outer tubes of the bridge arm, and switching tube T2 and switching tube T3 are the inner tubes of the bridge arm.

[0004] Currently, the commonly used current limiting control system for a one-word three-level inverter mainly includes a wave generation and fault drive protection module of DSP (Digital Signal Processor), CPLD (Complex Programmable Logic Device), an inverter current detection circuit, and an inverter topology circuit. Its basic control strategy is: DSP generates two drive signals, where the two drive signals are a positive half-wave drive signal PWMA and a negative half-wave drive signal PWMB, as well as an output voltage positive and negative half-cycle selection signal PWMS, and an enable signal PWMEN. When PWMEN is at a high level, CPLD generates four drives through the wave generation module according to the wave generation logic of the one-word three-level inverter. When PWMEN is at a high level and PWMS is at a high level, it indicates that the output voltage of the three-level inverter is in the positive half-cycle, switching tube T2 conducts, switching tube T4 cuts off, and switching tubes T1 and T3 conduct in a complementary manner and ensure a dead time; when PWMEN is at a high level and PWMS is at a low level, the output voltage is in the negative half-cycle, switching tube T3 conducts, switching tube T1 cuts off, and switching tubes T2 and T4 conduct in a complementary manner and ensure a dead time. The dead time is generated in the CPLD wave generation module to prevent the phenomenon of simultaneous conduction of complementary tubes due to the switching delay of the switching tubes.

[0005] However, the existing inverter current limiting control system performs the drive blocking and unlocking of the outer tube and the inner tube based on the drive signal of the outer tube and the hardware current limiting detection signal. To prevent the tubes from being damaged due to excessive stress, when performing drive blocking, the drive of the outer tube must be turned off first and then the drive of the inner tube. When unlocking, it must be ensured that the inner tube is turned on first and then the outer tube is turned on. When there is a delay in the processing of the hardware current limiting signal and / or an inter-phase short circuit, this method may cause current limiting to be triggered when the inner tube is being driven, and when unlocking, the switching frequency of the inner tube will become very high, that is, the switching state of the inner tube changes frequently, which is likely to cause damage to the inner tube, and at the same time, the switching loss of the inner tube will also increase. Summary of the Invention

[0006] Based on this, in view of the problem of large switching tube losses in the inverter in the traditional inverter current limiting circuit, it is necessary to provide a current limiting circuit and device for the inverter.

[0007] Provided is a current limiting circuit for an inverter. The current limiting circuit of the inverter includes: a main control module, a wave generating module, an overcurrent detection module, and a plurality of blocking and unlocking modules; the main control module is connected to the input end of the wave generating module, the wave generating module has a plurality of output ends, the input end of each blocking and unlocking module is connected to one of the output ends of the wave generating module, the output end of each blocking and unlocking module is used to be connected to a control signal input end in a three-level inverter, the input end of the overcurrent detection module is used to be connected to the output end of the three-level inverter, and the output end of the overcurrent detection module is connected to the input ends of each blocking and unlocking module.

[0008] In one embodiment, the number of the blocking and unlocking modules is equal to the number of control signal input ends in the three-level inverter.

[0009] In one embodiment, the output end of each blocking and unlocking module is used to be connected to a control signal input end in a one-word three-level inverter.

[0010] In one embodiment, the number of the locking and unlocking modules is four, namely a first locking and unlocking module, a second locking and unlocking module, a third locking and unlocking module, and a fourth locking and unlocking module. The wave generating module has four output terminals, namely a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The input terminal of the first locking and unlocking module is connected to the first output terminal, and the output terminal of the first locking and unlocking module is used to be connected to the first control signal input terminal of the three-level inverter. The input terminal of the second locking and unlocking module is connected to the second output terminal, and the output terminal of the second locking and unlocking module is used to be connected to the second control signal input terminal of the three-level inverter. The input terminal of the third locking and unlocking module is connected to the third output terminal, and the output terminal of the third locking and unlocking module is used to be connected to the third control signal input terminal of the three-level inverter. The input terminal of the fourth locking and unlocking module is connected to the fourth output terminal, and the fourth output terminal of the fourth locking and unlocking module is used to be connected to the fourth control signal input terminal of the three-level inverter.

[0011] In one embodiment, the main control module is further connected to the overcurrent detection module.

[0012] In one embodiment, the main control module is a digital signal processor.

[0013] In one embodiment, a current limiting device for an inverter is provided. The device includes a three-level inverter and the current limiting circuit of the inverter in any of the above embodiments. The output terminal of each locking and unlocking module is connected to a control signal input terminal in the three-level inverter, and the input terminal of the overcurrent detection module is connected to the output terminal of the three-level inverter.

[0014] In one embodiment, the three-level inverter is a one-dimensional three-level inverter.

[0015] In one embodiment, the three-level inverter includes: switching transistors T1, T2, T3, T4, diode D5, diode D6, and capacitor C1; the first end of the switching transistor T1 is used to connect to the positive half-wave power supply, the second end of the switching transistor T1 is connected to the first end of the switching transistor T2, the second end of the switching transistor T2 is connected to the first end of the switching transistor T3, the second end of the switching transistor T3 is connected to the first end of the switching transistor T4, the second end of the switching transistor T4 is used to connect to the negative half-wave power supply, the second end of the switching transistor T3 is connected to the anode of the diode D6, the cathode of the diode D6 is connected to the anode of the diode D5, the cathode of the diode D5 is connected to the second end of the switching transistor T1, the cathode of the diode D6 is also used to ground, the second end of the switching transistor D2 is connected to the first end of the capacitor C1, the second end of the capacitor C1 is used to ground, the first end of the capacitor C1 is also connected to the input end of the overcurrent detection module, and the control ends of the switching transistors T1, T2, T3, and T4 are respectively connected to the output end of a corresponding unlocking and locking module.

[0016] In one embodiment, the three-level inverter further includes diodes D1, D2, D3, and D4; the anode of the diode D1 is connected to the second end of the switching transistor T1, the cathode of the diode D1 is connected to the first end of the switching transistor T1, the anode of the diode D2 is connected to the second end of the switching transistor T2, the cathode of the diode D2 is connected to the first end of the switching transistor T2, the anode of the diode D3 is connected to the second end of the switching transistor T3, the cathode of the diode D3 is connected to the first end of the switching transistor T3, the anode of the diode D4 is connected to the second end of the switching transistor T4, and the cathode of the diode D4 is connected to the first end of the switching transistor T4.

[0017] The current limiting circuit of the above inverter, by setting multiple independent unlocking and locking modules and connecting them to the respective control signal input ends in the three-level inverter to independently drive each switching transistor of the three-level inverter, ensures that each switching transistor of the three-level inverter can be blocked and driven periodically when current limiting occurs, so as to better achieve the effect of current limiting for each wave, and when an inter-phase short circuit occurs in the three-level inverter, it can extend the switching time of the switching transistor state, that is, reduce the switching frequency of the switching transistor state, to reduce the damage to the switching transistor, reduce the loss of the switching transistor, and extend the service life of the switching transistor; further, by reducing the switching frequency of the switching transistor state, the frequent jump of the output waveform of the inverter can be reduced, that is, the current limiting current waveform output by the inverter is made better. Description of the Drawings

[0018] Figure 1 is the circuit schematic diagram of an existing inverter;

[0019] Figure 2 is the structural block diagram of the current limiting control system of an existing inverter;

[0020] Figure 3 is the structural block diagram of the current limiting circuit of the inverter in an embodiment of the present invention;

[0021] Figure 4 is Figure 2 the abnormal current limiting timing diagram of the current limiting control system of the existing inverter in

[0022] Figure 5 is the abnormal current limiting timing diagram of the current limiting circuit of the inverter in an embodiment of the present invention;

[0023] Figure 6 is the circuit schematic diagram of the current limiting circuit of the inverter in another embodiment of the present invention;

[0024] Figure 7 is the structural block diagram of the current limiting device of the inverter in an embodiment of the present invention;

[0025] Figure 8 is the circuit schematic diagram of the current limiting device of the inverter in another embodiment of the present invention;

[0026] Figure 9 is the circuit schematic diagram of the three-level inverter in the current limiting device of the inverter in an embodiment of the present invention. Detailed Embodiments

[0027] In order to make the above objects, features and advantages of the present invention more obvious and understandable, the following will describe the detailed embodiments of the present invention with reference to the accompanying drawings. Many specific details are set forth in the following description in order to fully understand the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0028] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or positional relationship shown in the drawings. These terms are only used for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0029] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0030] In the present invention, unless otherwise clearly specified and limited, the terms "mounted", "connected", "connected to", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal connection or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] In the present invention, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0032] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this article are only for the purpose of illustration and do not represent the only implementation.

[0033] For example, a current limiting circuit of an inverter is provided. The current limiting circuit of the inverter includes: a main control module, a wave generating module, an overcurrent detection module and a plurality of lock / unlock modules; the main control module is connected to the input end of the wave generating module, the wave generating module has a plurality of output ends, the input end of each lock / unlock module is connected to one of the output ends of the wave generating module, the output end of each lock / unlock module is used to be connected to a control signal input end in a three-level inverter, the input end of the overcurrent detection module is used to be connected to the output end of the three-level inverter, and the output end of the overcurrent detection module is connected to the input ends of each lock / unlock module.

[0034] In the above current limiting circuit of the inverter, by setting a plurality of independent lock / unlock modules and connecting them to the respective control signal input ends in the three-level inverter, each switching tube in the three-level inverter can be independently driven, so as to ensure that each switching tube in the three-level inverter can be blocked and driven cycle by cycle when current limiting occurs, so as to better achieve the effect of current limiting wave by wave, and when an inter-phase short circuit occurs in the three-level inverter, the switching time of the switching tube can be extended, that is, the switching frequency of the switching tube state can be reduced, so as to reduce the damage to the switching tube, reduce the loss of the switching tube, and extend the service life of the switching tube; further, by reducing the switching frequency of the switching tube state, the frequent jump of the output waveform of the inverter can be reduced, that is, the current limiting current waveform output by the inverter is better.

[0035] Refer to Figure 3 , Figure 3The structure block diagram of the current limiting circuit of an inverter in an embodiment of the present invention is shown. An embodiment of the present invention provides a current limiting circuit 10 of an inverter. The current limiting circuit 10 of the inverter includes: a main control module 100, a wave generating module 200, an overcurrent detection module 500, and a plurality of locking and unlocking modules 400; the main control module 100 is connected to the input end of the wave generating module 200. The wave generating module 200 has a plurality of output ends. The input end of each locking and unlocking module 300 is connected to one of the output ends of the wave generating module 200. The output end of each locking and unlocking module 300 is used to be connected to a control signal input end in a three-level inverter 400. The input end of the overcurrent detection module 500 is used to be connected to the output end of the three-level inverter 400. The output end of the overcurrent detection module 500 is connected to the input ends of each of the locking and unlocking modules 300.

[0036] Specifically, the control signal input end of the three-level inverter is the control end of the switching tube in the three-level inverter; the locking and unlocking module is used to send a logic level signal to the control signal input end of the three-level inverter to control the change of the working state of the corresponding switching tube in the three-level inverter. It should be understood that the three-level inverter has a plurality of control signal input ends, that is, the three-level inverter has a plurality of switching tubes, and each locking and unlocking module is used to be connected to one of the control signal input ends in one-to-one correspondence. That is, one locking and unlocking module is used to control the state switching of one switching tube.

[0037] Specifically, the overcurrent detection module is used to detect the magnitude of the output current of the three-level inverter. When it detects that the current is greater than a preset value, it outputs a first control signal, that is, a current limiting signal; and transmits the first control signal to the locking and unlocking module so that the locking and unlocking drive module outputs a blocking signal and enters the current limiting logic. When it detects that the current is less than or equal to the preset value, it outputs a second control signal and sends the second control signal to the locking and unlocking module so that the locking and unlocking module works normally, that is, the locking and unlocking module outputs a normal drive pulse signal; thus achieving the purpose of current limiting wave by wave. In this embodiment, the first control signal is a low-level signal, and the second control signal is a high-level signal. It is worth mentioning that the overcurrent detection module is a prior art. For example, the overcurrent detection module can be composed of a current detection unit and a comparator, and its specific circuit schematic diagram is not listed one by one in this embodiment.

[0038] The current-limiting circuit of the above inverter sets multiple independent lock / unlock modules, which are respectively connected to each control signal input end in the three-level inverter to independently drive each switching tube in the three-level inverter, so as to ensure that each switching tube in the three-level inverter can be blocked and driven periodically when current limiting occurs, so as to better achieve the effect of current limiting for each wave, and when an inter-phase short circuit occurs in the three-level inverter, it can extend the switching time of the switching tube state, that is, reduce the switching frequency of the switching tube state, so as to reduce the damage to the switching tube, reduce the loss of the switching tube, and extend the service life of the switching tube; further, by reducing the switching frequency of the switching tube state, the frequent jump of the output waveform of the inverter can be reduced, that is, the current-limiting current waveform output by the inverter is better.

[0039] To further illustrate the beneficial effects achieved by the current-limiting circuit of the inverter described in the present application, as Figure 4 shown, it shows the timing diagram of the current-limiting circuit of a traditional inverter when an inter-phase short circuit occurs in the positive half-wave signal, that is Figure 2 the current-limiting circuit of the inverter in Figure 1 In the inverter, its timing diagram when an inter-phase short circuit occurs in the positive half-wave signal is simply referred to as an abnormal current-limiting timing diagram; in the normal mode, overcurrent generally occurs when the outer tube is driven, but overcurrent has actually occurred when the outer tube is driven; the first control signal, that is, the current-limiting signal IC, takes effect when the inner tubes T2 and T4 are driven due to hardware delay. According to the existing technology of current limiting for each wave. As Figure 4 shown, at time t1, the current-limiting signal IC is detected, and the receiving potential of the lock / unlock module is pulled down, entering the current-limiting logic, and the outer tubes are turned off, that is, the switching tubes T1 and the switching tube T4 are turned off. At this time, the driving of the switching tubes T1 and the switching tube T4 themselves is in the off state, and the inner tubes are directly turned off at t1; that is, the switching tubes T2 and the switching tube T3; when the current-limiting signal is detected to be pulled down, and at the same time the rising edge of the positive half-wave drive arrives, the switching tubes T2 and the switching tube T3 are turned on at the same time, and it is delayed until t4, and the drive is performed according to the normal logic. The Δt time in the figure is very short, and the switching tubes frequently jump within one cycle. At this time, the switching frequency of the switching tube T3 will become very large, which will damage the switching tube and increase the switching loss of the switching tube.

[0040] For the current-limiting circuit of the inverter in the present application, applying this circuit to Figure 1 the three-level inverter circuit, that is Figure 1 the switching tubes T1, the switching tube T2, the switching tube T3 and the switching tube T4 in Figure 5As shown, taking the positive half-wave as an example, for instance, overcurrent actually occurs when driving the outer tube, but due to the hardware delay of the current-limiting signal, the signal takes effect when driving the inner tube. At time t1, the current-limiting signal IC is detected, and the receiving potential of the locking and unlocking module is pulled down, entering the current-limiting logic. The locking and unlocking module turns off the switching tubes T1 and T4. At this time, the drives of the switching tubes T1 and T4 themselves are in the off state, and the switching tubes T2 and T3 are directly turned off at t1. When the current-limiting signal is detected to be pulled down, since the control terminals of each switching tube are connected to different locking and unlocking modules, the operating states of each switching tube are not affected by the logic signals sent by other locking and unlocking modules, so that the drives of the switching tubes T2 and T3 are turned on or off according to the periodic source signal, that is, the switching tubes T2 and T3 are turned on at time t4, and then the drive is sent according to the normal timing. Figure 5 The Δt time in Figure 4 is longer than the Δt in

[0041] such that the switching tube T3 remains in the off state for nearly one cycle, that is, reducing the switching state switching frequency of the switching tube, so as to reduce the damage to the switching tube, reduce the loss of the switching tube, and extend the service life of the switching tube.

[0042] In one embodiment, the number of the locking and unlocking modules is equal to the number of control signal input terminals in the three-level inverter. Specifically, since the output terminal of each locking and unlocking module is used to connect to a control signal input terminal in the three-level inverter, that is, each control signal input terminal in the three-level inverter is connected to a locking and unlocking module. By setting the number of locking and unlocking modules to be equal to the number of control signal input terminals in the three-level inverter, while meeting the current-limiting protection of the inverter, the occupation of the locking and unlocking module resources is reduced, so as to reduce the production manufacturing cost.

[0043] Please refer to Figure 6, in one embodiment, the number of the blocking and unlocking modules is four. Specifically, a one-dimensional three-level inverter usually includes two outer transistors and two inner transistors. By setting four blocking and unlocking modules, the two outer transistors and the two inner transistors are respectively driven to meet the current limiting protection of the one-dimensional three-level inverter and reduce the loss of the switching transistors in the inverter. Specifically, the four blocking and unlocking modules are respectively the first blocking and unlocking module, the second blocking and unlocking module, the third blocking and unlocking module, and the fourth blocking and unlocking module; the wave generating module has four output terminals, namely the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal. The input terminal of the first blocking and unlocking module is connected to the first output terminal, and the output terminal of the first blocking and unlocking module is used to be connected to the first control signal input terminal of the three-level inverter. The input terminal of the second blocking and unlocking module is connected to the second output terminal, and the output terminal of the second blocking and unlocking module is used to be connected to the second control signal input terminal of the three-level inverter. The input terminal of the third blocking and unlocking module is connected to the third output terminal, and the output terminal of the third blocking and unlocking module is used to be connected to the third control signal input terminal of the three-level inverter. The input terminal of the fourth blocking and unlocking module is connected to the fourth output terminal, and the fourth output terminal of the fourth blocking and unlocking module is used to be connected to the fourth control signal input terminal of the three-level inverter.

[0044] Please refer to Figure 3 , in one embodiment, the main control module 100 is also connected to the overcurrent detection module 500. Specifically, the main control module is connected to the overcurrent detection module, that is, the main control module is connected to the adjustment terminal of the overcurrent detection module. The main control module is used to adjust the current limiting current of the overcurrent detection module, that is, to adjust the preset value, so as to meet the requirements of different products or users.

[0045] In one embodiment, the main control module is a digital signal processor. Specifically, a digital signal processor, that is, DSP (Digital Signal Processor), is a dedicated chip for digital signal processing. By setting a digital signal processor, the wave generating module can better send positive half-wave drive signals and negative half-wave drive signals.

[0046] Please refer to Figure 7, in one embodiment, a current limiting device 20 of an inverter is provided. The device includes a three-level inverter 400 and the current limiting circuit 10 of the inverter described in any of the above embodiments; the output end of each of the lock / unlock modules 300 is connected to a control signal input end in the three-level inverter 400, and the input end of the overcurrent detection module 500 is connected to the output end of the three-level inverter 400. In one embodiment, the current limiting circuit 10 of the inverter includes: a main control module 100, a wave generating module 200, an overcurrent detection module 500, and multiple lock / unlock modules 300; the main control module 100 is connected to the input end of the wave generating module 200, the wave generating module 200 has multiple output ends, the input end of each of the lock / unlock modules 300 is connected to one of the output ends of the wave generating module 200, the output end of each of the lock / unlock modules 300 is connected to a control signal input end in the three-level inverter 400, the input end of the overcurrent detection module is connected to the output end of the three-level inverter 400, and the output end of the overcurrent detection module 500 is connected to the input ends of each of the lock / unlock modules 300.

[0047] For the above current limiting device of the inverter, by setting multiple independent lock / unlock modules and connecting them to the respective control signal input ends in the three-level inverter, each switching tube in the three-level inverter can be independently driven, so as to ensure that each switching tube in the three-level inverter can be blocked and driven periodically when current limiting occurs, so as to better achieve the effect of current limiting for each wave, and when an inter-phase short circuit occurs in the three-level inverter, the switching time of the switching tube can be extended, that is, the switching frequency of the switching tube state can be reduced, so as to reduce the damage to the switching tube, reduce the loss of the switching tube, and extend the service life of the switching tube; further, by reducing the switching frequency of the switching tube state, the frequent jump of the output waveform of the inverter can be reduced, that is, the current limiting current waveform output by the inverter is better.

[0048] In one embodiment, the three-level inverter is a one-dimensional three-level inverter.

[0049] Please refer to Figure 8 and Figure 9, in one embodiment, the three-level inverter 400 includes: switching transistors T1, T2, T3, T4, diode D5, diode D6, and capacitor C1; the first end of the switching transistor T1 is used to connect to the positive half-wave power supply +BUS, the second end of the switching transistor T1 is connected to the first end of the switching transistor T2, the second end of the switching transistor T2 is connected to the first end of the switching transistor T3, the second end of the switching transistor T3 is connected to the first end of the switching transistor T4, the second end of the switching transistor T4 is used to connect to the negative half-wave power supply -BUS, the second end of the switching transistor T3 is connected to the anode of the diode D6, the cathode of the diode D6 is connected to the anode of the diode D5, the cathode of the diode D5 is connected to the second end of the switching transistor T1, the cathode of the diode D6 is also used to connect to the ground, the second end of the switching transistor D2 is connected to the first end of the capacitor C1, the second end of the capacitor C1 is used to connect to the ground, the first end of the capacitor C1 is also connected to the input end of the overcurrent detection module 500, and the control ends of the switching transistors T1, T2, T3, and T4 are respectively connected to the output end of a lockout and unlocking module. Specifically, the number of lockout and unlocking modules is four, namely the first lockout and unlocking module, the second lockout and unlocking module, the third lockout and unlocking module, and the fourth lockout and unlocking module; the control ends of the switching transistors T1, T2, T3, and T4 are respectively connected to the output end of a lockout and unlocking module; that is, the control end of the switching transistor T1 is connected to the output end of the first lockout and unlocking module, the control end of the switching transistor T2 is connected to the output end of the second lockout and unlocking module, the control end of the switching transistor T3 is connected to the output end of the third lockout and unlocking module, and the control end of the switching transistor T4 is connected to the output end of the fourth lockout and unlocking module. In the three-level inverter of this embodiment, by the logic level signals output by the lockout and unlocking module, the switching states of the switching transistors T1, T2, T3, and T4 are respectively controlled to change, so as to output three level signals. For example, controlling the switching transistors T1 and T2 to conduct and the switching transistors T3 and T4 to disconnect, so that the first end of the capacitor C1 outputs a positive half-wave signal. Another example is to control the switching transistors T1 and T2 to disconnect and the switching transistors T3 and T4 to conduct, so that the first end of the capacitor C1 outputs a negative half-wave signal. Another example is to control the switching transistors T1 and T4 to disconnect, so that the first end of the capacitor C1 is grounded, so that the inverter can output three-level signals. In one embodiment, the switching transistor is a field effect transistor. In another embodiment, the switching transistor is a bipolar transistor.

[0050] Please refer to Figure 9, in one embodiment, the three-level inverter 400 further includes an inductor L1. The first end of the inductor L1 is connected to the second end of the switching transistor D2, and the second end of the inductor L1 is connected to the first end of the capacitor C1.

[0051] Please refer to again Figure 9 , in one embodiment, the three-level inverter further includes diodes D1, D2, D3, and D4; the anode of the diode D1 is connected to the second end of the switching transistor T1, the cathode of the diode D1 is connected to the first end of the switching transistor T1, the anode of the diode D2 is connected to the second end of the switching transistor T2, the cathode of the diode D2 is connected to the first end of the switching transistor T2, the anode of the diode D3 is connected to the second end of the switching transistor T3, the cathode of the diode D3 is connected to the first end of the switching transistor T3, the anode of the diode D4 is connected to the second end of the switching transistor T4, and the cathode of the diode D4 is connected to the first end of the switching transistor T4. Specifically, by reversely paralleling a diode in each of the switching transistors T1, T2, T3, and T4, which is equivalent to a damping diode, a loop is provided for the energy feedback of the inductive load to prevent the back electromotive force generated by the inductive load from breaking down and damaging the switching transistor, thereby protecting the switching transistor.

[0052] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0053] The above embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A current limiting circuit for a three-level inline inverter, characterized in that: The current limiting circuit of the inverter includes: a main control module, a wave generating module, an overcurrent detection module and the first to fourth sealing and unlocking modules; The four output terminals of the main control module are respectively connected to the four input terminals of the wave generating module, and the four output terminals of the wave generating module are respectively connected to a corresponding input terminal of the first to fourth sealing and unlocking modules. The input terminal of the overcurrent detection module is connected to the output terminal of the inverter, and the output terminal of the overcurrent detection module is connected to the input terminal of each of the sealing and unlocking modules; the main control module is connected to the regulating terminal of the overcurrent detection module; The inline three-level inverter includes switches T1-T4, diodes D5-D6, an inductor L1, and a capacitor C1. The switches T1 and T4 are outer tubes, and the switches T2 and T3 are inner tubes. The output ends of the first to fourth locking and unlocking modules are respectively connected to a corresponding one of the control signal input ends of the switches T1-T4. During the positive half-wave operation of the inverter, when the overcurrent detection module detects a current limiting signal at time t1, the current limiting signal is transmitted to the first to fourth sealing and unlocking modules. The first to fourth sealing and unlocking modules turn off the switch tubes T1-T4. The control signal input end of each switch tube is connected to a different sealing and unlocking module. The operating state of each switch tube is not affected by the logic signal sent by other sealing and unlocking modules. The inner tubes T2-T3 are controlled by the periodic source signal again at time t4 and are turned on or off according to the normal timing. The time interval Δt between time t4 and time t1 is configured to be close to one switching cycle to reduce the switching frequency of the switch tube.

2. The current limiting circuit of the inverter according to claim 1, characterized in that: The main control module is a digital signal processor.

3. A current limiting device for a three-level inverter, characterized in that: The invention comprises a three-level inverter and a current limiting circuit of the inverter as claimed in any one of claims 1 to 2.

4. The current limiting device of the inverter according to claim 3, characterized in that: The first end of the switch tube T1 is used to be connected to the positive half-wave power supply, the second end of the switch tube T1 is connected to the first end of the switch tube T2, the second end of the switch tube T2 is connected to the first end of the switch tube T3, the second end of the switch tube T3 is connected to the first end of the switch tube T4, the second end of the switch tube T4 is used to be connected to the negative half-wave power supply, the second end of the switch tube T3 is connected to the anode of the diode D6, the cathode of the diode D6 is connected to the anode of the diode D5, the cathode of the diode D5 is connected to the second end of the switch tube T1, and the cathode of the diode D6 is also used for grounding. The second end of the switch tube T2 is connected to the first end of the capacitor C1 through the inductor L1, the second end of the capacitor C1 is used for grounding, and the first end of the capacitor C1 is also connected to the input end of the overcurrent detection module.

5. The current limiting device of the inverter according to claim 4, characterized in that: The inverter further includes diodes D1 - D4 connected in anti-parallel to the switch tubes T1 - T4 respectively.

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