Industrial chip-scale packaging for microelectronic devices

Abstract

A microelectronic device (100) includes a die (102) having input / output, I / O, terminals (104) and a dielectric layer (106) on the die (102). The microelectronic device (100) includes electrically conductive pillars (110) that are electrically coupled to the I / O terminals (104) and extend through the dielectric layer (106) to an exterior of the microelectronic device (100). Each pillar (110) includes a post (112) that is electrically coupled to one of the I / O terminals (104) and a head (114) that contacts the post (112) at an end of the post (112) opposite the I / O terminal (104). The head (114) extends laterally beyond the post (112) in at least one lateral direction.

Description

Technical Field

[0001] The present disclosure relates generally to microelectronic devices and, more particularly, to chip-scale packaging in microelectronic devices. Background Art

[0002] The size and cost of microelectronic devices are constantly decreasing. Furthermore, the density of components within these devices is increasing. As size decreases, power and current density increase through input / output (I / O) structures, such as bump bonding structures. This results in higher temperatures and the risk of failure due to electromigration. Meeting both reliability and cost targets simultaneously has always been challenging for package design. Summary of the Invention

[0003] In the described examples, a microelectronic device has a die with input / output (I / O) terminals, a dielectric layer on the die, and pillars electrically coupled to the I / O terminals and extending through the dielectric layer to the exterior of the microelectronic device. The pillars are electrically conductive. Each pillar includes a pillar and a head, the pillar electrically coupled to one of the I / O terminals, the head contacting the pillar at an end of the pillar opposite the I / O terminal. The head extends laterally beyond the pillar in at least one lateral direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a cross section of an example microelectronic device.

[0005] Figures 2A to 2L is a cross-section of a microelectronic device depicted at a stage in an example formation method.

[0006] Figures 3A to 3F is a cross-section of a microelectronic device depicted at a stage in another example formation method.

[0007] Figures 4A to 4F is a cross-section of a microelectronic device depicted at a stage in another example formation method.

[0008] Figures 5A to 5G is a cross-section of a microelectronic device depicted at a stage in another example formation method. DETAILED DESCRIPTION

[0009] The accompanying drawings are not drawn to scale. This specification is not limited by the order of the actions or events shown, as some actions or events can occur in different orders and / or simultaneously with other actions or events. In addition, some of the actions or events shown are optional for implementing the methods according to this specification.

[0010] A microelectronic device has a die with input / output (I / O) terminals. The die can be, for example, an integrated circuit, a discrete semiconductor device, or a microelectromechanical system (MEMS) device. The I / O terminals can include, for example, bonding pads, bonding areas of a redistribution layer (RDL), or bonding areas of a top interconnect layer. The microelectronic device includes a dielectric layer on the die. The dielectric layer can include, for example, an organic polymer, a silicone polymer, or an inorganic dielectric material. The microelectronic device further includes pillars electrically coupled to the I / O terminals. The pillars can directly contact the I / O terminals or can be electrically coupled to the I / O pads via a conductive material. The pillars extend through the dielectric layer to the exterior of the microelectronic device. The pillars are conductive. Each pillar includes at least one pillar electrically coupled to at least one of the I / O terminals. Each pillar further includes a head contacting the at least one pillar. The head is positioned at an end of the pillar opposite the I / O terminal. The head extends laterally beyond the pillar in at least one lateral direction. The dielectric layer extends from the die to the header and laterally surrounds the pillars.In this specification, the terms "lateral" and "laterally" refer to directions parallel to the plane of the surface of the die on which the I / O terminals are located.

[0011] Furthermore, in this specification, terms such as top, over, and above should not be interpreted as limiting the position or orientation of structures or elements, but should be used to provide spatial relationships between structures or elements.

[0012] In this specification, if an element is referred to as being connected to, coupled to, located on, or in contact with another element, the element may be directly connected to, directly coupled to, directly on, or in contact with the other element, or intervening elements may be present. Furthermore, in this specification, if an element is referred to as being directly connected to, directly coupled to, directly on, or in contact with another element, there may be no other intentionally placed intervening elements. Other terms used to describe the relationship between elements should be interpreted in a similar manner, for example, between versus directly between, adjacent versus directly adjacent, etc.

[0013] Figure 1is a cross-section of an example microelectronic device. Microelectronic device 100 includes die 102. Die 102 may include at least one integrated circuit having a semiconductor substrate and interconnect regions. Alternatively, die 102 may include at least one discrete semiconductor device, such as a power transistor. Further, die 102 may include a MEMS device, such as an accelerometer. Other embodiments of die 102 are also within the scope of this example. Die 102 includes I / O terminals 104. I / O terminals 104 may be bonding pads electrically coupled to interconnects of the microelectronic device. Alternatively, I / O terminals 104 may be bonding regions of an RDL positioned above and electrically coupled to interconnects of the microelectronic device. Further, I / O terminals 104 may be bump pads in a bond-over-active (BOAC) structure of the microelectronic device. Other embodiments of I / O terminals 104 are also within the scope of this example. The dimensions of I / O terminals 104 may vary across die 102, or their dimensions may be uniform.

[0014] Microelectronic device 100 includes a dielectric layer 106 on die 102. Dielectric layer 106 may comprise, for example, an organic polymer such as epoxy, cross-linked polyisoprene, polyimide, or methacrylate. Alternatively, dielectric layer 106 may comprise a silicone polymer. Furthermore, dielectric layer 106 may comprise an inorganic dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, or aluminum oxide. Dielectric layer 106 may have a thickness 108 of, for example, 5 to 100 microns.

[0015] The microelectronic device 100 includes pillars 110 electrically coupled to the I / O terminals 104. The pillars 110 extend through the dielectric layer 106 to the exterior of the microelectronic device 100. Each pillar 110 includes a column 112 electrically coupled to one of the I / O terminals 104. Figure 1 As depicted, pillars 112 can directly contact I / O terminals 104. Alternatively, pillars 112 can be electrically coupled to I / O terminals 104 through a conductive material, such as a seed layer for an electroplating operation. Pillars 112 are electrically conductive. Pillars 112 can have, for example, a copper core laterally surrounded by a pillar liner that reduces diffusion of copper from the copper core into dielectric layer 106. Alternatively, pillars 112 can comprise other metals, such as nickel, platinum, aluminum, tungsten, or gold, or other conductive materials, such as graphene or carbon nanotubes.

[0016] Pillar 110 further includes a head 114 on pillar 112. Each of pillars 112 is contacted by at least one of heads 114, and each of heads 114 contacts at least one of pillars 112. Head 114 can directly contact pillar 112, or can contact pillar 112 through a conductive material (such as a diffusion barrier layer or a portion of a seed layer). The composition of head 114 can be similar to or different from the composition of pillar 112. I / O terminal 104 is coupled to a first end of pillar 112, and head 114 contacts a second end of pillar 112, the second end being positioned opposite the first end. Each of heads 114 extends laterally beyond pillar 112 contacted by head 114 in at least one lateral direction and possibly in a lateral direction. The column 112 and the head 114 can have any configuration and can include any material disclosed in commonly assigned patent application serial number US16 / 030,371 filed on July 9, 2018, which is incorporated herein by reference, but which is not admitted to be prior art.

[0017] The support 110 may include a barrier layer 116 on the head 114. For example, the barrier layer 116 may include nickel, palladium, platinum, titanium, tantalum, cobalt, tungsten, molybdenum, or zinc. The barrier layer 116 may advantageously reduce oxidation or contamination of the head 114.

[0018] The pillar 110 may further include a solder layer 118 on the barrier layer 116 or on the head 114 (if the barrier layer 116 is omitted). The solder layer 118 is positioned at the exterior of the microelectronic device 100. For example, the solder layer 118 may include tin, silver, bismuth, or other metals. The barrier layer 116 may advantageously reduce the formation of intermetallic compounds.

[0019] The dielectric layer 106 extends from the die 102 to the header 114 and may optionally extend further to a barrier layer 116 or a solder layer 118. Pillars 110 extend from the I / O terminals 104 through the dielectric layer 106 to the exterior of the microelectronic device 100. The dielectric layer 106 may advantageously provide support for the pillars 110 and protection for the die 102 during subsequent assembly and packaging operations.

[0020] Figures 2A to 2L is a cross-section of a microelectronic device depicted at a stage in an example formation method. Figure 2A , microelectronic device 200 includes die 202. Die 202 may be part of a semiconductor wafer or a MEMS substrate. The semiconductor wafer or MEMS substrate may contain additional dies similar to die 202 (in Figure 2A). Alternatively, die 202 may be separated from the other dies, for example as a result of singulating die 202 from a semiconductor wafer or MEMS substrate.

[0021] Die 202 includes I / O terminals 204. I / O terminals 204 may primarily comprise aluminum or copper and may have a capping layer or under-bump metallization (UBM) layer of nickel, palladium, platinum, gold, or other metals. I / O terminals 204 may be electrically coupled to components in die 202 through vias 220 or other conductive structures in die 202.

[0022] A trench material layer 222 is formed on the die 202, covering the I / O terminals 204. The trench material layer 222 may comprise a photosensitive polymer material, such as a photoresist containing polyisoprene, a photosensitive polyimide, a photosensitive epoxy resin such as SU-8, or a photoresist containing methacrylate. The trench material layer 222 may comprise an organic resin, such as polymethyl methacrylate (PMMA), which is sensitive to electron beam radiation. The trench material layer 222 may be formed, for example, by a spin coating process or by applying it as a dry film.

[0023] The trench material layer 222 is exposed to patterned radiation 224, such as ultraviolet (UV) radiation from a photolithography tool. The patterned radiation 224 has a spatial distribution that is aligned with the spatial distribution of the I / O terminals 204. In one version of this example, where the photopolymer material in the trench material layer 222 has a negative tone, the patterned radiation 224 can expose the trench material layer 222 in areas of a subsequently formed pillar trench sub-layer 226, such as Figure 2B Return to reference Figure 2A ,like Figure 2A As depicted, the patterned radiation 224 may be blocked from areas of the pillar trench 228 over the I / O terminal 204. In an alternative version of this example, where the photopolymer material in the trench material layer 222 has a positive tone, the patterned radiation 224 may expose the trench material layer 222 in the areas of the pillar trench 228 and may be blocked from areas of a subsequently formed pillar trench sub-layer 226.

[0024] refer to Figure 2B , the development operation starts from Figure 2A The trench material layer 222 is removed from the pillar trench 228 to form a pillar trench sublayer 226. The pillar trench sublayer 226 may be heated to remove volatile materials (such as solvents) and optionally increase crosslinking between polymer molecules in the pillar trench sublayer 226 to provide higher durability. The pillar trench 228 in the pillar trench sublayer 226 exposes the I / O terminal 204.

[0025] Alternatively, the laser ablation process can be used to Figure 2A The pillar trench sublayer 226 is formed by removing material from the trench material layer 222. Using a laser ablation process enables the pillar trench sublayer 226 to be formed from a wider range of materials (including materials that are not photosensitive), which can advantageously reduce the manufacturing cost of the microelectronic device 200.

[0026] refer to Figure 2C , a column liner 230 is formed on the column trench sublayer 226, the column liner extending into the column trench 228 and contacting the I / O terminal 204. The column liner 230 may include an adhesive sublayer that directly contacts the column trench sublayer 226 in the column trench 228. The adhesive sublayer may include a metal with good adhesion to the column trench sublayer 226, such as titanium or titanium tungsten, and may be formed by a sputtering process. The column liner 230 may also include a barrier sublayer that effectively reduces the diffusion of copper into the column trench sublayer 226. The barrier sublayer may include, for example, titanium nitride or tantalum nitride, and may be formed by a reactive sputtering process or an atomic layer deposition (ALD) process. The column liner 230 may include a seed layer that provides a suitable conductive surface for subsequent electroplating operations. The seed layer may include, for example, nickel or copper, and may be formed by a sputtering process or an evaporation process.

[0027] refer to Figure 2D , a column electroplating process using a column plating tank 232 is used to form a column layer 234 on the column liner 230. The column layer 234 fills the column trench 228 and extends adjacent to the column trench 228 above the column trench sublayer 226. The column layer 234 can primarily contain copper, for example, greater than 90 weight percent copper. The column layer 234 can also contain other metals, such as nickel, silver, or gold. The column plating tank 232 contains copper, for example, in the form of copper sulfate. The column plating tank 232 can contain additives, such as a leveler; a suppressor, sometimes referred to as an inhibitor; and an accelerator, sometimes referred to as a whitening agent, to provide a desired low thickness column layer 234 adjacent to the column trench 228 above the column trench sublayer 226.

[0028] refer to Figure 2E, the pillar layer 234 and the pillar liner 230 above the pillar trench sublayer 226 adjacent to the pillar trench 228 are removed, thereby leaving the pillar liner 230 and the pillar layer 234 in the pillar trench 228 to provide the pillars 212. The pillar liner 230 extends around the lateral boundaries of each pillar 212. The pillar layer 234 above the pillar trench sublayer 226 can be removed, for example, by a copper chemical mechanical polishing (CMP) process using a polishing pad and a copper removal slurry. The pillar liner 230 above the pillar trench sublayer 226 can also be removed by a copper CMP process or can be removed by a selective wet etching process. As shown in reference Figure 2C to Figure 2E The disclosed method for forming pillars 212 is sometimes referred to as a damascene process, specifically a copper damascene process.

[0029] refer to Figure 2F , a header trench sublayer 236 is formed on the pillar trench sublayer 226. The header trench sublayer 236 has a header trench 238 that exposes the top of the pillar 212. Each of the header trenches 238 extends laterally beyond the top of the pillar 212 exposed by the header trench 238 in at least one lateral direction. The composition of the header trench sublayer 236 can be similar to that of the pillar trench sublayer 226. In addition, the header trench sublayer 236 can be formed by a method similar to that described in reference to FIG. Figure 2A and Figure 2B The disclosed process sequence of steps for forming the pillar trench sub-layer 226 is used to form the header trench sub-layer 236 .

[0030] refer to Figure 2G A header liner 240 is formed on the header trench sublayer 236, extending into the header trench 238 and contacting the pillar 212. The header liner 240 may have a sublayer structure and composition similar to that of the pillar liner 230, namely, an adhesion sublayer comprising titanium or titanium tungsten, a barrier sublayer comprising titanium nitride or tantalum nitride, and a seed layer comprising nickel or copper. The sublayer of the header liner 240 may be formed by a process similar to that used to form the sublayer of the pillar liner 230, namely, a sputtering process, a reactive sputtering process or an ALD process, and a sputtering process or an evaporation process.

[0031] A header layer 244 is formed on the header liner 240 using a header electroplating process in a header plating tank 242. The header layer 244 fills the header trench 238 and extends adjacent to the header trench 238 over the header trench sublayer 236. The header layer 244 may primarily contain copper and may have a composition similar to that of the pillar layer 234. The header plating tank 242 contains copper and may contain a composition similar to that of the pillar layer 234. Figure 2DSimilar additives to the pillar plating bath 232 , ie, levelers; suppressors; and accelerators, are used to provide a desired low thickness header layer 244 adjacent to the header trench 238 above the header trench sub-layer 236 .

[0032] refer to Figure 2H The header layer 244 and the header liner 240 above the header trench sublayer 236 adjacent to the header trench 238 are removed, leaving the header liner 240 and the header layer 244 in the header trench 238 to provide the headers 214. The header liner 240 extends around the lateral boundaries of each header 214. The header layer 244 and the header liner 240 can be removed from above the header trench sublayer 236 by a copper CMP process, optionally followed by a wet etching process. The headers 214 are electrically connected to the pillars 212. The pillars 212, in combination with the headers 214, provide the pillars 210 of the microelectronic device 200. The pillar liner 230 can advantageously reduce the diffusion of copper from the pillar layer 234 into the pillar trench sublayer 226. Similarly, the header liner 240 can advantageously reduce the diffusion of copper from the header layer 244 into the header trench sublayer 236. Diffusion of copper into the pillar trench sub-layer 226 or into the header trench sub-layer 236 may reduce the reliability of the microelectronic device 200 .

[0033] refer to Figure 2I , a barrier plating process using a barrier plating tank 246 is used to form a barrier layer 216 on the head 214. The barrier layer 216 is a portion of the pillar 210. The barrier plating process may be an electroless plating process. The barrier layer 216 may have a thickness as shown in FIG. Figure 1 The barrier layer 116 of the embodiment of the present invention may have the composition disclosed herein. The barrier plating bath 246 may contain nickel in the form of nickel sulfate and may contain other metals in the form of metal salts to form the desired composition of the barrier layer 216. The barrier layer 216 is a component of the pillar 210. Other methods of forming the barrier layer 216 are also within the scope of this embodiment.

[0034] refer to Figure 2J , the barrier layer 216 is exposed to a liquid solder source 248 containing molten solder, the molten solder forming a solder layer 218 on the barrier layer 216. The solder layer 218 is part of the pillar 210. The liquid solder source 248 can be pumped onto the microelectronic device 200 to expose the barrier layer 216 to the molten solder. Alternatively, the microelectronic device 200 can be immersed in the molten solder of the liquid solder source 248 to expose the barrier layer 216 to the molten solder. The solder layer 218 can have a Figure 1 The solder layer 118 may have the disclosed composition, ie, may contain tin, silver, bismuth, or other metals. The solder layer 218 is a component of the support 210 .

[0035] refer to Figure 2K, the microelectronic device 200 is assembled onto a circuit substrate 250. For example, the circuit substrate 250 can be a printed circuit board (PCB) or a ceramic wiring substrate. The circuit substrate 250 has a conductive pad 252 positioned on an insulating layer 254. The pad 252 can be a die pad, lead, trace, wiring or other conductive component of the circuit substrate 250. The pad 252 can be primarily composed of copper and can optionally contain gold, nickel or other metals to provide a suitable surface for solder joints. The insulating layer 254 can be a fiberglass reinforced plastic (FRP) board, a ceramic substrate or other insulating medium. The microelectronic device 200 is assembled onto the circuit substrate 250 by contacting the solder layer 218 with the pad 252 and heating the solder layer 218 to form a solder connection between the pillar 210 and the pad 252.

[0036] Figure 2L The microelectronic device 200 is depicted assembled onto a circuit substrate 250. A solder layer 218 provides a solder connection between the pillars 210 and the pads 252. The combination of the pillar trench sublayer 226 and the header trench sublayer 236 provides a dielectric layer 206. The pillar trench sublayer 226 laterally surrounds the pillars 212. The header trench sublayer 236 laterally surrounds the header 214. The dielectric layer 206 of this example extends from the die 202 to the barrier layer 216, laterally surrounding the pillars 212 and the header 214. The dielectric layer 206 advantageously provides support for the pillars 210 and protects the die 202 during assembly onto the circuit substrate 250 and thereafter during use of the assembled microelectronic device 200.

[0037] Figures 3A to 3F is a cross-section of a microelectronic device depicted at a stage in another example formation method. Figure 3A , microelectronic device 300 includes die 302. Die 302 may be part of a semiconductor wafer or MEMS substrate, or may be a separate workpiece. Die 302 includes I / O terminals 304. The composition of I / O terminals 304 may be similar to that of reference Figure 2A The die 302 may include conductive members 320 that electrically couple the I / O terminals 304 to one or more components in the die 302 .

[0038] A dielectric layer 306 is formed on the die 302. The dielectric layer 306 is formed with pillar trenches 328 that expose the I / O terminals 304. The dielectric layer is further formed with one or more header trenches 338 that open into the pillar trenches 328. In this example, the header trenches 338 open into two pillar trenches 328.

[0039] like Figure 3AAs depicted in FIG, dielectric layer 306 may be formed by a first additive process that uses a binder jetting apparatus 358 to deposit dielectric material 356 on die 302 to form at least a portion of dielectric layer 306. In this specification, the additive process deposits dielectric material 356 in desired areas and does not deposit dielectric material 356 outside of desired areas, such that it is not necessary to remove a portion of deposited dielectric material 356 to produce the final desired shape of dielectric layer 306. The additive process may enable dielectric layer 306 to be formed without a photolithography process, thereby advantageously reducing manufacturing cost and complexity. Examples of additive processes suitable for forming dielectric layer 306 include binder jetting, material jetting, directed energy deposition, material extrusion, powder bed melting, sheet lamination, vat photopolymerization, direct laser deposition, electrostatic deposition, laser sintering, and photopolymerization extrusion.

[0040] In one version of this example, dielectric layer 306 may comprise an organic polymer, such as epoxy, benzocyclobutene (BCB), polyimide, or acrylic. In another version, dielectric layer 306 may comprise a silicone polymer. In further versions, dielectric layer 306 may comprise an inorganic dielectric material, such as silicon dioxide, silicon nitride, boron nitride, or aluminum oxide. The inorganic dielectric material may be implemented as particles of an inorganic material that has been sintered or has a polymer binder.

[0041] Dielectric layer 306 may be heated after disposing dielectric material 356 to remove volatile materials from dielectric layer 306 or to cross-link polymer materials in dielectric layer 306. Dielectric layer 306 may be heated, for example, by a radiant heating process, by a hot plate heating process, by an oven heating process, or by a forced air convection heating process.

[0042] refer to Figure 3B , a pillar liner 360 is formed on the dielectric layer 306, the pillar liner extending into the head trench 338 and the pillar trench 328 and contacting the I / O terminal 304. The pillar liner 360 may have a similar structure to the reference Figure 2C Pillar liner 360 may have the layer structure and composition disclosed with reference to pillar liner 230, i.e., an adhesion sublayer comprising titanium or titanium tungsten, a barrier sublayer comprising titanium nitride or tantalum nitride, and a seed layer comprising nickel or copper. Pillar liner 360 may be formed by any of the processes disclosed with reference to pillar liner 230, i.e., a sputtering process, a reactive sputtering process or an ALD process, and a sputtering process or an evaporation process.

[0043] refer to Figure 3CA pillar layer 362 is formed on the pillar liner 360, the pillar layer filling the pillar trench 328 and the head trench 338 and extending adjacent to the head trench 338 on the pillar liner 360. The pillar layer 362 can be formed by an electroplating process. The pillar layer 362 can primarily contain copper, i.e., greater than 90 weight percent copper. The pillar layer 362 can optionally contain other metals, such as nickel, silver, or gold.

[0044] refer to Figure 3D , the pillar layer 362 and the pillar liner 360 above the dielectric layer 306 adjacent to the head trench 338 are removed, thereby leaving the pillar layer 362 and the pillar liner 360 in the pillar trench 328 and the head trench 338 to provide the pillar 312 and the head 314 of the pillar 310, respectively. The pillar layer 362 and the pillar liner 360 can be removed from the dielectric layer 306 adjacent to the head trench 338, for example, by a CMP process, an etch back process, or a combination thereof. As shown in reference Figures 3B to 3D The disclosed method for forming pillar 312 and head 314 is sometimes referred to as a dual damascene process. Compared to other methods of forming pillar 310, the dual damascene process can provide reduced manufacturing cost and complexity.

[0045] refer to Figure 3E , a barrier layer 316 is formed on the head 314. If there is an additional head 314 in the microelectronic device 300, an additional barrier layer 316 is formed on the additional head. The barrier layer 316 may have a Figure 1 The barrier layer 116 may have the disclosed composition, i.e., may contain nickel, palladium, platinum, titanium, tantalum, cobalt, tungsten, molybdenum, or zinc, and may be as described in reference Figure 2I The barrier layer 216 is formed as disclosed herein. The barrier layer 316 is a component of the pillar 310, i.e., by an electroless plating process using a barrier plating bath.

[0046] A solder layer 318 is formed on the barrier layer 316. The solder layer 318 can be formed by a second additive process, such as a material extrusion process that uses a material extrusion device 366 to place solder paste 364 on the barrier layer 316. The solder layer 318 can be heated to remove volatile materials or reduce the resistance between the solder layer 318 and the barrier layer 316. The solder layer 318 is a component of the pillar 310. An additional solder layer 318 is formed on the additional barrier layer 316, if present in the microelectronic device 300.

[0047] refer to Figure 3F, the microelectronic device 300 is assembled onto the circuit substrate 350. The circuit substrate 350 has a conductive pad 352 positioned on the insulating layer 354. The microelectronic device 300 is assembled onto the circuit substrate 350 by contacting the solder layer 318 with the pad 352 and heating the solder layer 318 to form a solder connection between the pillar 310 and the pad 352. The dielectric layer 306 can provide the microelectronic device 300 with a reference Figure 2L Advantages similar to those disclosed herein may provide support for the pillars 310 and protection for the die 302 during assembly to the circuit substrate 350 and thereafter during use of the assembled microelectronic device 300 .

[0048] Figures 4A to 4F is a cross-section of a microelectronic device depicted at a stage in another example formation method. Figure 4A , microelectronic device 400 includes die 402. Die 402 may be part of a workpiece containing another device, or may be a separate workpiece containing only die 402. Die 402 includes at least one I / O terminal 404. The composition of I / O terminal 404 may be similar to that of reference Figure 2A The I / O terminals 204 may be of the disclosed composition, ie, may primarily contain aluminum or copper, and may have a capping layer or UBM layer of nickel, palladium, platinum, gold, or other metals.

[0049] A dielectric layer 406 is formed on the die 402. The dielectric layer 406 is formed with a pillar trench 428 that exposes the I / O terminal 404. The dielectric layer is further formed with a header trench 438 that leads to the pillar trench 428. The dielectric layer 406 may have additional pillar trenches (not shown) that expose additional I / O terminals (not shown) and may have additional header trenches (also not shown) that lead to additional pillar trenches. Figure 4A As depicted, at least a portion of dielectric layer 406 may be formed by a first additive process, such as a directed energy process that uses a directed energy device 458 to deposit dielectric material 456 on die 402. The directed energy process delivers dielectric material 456 to die 402 in the form of microparticles or nanoparticles via an inert gas flow and melts dielectric material 456 onto die 402 using directed thermal energy (e.g., directed thermal energy from a focused laser beam). Dielectric layer 406 may include reference Figure 3A The dielectric layer 306 may be any of the materials disclosed, i.e., may comprise an organic polymer such as epoxy, BCB, polyimide, or acrylic, may comprise a silicone polymer, or may comprise an inorganic dielectric material such as silicon dioxide, silicon nitride, boron nitride, or aluminum oxide, optionally implemented as particles of an inorganic material sintered or with a polymer binder.

[0050] refer to Figure 4B Conductive material 468 is disposed in the stem trench 428 and the head trench 438 to form at least a portion of a pillar conductor 470. The pillar conductor 470 in the stem trench 428 provides a stem 412 of a pillar 410 of the microelectronic device 400. The pillar conductor 470 in the head trench 438 provides a head 414 of the pillar 410. As Figure 4B depicted, the conductive material 468 can be disposed in the stem trench 428 and the head trench 438 by a second additive process, such as an electrostatic deposition process using an electrostatic deposition apparatus 472. Other additive processes can be used to form the stem 412 and the head 414. The conductive material 468 can include metal nanoparticles, such as copper, gold, silver, or aluminum nanoparticles. The conductive material 468 can include carbon nanotubes, graphene, or other graphitic materials. In one version of the present example, the stem 412 and the head 414 can be formed by separate additive processes using different conductive materials. The stem 412 or the head 414 can be heated to remove volatile materials, such as solvents or carrier liquids, to fuse the conductive particles of the conductive material 468 together, or to melt the metal in the conductive material 468 to form an alloy in the stem 412 or the head 414. The metal nanoparticles in the conductive material 468 can be fused or melted at a temperature that is significantly lower than the melting temperature of a bulk metal having the same composition, which can advantageously reduce thermal degradation of the microelectronic device 400.

[0051] Referring to Figure 4C , a barrier layer 416 is formed on the head 414 in the first contact region 474 and the second contact region 476. The composition of the barrier layer 416 can be similar to the composition disclosed for the barrier layer 116 of Figure 1 . As Figure 4C depicted, the barrier layer 416 can be formed by a third additive process, such as an electrochemical deposition process using an electrochemical deposition apparatus 478. The barrier layer 416 can be formed by other methods, such as sputtering a thin film of a barrier metal followed by masking and etching. The barrier layer 416 is a component of the pillar 410.

[0052] Referring to Figure 4D , on the head 414, adjacent to the barrier layer 416, a spacer layer 480 is formed. The spacer layer 480 can prevent unintended electrical contact with the head 414. The spacer layer 480 can include, for example, an organic polymeric material, a silicone polymeric material, an inorganic material, or a combination thereof. The spacer layer 480 can be formed by a third additive process, such as a photopolymerization extrusion process using a photopolymerization extrusion apparatus 482 having a monomer source 482a and an ultraviolet laser 482b. The spacer layer 480 is a component of the pillar 410.

[0053] Referring to Figure 4E, a solder layer 418 may be formed on the barrier layer 416. The solder layer 418 may be formed by a fourth additive process, such as a material extrusion process in which a solder paste 464 is placed on the barrier layer 416 using a material extrusion device 466. Figure 3E As disclosed, the solder layer 418 may be heated to remove volatile materials or to reduce the electrical resistance between the solder layer 418 and the barrier layer 416. The solder layer 418 is a component of the support 410.

[0054] refer to Figure 4F , the microelectronic device 400 is assembled onto the circuit substrate 450. The circuit substrate 450 has an insulating layer 454 and conductive pads 452a, 452b, and 452c located on the insulating layer 454. The microelectronic device 400 is assembled onto the circuit substrate 450 by contacting the solder layer 418 with the pads 452a and 452c and heating the solder layer 418 to form solder connections between the pads 452a and 452c and the pillar 410 in the first contact area 474 and the second contact area 476, respectively. The isolation layer 480 can prevent electrical contact between the pad 452b and the header 414. The dielectric layer 406 can provide a connection between the microelectronic device 400 and the reference Figure 2L Advantages similar to those disclosed herein may provide support for the pillars 410 and protection for the die 402 during assembly to the circuit substrate 450 and thereafter during use of the assembled microelectronic device 400 .

[0055] Figures 5A to 5G is a cross-section of a microelectronic device depicted at a stage in another example formation method. Figure 5A , microelectronic device 500 includes a die 502. Die 502 includes I / O terminals 504. A seed layer 584 is formed over die 502. Seed layer 584 is conductive and in electrical contact with I / O terminals 504. Seed layer 584 may include an adhesion sublayer having titanium, tungsten, or nickel directly on die 502. Seed layer 584 may include an electroplating surface sublayer having copper or nickel to provide a suitable surface for an electroplating process.

[0056] A plating mask 586 is formed over the seed layer 584. The plating mask 586 has pillar openings 588 that expose the seed layer 584 above the I / O terminals 504. The pillar openings 588 may be tapered so as to be narrower at one end of each pillar opening 588 proximal to the I / O terminals 504 and wider at an opposite end of each pillar opening 588 distal to the I / O terminals 504.

[0057] In one version of this example, the plating mask 586 may comprise an organic polymer and may be formed by forming a mask layer of the organic polymer on the seed layer 584. Pillar openings 588 may be formed in the mask layer by a laser ablation process using a scanning laser ablation device 590. After the formation of the pillar openings 588 is completed, the remaining mask layer provides the plating mask 586. Figure 5A The tapered configuration of the pillar openings 588 may advantageously provide additional process latitude for the laser ablation process.

[0058] In another version, plating mask 586 can comprise photoresist, photosensitive polyimide, or photosensitive silicone polymer and can be formed by a photolithographic operation. Forming pillar openings 588 with a tapered configuration can advantageously provide additional process latitude for the photolithographic operation. Alternatively, plating mask 586 can be formed by an additive process or a screen printing process.

[0059] refer to Figure 5B , a pillar conductor 570 is formed in the pillar opening 588 by an electroplating operation using the seed layer 584. The pillar conductor 570 may include, for example, copper, nickel, gold, silver, palladium, platinum, or tungsten. Figure 5B Pillar conductor 570 is depicted halfway through completion of the electroplating operation.

[0060] refer to Figure 5C The electroplating operation continues to complete the pillar conductor 570. The pillar conductor 570 of this example extends above and laterally beyond the pillar opening 588. The portion of the pillar conductor 570 within the pillar opening 588 provides the pillar 512 of the pillar 510 of the microelectronic device 500. The portion of the pillar conductor 570 above the electroplating mask 586 provides the head 514 of the pillar 510.

[0061] refer to Figure 5D , a barrier layer 516 is formed on the head 514. The barrier layer 516 can be formed, for example, by one or more electroplating processes using the seed layer 584, one or more electroless plating processes, by an additive process, or by sputtering a thin film of barrier metal, followed by masking and etching. The barrier layer 516 can have a thickness as shown in FIG. Figure 1 The barrier layer 116 has the disclosed composition. The barrier layer 516 is a component of the support 510.

[0062] refer to Figure 5E , remove Figure 5D504 . The plating mask 586 is removed by, for example, an ashing process using oxygen, an ozone process, a wet cleaning process using an organic solvent, or a combination thereof. After removing the plating mask 586, the seed layer 584 is removed in the areas exposed by the pillars 512, thereby leaving the seed layer 584 between the pillars 512 and the I / O terminals 504. The seed layer 584 can be removed by, for example, a plasma etching process, a wet etching process, an electrochemical etching process (sometimes referred to as a reverse plating process), or a combination thereof. The portion of the seed layer 584 between the pillars 512 and the I / O terminals 504 is a component of the pillar 510.

[0063] refer to Figure 5F , a dielectric layer 506 is formed on the die 502. The dielectric layer 506 may include a reference Figure 1 The dielectric layer 506 may be any of the dielectric materials disclosed for the dielectric layer 106 of the die 502. The dielectric layer 506 extends from the die 502 to the header 514 and may optionally extend up halfway to the side of the header 514. The dielectric layer 506 may provide the advantages disclosed with reference to the dielectric layers 106, 206, 306, and 406 of other examples herein, namely, providing support for the pillars 510 and protection for the die 502 during assembly and thereafter during use of the assembled microelectronic device 500.

[0064] Dielectric layer 506 can be formed by a compression molding process in which a dielectric material is placed on die 502 between pillars 510 and then molded into the desired configuration using compression mold plate 592. Other methods for forming dielectric layer 506, such as a spin coating process followed by an etch-back process, are also within the scope of this example.

[0065] refer to Figure 5G , the microelectronic device 500 is assembled on a circuit substrate 550. The circuit substrate 550 has an insulating layer 554 and a pad 552. The pad 552 is conductive. A solder preform 594 can be placed on the pad 552. Figure 5G As shown, the microelectronic device 500 is assembled by contacting the pillars 510 and the pads 552 with a solder preform 594. The solder preform 594 is heated to reflow the solder preform 594, thereby forming solder joints between the pillars 510 and the pads 552.

[0066] The various features of the examples disclosed herein may be combined in other manifestations of the example integrated circuit. Figures 2A to 2L 、 Figures 3A to 3F 、 Figures 4A to 4F or Figures 5A to 5F Any of the disclosed methods forms Figure 1 Similarly, by referring to Figures 2A to 2L 、 Figures 3A to 3F 、 Figures 4A to 4F or Figures 5A to 5F Any of the disclosed methods forms Figure 1 The steps disclosed with reference to the example methods for forming dielectric layer 206, 306, 406, or 506 herein can be combined with the steps disclosed with reference to other examples for forming pillars 212, 312, 412, or 512 herein, and can be further combined with the steps disclosed with reference to further examples for forming heads 214, 314, 414, or 514 herein.

[0067] The described embodiments may be modified, and other embodiments are possible, within the scope of the claims.

Claims

1. A method of forming a microelectronic device, the method comprising: obtaining a die having input / output (I / O) terminals arranged thereon; forming a dielectric layer on the die; as well as forming a pillar outside the die, the pillar extending from the I / O terminal of the die through the dielectric layer to the outside of the microelectronic device, wherein a portion of the pillar connects the pillar to a circuit substrate, the portion being located outside the microelectronic device, wherein the pillar is formed by electroplating, and forming the pillar comprises: a columnar object forming the pillar; as well as forming a header electrically coupled to the pillar at an end of the pillar opposite the I / O terminal such that the header extends laterally beyond the pillar in at least one lateral direction and such that the dielectric layer extends from the die to the header; in: forming the dielectric layer includes forming a pillar trench sublayer on the die, the pillar trench sublayer having pillar trenches exposing the I / O terminals; and Forming the column comprises: forming a pillar liner on the pillar trench sublayer, wherein the pillar liner extends into the pillar trench and contacts the I / O terminal; forming a pillar layer on the pillar liner such that the pillar layer fills the pillar trench and extends adjacent to the pillar trench over the pillar trench sublayer; and The pillar layer and the pillar liner are removed from above the pillar trench sublayer adjacent to the pillar trench. 2 . The method of claim 1 , wherein forming the pillar layer comprises an electroplating process for electroplating metal on the pillar lining.

3. The method according to claim 1 , wherein forming the pillar trench sublayer comprises: forming a trench material layer on the die, the trench material layer comprising a photosensitive polymer material; exposing the trench material layer to patterned radiation having a spatial distribution aligned with a spatial distribution of the I / O terminals; and The trench material layer is developed to form the pillar trenches.

4. The method according to claim 1, wherein: Forming the dielectric layer includes forming a head trench sublayer on the pillar trench sublayer, the head trench sublayer having a head trench exposing the pillar; and Forming the header comprises: forming a head liner on the head groove sublayer, the head liner extending into the head groove and contacting the pillar; forming a header layer on the header liner such that the header layer fills the header groove and extends adjacent to the header groove over the header groove sublayer; as well as The header layer and the header liner are removed from above the header trench sublayer adjacent the header trench. 5 . The method of claim 1 , wherein forming the dielectric layer comprises an additive process that disposes a dielectric material on the die to form at least a portion of the dielectric layer.

6. The method of claim 1 , wherein forming the pillar comprises: forming a seed layer, the seed layer being electrically coupled to the I / O terminal, the seed layer being conductive; forming an electroplating mask on the seed layer, the electroplating mask comprising pillar openings exposing the seed layer; forming the pillars in the pillar openings by an electroplating process; removing the plating mask; as well as The seed layer is removed at locations exposed by the pillars. 7 . The method of claim 6 , wherein forming the plating mask comprises forming the pillar openings using a laser ablation process. 8 . The method of claim 1 , wherein forming the pillar comprises an additive process that deposits a conductive material on the die to form at least a portion of the pillar.

9. The method of claim 1, wherein forming the dielectric layer comprises disposing a dielectric material on the die around the pillars and molding the dielectric layer using a compression molding process.

10. The method of claim 1, wherein forming the pillar further comprises forming a barrier layer on the head, the barrier layer comprising a metal selected from the group consisting of nickel, palladium, platinum, titanium, tantalum, cobalt, tungsten, molybdenum, and zinc.

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