Voltage monitoring circuit to handle voltage drift caused by negative bias temperature instability

Abstract

The voltage at the input of an electronic device is regulated by performing at least the following: receiving a monitoring voltage corresponding to a power system at a voltage monitoring circuit (210), determining at the voltage monitoring circuit whether the monitoring voltage is equal to or exceeds a monitoring threshold voltage, (204) receiving an output at the voltage monitoring circuit indicating whether an input reference voltage at a comparator circuit is different from an input feedback voltage, (218) adjusting a feedback voltage at the voltage monitoring circuit to match the input reference voltage, (204), and providing the feedback voltage from the voltage monitoring circuit to the comparator circuit (220) as an updated input feedback voltage.

Description

Background Art

[0001] Negative bias temperature instability (NBTI) is the tendency of a p-type metal oxide semiconductor (PMOS) transistor to degrade when it is negatively biased at the gate terminal relative to the rest of the transistor. The extent of the degradation caused by NBTI varies depending on the amount of stress voltage over a period of time, the temperature and duration of the waveform transition, the aging of the transistor, and the characteristics of the transistor affected by the stress (e.g., threshold voltage and drive current). NBTI can increase the required threshold voltage of the transistor gate and reduce the drive current of the transistor. Therefore, NBTI is a reliability issue for circuit-based technologies that utilize PMOS transistors, such as advanced complementary metal oxide semiconductor (CMOS) technologies.

[0002] NBTI is also a problem when dealing with long-term parameter drift of comparators and other similar electronic devices that include one or more PMOS input pairs. In particular, for comparators used to monitor voltage levels, if the PMOS input pair does not work for a period of time under substantially similar operating conditions, the electronic device will experience parameter drift at two different PMOS inputs. As the device continues to operate, the input offset voltage of the electronic device may continue to drift higher. For example, depending on different processing technologies and / or inherent device characteristics, the input offset voltage of the comparator can drift up to tens of millivolts (mV) or even hundreds of mV. If large enough, the input offset voltage can cause long-term parameter drift away from the operating specifications of the device. To address the problem, it is difficult to detect long-term parameter drift during automatic test equipment (ATE) testing and / or simulation checks. Therefore, for electronic devices, such as comparators that monitor voltage levels, minimizing long-term parameter drift from NBTI is still valuable in improving the performance of electronic devices with PMOS inputs. Summary of the invention

[0003] A simplified overview of the disclosed subject matter is presented below to provide a basic understanding of some aspects of the subject matter disclosed herein. This overview is not an exhaustive review of the technology disclosed herein. It is not intended to identify key or important elements of the present invention or to describe the scope of the present invention. Its sole purpose is to present some concepts in a simplified form as a prelude to a more detailed description discussed later.

[0004] In one embodiment, a system includes: a comparator circuit and a voltage monitoring circuit, the comparator circuit including a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the voltage monitoring circuit including a first input monitoring terminal, a second monitoring input terminal, and an output monitoring terminal, wherein the first input monitoring terminal is configured to receive a monitored voltage level, wherein the first input terminal is configured to receive a reference voltage, wherein the second monitoring input terminal is connected to the first output terminal, and the output monitoring terminal is connected to the second input terminal to form a closed-loop circuit, and wherein the second output terminal is configured to provide a comparator output indicating an operating state of the voltage monitoring circuit.

[0005] In another embodiment, a voltage monitoring circuit includes: a voltage monitoring terminal configured to receive a monitoring voltage; a first resistor including a first resistor end coupled to the voltage monitoring terminal and a second resistor end coupled to a drain node of a monitoring transistor; a second resistor including a first resistor end coupled to a source node of the monitoring transistor and an input terminal of a comparator circuit; and a monitoring transistor coupled between the first resistor and the second resistor, wherein the monitoring transistor includes a gate node coupled to an output terminal of the comparator circuit, wherein the monitoring transistor is configured to match a feedback voltage provided to the input terminal of the comparator circuit with a reference voltage obtained by the comparator circuit based on a determination that the monitoring voltage is equal to or exceeds a monitoring threshold voltage.

[0006] In yet another embodiment, a method includes: receiving a monitoring voltage corresponding to a power supply system at a voltage monitoring circuit; determining at the voltage monitoring circuit whether the monitoring voltage is equal to or exceeds a monitoring threshold voltage; receiving an output at the voltage monitoring circuit indicating whether an input reference voltage and an input feedback voltage are different at a comparator circuit; adjusting a feedback voltage to match the input reference voltage at the voltage monitoring circuit based on the output and a determination that the monitoring voltage is equal to or exceeds the monitoring threshold voltage; and providing the feedback voltage from the voltage monitoring circuit to the comparator circuit as an updated input feedback voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To describe various examples in detail, reference will now be made to the accompanying drawings, in which:

[0008] Figure 1 is a block diagram of an electronic device according to various embodiments.

[0009] Figure 2 is a schematic diagram of an embodiment of a comparator system including a voltage monitoring circuit that prevents and / or minimizes input offset voltage and / or parameter drift.

[0010] Figure 3is a voltage-current graph corresponding to a monitoring transistor located within a voltage monitoring circuit.

[0011] Figure 4 is a schematic diagram of another embodiment of a comparator system including a voltage monitoring circuit that reduces input offset voltage and / or parameter drift.

[0012] Figure 5 is a flow chart of an embodiment of a method for preventing and minimizing input offset voltage and parameter drift of an electronic device.

[0013] Although certain embodiments will be described in conjunction with the illustrative embodiments shown herein, the present invention is not limited to these embodiments. On the contrary, all alternatives, modifications and equivalents are included in the spirit and scope of the present invention as defined by the claims. In the drawings that are not drawn to scale, the same reference numerals are used throughout the specification and in the drawings for components and elements having the same structure, and primed reference numerals are used for components and elements that are similar in function and structure to those components and elements having the same non-prime reference numerals. DETAILED DESCRIPTION

[0014] Certain terms are used throughout the specification and claims to refer to specific system components. As will be understood by those skilled in the art, different parties may refer to components by different names. This document does not intend to distinguish between components that differ in name but not in function. In the present disclosure and claims, the terms "including" and "comprising" are used in an open manner and should therefore be interpreted as meaning "including, but not limited to (including)..." In addition, the term "coupled" is intended to mean an indirect or direct wired or wireless connection. Therefore, if a first device is "coupled" to a second device, the connection may be through a direct connection, or through an indirect connection via other devices and connections. The expression "based on" is intended to mean "based at least in part". Therefore, if X is based on Y, X can be a function of Y and any number of other factors. Unless explicitly defined as such, the terms "one", "an" and "the" are not intended to refer to a singular entity, but rather a general category containing a specific instance that can be used for illustration. The use of the term "one" or "an" therefore may mean any number of at least one, including "one", "one or more", "at least one" and "one or more than one". The term "or" means any alternative and any combination of said alternatives, including all alternatives, unless such alternatives are expressly indicated as mutually exclusive. The phrase "at least one of," when combined with a list of items, means a single item from the list or any combination of items in the list. The phrase does not require all of the listed items unless expressly defined as such.

[0015] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Once the above disclosure is fully understood, many changes and modifications will become apparent to those skilled in the art. The appended claims are intended to be interpreted as including all such changes and modifications.

[0016] Various example embodiments of processing input offset voltage and / or parameter drift of a comparator are disclosed herein. The electronic device may include or be coupled to a voltage monitoring circuit that reduces the voltage difference between the input terminals of the electronic device caused by different operating conditions and / or inherent device characteristics. The comparator is configured to compare a reference voltage received at a first input terminal (e.g., a non-inverting input terminal) with a feedback voltage at a second input terminal (e.g., an inverting input terminal). The feedback voltage is based on a monitoring voltage received as an input by the voltage monitoring circuit. When the voltage monitoring circuit is in a regulating operation state, the voltage monitoring circuit adjusts the feedback voltage at the second input terminal to follow the reference voltage at the first input terminal. Specifically, the voltage monitoring circuit is configured to use a closed loop to adjust the feedback voltage so as to minimize the voltage difference provided to the two input terminals. Closed-loop voltage regulation allows the voltage monitoring circuit to continuously monitor and adjust the feedback voltage provided to the second input terminal so as to offset parameter drift and / or changes in the input offset voltage at the two input terminals. When the voltage monitoring circuit obtains a monitoring voltage that is equal to and / or exceeds a set monitoring threshold, the voltage monitoring circuit is in a regulating operation state. In one embodiment, the voltage monitoring circuit includes a monitoring transistor coupled to two resistors, wherein one resistor is coupled to a drain node of the monitoring transistor and the other resistor is coupled to a source node of the monitoring transistor. A monitoring threshold is set based on a reference voltage provided at a first terminal and resistance values ​​of the two resistors.

[0017] Figure 1 is a block diagram of an electronic device 100 according to various embodiments. As an example, the electronic device 100 may be a comparator, wherein the input terminal 110A represents a non-inverting input terminal, and the input terminal 110B represents an inverting input terminal 110B. Alternatively, in other embodiments of the electronic device 100, the input terminal 110A represents an inverting input terminal, and the input terminal 110B represents a non-inverting input terminal. As a comparator, the electronic device 100 is configured to compare two voltages or currents received at the input terminals 110A and 110B, and generate an output electrical signal (e.g., analog or digital) based on the comparison between the two input terminals. For example, the comparator may generate an output signal representing a zero value or a one value based on the voltage and / or current at the input terminals 110A and 110B. In Figure 1 In the embodiment, the electronic device 100 is configured to compare the monitored voltage with a reference voltage, wherein the reference voltage is either generated within the electronic device 100 or provided to the electronic device 100 from the outside.

[0018] like Figure 1 As shown, the electronic device 100 includes a differential amplifier circuit 102, a voltage monitoring circuit 104, a voltage amplifier circuit 106, and a voltage output circuit 108 to compare a monitored voltage (e.g., a voltage from a battery) with a reference voltage. The differential amplifier circuit 102 receives an input voltage at two different input terminals 110A and 110B of the electronic device 100. When the differential amplifier circuit 102 receives an input voltage at the input terminals 110A and 110B, the voltage difference detected at the input terminals 110A and 110B causes a differential current within the differential amplifier circuit 102 to rise. The differential amplifier circuit 102 can convert the rise of the differential current to generate one or more differential amplifier circuit outputs (e.g., a single-ended output and / or a differential output). Figure 4 , which uses p-type transistors for input terminals 110A and 110B. Other embodiments of electronic device 100 may utilize other differential amplifier circuit designs based on various design considerations including, but not limited to, balancing processing speed and power tradeoffs, improving input impedance and / or gain, reducing noise and / or device size, and / or minimizing operational defects.

[0019] The differential amplifier circuit 102 also generates a monitoring output voltage to the voltage monitoring circuit 104. The voltage monitoring circuit 104 also receives a monitoring voltage as an input at the Vmonitor terminal 114 from a monitored power source (e.g., a battery and / or some other charging power source), a power distribution line, a power circuit, and / or other types of power systems that provide a specified voltage level. The monitored power system may be directly connected to the voltage monitoring circuit 104 or indirectly coupled to the voltage monitoring circuit 104. Recall that due to temperature effects and other instabilities originating from inherent device characteristics, the electronic device 100 may suffer from offset voltage and / or long-term parameter drift problems caused by different operating conditions at the input terminal 110. For example, when the differential amplifier circuit 102 utilizes a PMOS input pair, the electronic device 100 may suffer from long-term parameter drift caused by NBT at either of the two input terminals 110A and 110B. The offset voltage and / or long-term parameter drift problem may then unexpectedly result in a considerable voltage difference between the two input terminals 110A and 110B.

[0020] When the voltage monitoring circuit 104 receives a monitored voltage at the Vmonitor terminal 114 that exceeds a set monitoring threshold, the voltage monitoring circuit 104 is in a regulation monitoring state and uses the differential amplifier circuit output to prevent and / or minimize the voltage difference at the two input terminals 110A and 110B to generate a feedback output. To compensate for these offset and drift issues, the voltage monitoring circuit 104 utilizes a closed loop to adjust the voltage at the input terminal 110B to closely match and follow the reference voltage level provided to the input terminal 110A. Figure 1 As shown in , the closed loop involves the voltage monitoring circuit 104 receiving the differential amplifier circuit output and generating a feedback output to the input terminal 110B based on the differential output. In the event that the monitored voltage provided at the Vmonitor terminal 114 is less than the set monitoring threshold, the voltage monitoring circuit 104 transitions to the on operating state and stops matching the voltage at the input terminal 110B to the reference voltage. Transitioning the voltage monitoring circuit 104 to the on operating state also causes the differential amplifier circuit 102 to detect the voltage and / or current difference between the two input terminals 110A and 110B. The voltage monitoring circuit 104 Figure 2-4 Discussed in more detail in .

[0021] The voltage amplifier circuit 106 receives the differential amplifier circuit output and generates a voltage gain circuit output to provide to the voltage output circuit 108. In other words, the voltage amplifier circuit 106 is configured to increase the voltage gain of the received differential output. Based on the voltage gain circuit output, the voltage output circuit 108 generates an output at the output terminal 112. Figure 1 As an example, the voltage output circuit 108 may generate a relatively low output to indicate that the monitored voltage provided to the Vmonitor terminal 114 is less than the set monitoring threshold. Conversely, the voltage output circuit 108 may generate a relatively high output to indicate that the monitored voltage provided to the Vmonitor terminal 114 is equal to or greater than the set monitoring threshold. Other embodiments of the voltage output circuit 108 may be configured in the opposite manner, wherein a relatively high output indicates that the monitored voltage provided at the Vmonitor terminal 114 is less than the set monitoring threshold, while a relatively low output indicates that the monitored voltage provided at the Vmonitor terminal 114 is equal to or greater than the set monitoring threshold.

[0022] although Figure 1 A specific embodiment of the electronic device 100 is shown for monitoring a monitoring voltage and comparing the monitoring voltage with a reference voltage, but the present disclosure is not limited to Figure 1 For example, although Figure 1The electronic device 100 is shown to include a differential amplifier circuit 102, a voltage monitoring circuit 104, a voltage amplifier circuit 106, and a voltage output circuit 108, but the electronic device 100 may also include other components commonly found in comparators and known to those of ordinary skill in the art. In addition, other embodiments of the electronic device 100 may combine one or more components into a single component. Figure 1 The use and discussion of are merely examples for ease of description and explanation.

[0023] Figure 2 is a schematic diagram of an embodiment of a comparator system 200 including a voltage monitoring circuit 210 that minimizes the effects of input offset voltage and / or parameter drift at input terminals 212 and 214. In one embodiment, the comparator system 200 corresponds to Figure 1 The electronic device 100 shown is or is a part of the electronic device 100 . Figure 2 The comparator system 200 is shown to include a comparator circuit 202 and a voltage monitoring circuit 210. The comparator circuit 202 includes a non-inverting input terminal 212 and an inverting input terminal 214. The non-inverting input terminal 212 receives a reference voltage (eg, provided internally or externally by the comparator circuit 202), which is Figure 2 The inverting input terminal 214 receives the feedback voltage, which is marked as Vref in Figure 2 The comparator circuit 202 generates an output voltage at the output terminal 216 of the comparator system 200, which is described as "div_open". Figure 2 and generates a monitoring gate voltage (at the monitoring terminal 218) Figure 2 The output voltage CompOut at the output terminal 216 changes as the monitoring circuit 210 transitions between the regulation operating state and the on operating state. Figure 2 Also depicted is the comparator circuit receiving the Figure 2 The supply voltage marked as "Vcc" in the figure.

[0024] The voltage monitoring circuit 210 includes a monitoring voltage terminal 224, a voltage monitoring input terminal 222, and a feedback output terminal 220. The monitoring voltage terminal 224 receives the monitoring voltage Vmonior by being directly connected to and / or indirectly coupled to a power supply, a power distribution line, a power supply circuit, and / or any other type of system that provides a specified voltage level. The voltage monitoring input terminal 222 connected to the gate node of the monitoring transistor 204 is connected to the monitoring terminal 218 and receives the monitoring gate voltage from the comparator circuit 202. The feedback output terminal 220 is connected to the inverting terminal 214 to form a closed-loop circuit between the comparator circuit 202 and the voltage monitoring circuit 210. Other embodiments of the comparator system 200 may have a voltage monitoring circuit 210 connected to a non-inverting terminal 212, and a reference voltage Vref is provided to the inverting terminal 214.

[0025] Figure 2 The voltage monitoring circuit is also shown to include a monitoring transistor 204, whose drain node is coupled to a resistor 206 and whose source node is coupled to a resistor 208. The monitoring transistor 204 can be implemented using various different types of electronic switches, such as field effect transistors (FETs). For example, the monitoring transistor 204 can be an enhancement mode n-channel metal oxide semiconductor field effect (NMOS) transistor. Alternatively, the monitoring transistor 204 can be other types of electronic switches, including other types of NMOS transistors, n-type junction gate field effect transistors (NJFETs), and bipolar junction transistors (BJTs), such as NPN transistors. Resistors 206 and 208 can also be implemented using various different types of resistors. Examples of resistors include, but are not limited to, carbon composition resistors and semiconductor resistors (e.g., surface mount resistors). Additionally or alternatively, it is understood by those skilled in the art that the voltage monitoring circuit 210 can use other types of electronic components (e.g., FETs operating in the triode region) instead of resistor components to set the resistance value of resistors 206 and / or 208.

[0026] exist Figure 2 In the embodiment, the voltage monitoring circuit 210 receives the monitoring voltage at the monitoring voltage terminal 224 (at Figure 2 The voltage monitoring circuit 210 is a circuit that generates a voltage monitor (labeled as "Vmonitor") and determines whether the monitored voltage exceeds a certain monitoring threshold. The monitored voltage may be provided directly or indirectly by a power system such as a battery. The voltage monitoring circuit 210 sets the monitoring threshold based on the resistance values ​​of resistors 206 and 208 and a reference voltage provided at a non-inverting input terminal 212. Equation 1 given below represents an expression for defining the monitoring threshold.

[0027] Vthreshold=Vref((R0+R1) / R1) (1)

[0028] In Equation 1 shown above, Vthreshold represents a monitoring threshold for the voltage monitoring circuit 210 ; Vref represents a reference voltage received at the non-inverting input terminal 212 ; R0 represents a resistance value of the resistor 206 ; and R1 represents a resistance value of the resistor 208 .

[0029] When Vmonitor is less than the monitoring threshold, the voltage monitoring circuit 210 is in the on-operation state, wherein the monitoring transistor 204 operates in the linear region. At this point in time, the monitoring transistor 204 is fully turned on and acts as a closed switch. Based on the closed-loop circuit, the monitoring gate voltage (which is the voltage to the gate node of the monitoring transistor 204) reaches the power supply voltage Vcc to fully turn on the monitoring transistor 204. During the on-operation state, the source voltage and the drain voltage of the monitoring transistor 204 are almost equal, and there is almost no voltage drop on the drain-source node of the monitoring transistor 204. The voltage drop of the resistor 206 is shown in the following equation 2, and the voltage drop of the resistor 208 is shown in the following equation 3.

[0030] Vdrop(R0)=Vmonitor(R0 / (R0+R1)) (2)

[0031] Vdrop(R1)=Vmonitor(R1 / (R0+R1)) (3)

[0032] In the above equations 2 and 3, Vdrop(R0) represents the voltage drop at the resistor 206 in the on-operation state; Vdrop(R1) represents the voltage drop at the resistor 208 in the on-operation state; Vmonitor represents the monitoring voltage at the monitoring voltage terminal 224; R0 represents the resistance value of the resistor 206; and R1 represents the resistance value of the resistor 208. The current flowing through the monitoring transistor 204 is given in the following equation 4.

[0033] Ids(monitoring transistor 204)=Vmonitor / (R0+R1) (4)

[0034] In Equation 4, Ids(monitoring transistor 204) represents the drain-to-source current of the monitoring transistor 204; Vmonitor represents the monitoring voltage at the monitoring voltage terminal 224; R0 represents the resistance value of the resistor 206; and R1 represents the resistance value of the resistor 208. Based on Equation 4, the voltage supplied to the inverting terminal 214 is expressed in the following Equation 5.

[0035] Vmonitor*R1 / (R0+R1) (5)

[0036] Consistent with Equations 2-4, Vmonitor represents the monitored voltage at the monitoring voltage terminal 224; R0 represents the resistance value of the resistor 206; and R1 represents the resistance value of the resistor 208. Because Vmonitor is less than the monitoring threshold as defined in Equation 1, the voltage provided to the inverting terminal 214 is less than the reference voltage Vref. In other words, during the on-state of operation, the closed-loop circuit cannot increase the voltage provided to the inverting terminal 214 to reach the reference voltage Vref.

[0037] When it is determined that the monitoring voltage Vmonitor is equal to or higher than the monitoring threshold, the monitoring circuit 210 is in a regulating operation state. In the regulating operation state, the monitoring transistor 204 operates in a saturation region. The amount of current flowing through the monitoring transistor 204 can be estimated by Equation 2.

[0038] Ids(monitoring transistor 204)=Vref / R1 (6)

[0039] In Equation 6 shown above, Ids(monitoring transistor 204) represents the drain-to-source current of the monitoring transistor 204; Vref represents the reference voltage received at the non-inverting input terminal 212; and R1 represents the resistance value of the resistor 208. When the monitoring circuit 210 is in a regulating operation state, the resistors 206 and 208 divide the monitoring voltage to generate a feedback voltage, which is set to follow the reference voltage due to the closed-loop circuit. Specifically, the voltage drops at the resistors 206 and 208 are shown in the following equations 7 and 8, respectively, and the voltage drop at the drain-source node of the monitoring transistor is provided in the following equation 9.

[0040] Vdrop(R0)=Vref(R0 / R1) (7)

[0041] Vdrop(R1)=Vref (8)

[0042] Vdrop(source-drain)=Vmonitor-Vref*((R0+R1) / R1) (9)

[0043] In equations 7-9 shown above, Vdrop(R0) represents the voltage drop at resistor 206 in the regulation operation state; Vdrop(R1) represents the voltage drop at resistor 208 in the regulation operation state; Vdrop(source-drain) represents the voltage drop at the source node and the drain node at the monitoring transistor 204; Vref represents the reference voltage received at the non-inverting input terminal 212; Vmonitor represents the monitoring voltage at the monitoring voltage terminal 224; R0 represents the resistance value of resistor 206; and R1 represents the resistance value of resistor 208.

[0044] like Figure 2 As shown, the feedback output terminal 220 provides the feedback voltage div_open as an input voltage to the comparator circuit 202 on the inverting terminal 214. Specifically, the source node of the monitoring transistor 204 is coupled to the inverting input terminal 214. In addition, when the monitoring voltage Vmonitor is equal to or greater than the monitoring threshold, the monitoring gate voltage received at the voltage monitoring input terminal 222 drops from the power supply voltage Vcc to a lower voltage estimated as shown in Equation 10 below.

[0045] Vgate=Vref+Vgs (10)

[0046] In Equation 10, Vgate represents a monitoring gate voltage supplied to a gate node of the monitoring transistor 204 , Vref represents a voltage value of a reference voltage, and Vgs represents a voltage difference between the monitoring gate voltage and a voltage at a source node of the monitoring transistor 204 .

[0047] Figure 3 is a voltage-current graph 300 corresponding to a monitoring transistor located within a voltage monitoring circuit. Figure 2 and 4 The voltage-current graph 300 controls and regulates the voltage at one of the input terminals of the comparator circuit (shown as the monitoring transistor 204). The voltage-current graph 300 includes a plurality of voltage curves 302 and 304, and a current curve 306 related to the operation of the monitoring transistor. Specifically, the voltage-current graph 300 depicts a monitoring gate voltage (Vgate) provided to the gate node of the monitoring transistor (e.g., Figure 2 The relationship between the monitoring terminal 218 in the figure), the feedback voltage (div_open), the drain-source current (Ids) and the monitoring voltage Vmonitor. Figure 3 It is shown that once the monitoring voltage exceeds the monitoring threshold, which is defined as "Vref(R0+R1) / R1" in the above equation 1, the monitoring transistor operates in the saturation region.

[0048] The voltage-current graph 300 shows the transition of the monitoring transistor from the linear region to the saturation region. Figure 31, when the monitoring transistor initially operates in the linear region, the voltage monitoring circuit is in the on-operation state until the monitoring voltage Vmonitor on the x-axis 308 reaches the monitoring threshold specified in Equation 1. During the on-operation state, the gate node voltage curve 302 illustrates that the monitoring gate voltage for the monitoring transistor is driven to Vcc. Since the monitoring transistor is fully turned on without a voltage difference between its source node and drain node, the feedback voltage curve 304 has a div_open that starts at about zero volts and gradually increases as the monitoring voltage Vmonitor increases. The Ids curve 306 of the monitoring transistor also initially starts at about zero volts and gradually increases as the monitoring voltage Vmonitor increases and as the monitoring transistor approaches the saturation region.

[0049] exist Figure 3 , when the monitoring voltage Vmonitor on the x-axis 308 is equal to or exceeds the monitoring threshold, the monitoring transistor enters the saturation region. When in the saturation region, the voltage monitoring circuit transitions to the regulation operation phase. The Ids curve 306 shows that the Ids current of the monitoring transistor reaches saturation at a value determined according to Equation 6. The feedback voltage curve 304 illustrates that the feedback voltage div_open reaches the reference voltage Vref. For the gate node voltage curve 302, the monitoring gate voltage drops from Vcc to a lower voltage value shown in Equation 10.

[0050] Figure 4 is a schematic diagram of another embodiment of a comparator system 400 including a voltage monitoring circuit that reduces input offset voltage and / or parameter drift. Figure 1 , the comparator system 400 can represent Figure 1 The electronic device 100 shown is or Figure 1 A portion of electronic device 100 is shown. Figure 4 The comparator system 400 is shown to include a differential amplifier circuit 402 coupled to the voltage monitoring circuit 210 and a voltage amplifier circuit 408. The differential amplifier circuit 402 is Figure 1 1 is an example embodiment of a differential amplifier circuit 102 shown. Differential amplifier circuit 402 includes p-type transistors 412, 414, and 422 and n-type transistors 416, 418, and 420. In one or more embodiments, p-type transistors 412, 414, and / or 422 may be any type of p-type FET, such as a PMOS transistor, a p-type junction gate field effect transistor (PJFET), and / or a PNP BJT. N-type transistors 416, 418, and 420 may be any type of n-type FET, such as an NMOS transistor, an NJFET, and an NPN BJT. Figure 4, the two input terminals to the differential amplifier circuit 402 are connected to p-type transistors 412 and 414 .

[0051] exist Figure 4 , the differential amplifier circuit 402 generates a voltage monitoring output, also referred to in the present disclosure as a monitoring gate voltage, to be provided as an input to the voltage monitoring circuit 210. The differential amplifier circuit 402 receives the Vref voltage at the p-type transistor 414 and the feedback voltage div_open at the p-type transistor 412. When the p-type transistor 412 receives the feedback voltage div_open that is less than the Vref voltage, the p-type transistor 414 conducts an additional current, which passes through the p-type transistor 412 and further causes the n-type transistors 416 and 418 to conduct. With the n-type transistor 418 further conducting, the n-type transistor 420 is non-conducting, thereby causing the p-type transistor 422 to also be non-conducting. With the p-type transistor 422 non-conducting within the differential amplifier circuit 402, the voltage source (e.g., Vcc) biases the circuit 404 so that the monitoring gate voltage of the gate node of the monitoring transistor 204 reaches a higher voltage level.

[0052] In review, the voltage monitoring circuit 210 is in a regulating operating state when the monitoring voltage Vmonitor is equal to or greater than the monitoring threshold, and is in an on operating state when the monitoring voltage Vmonitor is less than the monitoring threshold. Placing the voltage monitoring circuit 210 in the regulating operating state allows the feedback voltage div_open provided at one of the input terminals of the differential amplifier 402 to closely match and follow the voltage Vref provided at the other input terminal. When the voltage monitoring circuit 210 is in the regulating operating state, allowing the voltage source bias circuit 404 to make the monitoring gate voltage higher causes the feedback voltage div_open to increase. Since the feedback voltage is initially lower than the reference voltage, the voltage monitoring circuit 210 causes the feedback voltage to increase to better match the reference voltage Vref. The feedback voltage is then sent back to the gate node of the p-type transistor 412 to allow the differential amplifier circuit 402 to further evaluate the voltage difference between the reference voltage and the feedback voltage. When the voltage monitoring circuit 210 is in the on operating state, the voltage source bias circuit 404 causes the monitoring gate voltage of the gate node to reach the power supply voltage Vcc.

[0053] Figure 4 Also shown is a differential amplifier 402 that generates an output corresponding to the comparator system 400 (in Figure 4 The second output signal (shown as "CompOut") in FIG. Figure 4, the second output signal from the differential amplifier 402 is sent to the voltage amplifier circuit 408, which then sends the voltage gain circuit output to the voltage output circuit 410 to generate the output CompOut of the comparator system. The voltage source bias circuit 404 is connected to the drain node of the n-type transistor 420, where the connection point provides the second output signal. When the voltage monitoring circuit 210 is in the on operating state, the feedback voltage div_open is at a relatively low voltage and is less than the reference voltage. As previously described, when the feedback voltage is less than the reference voltage, the n-type transistor 420 is not turned on, which causes the second output signal to be a relatively high voltage. When the voltage monitoring circuit 210 is in the regulating operating state, the n-type transistor 420 is turned on to a greater extent, which causes the second output signal to be a relatively low voltage. Although Figure 4 The comparator system 400 is shown generating a single output signal “CompOut,” but other embodiments may cause the comparator system 400 to generate more than one output signal (eg, two differential outputs).

[0054] The voltage amplifier circuit 408 includes transistors 422, 424, and 426. The source node of the p-type transistor 424 receives the second output signal from the differential amplifier 402, and compares the voltage level of the second output signal with the Vref2 voltage level located between the source node of the p-type transistor 426 and the drain node of the p-type transistor 422. When the voltage monitoring circuit 210 is in the on operation state, the second output signal has a voltage level greater than the Vref2 voltage level. In this case, the voltage gain circuit output will be a relatively high voltage. When the voltage monitoring circuit 210 is in the regulating operation state, the second output signal has a voltage level less than the Vref2 voltage level. When this occurs, the voltage gain circuit output will be a relatively low voltage. In order to generate a relatively low voltage for the voltage gain circuit output, the comparator system 400 includes a ground bias circuit 406.

[0055] The voltage output circuit 410 generates the output CompOut of the comparator system based on the voltage gain circuit output received from the voltage gain circuit 408. Figure 4, the voltage output circuit 410 includes a p-type transistor 428 and an n-type transistor 430 to form a CMOS output driver circuit. When the voltage gain circuit output is a relatively low voltage, the voltage output circuit 410 generates a relatively high output value (e.g., a logic 1 output) and when the voltage gain circuit output is a relatively high voltage, a relatively low output value (e.g., a logic 0 output) is generated. In other words, the output CompOut of the comparator system is set to generate a relatively low output value when the monitoring voltage Vmonitor is less than the monitoring threshold, and a relatively high output value when the monitoring voltage Vmonitor is equal to or greater than the monitoring threshold.

[0056] Figure 5 is a flow chart of an embodiment of a method 500 for preventing and minimizing the effects of input offset voltage and parameter drift of an electronic device. Figure 2 and 4 As an example, the method 500 may be implemented using the comparator systems 200 and 400, respectively. In one or more embodiments, the method 500 is specifically implemented within the voltage monitoring circuit 210. Figure 5 The blocks of method 500 are shown to be implemented in sequential operations, but method 500 is not limited to this order of operations, but other embodiments of method 500 may have one or more blocks implemented in parallel operations. For example, blocks 504 and 506 may be implemented sequentially or in parallel.

[0057] The method 500 begins at block 502 and sets a monitoring threshold voltage of a startup voltage monitoring circuit. In one embodiment, as referenced in Equation 1, the monitoring threshold voltage is based on a reference voltage and two resistance values. One of the resistance values ​​corresponds to a resistor connected to a drain node of a monitoring transistor, and the second resistance value corresponds to a resistor connected to a source node of the monitoring transistor. Then, the method 500 proceeds to block 504 and obtains a monitoring voltage from a power system such as a battery. The method 500 continues to block 506 to determine whether the monitored voltage is equal to the monitoring threshold voltage or exceeds the monitoring threshold voltage. In one embodiment, the method 500 compares the monitored voltage with the monitoring threshold voltage to determine whether the voltage monitoring circuit is in a regulating operation state or in an on operation. In the regulating operation state, the method 500 can adjust the voltage received at the differential amplifier circuit to match the reference voltage Vref. In contrast, in the on operation state, the method 500 may not be able to adjust the voltage received at the differential amplifier circuit to match the reference voltage Vref.

[0058] The method 500 continues to block 508 and receives an output from the differential amplifier circuit based on the input reference voltage level and the input feedback voltage level. The output is based on the difference detected between the input reference voltage level and the feedback voltage level. For example, the method 500 may receive a relatively high output value (e.g., a Vcc voltage) when the feedback voltage level is less than the input reference voltage and receive a relatively low output value (e.g., Vref+Vgs (Equation 10)) when the feedback voltage is equal to or greater than the input reference voltage. The method 500 then proceeds to block 510 and adjusts the feedback voltage based on the differential output and a determination that the monitoring voltage exceeds the monitoring threshold voltage. As an example, when the feedback voltage is less than the reference voltage, the method 500 increases the feedback voltage to closely match the reference voltage. When the feedback voltage is greater than the reference voltage, the method 500 decreases the feedback voltage to closely match the reference voltage. If the monitoring voltage does not exceed the monitoring threshold, the method 500 may not adjust the feedback voltage. The method 500 then proceeds to block 512 and returns the adjusted feedback voltage to one of the input terminals of the differential amplifier circuit for further comparison.

[0059] At least one embodiment is disclosed, and variations, combinations and / or modifications of the embodiments and / or features of the embodiments made by those of ordinary skill in the art are within the scope of the present disclosure. Alternative embodiments resulting from combining, integrating and / or omitting features of the embodiments are also within the scope of the present invention. Where a numerical range or limitation is explicitly stated, such an expression range or limitation may be understood to include iterative ranges or limitations of similar magnitude that fall within the explicitly stated range or limitation (e.g., about 1 to about 10 includes 2, 3, 4, etc.; greater than 0.10 includes 0.11, 0.12, 0.13, etc.). Unless otherwise noted, the use of the term "about" refers to ±10% of the number that follows.

[0060] Although several embodiments have been provided in the present disclosure, it should be understood that the disclosed systems and methods may be implemented in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are considered to be illustrative rather than restrictive, and the invention is not limited to the details given herein. For example, various elements or components may be combined or integrated in another system, or certain features may be omitted or not implemented.

[0061] In addition, without departing from the scope of the present disclosure, the techniques, systems, subsystems and methods described and illustrated as discrete or separate in various embodiments may be combined or integrated with other systems, modules, techniques or methods. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicated through some interface, device or intermediate component (whether electrically, mechanically or otherwise).

Claims

1. A voltage monitoring system, comprising: a comparator circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal; as well as a voltage monitoring circuit having a first input monitoring terminal, a second monitoring input terminal and an output monitoring terminal; The first input monitoring terminal is a monitored voltage level input, The first input terminal is a reference voltage input. The second monitoring input terminal is connected to the first output terminal, and the output monitoring terminal is connected to the second input terminal to form a closed loop; and The second output terminal is configured to provide a comparator output indicating an operating state of the voltage monitoring circuit, wherein the comparator output is an output signal representing a zero value or a one value generated according to voltages and / or currents at the first input terminal and the second input terminal.

2. The voltage monitoring system of claim 1 , wherein the voltage monitoring circuit comprises a first resistor connected to a drain of a monitoring transistor and a second resistor connected to a source of the monitoring transistor, and the first resistor is connected to the first input monitoring terminal, and the output monitoring terminal is located between the monitoring transistor and the second resistor. 3 . The voltage monitoring system of claim 2 , wherein the second monitoring input terminal is connected to a gate of the monitoring transistor. 4 . The voltage monitoring system according to claim 3 , wherein a monitoring threshold is set based on a resistance value of the first resistor, a resistance value of the second resistor, and the reference voltage.

5. The voltage monitoring system of claim 2, wherein the monitoring transistor is an n-type transistor. 6 . The voltage monitoring system of claim 1 , wherein when the monitored voltage level is less than a monitoring threshold of the voltage monitoring circuit, the voltage monitoring circuit sets the voltage level of the second input terminal to be less than the reference voltage.

7. The voltage monitoring system of claim 1, wherein when the monitored voltage level is greater than or equal to a monitoring threshold of the voltage monitoring circuit, the voltage monitoring circuit adjusts the voltage level of the second input terminal to set it to the reference voltage. 8 . The voltage monitoring system of claim 1 , wherein the first input terminal is a non-inverting terminal and the second input terminal is an inverting terminal.

9. The voltage monitoring system of claim 1 , wherein the comparator circuit comprises a differential amplifier circuit having a first output connected to the first output terminal and a second output coupled to the second output terminal, the first output and the second output being connected to a voltage source bias circuit.

10. The voltage monitoring system of claim 9, wherein the comparator circuit comprises an inverter output coupled between the second output and the second output terminal.

11. A voltage monitoring circuit, comprising: a voltage monitoring terminal configured to receive a monitoring voltage; a first resistor including a first resistor end coupled to the voltage monitoring terminal and a second resistor end coupled to a drain node of the monitoring transistor; a second resistor including a first resistor end coupled to a source node of the monitor transistor and an input terminal of a comparator circuit and a second resistor end coupled to ground; as well as a monitoring transistor coupled between the first resistor and the second resistor, wherein the monitoring transistor includes a gate node coupled to an output terminal of the comparator circuit, Wherein the monitoring transistor is configured to match a feedback voltage provided to the input terminal of the comparator circuit with a reference voltage obtained by the comparator circuit based on a determination that the monitoring voltage equals or exceeds a monitoring threshold voltage. 12 . The voltage monitoring circuit of claim 11 , wherein the monitoring threshold voltage is based on a resistance value of the first resistor, a resistance value of the second resistor, and the reference voltage.

13. The voltage monitoring circuit of claim 11, wherein the monitoring transistor is configured to set the feedback voltage provided to the input terminal of the comparator circuit to be less than the reference voltage based on the determination that the monitoring voltage is less than the monitoring threshold voltage.

14. The voltage monitoring circuit of claim 13, wherein the monitoring transistor receives a relatively higher gate voltage at the gate node when the monitoring voltage is less than the monitoring threshold voltage compared to when the monitoring voltage is greater than the monitoring threshold voltage.

15. The voltage monitoring circuit of claim 11, wherein the monitoring transistor is an n-type transistor.

16. A voltage monitoring method, comprising: receiving, at a voltage monitoring circuit, a monitoring voltage corresponding to the power system; determining at the voltage monitoring circuit whether the monitoring voltage is equal to a monitoring threshold voltage or exceeds the monitoring threshold voltage; receiving at the voltage monitoring circuit an output indicating whether an input reference voltage and an input feedback voltage at a comparator circuit are different; adjusting a feedback voltage at the voltage monitoring circuit to match a reference voltage of the input based on the output and a determination that the monitored voltage equals or exceeds the monitoring threshold voltage; as well as The feedback voltage is provided from the voltage monitoring circuit as an updated input feedback voltage for the comparator circuit.

17. The voltage monitoring method according to claim 16, further comprising: Based on a determination that the monitored voltage is less than the monitoring threshold voltage, the feedback voltage is set at the voltage monitoring circuit to be less than a reference voltage of the input.

18. The voltage monitoring method of claim 16, wherein the monitoring threshold voltage is based on a resistance value of a first resistor within the voltage monitoring circuit, a resistance value of a second resistor within the voltage monitoring circuit, and a reference voltage of the input.

19. The voltage monitoring method according to claim 16, further comprising: A relatively higher output gate voltage is received at the voltage monitoring circuit from the comparator circuit when the monitoring voltage is less than the monitoring threshold voltage compared to when the monitoring voltage is greater than the monitoring threshold voltage.

20. The voltage monitoring method according to claim 16, further comprising: When the monitoring voltage is equal to or greater than the monitoring threshold voltage, a relatively high comparator output is generated.

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