Method for forming pattern and method for manufacturing semiconductor device using the same

Abstract

The present application provides a method for forming a pattern and a method for manufacturing a semiconductor device using the method. A first mask layer and a second mask layer are formed on a target layer. The second mask layer is patterned to form a second mask pattern, each of which has a rhombus shape, and the rhombus shape has a first diagonal line and a second diagonal line. The second mask pattern is trimmed by etching to form a second mask. The first portion of the relative first vertices of each second mask pattern is etched more than the second portion of the relative second vertices of each second mask pattern. The length of the first diagonal line between the relative first vertices is greater than the length of the second diagonal line between the relative second vertices. The first mask layer is patterned to form a first mask by etching the first mask layer using the second mask as an etching mask. The target layer is patterned to form a target pattern by etching the target layer using the first mask as an etching mask.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0001697 filed on January 7, 2019 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Example embodiments relate to a method of forming a pattern and a method of manufacturing a semiconductor device using the same. Background Art

[0004] In manufacturing a semiconductor device, a bit line and a conductive layer having a landing pad between the bit lines may be formed on a substrate. However, as the integration of semiconductor devices increases, the landing pad is formed with less process margin and the reliability of the semiconductor device may be reduced. Summary of the invention

[0005] According to an exemplary embodiment of the inventive concept, a method for forming a pattern is provided. A first mask layer is formed on a target layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a second mask pattern, each second mask pattern having a rhombus shape, the rhombus shape having a first diagonal line and a second diagonal line, the length of the second diagonal line being less than the length of the first diagonal line. A trimming process is performed on the second mask pattern to form a second mask. A first portion corresponding to the first vertex opposite to each second mask pattern is etched more than a second portion corresponding to the second vertex opposite to each second mask pattern. The length of the first diagonal line between the first vertices opposite to each other is greater than the length of the second diagonal line between the second vertices opposite to each other. The first mask layer is patterned to form a first mask by performing an etching process on the first mask layer using the second mask as an etching mask. The target layer is patterned to form a target pattern by performing an etching process on the target layer using the first mask as an etching mask.

[0006] According to an exemplary embodiment of the inventive concept, a method for forming a pattern is provided. A second mask layer on a first mask layer is patterned to form second mask patterns, each second mask pattern having a rhombus shape in a plan view. A trimming process is performed on the second mask pattern to form a second mask. A first portion corresponding to an opposite first vertex of each second mask pattern is etched more than a second portion corresponding to an opposite second vertex of each second mask pattern. A length of a first diagonal line between opposite first vertices is greater than a length of a second diagonal line between opposite second vertices. An etching process is performed on the first mask layer using the second mask as an etching mask to form a first mask.

[0007] According to an exemplary embodiment of the inventive concept, a method for manufacturing a semiconductor device is provided. An active region is formed on a substrate. A gate structure is formed to penetrate the active region. A conductive layer is formed on the active region. A first mask is formed on the conductive layer. A landing pad is formed by etching an upper portion of the conductive layer using the first mask as an etching mask. Capacitors are formed on the landing pads, respectively. Forming the first mask includes: forming a first mask layer on the conductive layer; forming a second mask layer on the first mask layer; patterning the second mask layer to form second mask patterns, each of which has a rhombus shape in a plan view; performing a trimming process on the second mask pattern to form a second mask; and performing an etching process on the first mask layer using the second mask as an etching mask to form a first mask. In the etching process, a first portion corresponding to an opposite first vertex of each second mask pattern is etched more than a second portion corresponding to an opposite second vertex of each second mask pattern. The length of a first diagonal line between first opposite vertices is greater than the length of a second diagonal line between second opposite vertices.

[0008] In a method of manufacturing a semiconductor device, by performing a trimming process on a mask for forming landing pads, a major axis and a minor axis of the mask are adjusted, thereby preventing reliability degradation of the semiconductor device due to electrical short circuits between landing pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 23 , Fig.24A , Fig. 24B and Figures 25 to 31 are plan views, cross-sectional views, and perspective views illustrating a method of forming a pattern according to example embodiments.

[0010] Figures 32 to 48 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0011] A method of forming a pattern and a method of manufacturing a semiconductor device using the same according to example embodiments will be described more fully below with reference to the accompanying drawings.

[0012] Hereinafter, two directions intersecting each other among the horizontal directions substantially parallel to the upper surface of the substrate are defined as a first direction and a second direction, respectively, and a vertical direction substantially perpendicular to the upper surface of the substrate is defined as a third direction. In example embodiments, the first direction and the second direction may be orthogonal to each other.

[0013] Figures 1 to 31 1 is a plan view, a cross-sectional view, and a perspective view illustrating a method of forming a pattern according to an example embodiment. Specifically, Figure 1 , Figure 3 , Figure 7 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.24A , Fig. 24B , Fig.26 , Fig.28 and Fig.30 It is a floor plan. Figure 2 , Figures 4 to 6 , Figures 8 to 12 , Fig.16 , Fig.18 and Figure 20 to Figure 23 is a cross-sectional view, and Fig.14 , Fig.25 , Fig. 27 , Fig.29 and Fig.31 Each cross-sectional view is taken along the line AA' of the corresponding plan view.

[0014] Reference Figure 1 and Figure 2 , a target layer 110 , a first mask layer 120 , an etch stop layer 130 , a second mask layer 140 , a first sacrificial layer 150 , and a second sacrificial layer 160 may be sequentially formed on a substrate 100 .

[0015] The target layer 110 may be a film to be finally patterned. In example embodiments, the target layer 110 may include a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), etc.) or polysilicon doped with impurities. The target layer 110 may be formed by, for example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, etc.

[0016] The first mask layer 120 may include, for example, an amorphous carbon layer (ACL), the etch stop layer 130 may include a nitride (e.g., silicon nitride), the second mask layer 140 may include an oxide (e.g., silicon oxide), the first sacrificial layer 150 may include, for example, silicon-on-hardmask (SOH), and the second sacrificial layer 160 may include an oxynitride (e.g., silicon oxynitride).

[0017] Reference Figure 3 and Figure 4 , an etching process using the first photoresist pattern (not shown) as an etching mask may be performed on the second sacrificial layer 160 to form a plurality of second sacrificial patterns 165. Each of the second sacrificial patterns 165 may have a line shape.

[0018] A portion of the upper surface of the first sacrificial layer 150 may be exposed between adjacent second sacrificial patterns 165 , and the first photoresist pattern may be removed by, for example, a stripping process after forming the second sacrificial patterns 165 .

[0019] In example embodiments, the second sacrificial patterns 165 may be formed to be spaced apart from each other in each of the first direction and the second direction, and each second sacrificial pattern 165 may extend in an oblique direction forming an acute angle or an obtuse angle with each of the first direction and the second direction, however, the inventive concept is not limited thereto.

[0020] Reference Figure 5 , a first spacer mask layer 170 may be formed to cover the exposed upper surface of the first sacrificial layer 150 and the upper surface and sidewalls of each second sacrificial pattern 165 .

[0021] First spacer mask layer 170 may be conformally formed using a material having high step coverage and / or under a process condition having high step coverage. In one embodiment, first spacer mask layer 170 may be formed by an ALD process and may include an oxide (eg, silicon oxide).

[0022] Reference Figure 6 , the first spacer mask layer 170 may be anisotropically etched to form a plurality of first spacer masks 175. Each of the first spacer masks 175 may cover a sidewall of a corresponding one of the second sacrificial patterns 165.

[0023] Reference Figure 7 and Figure 8 , the second sacrificial pattern 165 may be removed. In example embodiments, the second sacrificial pattern 165 may be removed by an ashing process and / or a stripping process, and the first spacer mask 175 may remain on the first sacrificial layer 150.

[0024] Reference Fig. 9 The first sacrificial layer 150 may be etched through an etching process using the first spacer mask 175 as an etching mask to form a plurality of first spacers 155. Each of the first spacers 155 may be formed under a corresponding one of the first spacer masks 175.

[0025] Thus, the first spacers 155 may be formed on the second mask layer 140, and a portion of the upper surface of the second mask layer 140 may be exposed between adjacent first spacers 155. The first spacer mask 175 may be removed.

[0026] Reference Fig.10, a plurality of third sacrificial patterns 180 may be formed to fill the spaces between adjacent first spacers 155. In example embodiments, a third sacrificial layer may be formed to cover the exposed upper surface of the second mask layer 140 and the upper surface and sidewalls of each first spacer 155, and the third sacrificial layer may then be planarized until the upper surface of each first spacer 155 is exposed. The planarized third sacrificial layer may be divided into a plurality of third sacrificial patterns 180 remaining in the spaces. The planarization process may be performed by, for example, a chemical mechanical polishing (CMP) process.

[0027] Reference Fig.11 , the first spacer 155 covering the sidewall of the third sacrificial pattern 180 may be removed, and thus a plurality of first openings 157 may be formed. Each first opening 157 may expose a portion of the upper surface of the second mask layer 140, extend in an oblique direction, and may be formed between adjacent third sacrificial patterns 180.

[0028] Reference Fig.12 , a plurality of initial second mask patterns 145 may be formed by performing an etching process on the second mask layer 140 using the third sacrificial pattern 180 as an etching mask. In the etching process, the first opening 157 may be transferred into the second mask layer 140, thereby forming a plurality of initial second openings 148a. Each first opening 157 may be connected to a corresponding one of the initial second openings 148a, so that a portion of the upper surface of the etch stop layer 130 may be exposed. Each initial second opening 148a extending in an oblique direction may be formed between adjacent initial second mask patterns 145. The third sacrificial pattern 180 may be removed.

[0029] Reference Fig.13 and Fig.14 , the preliminary second mask pattern 145 may have a parallelogram shape or a rectangular shape in a plan view.

[0030] In example embodiments, the preliminary second mask patterns 145 may be formed to be spaced apart from each other in each of the first and second directions, and each preliminary second mask pattern 145 may extend in an inclined direction forming an acute angle or an obtuse angle with the first and second directions.

[0031] So far, reference has been made to Figures 3 to 14 Describes forming a pattern by a double patterning process. In an example embodiment, reference may be made to Figures 3 to 14 The double patterning process is described to form the preliminary second mask pattern 145. However, the inventive concept is not limited thereto.

[0032] Reference Fig.15 and Fig.16 , a fourth sacrificial layer 190 and a fifth sacrificial layer 200 may be sequentially stacked on the preliminary second mask pattern 145 .

[0033] In example embodiments, the fourth sacrificial layer 190 may include a material with a low gap filling property and thus may not fill the initial second opening 148a. The fourth sacrificial layer 190 may include substantially the same material as the first sacrificial layer 150, for example, silicon on hard mask (SOH). The fifth sacrificial layer 200 may include substantially the same material as the second sacrificial layer 160, for example, nitride oxide such as silicon oxynitride.

[0034] Reference Fig.17 and Fig.18 , can be executed and referenced Figure 3 and Figure 4 The processes described are substantially the same or similar processes.

[0035] Thus, an etching process using the second photoresist pattern (not shown) as an etching mask may be performed on the fifth sacrificial layer 200 to form a plurality of fifth sacrificial patterns 205. Each of the fifth sacrificial patterns 205 may have a line shape.

[0036] A portion of the upper surface of the fourth sacrificial layer 190 may be exposed between adjacent fifth sacrificial patterns 205 , and the second photoresist pattern may be removed after the fifth sacrificial patterns 205 are formed.

[0037] In example embodiments, the fifth sacrificial patterns 205 may be formed to be spaced apart from each other in the first direction, and each of the fifth sacrificial patterns 205 may extend in the second direction. However, the inventive concept is not limited thereto.

[0038] Reference Fig.19 and Fig. 20 , can be executed and referenced Figure 5 and Figure 6 In an example embodiment, the processing described in the embodiment of the present invention is substantially the same or similar to the processing described in the embodiment of the present invention. Fig.17 and Fig.18 The resulting structure performs Figure 5 and Figure 6 processing.

[0039] Therefore, a second spacer mask layer may be conformally formed on the exposed upper surface of the fourth sacrificial layer 190 and the upper surface and sidewalls of each fifth sacrificial pattern 205, and then the second spacer mask layer may be anisotropically etched to form a plurality of second spacer masks 215. Each second spacer mask 215 may cover the sidewalls of a corresponding one of the fifth sacrificial patterns 205. In one embodiment, the second spacer mask layer may include substantially the same material as the first spacer mask layer 170, for example, an oxide such as silicon oxide.

[0040] Reference Fig.21 , can be executed and referenced Figures 7 to 9 In an example embodiment, the processing described in the embodiment of the present invention is substantially the same or similar to the processing described in the embodiment of the present invention. Fig.19 and Fig. 20 The resulting structure performs Figures 7 to 9 processing.

[0041] Thus, the fifth sacrificial pattern 205 may be removed, and then an etching process using the second spacer mask 215 as an etching mask may be performed on the fourth sacrificial layer 190, thereby forming a plurality of second spacers 195 on the preliminary second mask pattern 145. A portion of an upper surface of each preliminary second mask pattern 145 may be exposed between adjacent second spacers 195.

[0042] In example embodiments, the second spacers 195 may be formed to be spaced apart from each other in the first direction, and each of the second spacers 195 may extend in the second direction. The second spacers 195 may not fill the initial second openings 148a between adjacent initial second mask patterns 145, and may be formed across upper surfaces of adjacent initial second mask patterns 145. That is, a portion of the upper surface of the etch stop layer 130 may be exposed through the spaces between the adjacent second spacers 195 and the initial second openings 148a.

[0043] Reference Fig. 22 , can be executed and referenced Fig.10 and Fig.11 In an example embodiment, the processing described in the embodiment of the present invention is substantially the same or similar to the processing described in the embodiment of the present invention. Fig.21 The resulting structure performs Fig.10 and Fig.11 processing.

[0044] Therefore, after forming the sixth sacrificial layer to cover the exposed upper surface of the initial second mask pattern 145 and the upper surface and sidewalls of the second spacer 195, the sixth sacrificial layer may be planarized until the upper surface of the second spacer 195 may be exposed to form a plurality of sixth sacrificial patterns 220, and the second spacer 195 covering the sidewalls of the sixth sacrificial patterns 220 may be removed so that a plurality of third openings 197 exposing portions of the upper surface of the initial second mask pattern 145 and portions of the initial second openings 148a may be formed between adjacent sixth sacrificial patterns 220. The third openings 197 may extend in the second direction.

[0045] So far, reference has been made to Figures 17 to 22It is described that a pattern is formed by a double patterning process. However, the inventive concept is not limited thereto.

[0046] Reference Figure 23 to Figure 25 , an etching process using the sixth sacrificial pattern 220 as an etching mask may be performed on the preliminary second mask pattern 145 to form a plurality of second mask patterns 146 and a plurality of preliminary fourth openings 149 a .

[0047] Each initial fourth opening 149a extending in the second direction may be formed between adjacent initial second mask patterns 146. Each initial fourth opening 149a may correspond to one third opening 197 between adjacent sixth sacrificial patterns 220. The initial fourth opening 149a may be connected to partially combine with the initial second opening 148a extending in an oblique direction between adjacent initial second mask patterns 145. In example embodiments, the previously formed initial second opening 148a may be connected to the initial fourth opening 149a to define the second mask pattern 146. In this case, each second mask pattern 146 may be defined by two adjacent initial second openings 148a and two adjacent initial fourth openings 149a.

[0048] In example embodiments, a plurality of second mask patterns 146 may be formed to be spaced apart from each other in each of the first direction and the second direction, and each second mask pattern 146 may have a rhombus shape having a first diagonal line D1 and a second diagonal line D2. The length of the first diagonal line D1 may be greater than the length of the second diagonal line D2. The first diagonal line D1 and the second diagonal line D2 may be referred to as a first diagonal length and a second diagonal length, respectively.

[0049] Fig.24A The initial second openings 148a formed in the first direction and the initial fourth openings 149a formed in the second direction between adjacent second mask patterns 146 are shown, each of the initial second openings 148a may extend in an oblique direction, and each of the initial fourth openings 149a may extend in the second direction. However, the inventive concept is not limited thereto. In example embodiments, referring to Fig. 24B An initial second opening 148a can be formed in the first direction and an initial fourth opening 149a can be formed in the second direction between adjacent second mask patterns 146, each initial second opening 148a can extend in a first inclined direction different from the inclined direction, and each initial fourth opening 149a can extend in a second inclined direction different from the inclined direction.

[0050] An upper surface of the etch stop layer 130 may be partially exposed through the preliminary second opening 148 a and the preliminary fourth opening 149 a .

[0051] Reference Fig.26 and Fig. 27 , a trimming process may be performed on the edge portion of each second mask pattern 146, thereby forming a plurality of second masks 147, a plurality of second openings 148b, and a plurality of fourth openings 149b. The second mask patterns 146 subjected to the trimming process may correspond to the second masks 147, respectively. The initial second openings 148a subjected to the trimming process may correspond to the second openings 148b, respectively. The initial fourth openings 149a subjected to the trimming process may correspond to the fourth openings 149b, respectively.

[0052] Therefore, the second masks 147 may be formed to be spaced apart from each other in each of the first direction and the second direction. Each second opening 148b may be formed at a space between adjacent second masks 147 in the second direction. Each fourth opening 149b may be formed at a space between adjacent second masks 147 in the first direction. The second opening 148b and the fourth opening 149b may be connected to be partially combined with each other.

[0053] In example embodiments, the trimming process may be performed by, for example, a wet etching process, and portions corresponding to the respective opposite ends of the first diagonal line D1 of each second mask pattern 146 may be etched more than portions corresponding to the respective opposite ends of the second diagonal line D2 of each second mask pattern 146. Since an area of ​​each of the portions corresponding to the respective opposite ends of the second diagonal line D2 is smaller than an area of ​​each of the portions corresponding to the respective opposite ends of the first diagonal line D1, when the trimming process is uniformly performed on the vertex portions of the second mask pattern 146 during the same time, portions corresponding to the respective opposite ends of the first diagonal line D1 may be etched more than portions corresponding to the respective ends of the second diagonal line D2.

[0054] Therefore, the lengths of the third diagonal line D3 and the fourth diagonal line D4 of each second mask 147 that can be formed by trimming the second mask pattern 146 can be respectively less than the lengths of the first diagonal line D1 and the second diagonal line D2. In one embodiment, the ratio of the length of the third diagonal line D3 to the length of the fourth diagonal line D4 can be less than about 1.4.

[0055] In example embodiments, the second mask 147 may have a rhombus shape whose vertex portion is rounded in a plan view. In example embodiments, the vertex portion on one end of the third diagonal line D3 may be more rounded than the vertex portion on one end of the fourth diagonal line D4 because the vertex portion on the third diagonal line D3 may receive more etchant than the vertex portion on the fourth diagonal line D4. The vertex angle at one end of the third diagonal line D3 may have a wider influx angle than the vertex angle at one end of the fourth diagonal line D4.

[0056] After performing the trimming process, a CVD process, a PVD process, or an ALD process may be further performed on the second mask 147 to increase the width of the second mask 147. However, the inventive concept is not limited thereto. In example embodiments, the deposition process may be omitted.

[0057] Reference Fig.28 and Fig.29 An etching process using the second mask 147 as an etching mask may be performed on the etch stop layer 130 and the first mask layer 120 to form a plurality of first masks 125 , a plurality of fifth openings 128 , and a plurality of sixth openings 129 .

[0058] The fifth opening 128 and the sixth opening 129 extending in the second direction and the oblique direction, respectively, may expose the upper surface of the target layer 110. The fifth opening 128 may be formed between adjacent first masks 125 in the oblique direction. The sixth opening 129 may be formed between adjacent first masks 125 in the second direction. The fifth opening 128 and the sixth opening 129 may be connected to be partially combined with each other.

[0059] In an example embodiment, the first mask 125 may be formed to be spaced apart from each other in each of the first direction and the second direction, and each first mask 125 may have a rhombus shape in a plan view having a fifth diagonal D5 and a sixth diagonal D6. In an example embodiment, the length of the fifth diagonal D5 may be greater than the length of the sixth diagonal D6. The lengths of the fifth diagonal D5 and the sixth diagonal D6 of each first mask 125 may be the same as the lengths of the third diagonal D3 and the fourth diagonal D4 of the second mask 127, respectively. In one embodiment, although not shown, each first mask 125 may also have an elliptical shape in a plan view having a long major axis and a short minor axis according to the characteristics of the etching process. In an example embodiment, each first mask 125 may have an elliptical shape depending on the degree of rounding of the vertex portion.

[0060] Reference Fig.30 and Fig.31, an etching process using the first mask 125 as an etching mask may be performed on the target layer 110 to form a plurality of target patterns 115 .

[0061] Since the target patterns 115 are formed by an etching process using the first masks 125 each of which has an aspect ratio adjusted with respect to a corresponding one of the second mask patterns 146, the aspect ratio of a corresponding one of the target patterns 115 may also be adjusted. Therefore, the target patterns 115 may not contact each other and thus may not be electrically connected to each other, and the reliability of a semiconductor device including the target patterns 115 may be improved.

[0062] In example embodiments, the target patterns 115 may be formed to be spaced apart from each other in each of the first direction and the second direction, and each of the target patterns 115 may have an elliptical shape in a plan view having a major axis D7 and a minor axis D8. The lengths of the major axis D7 and the minor axis D8 of each of the target patterns 115 may be shorter than the lengths of the fifth diagonal line D5 and the sixth diagonal line D6 of the corresponding one of the first masks 125, respectively.

[0063] Alternatively, although not shown, the shapes of the target patterns 115 may be respectively the same as the shapes of the first mask 125. In this case, each target pattern 115 may have a seventh diagonal line D7 and an eighth diagonal line D8 corresponding to the major axis D7 and the minor axis D8, respectively, and may have a rhombus shape in a plan view, the vertex portion of which is rounded. The lengths of the seventh diagonal line D7 and the eighth diagonal line D8 may be respectively less than the lengths of the fifth diagonal line D5 and the sixth diagonal line D6.

[0064] In one embodiment, the target patterns 115 may be arranged in a honeycomb shape in a plan view.

[0065] As described above, the second mask layer 140 may be subjected to a double patterning process in an oblique direction that forms an acute angle or an obtuse angle with each of the first direction and the second direction to form an initial second mask pattern 145, and another double patterning process may be further performed on the initial second mask pattern 145 in the second direction or the first direction (i.e., in the longitudinal direction or the lateral direction) to form a second mask pattern 146. However, the inventive concept is not limited thereto. That is, first, the second mask layer 140 may be subjected to a double patterning process in the longitudinal direction or the lateral direction to form an initial second mask pattern 145, and then, another double patterning process may be further performed on the initial second mask pattern 145 in an oblique direction to form a second mask pattern 146.

[0066] A trimming process may be performed on the second mask pattern 146 to form a second mask 147, and an etching process using the second mask 147 as an etching mask may be performed on the first mask layer 120 to form a first mask 125. The trimming process may be performed so that portions corresponding to the respective opposite ends of the first diagonal line D1 of each second mask pattern 146 may be etched more than portions corresponding to the respective opposite ends of the second diagonal line D2 of each second mask pattern 146. Therefore, the lengths of the third diagonal line D3 and the fourth diagonal line D4 of each second mask 147 that can be formed by trimming the second mask pattern 146 may be smaller than the lengths of the first diagonal line D1 and the second diagonal line D2, respectively. In this case, the ratio of the lengths of the third diagonal line D3 to the fourth diagonal line D4 may be less than about 1.4.

[0067] An etching process using the first mask 125 as an etching mask may be performed on the target layer 110, and the target layer 110 may be etched to form a target pattern 115. The target pattern 115 may be formed by the etching process using the first mask 125. The aspect ratio of each first mask 125 is adjusted relative to a corresponding one of the second mask patterns 126, and the aspect ratio of each target pattern 115 may also be adjusted. Therefore, the target pattern 115 may be easily formed, and the target patterns 115 may not contact each other and thus may not be electrically connected to each other.

[0068] Hereinafter, a method of manufacturing a semiconductor device including a landing pad that can be fabricated by using a reference Figures 1 to 31 The method for forming a semiconductor device comprises the following steps: Figures 1 to 31 The described processing is substantially the same or similar processing, so a detailed description thereof is omitted herein.

[0069] Figures 32 to 48 1 is a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Fig.32 , Fig.34 , Fig.38 , Fig.41 , Fig.43 and Fig.46 is a plan view, and Fig.33 , Figure 35 to Figure 37 , Figure 39 to Figure 40 , Fig.42 , Figure 44 to Figure 45 and Figure 47 to Figure 48 Each of the cross-sectional views is taken along the line BB' and the line CC' of the corresponding plan view.

[0070] Reference Fig.32 and Fig.33, a plurality of active patterns 305 may be formed on the substrate 300 , and an isolation pattern 302 may be formed to cover a sidewall of each of the active patterns 305 .

[0071] The substrate 300 may include semiconductor materials (eg, silicon, germanium, silicon germanium, etc.) or III-V compounds (eg, GaP, GaAs, GaSb, etc.) In some embodiments, the substrate 300 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0072] In one embodiment, the active patterns 305 may be formed to be spaced apart from each other in each of the first direction and the second direction, and each active pattern 305 may extend in a fourth direction that is substantially parallel to the upper surface of the substrate 300 and forms an acute angle or an obtuse angle relative to each of the first direction and the second direction.

[0073] The active pattern 305 may be formed by removing an upper portion of the substrate 300 to form a first recess, and forming an isolation layer on the substrate 300 to cover the first recess, and planarizing the isolation layer until an upper surface of the active pattern 305 may be exposed. In example embodiments, the planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0074] Reference Fig.34 and Fig.35 An ion implantation process may be performed on an upper portion of the active pattern 305 to form an impurity region, and an upper portion of the active pattern 305 and an upper portion of the isolation pattern 302 may be partially removed to form a second recess 309 .

[0075] In example embodiments, the second recess 309 may extend in the first direction, and a plurality of second recesses 309 spaced apart from each other along the second direction may be formed. In one embodiment, two second recesses 309 may be formed on one active pattern 305, and thus, the impurity region may be divided into a first impurity region 301 and a second impurity region 303 by the second recesses 309. The first impurity region 301 and the second impurity region 303 may function as source / drain regions of a semiconductor device.

[0076] A plurality of gate structures 319 may be formed in the second recess 309. Each gate structure 319 may be formed to include: a gate insulating layer 313 located on a surface of a corresponding one of the active patterns 305 exposed by the second recess 309; a gate electrode 315 filling a lower portion of the second recess 309 on the gate insulating layer 313; and a first capping pattern 317 filling an upper portion of the second recess 309 on the gate insulating layer 313 and the gate electrode 315. Each gate structure 319 may extend in the first direction and may be formed to be spaced apart from each other in the second direction.

[0077] In example embodiments, the gate insulating layer 313 may be formed by performing a thermal oxidation process on the active pattern 305 exposed by the second recess 309 , and thus the gate insulating layer 313 may include oxide (eg, silicon oxide).

[0078] The gate electrode 315 may be formed by forming a gate electrode layer for filling the second recess 309 on the gate insulating layer 313 and the isolation pattern 302, and removing an upper portion of the gate electrode layer by a CMP process and / or an etch-back process. Thus, the gate electrode 315 may be formed in a lower portion of the second recess 309. The gate electrode layer may include a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), etc.) or a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride, etc.).

[0079] The first capping pattern 317 may be formed by forming a first capping layer for filling the remaining portion of the second recess 309 on the gate electrode 315, the gate insulating layer 313, the first impurity region 301, the second impurity region 303, and the isolation pattern 302, and planarizing an upper portion of the first capping layer until upper surfaces of the first and second impurity regions 301 and 303 and an upper surface of the isolation pattern 302 may be exposed. Thus, the first capping pattern 317 may be formed in an upper portion of the second recess 309. The first capping layer may include a nitride, such as silicon nitride.

[0080] A transistor including the first impurity region 301 and the second impurity region 303 and the gate structure 319 may be formed. Fig.36 , a first insulating interlayer 320 may be formed on the active pattern 305 and the isolation pattern 302 to cover the transistor. In one embodiment, the first insulating interlayer 320 may include silicon oxide, for example, TEOS.

[0081] The first insulating interlayer 320 may be partially etched to form a first trench 325 exposing the first impurity region 301. A plurality of first trenches 325 may be formed in each of the first direction and the second direction.

[0082] Reference Fig.37 , a first conductive layer 330 may be formed on the first insulating interlayer 320 to fill the first trench 325 , and then a barrier layer 340 and a second conductive layer 350 may be sequentially formed on the first conductive layer 330 , and a second capping pattern 365 may be formed on the second conductive layer 350 .

[0083] In example embodiments, the first conductive layer 330 may include polysilicon doped with impurities, the barrier layer 340 may include metal nitride or metal silicon nitride, and the second conductive layer 350 may include metal. The first conductive layer 330, the barrier layer 340, and the second conductive layer 350 may be formed by, for example, a sputtering process, a PVD process, an ALD process, or the like.

[0084] The second capping pattern 365 may include, for example, silicon nitride, and may have a line shape extending in the second direction.

[0085] Reference Fig.38 and Fig.39 , a plurality of bit line structures 375 may be formed. In example embodiments, an etching process using the second capping pattern 365 as an etching mask may be performed to sequentially etch the second conductive layer 350, the barrier layer 340, and the first conductive layer 330. Thus, the first conductive pattern 335, the barrier pattern 345, and the second conductive pattern 355 may be sequentially stacked on the first impurity region 301, which may form one of the bit line structures 375. In one embodiment, the bit line structures 375 may be arranged to be spaced apart from each other in the first direction, and each bit line structure 375 may extend in the second direction.

[0086] Reference Fig.40 After forming a third spacer to cover the bit line structure 375 and the first insulating interlayer 320, the third spacer may be anisotropically etched to form a third spacer 367 covering a sidewall of one of the bit line structures 375. The third spacer may include, for example, silicon nitride.

[0087] A second insulating interlayer 380 may be formed on the first insulating interlayer 320 to cover the bit line structure 375 and the third spacer 367. The second insulating interlayer 380 may also fill the remaining portion of the first trench 325. The second insulating interlayer 380 may be formed by a CVD process or a spin coating process, and an upper portion of the second insulating interlayer 380 may be planarized by a CMP process to expose an upper surface of the second capping pattern 365. The second insulating interlayer 380 may include, for example, silicon oxide.

[0088] Reference Fig.41 and Fig.42 , you can Fig.40 A plurality of second trenches 387 are formed in the resulting structure. In example embodiments, the first insulating interlayer 320 and the second insulating interlayer 380 may be partially etched to form each second trench 387, which may expose the second impurity region 303 and a portion of the isolation pattern 302. Thus, the first insulating interlayer 320 and the second insulating interlayer 380 may be converted into the first insulating pattern 327 and the second insulating pattern 385, respectively, and the first insulating pattern 327 and the second insulating pattern 385 may remain on the gate structure 319.

[0089] In one embodiment, the second trenches 387 may be arranged to be spaced apart from each other in the first direction, and each of the second trenches 387 may extend in the second direction.

[0090] Reference Fig.43 and Fig.44 , a plurality of barrier patterns 390 may be formed at spaces between the second trenches 387. Each barrier pattern 390 may extend between the second insulating patterns 385 in the first direction, and the barrier patterns 390 may be spaced apart from each other in the second direction.

[0091] In example embodiments, the barrier pattern 390 may be formed by forming a barrier layer to cover the exposed second impurity region 303, a portion of the isolation pattern 302, the sidewalls of the first insulating pattern 327, the upper surface and sidewalls of the second insulating pattern 385, and the upper surface of the second capping pattern 365, a planarization process may be performed on the barrier layer until the upper surface of the second insulating pattern 385 may be exposed, and an etching process using an etching mask may be performed. Thus, a portion of the isolation pattern 302 and a portion of the second impurity region 303 may be exposed.

[0092] The barrier pattern 390 may include nitride (eg, silicon nitride), and the planarization process may include a CMP process and / or an etch-back process.

[0093] Reference Fig.45 The third conductive layer 400 may be formed to fill the spaces between the second insulating patterns 385 and the spaces between the barrier patterns 390 and contact the exposed upper surface of the second impurity region 303. The third conductive layer 400 may at least partially cover the bit line structure 375, the second insulating patterns 385, and the barrier patterns 390.

[0094] The third conductive layer 400 may be a metal layer formed of metal (e.g., tungsten (W), titanium (Ti), (tantalum), etc.) or polycrystalline silicon doped with impurities, or may be a metal layer including metal (e.g., tungsten (W), titanium (Ti), (tantalum), etc.) or polycrystalline silicon doped with impurities, and the third conductive layer 400 may be formed by, for example, CVD processing, PVD processing, ALD processing, spin coating processing, etc.

[0095] Reference Fig.46 and Fig.47 , can be executed and referenced Figures 1 to 31 The described process is substantially the same or similar process, and the third conductive layer 400 may be patterned to form a plurality of landing pads 415. Portions of the third conductive layer 400 located below the landing pads 415 may be referred to as contact plugs.

[0096] In example embodiments, the landing pads 415 may be formed to be spaced apart from each other in each of the first direction and the second direction, and may be arranged in a honeycomb shape in a plan view. A third trench may be formed between the landing pads 415, and when the third trench is formed, portions of the second capping pattern 365, the third spacer 367, the second insulating pattern 385, and the blocking pattern 390 of the bit line structure 375 may also be removed.

[0097] The landing pad 415 may be formed by the following steps: forming a third mask layer and a fourth mask layer on the third conductive layer 400; performing a patterning process twice on the fourth mask layer to form a fourth mask pattern; performing a trimming process on the fourth mask pattern to form a fourth mask having an aspect ratio adjusted relative to the fourth mask pattern; performing an etching process using the fourth mask as an etching mask to form a third mask; and performing an etching process using the third mask as an etching mask on the third conductive layer 400. Therefore, the aspect ratio of the landing pad 415 may also be adjusted. As a result, the landing pads 415 may not contact each other, and degradation of reliability due to electrical short circuits may be prevented.

[0098] In an example embodiment, each landing pad 415 may have an elliptical shape in a plan view, the elliptical shape having a major axis and a minor axis.

[0099] Alternatively, the landing pad 415 may have a rhombus shape in a plan view, the rhombus shape having a first diagonal line and a second diagonal line. In an example embodiment, the length of the first diagonal line may be greater than the length of the second diagonal line. In this case, each vertex portion of the rhombus shape may have a circular shape in a plan view.

[0100] Reference Fig.48 , an insulating interlayer structure 440 filling the third trench and including a third insulating interlayer 420 and a fourth insulating interlayer 430 sequentially stacked may be formed, and a capacitor may be formed to contact an upper surface of the landing pad 415 .

[0101] The insulating interlayer structure 440 may be formed by forming a third insulating interlayer 420 on the bottom and sidewalls of the third trench and forming a fourth insulating interlayer 430 for filling the remaining portion of the third trench on the third insulating interlayer 420. The third insulating interlayer 420 and the fourth insulating interlayer 430 may include oxide (e.g., silicon oxide) or nitride (e.g., silicon nitride).

[0102] An etch stop layer 450 and a mold layer (not shown) may be sequentially formed on the landing pad 415 and the insulating interlayer structure 440 , and the etch stop layer 450 and the mold layer may be partially etched to form a fourth groove (not shown) that may partially expose the upper surface of the landing pad 415 .

[0103] A lower electrode layer may be formed on the sidewall of the fourth trench, the exposed upper surface of the landing pad 415, and the upper surface of the mold layer, a sacrificial layer (not shown) may be formed on the lower electrode layer to fully fill the remaining portion of the fourth trench, and the upper portions of the lower electrode layer and the sacrificial layer may be planarized until the upper surface of the mold layer may be exposed, so that the lower electrode layer may be node-separated. The remaining sacrificial layer and the mold layer may be removed by, for example, performing a wet etching process, and thus lower electrodes 460 may be formed on the exposed upper surfaces of the landing pads 415, each having a cylindrical shape. Alternatively, lower electrodes 460 may be formed that completely fill the fourth trench, each having a columnar shape.

[0104] A dielectric layer 470 may be formed on surfaces of the lower electrode 460 and the etch stop layer 450 , and an upper electrode 480 may be formed on the dielectric layer 470 , so that a capacitor 490 including the lower electrode 460 , the dielectric layer 470 , and the upper electrode 480 may be formed.

[0105] In example embodiments, the lower electrode 460 and the upper electrode 480 may include substantially the same material, for example, polysilicon or metal doped with impurities. The dielectric layer 470 may include an oxide (e.g., silicon oxide, metal oxide, etc.) and / or a nitride (e.g., silicon nitride, metal nitride, etc.), and the metal may include aluminum (Al), zirconium (Zr), titanium (Ti), hafnium (Hf), etc.

[0106] A fifth insulating interlayer 500 covering the capacitor 490 may be formed to complete the manufacture of the semiconductor device.

[0107] As described above, in the method for manufacturing a semiconductor device, before forming the landing pad 415 by the etching process using the third mask as an etching mask, the fourth mask layer may be subjected to a patterning process twice to form a fourth mask pattern, and the fourth mask pattern may be subjected to a trimming process so that the aspect ratio of the fourth mask pattern (i.e., the length of the relatively long diagonal line and the length of the relatively short diagonal line of the fourth mask pattern) may be adjusted. Therefore, when the third mask is formed by the etching process using the fourth mask as an etching mask, wherein the fourth mask may be formed by trimming the fourth mask pattern, the aspect ratio of the third mask may also be adjusted, and when the landing pads 415 that are finally patterned are formed by the etching process using the third mask whose aspect ratio may be adjusted, the aspect ratio of each landing pad 415 may also be adjusted. That is, the relatively long major axis and the relatively short minor axis (or the relatively long diagonal and the relatively short diagonal) of the landing pad 415 may also be adjusted so that the landing pads 415 may be prevented from contacting and electrically connecting to each other, and the reliability of the semiconductor device including the landing pad 415 may be improved.

[0108] As indicated above, although the invention has been described with reference to example embodiments, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept.

Claims

1. A method for forming a pattern, the method comprising: forming a first mask layer on the target layer; forming a second mask layer on the first mask layer; patterning the second mask layer to form a plurality of second mask patterns, each of the plurality of second mask patterns having a rhombus shape, the rhombus shape having a first diagonal line and a second diagonal line, the second diagonal line having a length shorter than the first diagonal line; performing a trimming process on the plurality of second mask patterns to form a plurality of second masks, wherein in the trimming process, a first portion corresponding to an opposite first vertex of a first diagonal line of each of the plurality of second mask patterns is etched more than a second portion corresponding to an opposite second vertex of a second diagonal line of each of the plurality of second mask patterns; patterning the first mask layer to form a plurality of first masks by performing an etching process on the first mask layer using the plurality of second masks as etching masks; and The target layer is patterned to form a plurality of target patterns by performing an etching process on the target layer using the plurality of first masks as etching masks.

2. The method according to claim 1, in, Each of the plurality of second masks has a rhombus shape with a rounded vertex portion in a plan view, the rhombus shape having a third diagonal line and a fourth diagonal line, and Wherein, the ratio of the length of the third diagonal line to the length of the fourth diagonal line is less than 1.

4.

3. The method according to claim 2, in, Each of the plurality of target patterns has an elliptical shape in a plan view, and Wherein, the ratio of the length of the major axis of the elliptical shape to the length of the minor axis of the elliptical shape is less than 1.

4.

4. The method according to claim 1, in, Each of the plurality of first masks has a rhombus shape with a rounded vertex portion in a plan view.

5. The method according to claim 1, in, The trimming process is performed by a wet etching process.

6. The method according to claim 1, in, The patterning of the second mask layer comprises: forming a plurality of first openings in the second mask layer, each of the plurality of first openings extending in a first direction; and A plurality of second openings are formed in the second mask layer, each of the plurality of second openings extending in a second direction different from the first direction.

7. The method according to claim 6, further comprising: forming a plurality of first spacers on the second mask layer, each of the plurality of first spacers having a line shape extending in the first direction; forming a plurality of third sacrificial patterns on the second mask layer, wherein each of the plurality of third sacrificial patterns fills a space between two adjacent first spacers among the plurality of first spacers; removing the plurality of first spacers; and An etching process is performed on the second mask layer by using the plurality of third sacrificial patterns as an etching mask to form a plurality of preliminary second mask patterns.

8. The method according to claim 7, further comprising: forming a plurality of second spacers on the plurality of preliminary second mask patterns, each of the plurality of second spacers having a line shape extending in the second direction; forming a plurality of fourth sacrificial patterns to cover sidewalls of the plurality of second spacers; as well as removing the plurality of second spacers, The patterning of the second mask layer to form a plurality of second mask patterns includes: using the plurality of fourth sacrificial patterns as etching masks to perform an etching process on the second mask layer to form the plurality of second mask patterns.

9. The method according to claim 7, in, The forming of a plurality of first spacers comprises: forming a first sacrificial layer on the second mask layer; forming a plurality of second sacrificial patterns on the first sacrificial layer, each of the plurality of second sacrificial patterns having a line shape extending in the first direction; forming a first spacer mask layer on the first sacrificial layer to cover the plurality of second sacrificial patterns; anisotropically etching the first spacer mask layer to form a plurality of first spacer masks; and The first sacrificial layer is etched using the plurality of first spacer masks as an etching mask to form the plurality of first spacers.

10. The method according to claim 8, in, The forming of a plurality of second spacers comprises: forming a third sacrificial layer on the plurality of initial second mask patterns; forming a plurality of fourth sacrificial patterns on the third sacrificial layer, each of the plurality of fourth sacrificial patterns having a line shape extending in the second direction; forming a second spacer mask layer on the third sacrificial layer to cover the plurality of fourth sacrificial patterns; anisotropically etching the second spacer mask layer to form a plurality of second spacer masks; and The third sacrificial layer is etched using the plurality of second spacer masks as an etching mask to form the plurality of second spacers.

11. A method for forming a pattern, the method comprising: patterning a second mask layer on the first mask layer to form a plurality of second mask patterns, each of the plurality of second mask patterns having a diamond shape in a plan view; performing a trimming process on the plurality of second mask patterns to form a plurality of second masks, wherein in the trimming process, a first portion corresponding to opposite first vertices of each of the plurality of second mask patterns is etched more than a second portion corresponding to opposite second vertices of each of the plurality of second mask patterns, wherein a length of a first diagonal line between the opposite first vertices is greater than a length of a second diagonal line between the opposite second vertices; and An etching process is performed on the first mask layer by using the plurality of second masks as etching masks to form a plurality of first masks.

12. The method according to claim 11, in, Each of the plurality of first masks has an elliptical shape in a plan view, and Wherein, the ratio of the length of the major axis of the elliptical shape to the length of the minor axis of the elliptical shape is less than 1.

4.

13. The method according to claim 11, in, Each of the plurality of second masks has a rhombus shape with a rounded vertex portion in a plan view.

14. The method according to claim 11, in, The plurality of second mask patterns include first openings extending in a first direction and second openings extending in a second direction different from the first direction.

15. A method for manufacturing a semiconductor device, the method comprising: forming an active region on a substrate; forming a gate structure penetrating the active area; forming a conductive layer on the active area; forming a plurality of first masks on the conductive layer; forming a plurality of landing pads by etching an upper portion of the conductive layer using the plurality of first masks as etching masks; as well as forming a plurality of capacitors on the plurality of landing pads, respectively; Wherein, forming a plurality of first masks comprises: forming a first mask layer on the conductive layer; forming a second mask layer on the first mask layer; patterning the second mask layer to form a plurality of second mask patterns, each of the plurality of second mask patterns having a diamond shape in a plan view; performing a trimming process on the plurality of second mask patterns to form a plurality of second masks, wherein in the trimming process, a first portion corresponding to opposite first vertices of each of the plurality of second mask patterns is etched more than a second portion corresponding to opposite second vertices of each of the plurality of second mask patterns, and a length of a first diagonal line between the opposite first vertices is greater than a length of a second diagonal line between the opposite second vertices; and An etching process is performed on the first mask layer using the plurality of second masks as etching masks to form the plurality of first masks.

16. The method according to claim 15, in, Each of the plurality of landing pads has a diamond shape with a rounded vertex portion in a plan view.

17. The method according to claim 16, in, A ratio of a length of a first diagonal line to a length of a second diagonal line of the rhombus shape is less than 1.

4.

18. The method according to claim 15, in, Each of the plurality of landing pads has an elliptical shape, and a ratio of a length of a major axis to a length of a minor axis of the elliptical shape is less than 1.

4.

19. The method according to claim 15, in, The plurality of landing pads are arranged in a honeycomb shape in a plan view.

20. The method according to claim 15, in, A first impurity region and a second impurity region are formed on the active region, and the conductive layer is in contact with an upper surface of the second impurity region, and Wherein, the method further comprises: A bit line is formed on the first impurity region.

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