Semiconductor Devices

Abstract

A semiconductor device includes: an active area extending along a first direction on a substrate; a gate structure on the substrate intersecting the active area and extending along a second direction; and a source / drain area on the active area on at least one side of the gate structure, wherein the source / drain area includes: a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling spaces between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The entire contents of Korean Patent Application No. 10-2019-0002425 filed on January 8, 2019, Korean Patent Application No. 10-2019-0009967 filed on January 25, 2019, and Korean Patent Application No. 10-2019-0068894 filed on June 11, 2019, entitled “Semiconductor Device”, filed in the Korean Intellectual Property Office, are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments relate to a semiconductor device. Background Art

[0004] As the demand for high performance, high speed, and multi-functions of semiconductor devices continues to increase, the integration density of semiconductor devices also increases. In order to meet the demand for high integration of semiconductor devices, semiconductor devices with fine patterns have been developed, and the patterns can have a fine width or a fine spacing distance. Summary of the invention

[0005] An embodiment can be implemented by providing a semiconductor device, which includes: an active area extending along a first direction on a substrate; a gate structure on the substrate intersecting the active area and extending along a second direction; and a source / drain region on the active area on at least one side of the gate structure, wherein the source / drain region includes: a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling spaces between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

[0006] An embodiment can be implemented by providing a semiconductor device, which includes: an active area extending along a first direction on a substrate; a plurality of channel layers on the active area, the plurality of channel layers being spaced apart from each other in a third direction perpendicular to the first direction; a gate structure on the substrate intersecting the active area and the plurality of channel layers and extending along a second direction, the gate structure surrounding the plurality of channel layers; and a source / drain region on the active area on at least one side of the gate structure, the source / drain region contacting the plurality of channel layers, wherein the source / drain region includes: a plurality of first epitaxial layers on side surfaces of the plurality of channel layers facing each other in the first direction, each of the plurality of first epitaxial layers including a first impurity of a first conductivity type; and a second epitaxial layer, the second epitaxial layer filling a space between the plurality of first epitaxial layers and including a second impurity of the first conductivity type.

[0007] An embodiment can be implemented by providing a semiconductor device, which includes: an active structure extending along a first direction on a substrate and having a channel region; a gate structure intersecting the channel region and extending along a second direction; and source / drain regions on both sides of the gate structure, wherein each source / drain region includes: a first semiconductor layer, the first semiconductor layer includes a first impurity at a first concentration; and a plurality of second semiconductor layers between the first semiconductor layer and the channel region, the plurality of second semiconductor layers are separated from each other to respectively contact the channel region and include a second impurity at a second concentration, the second concentration being lower than the first concentration. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various features will become apparent to those skilled in the art by describing exemplary embodiments in detail with reference to the accompanying drawings, in which:

[0009] Figure 1 shows a plan view of a semiconductor device according to an exemplary embodiment;

[0010] Figure 2 shows a cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0011] Figure 3A and Figure 3B shows an enlarged view of a semiconductor device according to an exemplary embodiment;

[0012] Figure 4 shows a cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0013] Figure 5 A graph showing impurity concentrations of source / drain regions in a semiconductor device according to an exemplary embodiment;

[0014] FIG. 6A to FIG. 6G Cross-sectional views showing in sequence some stages in a method of manufacturing a semiconductor device according to an exemplary embodiment;

[0015] Figure 7 shows a plan view of a semiconductor device according to an exemplary embodiment;

[0016] Figure 8 shows a cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0017] Figures 9 to 11 shows a cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0018] Fig. 12A and Fig. 12B shows a cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0019] Fig.13 A cross-sectional view showing a semiconductor device according to an exemplary embodiment; and

[0020] FIG. 14A to FIG. 14L Cross-sectional views showing some stages in a method of manufacturing a semiconductor device according to an exemplary embodiment are shown in sequence. DETAILED DESCRIPTION

[0021] Figure 1 A plan view of a semiconductor device according to an exemplary embodiment is shown.

[0022] Figure 2 A cross-sectional view of a semiconductor device according to an exemplary embodiment is shown. For example, Figure 2 Shows Figure 1 The cross-sectional view of the semiconductor device taken along lines II′ and II-II′. Figure 1 and Figure 2 Only main components of the semiconductor device are shown.

[0023] Reference Figure 1 and Figure 2 , the semiconductor device 100 may include a substrate 101, an active region 105, a device isolation layer 110, a source / drain region 150, a gate structure 160, a contact plug 180, and an interlayer insulating layer 190. The semiconductor device 100 may include a FinFET device, that is, a transistor having a fin structure in the active region 105. The FinFET device may include a transistor around the active region 105 and the gate structure 160 intersecting each other. For example, the transistor may be an NMOS transistor.

[0024] The substrate 101 may have an upper surface extending in the x-direction and the y-direction (e.g., may be located in a plane formed by the x-direction and the y-direction). The substrate 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. In one embodiment, the Group IV semiconductor may include, for example, silicon, germanium, or silicon germanium. The substrate 101 may be configured as, for example, a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0025] The device isolation layer 110 may define an active region 105 on the substrate 101. The device isolation layer 110 may be formed, for example, by a shallow trench isolation (STI) process. In one embodiment, the device isolation layer 110 may further include a region extending further toward a lower portion of the substrate 101. In one embodiment, the device isolation layer 110 may have a curved upper surface, and its height (e.g., in the z-direction relative to the height of the substrate 101) may increase toward the active region 105. The device isolation layer 110 may be formed of an insulating material. The device isolation layer 110 may be formed of, for example, an oxide, a nitride, or a combination thereof.

[0026] The active region 105 may be defined by the device isolation layer 110 and may extend in a first direction (e.g., x-direction) in or on the substrate 101. The active region 105 may protrude from the substrate 101 (e.g., along the z-direction). The upper end of the active region 105 may be away from the upper surface of the device isolation layer 110 or protrude a certain height above the upper surface of the device isolation layer 110 (e.g., along the z-direction). In one embodiment, the active region 105 may be a part of the substrate 101, or may include an epitaxial layer grown from the substrate 101. In the two side regions of the gate structure 160 or at the two side regions of the gate structure 160, a part of the active region 105 on the substrate 101 may be recessed, and the source / drain region 150 may be in the recessed active region 105.

[0027] The active region 105 may include a doped region 105D containing an impurity. The doped region 105D may be in an outer region (e.g., outside) of a recessed region in which the source / drain region 150 is disposed or included, so that the doped region 105D may be in contact with the source / drain region 150. The doped region 105D may include an impurity having the same conductivity type as that of the impurity included in the source / drain region 150 and a lower concentration than that of the impurity included in the source / drain region 150. In one embodiment, the doped region 105D may be a portion of the source / drain region 150. In one embodiment, the doped region 105D may include a first impurity, such as arsenic (As), and the arsenic (As) may be present at a concentration of about 1×10 15 / cm 3 Up to 2×10 15 / cm 3 The doping regions 105D contacting a single source / drain region 150 may be spaced apart from each other in one direction (eg, the x direction) and may be located on both sidewalls of the source / drain region 150. In one implementation, the doping region 105D may be omitted.

[0028] The source / drain region 150 may be located in a recessed region on both sides of the gate structure 160 in which the active region 105 is recessed. The recessed region may extend in the x-direction (e.g., between the gate structures 160) and may have inner sidewalls on both ends taken along the x-direction and a bottom surface between the inner sidewalls. The source / drain region 150 may be a source region or a drain region of a transistor. The height at which the upper surface of the source / drain region 150 is located may be similar to or higher than (e.g., farther from the substrate 101) the height of the lower surface of the gate structure 160. In an exemplary embodiment, the relative heights of the source / drain region 150 and the gate structure 160 may vary. In one embodiment, the source / drain region 150 may have a raised source / drain form in which the upper surface of the source / drain region 150 is higher than the lower surface (e.g., the surface facing the substrate) of the gate structure 160 (e.g., the gate electrode 165).

[0029] The cross-sectional view of the source / drain region 150 taken in the y direction may have, for example, a pentagonal shape, a hexagonal shape, or a shape similar to a pentagon or a hexagon. In one embodiment, the source / drain region 150 may have various shapes, and may have, for example, one of a polygon, a circle, and a rectangle. The upper surface of the cross-sectional view of the source / drain region 150 taken in the x direction may be a plane, such as Figure 2 As shown, the lower portion of the upper surface may have a curved shape similar to a portion or segment of a circle, a portion or segment of an ellipse, etc. In an exemplary embodiment, the above shape may be changed according to the distance between adjacent gate structures 160, the height of the active region 105, etc.

[0030] The source / drain region 150 may include a first epitaxial layer 152 and a second epitaxial layer 154 stacked in sequence. The second epitaxial layer 154 may fill the space between the first epitaxial layers 152. The first epitaxial layer 152 and the second epitaxial layer 154 may include silicon (Si), and may also include different elements and / or impurities of different concentrations. In an exemplary embodiment, the number of epitaxial layers included in the source / drain region 150 may vary.

[0031] The first epitaxial layer 152 may include an impurity having a higher concentration than the impurity included in the doping region 105D. The impurity may be a first impurity included in the doping region 105D, or may be a second impurity different from the first impurity. In one embodiment, the first epitaxial layer 152 may include an impurity of a first conductivity type, such as arsenic (As) and / or phosphorus (P), and may be, for example, a SiAs layer, a SiP layer, a SiPC layer, or a SiGeP layer. For example, the concentration of the impurity may be about 2×10 20 / cm 3 About 8×10 20 / cm 3 The first conductivity may be, for example, n-type conductivity. The first epitaxial layer 152 may be a layer having an epitaxially grown crystal structure, and may further include a growth seed layer.

[0032] The first epitaxial layer 152 may be located on the doped region 105D on both side walls of the recessed region (e.g., opposite to each other in the x-direction). For example, similar to the doped region 105D, the first epitaxial layer 152 may be spaced apart from each other on both inner side walls of the source / drain region 150 in the extension direction of the active region 105 between adjacent gate structures 160. In one embodiment, the thickness of the first epitaxial layer 152 may be, for example, about 3 nm to about 5 nm. As described above, the first epitaxial layer 152 may be spaced apart from each other on both inner side walls of the source / drain region 150 together with the doped region 105D, and the short channel effect caused by the diffusion of impurities of the second epitaxial layer 154 may be effectively prevented. For example, the first impurity of the first epitaxial layer 152 may include an element having a size larger than the size of an element of the second impurity included in the second epitaxial layer 154. For example, the diffusion of the second impurity may be more effectively prevented, thereby preventing the short channel effect.

[0033] The second epitaxial layer 154 may completely fill the recessed region, and may be a region including impurities having a higher concentration than the concentration of impurities included in the first epitaxial layer 152. The second epitaxial layer 154 may be an epitaxially grown layer, and may have a crystal structure continuously connected to the first epitaxial layer 152. The first epitaxial layer 152 and the second epitaxial layer 154 may be epitaxial layers, and film damage caused by an ion implantation process may be prevented when the first epitaxial layer 152 and the second epitaxial layer 154 are doped regions, thereby improving electrical properties of the semiconductor device 100.

[0034] The impurities included in the second epitaxial layer 154 may be the same as or different from the impurities included in the first epitaxial layer 152. For example, the first epitaxial layer 152 may include a first impurity of a first conductivity type at a first concentration, and the second epitaxial layer 154 may include a second impurity of the same first conductivity type at a second concentration, the second concentration being higher than the first concentration. In one embodiment, the second epitaxial layer 154 may be a SiP layer including phosphorus (P), and the concentration of the impurity may be, for example, about 3.1×10 21 / cm 3 About 3.9×10 21 / cm 3. In one embodiment, the doping region 105D may include arsenic (As), the first epitaxial layer 152 may be a SiAs layer, and the second epitaxial layer 154 may be a SiP layer. The second impurity of the second epitaxial layer 154 may be partially diffused into the adjacent first epitaxial layer 152 and the doping region 105D, and may be partially included in the first epitaxial layer 152 and the doping region 105D. Similarly, the first impurity of the first epitaxial layer 152 may be partially diffused into the adjacent second epitaxial layer 154 and the doping region 105D, and may be partially included in the second epitaxial layer 154 and the doping region 105D. For example, the first epitaxial layer 152 may include a region where the concentration of the first impurity is the largest, and the second epitaxial layer 154 may include a region where the concentration of the second impurity is constant and higher than the concentration of the impurity included in the first epitaxial layer 152.

[0035] The second epitaxial layer 154 may be in contact with the active region 105 of the substrate 101 on the bottom surface of the recessed region. For example, the second epitaxial layer 154 may be located in a region where the doped region 105D and the first epitaxial layer 152 are removed or have been removed on the bottom surface of the recessed region. The second epitaxial layer 154 may be a single layer in or between the upper portions of the first epitaxial layer 152 spaced apart from each other in the extension direction of the active region 105. For example, in the semiconductor device 100, the second epitaxial layer 154 may be formed after removing the first epitaxial layer 152 in the central region of the source / drain region 150 taken along the extension direction of the active region 105. For example, the volume of the second epitaxial layer 154 (a region including relatively high concentration of impurities in the source / drain region 150) may be increased, and the electrical performance of the semiconductor device 100 may be further improved.

[0036] The gate structure 160 may intersect the active region 105, and may extend in one direction (e.g., y direction) in or on an upper portion of the active region 105. A channel region of the transistor may be formed in the active region 105 intersecting with the gate structure 160 or below the gate structure 160. "Channel region" may refer to a region of the transistor including a depletion region, and may refer to a region where the active region 105 intersects with the gate structure 160 and is adjacent to the gate structure 160. The gate structure 160 may include, for example, a first gate dielectric layer 162, a second gate dielectric layer 163, a gate electrode 165, a gate spacer layer 164, and a gate cap layer 166.

[0037] The first gate dielectric layer 162 and the second gate dielectric layer 163 may be located between the active region 105 and the gate electrode 165, the first gate dielectric layer 162 may be located (e.g., located only) on the lower surface (e.g., the surface facing the substrate) of the second gate dielectric layer 163 on the lower surface of the gate electrode 165, and the second gate dielectric layer 163 may cover the lower surface and both side surfaces of the gate electrode 165. In one embodiment, one of the first gate dielectric layer 162 and the second gate dielectric layer 163 may be omitted. The first gate dielectric layer 162 and the second gate dielectric layer 163 may include, for example, oxides, nitrides, or high-k materials. High-k materials may refer to materials having a dielectric constant higher than that of silicon oxide (SiO 2 ) dielectric material with a dielectric constant of . The high-k material may be, for example, one of the following: aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 )、ZrO 2 ), zirconium oxide silicon (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAI x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ) or praseodymium oxide (Pr 2 O 3 ).

[0038] The gate electrode 165 may include a conductive material. For example, the gate electrode 165 may include a metal nitride material such as a titanium nitride film (TiN), a tantalum nitride film (TaN) or a tungsten nitride film (WN) and / or a metal material such as aluminum (Al), tungsten (W), molybdenum (Mo), etc., or a semiconductor material such as doped polysilicon. The gate electrode 165 may include multiple layers, such as two or more layers. Depending on the configuration of the semiconductor device 100, the gate electrodes 165 may be separated from each other between at least a portion of adjacent transistors.

[0039] The gate spacer layer 164 may be located on both side surfaces of the gate electrode 165. The gate spacer layer 164 may insulate the source / drain region 150 from the gate electrode 165. In one embodiment, the gate spacer layer 164 may have a multi-layer structure. The gate spacer layer 164 may be formed of, for example, an oxide, a nitride, an oxynitride, and / or a low-k material film.

[0040] The gate capping layer 166 may be located in or on an upper portion of the gate electrode 165 , and both a lower surface and a side surface of the gate capping layer 166 may be surrounded by the gate electrode 165 and the gate spacer layer 164 .

[0041] The interlayer insulating layer 190 may cover the source / drain regions 150 and the gate structure 160, and cover the device isolation layer 110. The interlayer insulating layer 190 may include, for example, one of oxide, nitride, and oxynitride, and may include a low-k material film.

[0042] The contact plug 180 may penetrate the interlayer insulating layer 190 and may be connected to the source / drain region 150, and may apply an electrical signal to the source / drain region 150. Figure 1 As shown, the contact plug 180 may be located on the source / drain region 150 and may have a length shorter than the length of the source / drain region 150 in the y direction. In one embodiment, the contact plug 180 may have a length longer than the length of the source / drain region 150 in the y direction. In one embodiment, the contact plug 180 may have an inclined side surface with a lower width smaller than an upper width according to an aspect ratio. In one embodiment, the contact plug 180 may be recessed or may extend to a certain depth in the source / drain region 150. In one embodiment, the contact plug 180 may not be recessed into the source / drain region 150 and may be in contact with an upper surface (e.g., a flat upper surface) of the source / drain region 150.

[0043] Figure 3A and Figure 3B An enlarged view of a semiconductor device according to an exemplary embodiment is shown. Figure 3A and Figure 3B Shown in enlarged form with Figure 1 The area shown corresponds to the area "A".

[0044] Reference Figure 3A In the semiconductor device 100a, the source / drain region 150a may have the following form: the second epitaxial layer 154 is recessed deeper downward (e.g., closer to the substrate 101 in the z direction) than in the aforementioned exemplary embodiment. The second epitaxial layer 154 may be located on a region that is recessed deeper by a first length L1 from the lower end of the recessed region before the first epitaxial layer 152 is formed. For example, the second epitaxial layer 154 may further protrude downward from the lower surface of the doped region 105D. In one embodiment, the first length L1 may be changed.

[0045] Reference Figure 3B In the semiconductor device 100b, the source / drain region 150b may have the following form: the second epitaxial layer 154 is recessed shallower than the aforementioned exemplary embodiment. For example, the doped region 105D may not be divided into two sides (e.g., separated in the x direction) in or at the lower portion of the source / drain region 150b, and a single continuous region may be formed. For example, in the lower portion of the source / drain region 150b, the doped region 105D may not be divided by the second epitaxial layer 154. In addition, impurities diffused from the first epitaxial layer 152 may remain in the active region 105 in contact with the lower end of the source / drain region 150b from which the first epitaxial layer 152 is removed.

[0046] Figure 4 A cross-sectional view of a semiconductor device according to an exemplary embodiment is shown. Figure 4 Shown along with Figure 1 The area corresponding to the cross section taken by line II′ in .

[0047] Reference Figure 4 In the semiconductor device 100c, the source / drain region 150c may include a first epitaxial layer 152c and a second epitaxial layer 154, each of which is integrated into a single continuous layer. Figure 2 Unlike the semiconductor device 100a shown, at the bottom of the second epitaxial layer 154, the doped region 105D may be a single layer, and the first epitaxial layer 152c may be a single layer. The thickness of the first epitaxial layer 152c may be different, for example, its thickness on the sidewall of the recessed region (taken along the x direction) may be different from its thickness on the bottom surface of the recessed region (where the source / drain region 150c is set). The first epitaxial layer 152c may have a first thickness T1 on the sidewall of the recessed region, and may have a second thickness T2 greater than the first thickness T1 on the bottom surface of the recessed region. In one embodiment, the second thickness T2 may be twice or more of the first thickness T1. The above structure can be controlled by adjusting the crystal plane type of the active region 105 exposed through the recessed region. The crystal plane type may refer to a crystal plane represented by a Miller index.

[0048] Figure 5 A graph illustrating impurity concentrations of source / drain regions in a semiconductor device according to an exemplary embodiment.

[0049] Figure 5 The analysis along the depth direction (eg, the z direction toward the substrate 101) starting from the upper surface of the source / drain region 150 is shown. Figure 4 The impurity concentration of the source / drain region 150 of the semiconductor device 100c is shown in FIG. The analysis is performed using secondary ion mass spectrometry (SIMS), and this figure illustrates the analysis results of the following example: the first epitaxial layer 152c is composed of about 6.5×1020 / cm 3 The second epitaxial layer 154 is a SiAs layer including about 3.8×10 21 / cm 3 The first concentration of phosphorus (P) and the second concentration of arsenic (As) are determined with reference to different vertical axes on the right and left sides, respectively, and each vertical axis is independent of each other.

[0050] As shown in the figure, it can be understood that in the region adjacent to the surface, the section L2 where the concentration of phosphorus (P) is constant may be the region of the second epitaxial layer 154; in the lower part, the section L1 including the region where the concentration of arsenic (As) has a maximum value may be the region of the first epitaxial layer 152c. For example, even when impurities are partially diffused to the peripheral region during the process of manufacturing the semiconductor device 100c, each region of the first epitaxial layer 152c and the second epitaxial layer 154 can be clearly identified as shown in the figure.

[0051] FIG. 6A to FIG. 6G Cross-sectional views showing some stages in a method of manufacturing a semiconductor device according to an exemplary embodiment are shown in sequence. FIG. 6A to FIG. 6G Shown for manufacturing Figure 1 and Figure 2 An exemplary embodiment of a semiconductor device and method is shown in Figure 2 The area shown corresponds to the area.

[0052] Reference Fig. 6A , an active region 105 may be defined by patterning the substrate 101 , a device isolation layer 110 may be formed, and a sacrificial gate structure 170 may be formed.

[0053] The active region 105 may be formed by anisotropically etching the substrate 101 using a mask layer to form a trench. The trench region may have a relatively high aspect ratio, the width of the trench region may decrease downward, and the active region 105 may have a shape in which its width (e.g., in the y direction) may decrease upward (e.g., the width of the active region 105 close to the substrate 101 in the y direction may be greater than the width of the active region 105 far from the substrate 101 in the y direction). The device isolation layer 110 may be formed by filling the trench region with an insulating material and planarizing the trench region along the upper surface of the active region 105.

[0054] The sacrificial gate structure 170 may be located in or on the active region 105 in a line shape intersecting the active region 105 and extending in the y direction. The sacrificial gate structure 170 may be located in a region such as Figure 2In the example shown, the first gate dielectric layer 162 and the third gate dielectric layer 163 and the gate electrode 165 are provided by subsequent processes. The sacrificial gate structure 170 may include the first sacrificial gate layer 172 and the second sacrificial gate layer 175 and a mask pattern layer 176. The mask pattern layer 176 may be used to pattern the first sacrificial gate layer 172 and the second sacrificial gate layer 175.

[0055] In one embodiment, the first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be an insulating layer and a conductive layer, respectively. In one embodiment, the first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be integrated into a single layer. In one embodiment, the first sacrificial gate layer 172 may include silicon oxide, and the second sacrificial gate layer 175 may include polysilicon. The mask pattern layer 176 may include silicon oxide and / or silicon nitride. In an exemplary embodiment, the structure of the sacrificial gate structure 170 may be changed.

[0056] Reference Figure 6B The gate spacer layer 164 may be located on both sidewalls of the sacrificial gate structure 170 , and a recessed region RC may be formed by recessing the active region 105 exposed between the sacrificial gate structures 170 .

[0057] The gate spacer layer 164 may be located on the side surface of the sacrificial gate structure 170. The gate spacer layer 164 may be formed of a low-k material. For example, the gate spacer layer 164 may include one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0058] The recessed region RC may be formed by recessing the active region 105 from the upper surface to a certain depth (e.g., in the z direction toward the substrate 101). For example, in the recessing process, the recessed region RC may be formed by sequentially performing a dry etching process and a wet etching process. For example, in this process, the height of the active region 105 in or near the outer region or the outside of the sacrificial gate structure 170 may be less than the height in the lower portion of the sacrificial gate structure 170. In one embodiment, the recessed region RC may have a form extending to the lower portion of the gate spacer layer 164 and the lower portion of the sacrificial gate structure 170 or extending below the lower portion of the gate spacer layer 164 and the lower portion of the sacrificial gate structure 170. In one embodiment, after the recessing process, a process for repairing the surface of the recessed active region 105 may be performed.

[0059] Reference Figure 6C , the doping region 105D of the source / drain region 150 may be formed by implanting impurities into the active region 105 , and the first epitaxial layer 152 of the source / drain region 150 may be formed.

[0060] The doped region 105D may be formed by implanting impurities into the active region 105 using the sacrificial gate structure 170 and the gate spacer layer 164 as a mask. The impurities may be, for example, arsenic (As). The doped region 105D may be formed on the exposed upper surface of the active region 105 along the lower surface and side surfaces (eg, inner surfaces) of the concave region RC.

[0061] The first epitaxial layer 152 may be grown from the active region 105 using, for example, a selective epitaxial growth (SEG) process. The first epitaxial layer 152 may include a first impurity by an in-situ doping process. The first epitaxial layer 152 may be a SiAs layer, a SiP layer, a SiPC layer, a SiC layer, or a SiGeP layer. The concentration of arsenic (As) and / or phosphorus (P) included in the first epitaxial layer 152 may be higher than the concentration of arsenic (As) included in the doping region 105D. The first epitaxial layer 152 may be formed on the doping region 105D along the lower surface and the side surface of the recessed region RC. The first epitaxial layer 152 may have a relatively greater thickness on or at the bottom surface of the recessed region RC than on the side surface, or may have a substantially uniform thickness on the side surface and the bottom surface, depending on the crystal plane of the active region 105 exposed by the recessed region RC.

[0062] Reference Fig.6D , a portion of the doped region 105D and a portion of the first epitaxial layer 152 may be removed from a central (eg, bottom) region (taken along the x-direction) of the recessed region RC.

[0063] The process for removing the doped region 105D and the first epitaxial layer 152 may be performed using a mask layer, or may be performed without using a mask layer. For example, a dry etching process may be used as a removal process. For example, the doped region 105D and the first epitaxial layer 152 may be removed from the bottom surface of the recessed region RC, and the active region 105 of the substrate 101 may be exposed. Therefore, the doped region 105D and the first epitaxial layer 152 may be divided to both sides of each inner wall of the recessed region RC (e.g., may be separated from each other and located on the inner wall of the recessed region RC).

[0064] exist Figure 3A and Figure 3B In an exemplary embodiment of the present invention, the exposed active region 105 may be further recessed to a certain depth during the removal process, or may be recessed less. Figure 4 In an exemplary embodiment of the present invention, the above-mentioned etching process may not be performed.

[0065] Reference Fig. 6E , a second epitaxial layer 154 of the source / drain region 150 filling the recessed region RC may be formed.

[0066] The second epitaxial layer 154 may be grown from the first epitaxial layer 152 using a SEG process. The second epitaxial layer 154 may include a second impurity by an in-situ doping process. For example, the second epitaxial layer 154 may be a SiP layer. The concentration of phosphorus (P) included in the second epitaxial layer 154 may be higher than the concentration of arsenic (As) or phosphorus (P) included in the first epitaxial layer 152. For example, the source / drain region 150 may be formed.

[0067] The second epitaxial layer 154 may be formed on the first epitaxial layer 152 along the bottom and side surfaces of the recessed region RC. For example, the second epitaxial layer 154 may contact the active region 105 in a central (e.g., bottom) region of the source / drain region 150. In one implementation, the second epitaxial layer 154 may be formed after removing a portion of the doped region 105D and the first epitaxial layer 152 from the central region of the source / drain region 150, and the volume of the second epitaxial layer 154 may be secured.

[0068] Reference Fig. 6F , an interlayer insulating layer 190 may be formed on the source / drain regions 150 , and the sacrificial gate structure 170 may be removed.

[0069] The interlayer insulating layer 190 may be formed by depositing an insulating material to cover the source / drain region 150, the sacrificial gate structure 170, and the gate spacer layer 164, and performing a planarization process to expose the upper surface of the second sacrificial gate layer 175 or the mask pattern layer 176. In one embodiment, the mask pattern layer 176 may be removed during the planarization process. The interlayer insulating layer 190 may include at least one of an oxide, a nitride, and an oxynitride, and may include a low-k material.

[0070] The remaining sacrificial gate structure 170 including the first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be selectively removed relative to the lower active region 105 and the device isolation layer 110, thereby forming an opening OR. As a process for removing the sacrificial gate structure 170, at least one of a dry etching process and a wet etching process may be used.

[0071] Reference Figure 6G , a gate structure 160 may be formed by forming a first gate dielectric layer 162 and a second gate dielectric layer 163 , a gate electrode 165 , and a gate capping layer 166 in the opening OR.

[0072] The first gate dielectric layer 162 and the second gate dielectric layer 163 may be substantially conformally formed along the sidewalls and bottom surface of the opening OR. Each of the first gate dielectric layer 162 and the second gate dielectric layer 163 may include an oxide, a nitride, or a high-k material. The gate electrode 165 may fill the inner space of the first gate dielectric layer 162 and the second gate dielectric layer 163. The gate electrode 165 may include a metal or a semiconductor material.

[0073] After forming the first and second gate dielectric layers 162 and 163 and the gate electrode 165 , a planarization process such as a chemical mechanical polishing (CMP) process may be used to remove materials remaining on the interlayer insulating layer 190 .

[0074] Return to reference Figure 2 , a contact plug 180 may be formed.

[0075] The contact hole may be formed by patterning the interlayer insulating layer 190, and the contact hole may be filled with a conductive material to form the contact plug 180. The contact hole may be formed by removing the interlayer insulating layer 190 on both side regions of the gate structure 160 using a mask layer such as a photoresist pattern. The lower surface of the contact hole may have a curvature formed along the upper surface of the source / drain region 150. When the interlayer insulating layer 190 is removed, the upper portion of the source / drain region 150 may be partially recessed. In an exemplary embodiment, the shape and position of the contact plug 180 may be changed.

[0076] Figure 7 A plan view of a semiconductor device according to an exemplary embodiment is shown.

[0077] Figure 8 A cross-sectional view of a semiconductor device according to an exemplary embodiment is shown. Figure 8 Shows Figure 7 The semiconductor device shown is a cross-sectional view taken along lines III-III′ and IV-IV′. Figure 7 and Figure 8 Only main components of the semiconductor device are shown.

[0078] Reference Figure 7 and Figure 8 , the semiconductor device 100d may include a substrate 101, an active region 105 on the substrate 101, a channel structure 140 (including a plurality of channel layers 141, 142, and 143 vertically spaced apart from each other in the active region 105, for example, in the z direction), a source / drain region 150d in contact with the plurality of channel layers 141, 142, and 143, a gate structure 160a intersecting the active region 105, and a contact plug 180 connected to the source / drain region 150d. The semiconductor device 100d may further include a device isolation layer 110, an inner spacer layer 130, and an interlayer insulating layer 190. The gate structure 160a may include a gate dielectric layer 162, a gate electrode 165, a spacer layer 164, and a gate cap layer 166.

[0079] In the semiconductor device 100d, the active region 105 may have a fin structure, and the gate electrode 165 may be located between the active region 105 and the channel structure 140 and between the plurality of channel layers 141, 142, and 143 of the channel structure 140. For example, the semiconductor device 100d may include a gate-around field effect transistor formed by the channel structure 140, the source / drain region 150d, and the gate structure 160a. For example, the transistor may be an NMOS transistor. In the following description, Figure 1 and Figure 2 The same reference numerals in the drawings represent the same elements and are not described in detail.

[0080] The channel structure 140 may include two or more channel layers, namely, first to third channel layers 141, 142, and 143, spaced apart from each other in a direction perpendicular to the upper surface of the active region 105 (e.g., z direction) in the active region 105. The first to third channel layers 141, 142, and 143 may be connected to the source / drain region 150d and may be spaced apart from the upper surface of the active region 105. The first to third channel layers 141, 142, and 143 may have a width that is the same or similar to that of the active region 105 in the y direction, and may have a width that is the same or similar to that of the gate structure 160a in the x direction. In one embodiment, the first to third channel layers 141, 142, and 143 may also have a reduced width so that the side surfaces of the first to third channel layers 141, 142, and 143 are located in or below the lower portion of the gate structure 160a in the x direction.

[0081] The first to third channel layers 141, 142 and 143 may be formed of a semiconductor material. For example, the first to third channel layers 141, 142 and 143 may include at least one of silicon (Si), germanium (Ge) and silicon germanium (SiGe). The first to third channel layers 141, 142 and 143 may be formed of, for example, the same material as the substrate 101. In an exemplary embodiment, the number and shape of the channel layers 141, 142 and 143 included in a single channel structure 140 may be changed. In one embodiment, another channel layer may be located in a region where the active region 105 contacts the gate electrode 165.

[0082] The source / drain region 150d may be located in the active region 105 on both side regions of the channel structure 140. The source / drain region 150d may include a first epitaxial layer 152d located on side surfaces of the first to third channel layers 141, 142, and 143 of the channel structure 140, respectively, and a second epitaxial layer 154d filling a space between the first epitaxial layers 152d. The first epitaxial layer 152d and the second epitaxial layer 154d may be semiconductor layers including silicon (Si), and may include impurities of different types and / or different concentrations.

[0083] The first epitaxial layer 152d may be a region including impurities having a higher concentration than the impurity concentration included in the active region 105. In one embodiment, the first epitaxial layer 152d may include, for example, arsenic (As) and / or phosphorus (P), and may be, for example, a SiAs layer, a SiP layer, a SiPC layer, a SiC layer, a SiPAs layer, or a SiGeP layer. The first epitaxial layer 152d may be epitaxially grown from the first to third channel layers 141, 142, and 143, and may be located on both side surfaces (in the x direction or relative to the x direction) of the channel structure 140. The first epitaxial layer 152d may not be located on or at the bottom surface of the source / drain region 150d. In one embodiment, the thickness of the first epitaxial layer 152d may be, for example, about 4nm to about 8nm. The first epitaxial layer 152d may be located on both side surfaces of the channel structure 140, and may effectively prevent the short channel effect that occurs due to the diffusion of impurities included in the second epitaxial layer 154d.

[0084] The first epitaxial layer 152d may be separated from each other between the plurality of channel layers 141, 142, and 143 vertically disposed in the z direction. The first epitaxial layer 152d may protrude (e.g., toward the second epitaxial layer 154d) from a side surface formed by the inner partition wall layer 130 and the first to third channel layers 141, 142, and 143. The first epitaxial layer 152d may not overlap with the inner partition wall layer 130 on a plane (e.g., when viewed in the z direction).

[0085] The second epitaxial layer 154d can completely fill the area between adjacent channel structures 140, can surround the surface of the first epitaxial layer 152d on which the first epitaxial layer 152d is not in contact with the channel structure 140, and can cover the side surface of the inner partition wall layer 130. The second epitaxial layer 154d can fill the space between the first epitaxial layers 152d spaced apart from each other up and down (e.g., in the z direction). For example, at least a portion of the second epitaxial layer 154d can overlap with the first epitaxial layer 152d on a plane (e.g., when viewed in the z direction).

[0086] The second epitaxial layer 154d may be a region including impurities having a higher concentration than the impurities included in the first epitaxial layer 152d. The second epitaxial layer 154d may be epitaxially grown from the first epitaxial layer 152d. The impurities included in the second epitaxial layer 154d may be the same as or different from the impurities included in the first epitaxial layer 152d. For example, the second epitaxial layer 154d may be a SiP layer including phosphorus (P). In one embodiment, the first epitaxial layer 152d may be a SiAs epitaxial layer, and the second epitaxial layer 154d may be a SiP epitaxial layer.

[0087] The impurities of the second epitaxial layer 154d may be partially diffused into the adjacent first epitaxial layer 152d, and may be partially included in the first epitaxial layer 152d at a concentration lower than the concentration of the impurities included in the second epitaxial layer 154d. In one embodiment, the impurities of the first epitaxial layer 152d may be partially diffused into the adjacent second epitaxial layer 154d, and may be partially included in the second epitaxial layer 154d at a relatively low concentration. The first epitaxial layer 152d and the second epitaxial layer 154d may be epitaxial layers, and film damage caused by an ion implantation process may be prevented when the first epitaxial layer 152d and the second epitaxial layer 154d are doped regions, thereby improving the electrical performance of the semiconductor device 100d.

[0088] In one embodiment, in the semiconductor device 100d, the first epitaxial layer 152d may be partially removed from the central region of the source / drain region 150d between the adjacent gate structure 160a and the channel structure 140 in the extension direction of the active region 105, and the second epitaxial layer 154d may be formed. For example, the volume of the second epitaxial layer 154d (including a relatively high concentration of impurities) may be increased in the source / drain region 150d, and the first epitaxial layer 152d (including a relatively low concentration of impurities) may be located only on the side surface of the channel structure 140 with a relatively small volume, thereby improving the electrical performance of the semiconductor device 100d. In one embodiment, the first epitaxial layer 152d may not remain in the central region adjacent to the side surface of the lowermost first channel layer 141, and the electrical function of the first channel layer 141 may be ensured.

[0089] In one embodiment, the source / drain region 150d may further include at least one doped region of the first to third channel layers 141, 142, and 143 in the inner region of the first epitaxial layer 152d, for example, Figure 1 and Figure 2 The doped region 105D of the semiconductor device 100 in the exemplary embodiment is shown.

[0090] The gate structure 160a may intersect the active region 105 and the channel structure 140, and extend in one direction (e.g., y direction) at the upper portion of the active region 105 and the channel structure 140. The channel region of the transistor may be formed in the active region 105 and the channel structure 140 intersecting the gate structure 160a. The gate structure 160a may include a gate electrode 165, a gate dielectric layer 162 between the gate electrode 165 and the plurality of channel layers 141, 142, and 143, a gate spacer layer 164 on the side surface of the gate electrode 165, and a gate capping layer 166 on the upper surface of the gate electrode 165.

[0091] The gate dielectric layer 162 may be located between the active region 105 and the gate electrode 165 and between the channel structure 140 and the gate electrode 165, and may cover at least a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 may surround all surfaces of the gate electrode 165 except for the uppermost surface. In one embodiment, the gate dielectric layer 162 may extend to a region between the gate electrode 165 and the gate spacer layer 164. The gate dielectric layer 162 may include, for example, an oxide, a nitride, or a high-k material.

[0092] The gate electrode 165 may fill the space between the plurality of channel layers 141, 142, and 143, and may extend to the upper portion of the channel structure 140 in the upper portion of the active region 105. The gate electrode 165 may be spaced apart from the plurality of channel layers 141, 142, and 143 by the gate dielectric layer 162. The gate electrode 165 may include a conductive material. In one embodiment, the gate electrode 165 may include, for example, a metal nitride material such as a titanium nitride film (TiN), a tantalum nitride film (TaN), or a tungsten nitride film (WN) and / or a metal material such as aluminum (Al), tungsten (W), molybdenum (Mo), etc., or a semiconductor material such as doped polysilicon. The gate electrode 165 may include multiple layers, for example, two or more layers. According to the configuration of the semiconductor device 100d, the gate electrodes 165 may be separated from each other by a separation portion between at least a portion of adjacent transistors.

[0093] The inner partition wall layer 130 may be arranged side by side with the gate electrode 165 between the channel structures 140. At the lower portion of the third channel layer 143, the gate electrode 165 may be spaced apart and electrically isolated from the source / drain region 150d by the inner partition wall layer 130. In one embodiment, the side surface of the inner partition wall layer 130 facing the gate electrode 165 may have an inwardly curved shape that curves inwardly toward the gate electrode 165. The inner partition wall layer 130 may be formed of, for example, oxide, nitride, or oxynitride, and may be formed of a low-k material.

[0094] The contact plug 180 may penetrate the interlayer insulating layer 190 and may extend vertically (e.g., in the z direction) from the upper portion to the lower portion. In one embodiment, the contact plug 180 may extend downward beyond the third channel layer 143 (e.g., closer to the substrate 101). In one embodiment, the contact plug 180 may be recessed to or extended to be flush with the upper surface of the second channel layer 142. In one embodiment, the contact plug 180 may not be recessed into the source / drain region 150d and may contact the upper surface (e.g., a flat upper surface) of the source / drain region 150d.

[0095] Figures 9 to 11 A cross-sectional view of a semiconductor device according to an exemplary embodiment is shown. Figures 9 to 11 Shown along with Figure 7The area corresponding to the cross-sections taken by lines III-III′ and IV-IV′ in .

[0096] Reference Fig. 9 The source / drain region 150e in the semiconductor device 100e may further include a first side surface epitaxial layer 152e1 and a second epitaxial layer 154e, and may also include a first lower epitaxial layer 152e2 on a lower end of the source / drain region 150e.

[0097] The first lower epitaxial layer 152e2 may be formed together with the first side surface epitaxial layer 152e1, and may be formed of the same material as that of the first side surface epitaxial layer 152e1. For example, the first lower epitaxial layer 152e2 may include at least one of SiAs, SiP, SiPC, SiC, SiGeAs, and SiGeP. The thickness of the first lower epitaxial layer 152e2 may be greater than the thickness of the first side surface epitaxial layer 152e1 according to the crystal plane of the active region 105. In one embodiment, the width of the upper portion of the first lower epitaxial layer 152e2 may be narrower than the width of the lower portion, and the first lower epitaxial layer 152e2 may have an upwardly curved shape (for example, the width of the first lower epitaxial layer 152e2 may decrease as the height relative to the substrate 101 increases). In one embodiment, the lower surface of the source / drain region 150e may have a downwardly curved shape, and in an exemplary embodiment, the shape of the first lower epitaxial layer 152e2 may change.

[0098] Reference Fig.10 In the source / drain region 150f of the semiconductor device 100f, the first epitaxial layer 152f may extend (e.g., continuously) onto or along the side surfaces of the plurality of channel layers 141, 142, and 143 of the channel structure 140, and may also extend onto or along the side surfaces of the inner partition wall layer 130. The first epitaxial layer 152f may extend to the lower portion of the source / drain region 150f, and may contact the active region 105 at the lower end. In one embodiment, the first epitaxial layer 152f may not remain in the central region of the lower end portion of the source / drain region 150f. The first epitaxial layer 152f may have a relatively large thickness on the side surfaces of the plurality of channel layers 141, 142, and 143 of the source / drain region 150f, and thus may have a curvature. The second epitaxial layer 154f may fill the space between the first epitaxial layers 152f.

[0099] Reference Fig.11, in the source / drain region 150g in the semiconductor device 100g, the first epitaxial layer 152g may extend (e.g., continuously) along the side surfaces of the plurality of channel layers 141, 142, and 143 of the channel structure 140 and the side surface of the inner partition wall layer 130, and may form the lower surface of the source / drain region 150g at the lower end. For example, the first epitaxial layer 152g may completely surround the lower surface and the side surface (in the x-direction) of the second epitaxial layer 154g. For example, the second epitaxial layer 154g may not directly contact the active region 105. In one embodiment, the first epitaxial layer 152g may contact (e.g., directly contact) the gate partition wall layer 164 at the upper end.

[0100] In one embodiment, the thickness of the first epitaxial layer 152g may not be uniform. The first epitaxial layer 152g may have a third thickness T3 (e.g., measured along the x direction) on the sidewalls of the plurality of channel layers 141, 142, and 143, and may have a fourth thickness T4 (e.g., measured along the z direction) greater than the third thickness T3 at the bottom. In one embodiment, the fourth thickness T4 may be twice or more than the third thickness T3. The structure may be controlled by the crystal plane of the active region 105 at the bottom of the source / drain region 150g. The first epitaxial layer 152g may have a relatively large thickness on the side surfaces of the plurality of channel layers 141, 142, and 143 on the two side regions of the source / drain region 150g (taken along the x direction), and thus may have a curvature. In one embodiment, the shape of the lower surface of the source / drain region 150g may change. For example, the depth of the curved portion of the lower surface may be different. In one embodiment, the shape of the first epitaxial layer 152g on the lower surface of the source / drain region 150g may also change.

[0101] Fig. 12A and Fig. 12B A cross-sectional view of a semiconductor device according to an exemplary embodiment is shown. Fig. 12A and Fig. 12B Shown along with Figure 7 The area corresponding to the cross-sections taken by lines III-III′ and IV-IV′ in .

[0102] Reference Fig. 12A , with reference Figure 8 Unlike the aforementioned exemplary embodiments, the semiconductor device 100h may not include the inner partition wall layer 130. The gate electrode 165 may expand or extend outward along the x-direction between the plurality of channel layers 141, 142, and 143 of the channel structure 140. For example, both side surfaces (taken along the x-direction) of the lower gate structure 160a may be arranged side by side with both side surfaces of the channel structure 140 (e.g., aligned in the z-direction).

[0103] Reference Fig. 12B , with reference Figure 8Unlike the aforementioned exemplary embodiments, in the semiconductor device 100i, both side surfaces (taken along the x-direction) of the channel structure 140 and the inner partition wall layer 130 may be located at (e.g., narrower than) the lower portion of the gate structure 160a. For example, the channel structure 140 may have a width (e.g., in the x-direction) that is relatively smaller than the width of the upper portion of the gate structure 160a.

[0104] In one embodiment, if Fig. 12B As shown, both side surfaces (taken along the x direction) of the channel structure 140 and the inner spacer layer 130 may be located at or narrower than the lower portion of the gate spacer layer 164. In one embodiment, the side surfaces may be located at or aligned with the lower portion of the gate electrode 165.

[0105] Fig.13 A cross-sectional view of a semiconductor device according to an exemplary embodiment is shown. Fig.13 Shown along with Figure 7 The area corresponding to the cross section taken by line IV-IV′ in .

[0106] Reference Fig.13 In the semiconductor device 100j, the widths of the active region 105a and the channel structure 140a may be Figure 8 The example shown is different. The active region 105a and the channel structure 140a may each have a relatively small width, so each of the plurality of channel layers 141a, 142a, and 143a of the channel structure 140a may have a circular shape or an elliptical shape, wherein the difference between the major axis and the minor axis in a cross-sectional view taken along the y direction is relatively small. For example, in Figure 8 In the exemplary embodiment shown, each of the plurality of channel layers 141, 142, and 143 may have a width of about 20 nm to 50 nm in the y direction, and each of the plurality of channel layers 141a, 142a, and 143a in the exemplary embodiment may have a width of about 3 nm to 12 nm in the y direction. As described above, in exemplary embodiments, the width and shape of the active region 105a and the channel structure 140a may vary.

[0107] FIG. 14A to FIG. 14L Cross-sectional views showing some stages in a method of manufacturing a semiconductor device according to an exemplary embodiment are shown in sequence. FIG. 14A to FIG. 14L Shown for manufacturing Figure 7 and Figure 8 An exemplary embodiment of a semiconductor device and method is shown in Figure 8 The area shown corresponds to a cross section.

[0108] Reference Fig.14A , a sacrificial layer 120 and a plurality of channel layers 141 , 142 , and 143 may be alternately stacked on the substrate 101 .

[0109] The sacrificial layer 120 can be replaced by the gate dielectric layer 162 and the gate electrode 165 through subsequent processes, such as Figure 7 As shown. The sacrificial layer 120 may be formed of a material having an etching selectivity relative to the plurality of channel layers 141, 142, and 143. The plurality of channel layers 141, 142, and 143 may include a material different from that of the sacrificial layer 120. For example, the sacrificial layer 120 and the plurality of channel layers 141, 142, and 143 may include a semiconductor material (including at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe)) and may include different materials, and the sacrificial layer 120 and the plurality of channel layers 141, 142, and 143 may or may not include impurities. For example, the sacrificial layer 120 may include silicon germanium (SiGe), and the plurality of channel layers 141, 142, and 143 may include silicon (Si).

[0110] The sacrificial layer 120 and the plurality of channel layers 141, 142, and 143 may be formed by performing an epitaxial growth process using the substrate 101 as a seed crystal. Each of the sacrificial layer 120 and the plurality of channel layers 141, 142, and 143 may have a thickness of about 1A to 100 nm. In an exemplary embodiment, the number of layers of the plurality of channel layers 141, 142, and 143 alternately stacked with the sacrificial layer 120 may vary.

[0111] Reference Fig. 14B An active structure may be formed by removing the stacked structure of the sacrificial layer 120 and the plurality of channel layers 141 , 142 , and 143 , and a portion of the substrate 101 .

[0112] The active structure may include alternately stacked sacrificial layers 120 and a plurality of channel layers 141, 142, and 143, and may further include an active region 105 protruding onto or from an upper surface of the substrate 101 by removing a portion of the substrate 101. The active structures may have a linear shape extending in one direction (e.g., the x-direction) and may be spaced apart from each other in the y-direction.

[0113] In the region where a portion of the substrate 101 is removed, a device isolation layer 110 may be formed by filling the region with an insulating material and configuring the insulating material to be recessed so that the active region 105 protrudes. The upper surface of the device isolation layer 110 may be lower than the upper surface of the active region 105 (e.g., closer to the substrate 101 in the z direction).

[0114] Reference Fig. 14C , a sacrificial gate structure 170 and a gate spacer layer 164 may be formed on the active structure.

[0115] The sacrificial gate structure 170 may be a sacrificial structure formed in a region where the gate dielectric layer 162 and the gate electrode 165 will be located on the upper portion of the channel structure 140 through subsequent processes, such as Figure 8 As shown. The sacrificial gate structure 170 may include: a first sacrificial gate layer 172 and a second sacrificial gate layer 175 stacked sequentially, and a mask pattern layer 176. The mask pattern layer 176 may be used to pattern the first sacrificial gate layer 172 and the second sacrificial gate layer 175. In one embodiment, the first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be, for example, an insulating layer and a conductive layer, respectively. The first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be integrated into a single layer. In one embodiment, the first sacrificial gate layer 172 may include silicon oxide, and the second sacrificial gate layer 175 may include polysilicon. The mask pattern layer 176 may include silicon oxide and / or silicon nitride. The sacrificial gate structure 170 may have a linear shape that intersects with the active structure and extends in one direction. In one embodiment, the sacrificial gate structure 170 may extend in the y direction and may be spaced apart from each other in the x direction.

[0116] The gate spacer layer 164 may be located on both sidewalls of the sacrificial gate structure 170. The gate spacer layer 164 may be formed by forming a film with a uniform thickness along the upper and side surfaces of the sacrificial gate structure 170 and the active structure and performing an anisotropic etching process. The gate isolation layer 164 may be formed of a low-k material and may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0117] Reference Fig.14D , the recessed region RC may be formed by removing the sacrificial layer 120 and the plurality of channel layers 141 , 142 , and 143 exposed between the sacrificial gate structures 170 , thereby forming the channel structure 140 .

[0118] The sacrificial gate structure 170 and the gate spacer layer 164 may be used as a mask to remove the exposed sacrificial layer 120 and the plurality of channel layers 141, 142, and 143. For example, each of the plurality of channel layers 141, 142, and 143 may have a limited length in the x-direction and may form the channel structure 140. In one embodiment, as shown in FIG. Fig. 12B As shown, the sacrificial layer 120 and the channel structure 140 may be partially removed from the side surfaces of the sacrificial gate structure 170 at the bottom of the sacrificial gate structure 170 , and both side surfaces taken in the x direction may be located at the bottom of the sacrificial gate structure 170 and the gate spacer layer 164 .

[0119] Reference Fig.14E , the exposed sacrificial layer 120 may be partially removed from the side surface.

[0120] The sacrificial layer 120 may be selectively etched relative to the channel structure 140 by a wet etching process, and may be removed to a certain depth from a side surface taken in the x-direction. In one embodiment, the sacrificial layer 120 may have a side surface that is concave inwardly by the side surface etching process as described above. In one embodiment, the shape of the side surface of the sacrificial layer 120 may be changed.

[0121] Reference Fig.14F , an inner partition wall layer 130 may be formed in a region where the sacrificial layer 120 has been removed.

[0122] The inner partition wall layer 130 may be formed by filling the region from which the sacrificial layer 120 has been removed with an insulating material and removing the insulating material from the outer region of the channel structure 140. In one embodiment, the inner partition wall layer 130 may be formed of the same material as the gate partition wall layer 164. In one embodiment, the inner partition wall layer 130 may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN.

[0123] Reference Figure 14G , a seed layer 152S (for forming the source / drain region 150 d ) may be formed in the recessed region RC at both side regions or at both sides of the sacrificial gate structure 170 .

[0124] The seed layer 152S may be formed on the side surfaces of the first to third channel layers 141, 142, and 143 by the SEG process, and may also be formed on the bottom surface of the recessed region RC in the active region 105. The seed layer 152S may include impurities having a lower concentration than the impurities included in the first epitaxial layer 152d and the second epitaxial layer 154d to be formed in a subsequent process, or may not include impurities. For example, the growth of the first epitaxial layer 152d may be promoted or the lattice mismatch may be reduced by the seed layer 152S. In one embodiment, the process for forming the seed layer 152S may be omitted.

[0125] Reference Fig.14H , a first epitaxial layer 152d of the source / drain region 150d may be formed in the recessed region RC.

[0126] The first epitaxial layer 152d may be formed by epitaxial growth from the seed layer 152S, and may include impurities by an in-situ doping process. The first epitaxial layer 152d may be a SiAs layer, a SiP layer, a SiPC layer, a SiC layer, a SiPAs layer, or a SiGeP layer. The first epitaxial layer 152d may be formed on the side surfaces of the first to third channel layers 141, 142, and 143 on the active region 105 and on the bottom surface of the recessed region RC. In one embodiment, the first epitaxial layer 152d on the first to third channel layers 141, 142, and 143 may have an outwardly curved surface (e.g., a surface convex outwardly) curved from the side surfaces of the first to third channel layers 141, 142, and 143. In one embodiment, the first epitaxial layer 152d on the bottom surface of the recessed region RC may have an upwardly curved or convex surface on the surface of the active region 105. In one embodiment, as Fig.10 and Fig.11 As shown, the manufacturing process may be performed while controlling the growth speed and growth thickness of the first epitaxial layer 152d in the above process.

[0127] Reference Fig.14I , the first epitaxial layer 152 d on the active region 105 (eg, at the bottom of the recessed region RC) may be removed between the sacrificial gate structures 170 .

[0128] The process for removing the first epitaxial layer 152d may be performed using a mask layer or using the sacrificial gate structure 170 as a mask (without using an additional mask). For example, a dry etching process may be used as the removal process. For example, the first epitaxial layer 152d may be removed from the bottom surface of the recessed region RC, and the active region 105 of the substrate 101 may be exposed. For example, the first epitaxial layer 152d may be located only on (e.g., may remain on) the side surfaces of the first to third channel layers 141, 142, and 143. In one embodiment, as shown in FIG. Fig. 9 and Fig.11 As shown, the above process may not be performed.

[0129] Reference Fig.14J , a second epitaxial layer 154d of the source / drain region 150d may be formed to fill the recessed region RC.

[0130] The second epitaxial layer 154d may be grown from the first epitaxial layer 152d and the active region 105 using a SEG process and may be formed as an in-situ doped semiconductor layer, such as a SiP layer. The concentration of phosphorus (P) included in the second epitaxial layer 154d may be higher than the concentration of arsenic (As) or phosphorus (P) included in the first epitaxial layer 152d. Thus, the source / drain region 150d may be formed.

[0131] The second epitaxial layer 154d may have a form similar to an ellipse together with the first epitaxial layer 152d, and the upper surface of the second epitaxial layer 154d may be planar. The second epitaxial layer 154d may fill the space between the first epitaxial layers 152d disposed up and down in the z direction, and may fill the space between the first epitaxial layers 152d on both side surfaces of the recessed region RC in the x direction. The second epitaxial layer 154d may contact the active region 105 in the central region of the source / drain region 150d. The second epitaxial layer 154d may be formed after removing the first epitaxial layer 152d from the central region of the source / drain region 150d, the function of the first channel layer 141 as a channel region may be ensured, and the volume of the second epitaxial layer 154d may be relatively increased, so that the electrical performance of the semiconductor device may be improved.

[0132] In the source / drain region 150d, the first epitaxial layer 152d and the second epitaxial layer 154d may be epitaxially grown. For example, in the source / drain region 150d formed by the above process, the boundary between the first epitaxial layer 152d and the second epitaxial layer 154d may not be obvious in a microscope image. The compositions of the first epitaxial layer 152d and the second epitaxial layer 154d may be different from each other, and the first epitaxial layer 152d and the second epitaxial layer 154d may be substantially distinguished by analysis such as transmission electron microscope energy dispersive X-ray spectroscopy (TEM-EDX) analysis.

[0133] Reference Figure 14K , the interlayer insulating layer 190 may be formed, and the sacrificial layer 120 and the sacrificial gate structure 170 may be removed.

[0134] The interlayer insulating layer 190 may be formed by forming an insulating film covering the sacrificial gate structure 170 and the source / drain regions 150 d and performing a planarization process.

[0135] The sacrificial layer 120 and the sacrificial gate structure 170 may be selectively removed relative to the gate spacer layer 164, the interlayer insulating layer 190, and the channel structure 140. The upper gap region UR may be formed by removing the sacrificial gate structure 170, and the lower gap region LR may be formed by removing the sacrificial layer 120 exposed by the upper gap region UR. For example, when the sacrificial layer 120 includes silicon germanium (SiGe) and the channel structure 140 includes silicon (Si), the sacrificial layer 120 may be selectively removed by performing a wet etching process using peracetic acid as an etchant. During the removal process, the source / drain region 150d may be protected by the interlayer insulating layer 190 and the inner spacer layer 130.

[0136] Reference Figure 14L , the gate structure 160a may be located in the upper gap region UR and the lower gap region LR.

[0137] The gate dielectric layer 162 may conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. The gate electrode 165 may completely fill the upper gap region UR and the lower gap region LR, and may be removed to a certain depth from the upper portion of the upper gap region UR. The gate capping layer 166 may be formed in the region of the upper gap region UR where the gate electrode 165 has been removed. For example, a gate structure 160a including a gate dielectric layer 162, a gate electrode 165, a gate spacer layer 164, and a gate capping layer 166 may be formed.

[0138] Return to reference Figure 8 , a contact plug 180 may be formed.

[0139] The contact hole may be formed by patterning the interlayer insulating layer 190, and the contact plug 180 may be formed by filling the contact hole with a conductive material. The lower surface of the contact hole may be recessed or extended into the source / drain region 150d, or may have a curved portion formed along the upper surface of the source / drain region 150d. In one embodiment, the shape and position of the contact plug 180 may be changed.

[0140] As a summary and review, in order to overcome the limitations of operating performance of planar metal oxide semiconductor FETs (MOSFETs) with reduced size, semiconductor devices including FinFETs may have three-dimensional channels.

[0141] According to the aforementioned exemplary embodiments, by controlling the structure of the source / drain regions, a semiconductor device having improved electrical performance may be provided.

[0142] One or more embodiments may provide a semiconductor device having improved electrical performance.

[0143] According to an embodiment, the first impurity may include an element having a size larger than that of an element of the second impurity. For example, diffusion of the second impurity may be more effectively prevented, thereby preventing a short channel effect.

[0144] Exemplary embodiments have been disclosed herein, and although specific terms are employed, these terms should be used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art at the time of filing this application that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly stated otherwise. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: an active region extending along a first direction on the substrate; a plurality of channel layers on the active region, the plurality of channel layers being spaced apart from each other in a third direction perpendicular to the first direction; a gate structure on the substrate intersecting with the active region and extending along a second direction, wherein the gate structure surrounds the plurality of channel layers; as well as a source / drain region on the active region on at least one side of the gate structure, The source / drain region comprises: a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling spaces between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type, The plurality of first epitaxial layers are on side surfaces of the plurality of channel layers and are spaced apart from each other in the third direction.

2. The semiconductor device according to claim 1, wherein: Each of the plurality of first epitaxial layers includes a first concentration of the first impurity; and The second epitaxial layer includes the second impurity at a second concentration, the second concentration being higher than the first concentration.

3. The semiconductor device according to claim 1, wherein: The first impurity includes arsenic As, and The second impurity includes phosphorus (P).

4. The semiconductor device according to claim 1, wherein: The plurality of first epitaxial layers are SiAs layers, and The second epitaxial layer is a SiP layer.

5. The semiconductor device according to claim 1, wherein: The active region includes a doped region in contact with the plurality of first epitaxial layers, the doped region includes the first impurity, and The doping regions are spaced apart from each other in the first direction.

6. The semiconductor device according to claim 5, wherein: Each of the plurality of first epitaxial layers includes the first impurity at a first concentration, and Each of the doping regions includes the first impurity at a third concentration, the third concentration being lower than the first concentration.

7. The semiconductor device according to claim 1, wherein: The active region includes a recessed region, the recessed region being recessed from an upper surface of the active region at the at least one side of the gate structure, and The source / drain region is located in the recessed region.

8. The semiconductor device according to claim 7, wherein: The plurality of first epitaxial layers are located on each of two sidewalls of the recessed region, and The second epitaxial layer fills the remaining portion of the recessed region.

9. The semiconductor device according to claim 1, wherein: The plurality of first epitaxial layers further include the second impurity, and The second epitaxial layer also includes the first impurity. 10 . The semiconductor device according to claim 9 , wherein a concentration of the first impurity in the plurality of first epitaxial layers, the second epitaxial layer, and the active region has a maximum value in the plurality of first epitaxial layers.

11. The semiconductor device according to claim 1, wherein the plurality of first epitaxial layers comprises: first regions respectively on the side surfaces of the plurality of channel layers, the first regions being spaced apart from each other in the third direction, and A second region is spaced apart from the first region and is on the active region at a lower end of the source / drain region. 12 . The semiconductor device according to claim 1 , wherein the plurality of first epitaxial layers continuously extend along sides of the plurality of channel layers on the active region.

13. A semiconductor device comprising: an active region extending along a first direction on the substrate; a plurality of channel layers on the active region, the plurality of channel layers being spaced apart from each other in a third direction perpendicular to the first direction; a gate structure on the substrate intersecting the active region and the plurality of channel layers and extending along a second direction, the gate structure surrounding the plurality of channel layers; as well as a source / drain region on the active region on at least one side of the gate structure, the source / drain region being in contact with the plurality of channel layers, The source / drain region comprises: a plurality of first epitaxial layers on side surfaces of the plurality of channel layers in the first direction, each of the plurality of first epitaxial layers including a first impurity of a first conductivity type; as well as a second epitaxial layer filling spaces between the plurality of first epitaxial layers and including second impurities of the first conductivity type, The plurality of first epitaxial layers are spaced apart from each other in the third direction. 14 . The semiconductor device according to claim 13 , wherein the second epitaxial layer extends between the plurality of first epitaxial layers spaced apart from each other in the third direction.

15. The semiconductor device according to claim 13, further comprising inner partition wall layers on both sides of the gate structure on the lower surface of each of the plurality of channel layers, The plurality of first epitaxial layers protrude toward the second epitaxial layer in the first direction relative to a side surface formed by the inner partition wall layer and the channel layer.

16. A semiconductor device comprising: An active structure extending along a first direction on the substrate and having a channel region; a gate structure intersecting the channel region and extending along a second direction; as well as The source / drain regions on both sides of the gate structure, Each of the source / drain regions comprises: a plurality of first epitaxial layers spaced apart from each other in the first direction and comprising a first impurity at a first concentration; and a second epitaxial layer filling spaces between the plurality of first epitaxial layers and comprising a second impurity at a second concentration, the second concentration being higher than the first concentration, The active structure includes a doped region in contact with the plurality of first epitaxial layers, the doped region includes the first impurities and is spaced apart from each other in the first direction. 17 . The semiconductor device according to claim 16 , wherein the first impurity and the second impurity have the same conductivity type.

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