Plasma processing method and plasma processing device

Abstract

A plasma processing method and a plasma processing apparatus are provided. In the plasma processing method, a substrate is loaded onto a lower electrode in a chamber. Plasma power is applied to form plasma in the chamber. A non-sinusoidal voltage function having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting the slope of the ramp portion and setting the duration ratio of the ramp portion to the cycle of the voltage function to control the ion energy distribution generated at the surface of the substrate. The non-sinusoidal bias power is applied to the lower electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0003085 filed on January 10, 2019, in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Example embodiments relate to a plasma processing method and a plasma processing apparatus. For example, example embodiments relate to a plasma processing method for etching an object layer on a substrate using plasma and a plasma processing apparatus for performing the plasma processing method. The present disclosure also relates to a method for manufacturing a semiconductor device using a plasma processing apparatus and / or a plasma processing method. Background Art

[0004] Various types of semiconductor devices are manufactured using plasma-based etching techniques. For example, a plasma etching device such as an inductively coupled plasma etching device can generate plasma in a chamber to perform an etching process. However, as the patterns of semiconductor devices become smaller, the uniformity control of the patterns becomes more difficult. In order to improve the etching uniformity between fine recessed patterns in a cell area, more precise plasma control may be beneficial. Summary of the invention

[0005] Example embodiments provide a plasma processing method capable of improving etching performance.

[0006] Example embodiments provide a plasma processing apparatus for performing the plasma processing method.

[0007] According to an example embodiment, in a plasma processing method, a substrate is loaded onto a lower electrode in a chamber. Plasma power is applied to form plasma in the chamber. A non-sinusoidal voltage function having a DC pulse portion and a ramp portion is generated. Generating the voltage function includes setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function to control an ion energy distribution generated at a surface of the substrate. The non-sinusoidal bias power is applied to the lower electrode.

[0008] According to an example embodiment, in a plasma processing method, a semiconductor substrate is loaded onto a lower electrode in a chamber, the semiconductor substrate including a photoresist pattern having an opening. Plasma power is applied to form plasma in the chamber. A non-sinusoidal voltage function having a DC pulse portion and a ramp portion is generated. Generating the voltage function includes setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function to reduce etching differences between different openings to be formed on the semiconductor substrate. The non-sinusoidal bias power is applied to the lower electrode.

[0009] According to example embodiments, a plasma processing apparatus includes: a chamber; a substrate stage configured to support a substrate in the chamber, the substrate stage including a lower electrode; an upper electrode disposed above the lower electrode to face the substrate; a plasma power supply configured to apply plasma power to the upper electrode to form plasma in the chamber; a bias power supply configured to apply a non-sinusoidal bias power having a DC pulse portion and a ramp portion to the lower electrode in response to a bias power control signal; and a controller configured to determine a slope of the ramp portion and a duration ratio of the ramp portion to a cycle of the bias power so that an ion energy distribution is generated at a surface of the substrate, and output the bias power control signal to the bias power supply corresponding to the determined non-sinusoidal bias power.

[0010] According to example embodiments, in a plasma processing method and in a plasma processing apparatus, a bias power of a non-sinusoidal wave having a DC pulse portion and a ramp portion may be applied to a lower electrode. The slope of the ramp portion and the duration ratio of the ramp portion to the non-sinusoidal wave may be adjusted to obtain a desired / appropriate ion energy distribution at the surface of the substrate and minimize IC load. In addition, the on / off duty ratio of the non-sinusoidal wave may be adjusted to improve the IC load.

[0011] Therefore, the non-sinusoidal voltage function can be adjusted to obtain the desired / appropriate process conditions, thereby improving etching performance, such as etching rate, etching selectivity, IC load, ion flux, UPEH (Uni-Purpose Equipment Per Hour), etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 14 represents non-limiting example embodiments described herein.

[0013] Figure 1 is a block diagram illustrating a plasma processing apparatus according to example embodiments.

[0014] Figure 2 It shows Figure 1 FIG. 1 is a view of plasma generated within a chamber of a plasma processing apparatus.

[0015] Figure 3 It is shown by Figure 1 A waveform diagram of a sinusoidal wave power signal generated by a plasma power supply of a plasma processing device.

[0016] Figure 4 It shows Figure 1 Block diagram of a bias power supply for a plasma processing apparatus.

[0017] Figure 5 It is shown by Figure 1 FIG. 1 is a waveform diagram of a non-sinusoidal power signal generated by a bias power supply of a plasma processing device.

[0018] Figure 6 is a flowchart illustrating a plasma processing method according to example embodiments.

[0019] Figure 7 is a flow chart illustrating steps of applying bias power having a non-sinusoidal voltage waveform according to an example embodiment.

[0020] FIG. 8A to FIG. 8D is a graph showing a voltage induced in a substrate according to a slope of a ramp portion of a non-sinusoidal voltage waveform.

[0021] Fig. 9 is a graph showing ion energy distribution according to the slope of the ramp portion.

[0022] Fig.10 is a graph showing the IC load according to the voltage value of the slope portion.

[0023] Fig.11 is a graph showing a duration ratio of a ramp portion according to an example embodiment.

[0024] Fig.12 It shows that according to Fig.11 A graph showing the duration of the ramp portion versus the etch rate difference (IC load).

[0025] Fig.13 is a graph showing the on / off duty ratio of a non-sinusoidal voltage waveform.

[0026] Fig.14 is a cross-sectional view illustrating a method of forming a pattern of a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0027] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram illustrating a plasma processing apparatus according to example embodiments. Figure 2 It shows Figure 1 FIG. 1 is a view of plasma generated within a chamber of a plasma processing apparatus. Figure 3 It is shown by Figure 1 A waveform diagram of a sinusoidal wave power signal generated by a plasma power supply of a plasma processing device. Figure 4 It shows Figure 1 Block diagram of a bias power supply for a plasma processing apparatus. Figure 5 It is shown by Figure 1 FIG. 1 is a waveform diagram of a non-sinusoidal power signal generated by a bias power supply of a plasma processing device.

[0029] Reference Figures 1 to 5 The plasma processing apparatus 10 may include a chamber 20, a substrate stage, an upper electrode 50, a plasma power supply 51, a bias power supply 41, and a controller 80. The plasma processing apparatus 10 may also include a gas supply unit, an exhaust unit 26, etc. The substrate stage may include a lower electrode 40, an electrostatic chuck 30, and / or a heater 32.

[0030] In an example embodiment, the plasma processing apparatus 10 may be an apparatus configured to etch a layer on a substrate such as a semiconductor wafer W disposed in an inductively coupled plasma (ICP) chamber 20. However, the plasma generated by the plasma processing apparatus may not be limited to inductively coupled plasma, for example, the plasma processing apparatus may generate capacitively coupled plasma (CCP), microwave plasma, etc. For example, the plasma processing apparatus 10 may include one of an ICP chamber, a CCP chamber, and a microwave plasma chamber, which include components different from each other. The plasma processing apparatus may not be limited to an etching apparatus, for example, the plasma processing apparatus may be a deposition apparatus, a cleaning apparatus, etc. Here, the substrate may include a semiconductor substrate, a glass substrate, etc.

[0031] The chamber 20 may provide a sealed space for performing a plasma etching process on the wafer W. The chamber 20 may be a cylindrical vacuum chamber. The chamber 20 may include a metal such as aluminum, stainless steel, or the like.

[0032] A substrate stage may be arranged in the chamber 20 to support a substrate. For example, the substrate stage may be used as a susceptor for supporting a wafer W thereon. The substrate stage may include an electrostatic chuck 30 for holding the wafer W using an electrostatic force. When direct current is applied to the electrostatic chuck 30 by a DC (direct current) power supply (not shown), the wafer W may be adsorbed and held on the electrostatic chuck 30.

[0033] The lower electrode 40 included in the substrate stage may have a circular plate shape, and the lower electrode 40 may be disposed below the electrostatic chuck 30. The lower electrode 40 may be supported by the driving part 34 so that the lower electrode 40 may move upward and downward. For example, the lower electrode 40 and / or the substrate stage may be moved upward and downward by the driving part 34.

[0034] The wafer W may be mounted on the upper surface of the electrostatic chuck 30, and a focusing ring (not shown) may be mounted on the substrate stage to surround the wafer W. The diameter of the lower electrode 40 may be greater than the diameter of the wafer W. The lower electrode 40 may have a cooling channel (not shown) therein. In order to improve the control accuracy of the wafer temperature, a heat transfer gas such as He gas may be supplied to the gap between the electrostatic chuck 30 and the wafer W.

[0035] An access port (not shown) for loading / unloading the wafer W may be provided at a side wall of the chamber 20. The wafer W may be loaded / unloaded onto / from the substrate stage through the access port.

[0036] An exhaust port 24 may be provided in the bottom of the chamber 20. An exhaust unit 26 may be connected to the exhaust port 24 through an exhaust line. The exhaust unit may include a vacuum pump such as a turbomolecular pump to control the pressure of the chamber 20 so that the processing space in the chamber 20 may be decompressed to a desired / appropriate / predetermined vacuum level. In addition, process byproducts and residual process gases may be exhausted through the exhaust port 24.

[0037] The chamber 20 may include a lid 22 covering the upper portion of the chamber 20. The lid 22 may hermetically seal the upper portion of the chamber 20. The upper electrode 50 may be disposed outside the chamber 20 such that the upper electrode 50 faces / opposes the lower electrode 40. The upper electrode 50 may be disposed on the lid 22. The upper electrode 50 may include an RF antenna. The RF antenna may have a planar coil shape. For example, the RF antenna may have a spiral shape originating from the center of the upper surface of the lid 22 and moving away as it rotates around the center of the upper surface of the lid 22. The lid 22 may include a circular plate dielectric window. The dielectric window may include a dielectric material. For example, the dielectric window may include aluminum oxide (Al2O3). 2 O 3 ). The electromagnetic signal generated from the plasma power supply 51 can be transmitted from the antenna to the chamber 20 through the dielectric window.

[0038] For example, the upper electrode 50 may include an inner coil 50a and an outer coil 50b. The inner coil 50a and the outer coil 50b may have a spiral shape or a coaxial shape. The inner coil 50a and the outer coil 50b may generate an inductively coupled plasma in the plasma space P of the chamber 20. Herein, two coils 50a and 50b may be exemplarily described, however, it is understood that the number, arrangement, etc. of the coils may not be limited thereto.

[0039] In example embodiments, the gas supply unit may include gas supply lines 60a, 60b, a flow controller 62, and a gas source 64 (e.g., a gas reservoir). For example, the gas supply unit may refer to a group of gas supply elements. The gas supply lines 60a, 60b may be connected to the upper portion and / or the side of the chamber 20 to supply gas into the chamber 20 therethrough. For example, the gas supply lines may include a vertical gas supply line 60a connected to the chamber 20 through the lid 22 and a horizontal gas supply line 60b connected to the chamber 20 through the sidewall of the chamber 20. Various gases may be supplied to the plasma space P of the chamber 20 through the vertical gas supply line 60a and the horizontal gas supply line 60b.

[0040] The gas supply unit can supply different gases with a desired / predetermined mixing ratio. The gas source 64 can store gas and can supply gas separately through a plurality of gas lines connected to the gas supply lines 60a, 60b. The flow controller 62 can control the amount of gas supplied to the chamber 20 through the gas supply lines 60a, 60b. The flow controller 62 can independently or jointly control the supply amount of gas supplied to the vertical gas supply line 60a and the horizontal gas supply line 60b, respectively. For example, the gas source 64 may include a plurality of gas tanks, and the flow controller 62 may include a plurality of mass flow controllers (MFCs) corresponding to the gas tanks (e.g., connected to the gas tanks, respectively). The mass flow controllers can independently control the supply amount of the gas, respectively.

[0041] The gas supply unit may supply various process gases into the chamber 20. The process gas may include an inert gas.

[0042] In example embodiments, the plasma power supply 51 may apply plasma source power to the upper electrode 50. The plasma power supply 51 may apply sinusoidal wave power to the upper electrode 50 to form plasma in the chamber 20. The bias power supply 41 may apply bias source power to the lower electrode 40. The bias power supply 41 may apply non-sinusoidal wave power to the lower electrode 40.

[0043] The controller 80 may be connected to the plasma power supply 51 and the bias power supply 41, and may control the operation of the plasma power supply 51 and the bias power supply 41. The controller 80 may include a microcomputer and various interface circuits, and may control the operation of the plasma processing apparatus based on a program and recipe information stored in an external memory or an internal memory.

[0044] For example, the controller 80 may be a computer (or several interconnected computers) command, and include, for example, one or more processors configured by software (e.g., CPU (central processing unit), controller, etc.) forming various functional modules of the computer. The computer may be a general-purpose computer, or may be dedicated hardware or firmware (e.g., an electronic circuit or optical circuit such as dedicated hardware, such as a digital signal processor (DSP) or a field programmable gate array (FPGA)). The computer may be configured by several interconnected computers. Each functional module (or unit) described herein may include a separate computer, or some or all functional modules (or units) may be composed of and share the hardware of the same computer. The connections and interactions between the units described herein may be hardwired and / or in the form of data (e.g., as data stored in and retrieved from the computer's memory (e.g., registers, buffers, cache memory, storage drives, etc.)), such as part of an application program interface (API). As understood, "software" refers to prescribed rules for operating a computer, such as code or scripts.

[0045] For example, the plasma power supply 51 may include a radio frequency (RF) power supply 54 as a plasma source element and an RF matcher 52. The RF power supply 54 may generate an RF signal. The RF matcher 52 may use coils 50a and 50b to match the impedance of the RF signal generated by the RF power supply 54 to control the generation of plasma.

[0046] The plasma power supply 51 may apply a radio frequency power signal to the upper electrode 50 in response to the plasma power control signal. For example, radio frequency power having a frequency range of about 13 MHz to about 2.45 GHz and an RF power range of about 100 W to about 1000 W may be generated.

[0047] When radio frequency power having a predetermined frequency (eg, 13.56 MHz) is applied to the upper electrode 50 , an electromagnetic field induced by the upper electrode 50 may be applied to a source gas supplied within the chamber 20 to generate plasma.

[0048] The bias power supply 41 may apply a bias power signal to the lower electrode 40 in response to the bias power control signal. The bias power supply 41 may include various circuits configured to generate a pulse signal having a non-sinusoidal voltage waveform and supply / output a compensation current, and may apply a bias power having a desired / predetermined non-sinusoidal voltage waveform to the lower electrode 40.

[0049] The voltage waveform of the bias power signal applied by the bias power supply 41 can be controlled so that a desired / predetermined voltage and a predetermined ion energy distribution can be generated in the surface of the wafer W, and a desired / predetermined ion flux and a predetermined etching rate can be obtained.

[0050] like Figure 4 As shown in the figure, the bias power supply 41 may include a DC power generator 44 and a modulator 42. The modulator 42 may include a pulse adjustment part 42a and a slope adjustment part 42b. The modulator 42 may also include a filtering part 42c. Although not shown in the figure, the output part of the modulator 42 may be connected to an output (V / I) sensor. The V / I sensor may detect the voltage value and the current value of the bias power signal applied to the lower electrode 40, and the controller 80 may receive the detected value and may monitor and control the bias power signal.

[0051] like Figure 5 As shown in , the power signal applied to the lower electrode 40 may have a non-sinusoidal voltage waveform. The bias power signal output from the bias power supply 41 may have a first portion S1, a second portion S2, a third portion S3, and a fourth portion R within one cycle / cycle of the bias power signal. The first portion S1, the second portion S2, and the third portion S3 may constitute a DC pulse portion S, and the fourth portion R may constitute a ramp portion. For example, the second portion S2 may be a DC signal portion, and the first portion S1 and the third portion S3 may be transition portions. For example, the first portion S1 may be a transition portion rising from the ramp portion R to the DC signal portion S2, and the third portion S3 may be a transition portion falling from the DC signal portion S2 to the ramp portion R. For example, the ramp portion R may be located between the DC pulses S. The ramp portion R may be a portion modulated by the ramp adjustment portion 42b, and may have a waveform that gradually decreases over time, while decreasing from the maximum value of the ramp portion R to the minimum value of the ramp portion R. For example, the ramp portion R may have a negative slope. For example, the slope portion R may continuously decrease in negative increments throughout the slope portion R.

[0052] The modulator 42 can adjust the positive voltage value (V1) of the DC pulse part S, the negative voltage value (V2) of the DC pulse part S, the voltage value (V3) of the ramp part R, the slope (dV / dt) of the ramp part R, the duration (t1) of the ramp part R (ratio (t1 / t2)), the on / off duty cycle of the non-sinusoidal wave, etc. in response to the bias power control signal from the controller 80.

[0053] For example, the frequency of the DC pulse portion S can be adjusted within the range of 100kHz to 400kHz. The positive voltage value (V1) of the DC pulse portion S can be adjusted within the range of 0V to 600V. The negative voltage value (V2) of the DC pulse portion S can be adjusted within the range of 0V to -700V. The voltage value (V3) of the ramp portion R can be adjusted within the range of -100V to -800V. The time ratio (t1 / t2) of the ramp portion R within one cycle / cycle of the bias power signal (for example, the duration ratio of the ramp portion R) can be adjusted within the range of 20% to 80%. The on / off frequency of the non-sinusoidal wave within the process cycle / cycle can be adjusted within the range of 10Hz to 1000Hz. The on / off duty cycle of the non-sinusoidal wave within the process cycle / cycle can be adjusted within the range of 5% to 95%.

[0054] The slope of the ramp portion R of the non-sinusoidal wave can be adjusted to have a desired / predetermined voltage in the substrate surface, so as to produce a desired / predetermined ion energy distribution on the substrate, for example. The slope of the ramp portion R can be adjusted to produce an ion energy distribution with a narrow single peak. For example, the slope of the ramp portion R can help to achieve a narrow single peak of ion energy distribution, for example, a low deviation of ion energy distribution on the substrate. For example, the ion energy distribution on the substrate can depend on the slope of the ramp portion R of the bias power signal. The low deviation narrow peak ion energy distribution can help the etching process to achieve a uniform pattern on the substrate. The duration of the ramp portion R can be adjusted to control the ion flux, so as to improve the etching depth difference between the openings (with different widths) in the unit area, for example, the intra-unit (IC) load. For example, the IC load in the present disclosure can refer to a non-uniform pattern formed in a unit area of ​​a semiconductor device caused by different etching rates between different pattern widths, or the IC load can be a phenomenon that the etching rate depends on the pattern width. The non-sinusoidal on / off duty cycle within a process period / cycle can be adjusted to improve IC loading and UPEH (Uni Equipment Production Per Hour). Thus, the controllability of the etching profile for forming holes with high aspect ratios can be improved.

[0055] Although not shown in the figure, the bias power supply 41 may also include a sinusoidal power supply configured to apply sinusoidal power to the lower electrode 40. In addition, the bias power supply 41 may also include a switch portion configured to simultaneously or selectively select non-sinusoidal power and sinusoidal power from the sinusoidal power supply, and apply the non-sinusoidal power and the sinusoidal power from the sinusoidal power supply to the lower electrode 40. The switch portion may be installed between the sinusoidal power supply and the lower electrode 40 to selectively apply sinusoidal power or non-sinusoidal power. For example, when sinusoidal power and non-sinusoidal power are simultaneously applied to the lower electrode 40, the power applied to the lower electrode 40 may have a composite waveform of the sinusoidal power and the non-sinusoidal power.

[0056] In an example embodiment, the plasma processing apparatus 10 may include a temperature control device located in the substrate stage. The temperature control device may include a heater and / or a cooler. For example, the temperature control device may include a heater 32, a heater power supply 70, and a filter 72, wherein the heater 32 is used in the electrostatic chuck 30 to control the temperature of the electrostatic chuck 30, the heater power supply 70 is configured to supply power to the heater 32, and the filter 72 is disposed between the heater 32 and the heater power supply 70.

[0057] In the following, we will explain the use of Figure 1 A method for processing a substrate using a plasma processing device.

[0058] Figure 6 is a flowchart illustrating a plasma processing method according to example embodiments.

[0059] Reference Figure 1 and Figure 6 , after loading a substrate into the inductively coupled plasma chamber 20 ( S100 ), a process gas may be supplied onto the substrate within the chamber 20 ( S110 ).

[0060] For example, a semiconductor wafer W may be loaded on an electrostatic chuck 30 of a substrate stage within the chamber 20. Process gas (e.g., etching process gas) may be introduced into the chamber 20 through gas supply lines 60a, 60b, and the pressure of the chamber 20 may then be controlled to a desired / predetermined vacuum level through the exhaust unit 26.

[0061] Then, plasma power may be applied to the upper electrode 50 to generate plasma within the chamber 20 ( S120 ), and bias power may be applied to the lower electrode 40 ( S130 ) to perform an etching process on the object layer on the substrate ( S140 ).

[0062] The plasma power supply 51 may apply a radio frequency power signal to the upper electrode 50 in response to a plasma power control signal from the controller 80. For example, when radio frequency power having a predetermined frequency (e.g., 13.56 MHz) is applied to the upper electrode 50, an electromagnetic field induced by the upper electrode 50 may be applied to the source gas in the chamber 20 to generate plasma.

[0063] The bias power supply 41 may apply a bias power signal (e.g., having a non-sinusoidal voltage waveform) to the lower electrode 40 in response to a bias power control signal from the controller 80. In some embodiments, the bias power supply 41 may apply a bias power signal having a sinusoidal voltage waveform as well as a bias power signal having a non-sinusoidal voltage waveform, or apply a bias power signal having a sinusoidal voltage waveform instead of a bias power signal having a non-sinusoidal voltage waveform.

[0064] When the bias power having a non-sinusoidal voltage waveform is applied to the lower electrode 40, an ion energy distribution having a relatively narrow single peak can be generated in the surface of the wafer W. Therefore, the controllability of the etching profile for forming a hole having a high aspect ratio can be improved. For example, the narrow single peak ion energy distribution can be conducive to achieving a uniform etching rate over the entire surface of the wafer W.

[0065] In the following, it will be explained Figure 6 A bias power applying step in the plasma processing method.

[0066] Figure 7 is a flow chart illustrating steps of applying bias power having a non-sinusoidal voltage waveform according to an example embodiment. FIG. 8A to FIG. 8D is a graph showing a voltage induced in a substrate according to a slope of a ramp portion of a non-sinusoidal voltage waveform. Fig. 9 is a graph showing ion energy distribution according to the slope of the ramp portion. Fig.10 is a graph showing the IC load according to the voltage value of the slope portion. Fig.11 is a graph showing a duration ratio of a ramp portion according to an example embodiment. Fig.12 It shows that according to Fig.11 A graph showing the duration of the ramp portion versus the etch rate difference (IC load). Fig.13 is a graph showing the on / off duty ratio of a non-sinusoidal voltage waveform.

[0067] Reference Figure 1 , Figure 4 , Figure 5 and Figure 7 , first, a non-sinusoidal voltage function (eg, a waveform) having a DC pulse portion S and a ramp portion R may be generated ( S131 ).

[0068] The bias power supply 41 may generate and mix / combine / synthesize a switching (DC) signal to output a non-sinusoidal voltage function having a DC pulse portion S and a ramp portion R. The ramp portion R may be a portion modulated by the ramp adjustment portion 42 b, and may have a waveform that gradually decreases over time while decreasing from a maximum value of the ramp portion R to a minimum value of the ramp portion R. For example, the ramp portion R may have a negative slope over the entire ramp portion R, for example.

[0069] The output non-sinusoidal voltage function may then be monitored by an output (V / I) sensing portion of the modulator 42 and may be adjusted based on process conditions within the plasma chamber 20 .

[0070] The pulse adjustment part 42a and the slope adjustment part 42b of the modulator 42 can be used to adjust the frequency of the non-sinusoidal voltage function, the positive voltage value (V1) of the DC pulse part S, the negative voltage value (V2) of the DC pulse part S and the voltage value (V3) of the slope part R.

[0071] For example, the frequency of the DC pulse portion S can be adjusted within a range of 100kHz to 400kHz. The positive voltage value (V1) of the DC pulse portion S can be adjusted within a range of 0V to 600V. The negative voltage value (V2) of the DC pulse portion S can be adjusted within a range of 0V to -700V. The voltage value (V3) of the ramp portion R can be adjusted within a range of -100V to -800V.

[0072] In example embodiments, a slope of the slope portion R may be determined based on a voltage to be induced in the substrate ( S132 ).

[0073] As in FIG. 8A to FIG. 8D As shown in FIG. 1 , the voltage Vs induced in the surface of the wafer W can be controlled by the negative slope of the ramp portion R. The slope of the ramp portion R (curve P3) can be selected so that the voltage Vs induced in the surface of the wafer W has a desired / predetermined constant value. The slope of the voltage ramp portion R can be adjusted to prevent the wafer surface from being positively charged with positive ions. For example, the slope of the voltage ramp portion R can be adjusted to compensate for the accumulation of positive ions on the wafer surface.

[0074] like Fig. 9 As shown in , the ion energy distribution on the wafer W can be controlled by the negative slope of the ramp portion R. The slope of the ramp portion R (curve P3) can be selected so that the ion energy distribution has a narrow single peak. The slope of the ramp portion R can be adjusted to control the ion energy distribution in the surface of the wafer W.

[0075] like Fig.10As shown in , the etching depth difference between openings with different sizes (widths) in the cell area, for example, IC (in-cell) load, can be improved by the voltage value (V3) of the slope portion R. After determining the slope of the slope portion R, the voltage value (V3) of the slope portion R that can minimize the IC load can be selected. When the slope of the slope portion R is maintained at a determined value, the voltage value V3 of the slope portion R can be adjusted to improve the IC load.

[0076] Then, a duration ratio of the ramp portion R may be determined based on the IC load (S133).

[0077] like Fig.11 As shown in , the time ratio (t1 / t2) of the ramp portion R to the cycle of the voltage function within one period / cycle of the non-sinusoidal voltage function, for example, the duration ratio of the ramp portion R to the cycle of the non-sinusoidal wave can be adjusted. The duration ratio of the ramp portion R to the corresponding period / cycle can be adjusted within a range of 20% to 80%. When the slope of the ramp portion R is maintained at a certain value, the duration ratio of the ramp portion R can be adjusted. For example, when one cycle (t2) is 2.5μs, curve G1 may represent the case where the duration ratio of the slope portion R is adjusted to 30% (the duration (t1) of the slope portion R is 0.75μs), curve G2 may represent the case where the duration ratio of the slope portion R is adjusted to 40% (the duration (t1) of the slope portion R is 1.0μs), curve G3 may represent the case where the duration ratio of the slope portion R is adjusted to 50% (the duration (t1) of the slope portion R is 1.25μs), and curve G4 may represent the case where the duration ratio of the slope portion R is adjusted to 70% (the duration (t1) of the slope portion R is 1.75μs).

[0078] like Fig.12 As shown in , the etching rate difference between openings with different sizes in the unit area, for example, IC load, can be controlled according to the duration ratio of the slope portion R. The duration ratio of the slope portion R that can minimize the IC load can be selected (70%, curve G3). The duration ratio of the slope portion R can be adjusted to improve the IC load.

[0079] Then, the on / off duty ratio of the non-sinusoidal wave may be determined based on the ion flux (S134).

[0080] like Fig.13As shown in , the on / off duty ratio of the non-sinusoidal wave within a process period / cycle can be adjusted within a range of 5% to 95%. For example, the on / off duty ratio of the non-sinusoidal wave can be adjusted within a range of 50% to 80%. The on / off duty ratio of the non-sinusoidal wave can be adjusted to effectively remove gases and process byproducts within the pattern (opening) formed during the etching process.

[0081] Then, the bias power having the determined voltage waveform may be output (S135).

[0082] As described above, the slope of the ramp portion R of the non-sinusoidal wave can be adjusted to have a desired / appropriate / predetermined voltage in the substrate surface, thereby producing a desired / appropriate / predetermined ion energy distribution in the substrate surface. The slope of the ramp portion R can be adjusted to produce an ion energy distribution with a narrow single peak. The duration of the ramp portion R can be adjusted to control the ion flux, thereby improving the etching depth difference between openings of different sizes in the unit area, for example, IC load. The on / off duty cycle of the non-sinusoidal wave within the process cycle / cycle can be adjusted to improve the IC load. Therefore, the controllability of the etching profile for forming a hole with a high aspect ratio can be improved.

[0083] In the following, we will explain the use of Figure 6 and Figure 7 A method for forming a pattern of a semiconductor device by a plasma processing method.

[0084] Fig.14 is a cross-sectional view illustrating a method of forming a pattern of a semiconductor device according to example embodiments.

[0085] Reference Fig.14 After the thin layer 110 and the object layer 120 are sequentially formed on the semiconductor substrate 100 , a photoresist pattern 130 may be formed on the object layer 120 , and an etching process may be performed on the object layer 120 using the photoresist pattern 130 as an etching mask.

[0086] The object layer 120 may include a metal layer, a metal nitride layer, an insulating layer, a semiconductor layer, etc. In some embodiments, the thin layer 110 and the object layer 120 may be omitted, and the semiconductor substrate 100 may be the object layer to be etched.

[0087] For example, the substrate 100 on which the photoresist pattern 130 is formed may be loaded into Figure 1 In the chamber 20 of the plasma processing apparatus 10 in FIG. 1 , a process gas may be supplied onto / over the substrate 100. The process gas (e.g., etching gas) may be introduced into the chamber 20 through gas supply lines 60 a, 60 b, and then the pressure of the chamber 20 may be controlled to a desired / predetermined vacuum level through the exhaust unit 26.

[0088] Then, plasma power may be applied to the upper electrode 50 to generate plasma within the chamber 20 , and bias power may be applied to the lower electrode 40 to perform an etching process.

[0089] Sinusoidal wave power may be applied to the upper electrode 50 to form plasma within the chamber 20 , and non-sinusoidal wave power may be applied to the lower electrode 40 .

[0090] In example embodiments, the photoresist pattern 130 may include a plurality of openings. For example, the openings may have different diameters / widths / lengths. An etching process may be performed to form a first opening 122a having a first diameter / width D1 and a second opening 122b having a second diameter / width D2. For example, the first opening 122a and the second opening 122b may have an aspect ratio of at least 14. The first opening 122a and the second opening 122b may be grooves for forming an isolation layer pattern in a semiconductor substrate. For example, an isolation pattern may be formed in the first opening 122a and the second opening 122b.

[0091] When the first opening 122a and the second opening 122b have different sizes and are formed together in the cell region by an etching process, an etching depth difference (Δh) between the first opening 122a and the second opening 122b may occur, for example, IC load. The non-sinusoidal voltage function may be adjusted to reduce IC load.

[0092] The non-sinusoidal voltage function (e.g., waveform) applied to the lower electrode 40 can be adjusted to improve IC load and UPEH (Uni-Purpose Equipment Production per Hour). For example, an appropriate waveform of the bias voltage can improve the uniformity of the etching rate, thereby increasing the throughput of the etching process. For example, the negative slope of the ramp portion R of the non-sinusoidal voltage function that can minimize the IC load and the duration ratio of the ramp portion R to the cycle of the waveform (e.g., curve G3) can be selected. The slope and duration ratio of the ramp portion R can be adjusted to improve the IC load.

[0093] Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present disclosure will be described.

[0094] According to the method of manufacturing a semiconductor device, one of the above embodiments can be used to set the plasma processing device 10 including the plasma chamber 20 to provide RF power to the upper electrode 50 and bias power to the lower electrode 40. Then, the substrate can be provided in the chamber 20 on the lower electrode 40 (for example, on an electrostatic chuck provided on the lower electrode 40). The substrate can be a semiconductor substrate, such as a crystalline silicon substrate, a crystalline germanium substrate, or a crystalline silicon germanium substrate, and can be in the form of a wafer W. An etching process can be performed on the substrate to form a pattern. The pattern can be a semiconductor pattern, an insulator pattern, or a conductor pattern. Before and / or after performing the etching process, various semiconductor patterns and various conductor patterns can be additionally formed on the substrate to form a circuit including a transistor, a capacitor, and / or a switch through a plurality of manufacturing processes including a plurality of photolithography process steps. For example, when the substrate is provided to the chamber, the substrate can be a bare semiconductor substrate, or one or more layers of patterns and / or films can be formed on the substrate before the substrate is supplied to the plasma processing chamber 20 and a film is formed thereon. The thin film formed on the substrate may be patterned by an etching process performed in the plasma processing chamber 20 to form a portion of a circuit and / or an insulating pattern as a portion of an integrated circuit of a formed semiconductor device. For example, the pattern of the thin film formed in the plasma processing chamber 20 may be a conductor film or an insulator film. After various circuits are formed on the substrate, the resulting wafer including the substrate may be cut and packaged to form a semiconductor device.

[0095] Semiconductor devices manufactured by plasma processing apparatuses and plasma processing methods according to example embodiments may be used in various systems such as computing systems. Semiconductor devices may include finFETs, DRAMs, V-NANDs, etc. Systems may include lighting devices. Systems including semiconductor devices may be applied to computers, portable computers, laptop computers, personal portable terminals, tablet computers, mobile phones, digital music players, etc.

[0096] The foregoing is illustrative of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims.

Claims

1. A plasma treatment method, comprising: loading a substrate onto a lower electrode in a chamber; applying plasma power to form a plasma in the chamber; generating a non-sinusoidal voltage function having a DC pulse portion and a ramp portion, including setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function to control an ion energy distribution generated at the surface of the substrate; as well as applying the non-sinusoidal bias power to the lower electrode, Wherein, setting the slope of the ramp portion and the duration ratio of the ramp portion to the cycle of the voltage function comprises: adjusting the slope of the ramp portion based on a voltage to be induced in the substrate; and The duration ratio of the ramp portion to the cycle of the voltage function is adjusted to reduce etching differences between openings having different sizes to be formed in the substrate.

2. The plasma processing method according to claim 1, wherein: The slope of the ramp portion is set so that a voltage having a constant value is induced in the substrate while the ramp portion of the bias power is applied to the lower electrode.

3. The plasma processing method according to claim 1, wherein: The ratio of the duration of the ramp portion to the cycle of the voltage function is adjusted to minimize the etch differential.

4. The plasma processing method according to claim 1, wherein: The duration ratio of the ramp portion to the cycle of the voltage function is adjusted while maintaining the slope of the ramp portion at a constant value.

5. The plasma processing method according to claim 1, further comprising: The on / off duty cycle of the non-sinusoidal wave is adjusted to control the flux of ions moving toward the substrate.

6. The plasma processing method according to claim 5, wherein: The on / off duty ratio of the non-sinusoidal wave is adjusted within a range of 50% to 80% within one cycle.

7. The plasma processing method according to claim 1, wherein: The waveform of the slope portion has a negative slope throughout the slope portion.

8. The plasma processing method according to claim 1, wherein: Generating the voltage function of the non-sinusoidal wave includes determining a positive voltage value of the DC pulse portion and a voltage value of the ramp portion.

9. The plasma processing method according to claim 1, further comprising: The bias power applied to the lower electrode is monitored.

10. A plasma treatment method, comprising: loading a semiconductor substrate onto the lower electrode in the chamber, the semiconductor substrate comprising a photoresist pattern having an opening; applying plasma power to form a plasma in the chamber; generating a non-sinusoidal voltage function having a DC pulse portion and a ramp portion, including setting a slope of the ramp portion and a duration ratio of the ramp portion to a cycle of the voltage function to reduce etching differences between different openings to be formed on the semiconductor substrate; and The non-sinusoidal bias power is applied to the lower electrode.

11. The plasma processing method according to claim 10, wherein: The duration ratio of the ramp portion to the cycle of the voltage function is set to minimize the etch difference.

12. The plasma processing method according to claim 10, wherein: The slope of the ramp portion is set so that a voltage having a constant value is induced in the semiconductor substrate while the ramp portion of the bias power is applied to the lower electrode.

13. The plasma processing method according to claim 10, wherein: The slope of the slope portion is set so that an ion energy distribution is generated at the surface of the semiconductor substrate.

14. The plasma processing method according to claim 10, wherein: The openings include a first opening having a first diameter and a second opening having a second diameter greater than the first diameter.

15. The plasma processing method according to claim 10, further comprising: The on / off duty ratio of the non-sinusoidal wave is adjusted to control the flux of ions moving toward the semiconductor substrate.

16. The plasma processing method according to claim 15, wherein: The on / off duty ratio of the non-sinusoidal wave is adjusted within a range of 50% to 80% within one cycle.

17. The plasma processing method according to claim 10, wherein: The slope portion has a waveform that gradually decreases throughout the slope portion.

18. The plasma processing method according to claim 10, wherein: Generating the voltage function of the non-sinusoidal wave includes determining a positive voltage value of the DC pulse portion and a voltage value of the ramp portion.

19. The plasma processing method according to claim 10, further comprising: The bias power applied to the lower electrode is monitored.

20. A plasma processing device, comprising: Chamber; a substrate stage configured to support a substrate within the chamber, the substrate stage comprising a lower electrode; an upper electrode, the upper electrode being disposed above the lower electrode to face the substrate; a plasma power supply configured to apply plasma power to the upper electrode to form plasma within the chamber; a bias power supply configured to apply a non-sinusoidal bias power having a DC pulse portion and a ramp portion to the lower electrode in response to a bias power control signal; as well as a controller configured to determine a slope of the ramp portion and a duration ratio of the ramp portion to a cycle of the bias power so as to generate an ion energy distribution at the surface of the substrate, and output the bias power control signal to the bias power supply corresponding to the determined non-sinusoidal bias power, wherein the bias power supply comprises a modulator configured to adjust the DC pulse portion and the ramp portion, and Wherein, the modulator is configured to determine the duration ratio of the ramp portion to the cycle of the bias power to reduce an etching rate difference between openings to be formed on the substrate.

21. The plasma processing apparatus according to claim 20, wherein: The modulator is configured to adjust the slope of the ramp portion so that a voltage induced in the surface of the substrate has a constant value.

22. The plasma processing apparatus according to claim 20, wherein: The modulator is configured such that the duration ratio of the ramp portion to the cycle of the bias power in one cycle is determined to be within a range of 20% to 80%.

23. The plasma processing apparatus according to claim 20, wherein: The modulator is configured to determine an on / off duty cycle of the non-sinusoidal wave based on a flux of ions moving toward the substrate.

24. The plasma processing apparatus according to claim 23, wherein: The modulator is configured such that the on / off duty ratio of the non-sinusoidal wave in one cycle is determined to be within a range of 50% to 80%.

25. The plasma processing apparatus according to claim 20, wherein: The modulator further includes a sensing part configured to detect a voltage value and a current value of the bias power applied to the lower electrode.

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