Cell structure of multi-time programmable memory and manufacturing method thereof

Abstract

The present invention provides a cell structure of a multi-time programmable memory and a manufacturing method thereof, comprising a substrate, a floating gate located on the substrate, a first sidewall located on the sidewall of the floating gate, and a SAB film and a control gate located on the floating gate in sequence, wherein the control gate and the SAB film extend in a direction perpendicular to the thickness of the floating gate to cover part of the first sidewall. In the cell structure of the multi-time programmable memory provided by the present invention, the control gate stores and erases data by coupling with the floating gate, without the need for an additional tunneling area, so that the size of the cell structure of the multi-time programmable memory is reduced, meeting the small size requirements of the MTP device. Furthermore, the SAB film and the control gate extend in a direction perpendicular to the thickness of the floating gate to cover part of the first sidewall, so as to reduce or avoid damage to the first sidewall when etching the SAB film, thereby improving the performance of the multi-time programmable memory.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a cell structure of a multi-time programmable (MTP) memory and a manufacturing method thereof. Background Art

[0002] Memory is an important component of digital integrated circuits, and it is an indispensable part of building microprocessor-based application systems. In recent years, people have embedded various memories inside processors to improve the integration and work efficiency of processors.

[0003] Compared with One Time Program Memory (OTP), Multi-Time Program Memory (MTP) memory has the advantages of being able to store, read, and erase data multiple times, and the stored data will not disappear after power failure. It has gradually become a memory device widely used in personal computers, electronic devices, mobile storage and other fields.

[0004] However, the cell structure of the multi-time programmable memory formed by the conventional method is relatively large in size and its performance is not ideal. Summary of the invention

[0005] The object of the present invention is to provide a cell structure of a multi-time programmable memory and a manufacturing method thereof, so as to reduce the size of the cell structure of the multi-time programmable memory and improve the performance of the multi-time programmable memory.

[0006] To achieve the above object, the present invention provides a cell structure of a multi-time programmable memory, comprising:

[0007] Substrate,

[0008] a floating gate located on the substrate, and a first spacer located on a sidewall of the floating gate; and

[0009] A SAB film and a control gate are sequentially located on the floating gate, and the SAB film and the control gate extend in a direction perpendicular to the thickness of the floating gate to cover a portion of the first sidewall.

[0010] Optionally, it further includes a selection gate located on the substrate, and a second spacer is formed on the sidewall of the selection gate.

[0011] Optionally, an active region is formed in the substrate, and an active doping region and a drain doping region are formed in the active region.

[0012] Optionally, the floating gate and the select gate are located between the source doping region and the drain doping region.

[0013] Optionally, a self-aligned silicide layer is further included, and the self-aligned silicide layer covers the selection gate, the control gate, the source doping region, and the drain doping region.

[0014] Optionally, it also includes an interlayer dielectric layer located on the self-aligned silicide layer and covering the substrate, a conductive plug located in the interlayer dielectric layer and connected to the self-aligned silicide layer, and an electrode structure located on the interlayer dielectric layer and connected to the conductive plug.

[0015] Optionally, a gate oxide layer is formed between the floating gate and the substrate.

[0016] Optionally, the SAB film includes an oxide layer and a nitride layer sequentially stacked on the surface of the floating gate.

[0017] Optionally, both the first side wall and the second side wall have an ONO structure.

[0018] Accordingly, the present invention also provides a method for manufacturing a cell structure of a multi-time programmable memory, comprising:

[0019] providing a substrate;

[0020] forming a floating gate on the substrate, and forming a first spacer on the sidewall of the floating gate; and,

[0021] A SAB film and a control gate are sequentially formed on the floating gate, and the SAB film and the control gate extend in a direction perpendicular to the thickness of the floating gate to cover a portion of the first sidewall spacer.

[0022] Optionally, the method further includes: forming a select gate on the substrate while forming a floating gate on the substrate; and forming a second spacer on the sidewall of the select gate while forming a first spacer on the sidewall of the floating gate.

[0023] Optionally, before forming the floating gate on the substrate, the method further includes: forming a gate oxide layer on the substrate.

[0024] Optionally, after forming a first sidewall spacer on the sidewall of the floating gate and before sequentially forming a SAB film layer and a control gate layer on the substrate, the method further includes: performing ion implantation on the substrate to form a source doping region and a drain doping region.

[0025] Optionally, the SAB film includes an oxide layer and a nitride layer sequentially stacked on the surface of the floating gate, and the first sidewall spacer and the second sidewall spacer both have an ONO structure.

[0026] Optionally, sequentially forming the SAB film and the control gate on the floating gate comprises the following steps:

[0027] forming a SAB thin film material layer and a control gate material layer on the substrate;

[0028] Using a SAB mask, forming a patterned photoresist layer on the control gate material layer;

[0029] The control gate material layer and the SAB film material layer are sequentially etched to sequentially form the SAB film and the control gate on the floating gate.

[0030] Optionally, after forming the SAB film and the control gate on the floating gate, the method further includes:

[0031] Forming a self-aligned silicide layer on the substrate, wherein the self-aligned silicide layer covers the select gate, the control gate, the source doping region, and the drain doping region;

[0032] forming an interlayer dielectric layer on the substrate;

[0033] forming a contact hole in the interlayer dielectric layer to expose the select gate, the control gate, the source doped region, and the drain doped region;

[0034] Filling the inner wall of the contact hole with a conductive material to form a conductive plug;

[0035] A metal layer is formed on the interlayer dielectric layer, and the metal layer is patterned to form an electrode structure.

[0036] In summary, the present invention provides a cell structure of a multi-time programmable memory and a manufacturing method thereof, comprising a substrate, a floating gate located on the substrate, a first sidewall located on the sidewall of the floating gate, and a SAB film and a control gate located on the floating gate in sequence, and the control gate and the SAB film extend in a direction perpendicular to the thickness of the floating gate to cover part of the first sidewall. In the cell structure of the multi-time programmable memory provided by the present invention, the control gate stores and erases data by coupling with the floating gate, without the need for an additional tunneling area, so that the size of the cell structure of the multi-time programmable memory is reduced to meet the small size requirements of the MTP device. Furthermore, the SAB film and the control gate extend in a direction perpendicular to the thickness of the floating gate to cover part of the first sidewall, so as to reduce or avoid damage to the first sidewall when etching the SAB film, thereby improving the performance of the multi-time programmable memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1A Schematic diagram of a top view of a cell structure of a multi-time programmable memory. Figure 1B For multi-time programmable memory cell structure along Figure 1A Schematic cross-sectional view of line aa′ in FIG.

[0038] Figure 2A flowchart of a method for manufacturing a cell structure of a multi-time programmable memory provided by an embodiment of the present invention;

[0039] Figures 3 to 7B A schematic structural diagram corresponding to corresponding steps of a method for manufacturing a unit structure of a multi-time programmable memory provided by an embodiment of the present invention;

[0040] Figure 7C A schematic top view of a unit structure of a multi-time programmable memory provided by another embodiment of the present invention;

[0041] FIG. 8A to FIG. 8B A schematic diagram of a cell structure of a multi-time programmable memory for implementing data writing and erasing according to an embodiment of the present invention.

[0042] Wherein, the accompanying drawings are marked as follows:

[0043] 10.20-Multiple-Time Programmable Memory Cell Structure;

[0044] 103, 104, 105, 203, 204, 205 - N+ doped regions;

[0045] 100, 200-substrate;

[0046] 110, 210- floating gate;

[0047] 120, 220-select gate;

[0048] 130 - tunneling area;

[0049] 211- first side wall;

[0050] 221-second side wall;

[0051] 230′-SAB thin film material layer;

[0052] 230-SAB film;

[0053] 231′, 231- oxide layer;

[0054] 232′, 232-nitride layer;

[0055] 240′-control gate material layer;

[0056] 240- control grid;

[0057] 250 - patterned photoresist;

[0058] 101, 201-P well;

[0059] 202-gate oxide layer;

[0060] 206-self-aligned metal silicide layer;

[0061] 207-interlayer dielectric layer;

[0062] 108, 208-conductive plug;

[0063] 113, 213-source electrode;

[0064] 114, 214-selecting a signal electrode;

[0065] 115, 215-drain electrode;

[0066] 116, 216-Programming signal electrodes. DETAILED DESCRIPTION

[0067] Figure 1A Schematic diagram of a top view of a cell structure of a multi-time programmable memory. Figure 1B For multi-time programmable memory cell structure along Figure 1A The cross-sectional diagram of the aa′ line in FIG. Figure 1A and Figure 1B As shown, the cell structure 10 of the multi-time programmable memory includes a P-well region (P-Well) 101 formed in a substrate 100, a floating gate 110 (FG) and a select gate 120 (SG) formed on the P-well 101, N+ doped regions 103, 104, 105 on both sides of the floating gate 110 and the select gate 120, and a programming signal electrode 116, a select signal electrode 114, a source electrode 113 and a drain electrode 115 electrically connected to the floating gate 110, the select gate 120, the N+ doped region 103 and the N+ doped region 105 respectively through a conductive plug 108. For a single-layer polysilicon gate (floating gate) structure, the programming (PGM) and erasing (ERS) operations of the MTP cell are realized by injecting electrons or holes into the floating gate 110 or erasing electrons or holes. An additional tunneling area 130 is required to realize the above functions, which will lead to an increase in the size of the cell structure 10 (1 Bit-cell) of the multi-time programmable memory (about 10-90 um). 2 ), which is not conducive to the miniaturization of MTP devices.

[0068] The core idea of ​​the present invention is to provide a cell structure of a multi-time programmable memory and a manufacturing method thereof, comprising a substrate, a floating gate located on the substrate, a first sidewall located on the sidewall of the floating gate, and a SAB film and a control gate located on the floating gate in sequence, and extending to cover part of the first sidewall in a direction perpendicular to the thickness of the floating gate. In the cell structure of the multi-time programmable memory provided by the present invention, the control gate controls the floating gate by coupling to store and erase data, without the need for an additional tunneling area, so that the size of the cell structure of the multi-time programmable memory is reduced to meet the small size requirements of the MTP device. Furthermore, the SAB film and the control gate extend to cover part of the first sidewall in a direction perpendicular to the thickness of the floating gate to reduce or avoid damage to the first sidewall when etching the SAB film, thereby improving the performance of the multi-time programmable memory.

[0069] The unit structure of the multi-time programmable memory of the present invention and the method for making the same are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, it should be easily understood that the meaning of "on" and "on" in this document should be interpreted in the broadest sense, so that "on" and "on" mean not only "directly on something" without intermediate features or intermediate layers, but also include the meaning of "on something" with intermediate features or intermediate layers. In order to facilitate a clear introduction to the unit structure of the multi-time programmable memory provided by the present invention, the description is as follows. Fig. 7A and Figure 7C In the top view schematic diagram of the cell structure of the multi-time programmable memory shown in FIG, the interlayer dielectric layer is omitted, and the floating gate covered by the control gate is shown by a dotted line.

[0070] The terms "first", "second", etc. in the specification are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that, where appropriate, these terms used in this way are interchangeable, for example, so that the embodiments of the present invention described herein can be operated in an order other than that described or shown herein. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method. If the components in a certain figure are the same as the components in other figures, although these components can be easily identified in all figures, in order to make the description of the figures clearer, this specification will not mark all the same component numbers in each figure.

[0071] Fig. 7A A schematic top view of a unit structure of a multi-time programmable memory provided in this embodiment; Figure 7B The cell structure of multi-time programmable memory is along Fig. 7A The cross-sectional diagram of the bb′ line in FIG. Fig. 7A and Figure 7B As shown, a cell structure 20 of a multi-time programmable memory provided in this embodiment includes: a substrate 200, a floating gate 210 and a select gate 220 located on the substrate 200, a first sidewall 211 located on the sidewall of the floating gate 210, a second sidewall 221 located on the sidewall of the select gate 220, and a SAB film 230 and a control gate 240 located on the floating gate 210, wherein the SAB film 230 and the control gate 240 extend in a direction perpendicular to the thickness of the floating gate 210 to cover a portion of the first sidewall 211.

[0072] The material of the substrate 200 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or silicon on insulator (SOI), germanium on insulator (GOI); or other materials, such as III-V compounds such as gallium arsenide. The substrate 200 in this embodiment adopts a silicon substrate, which is only an example here, and the present invention is not limited to this. Preferably, the substrate 200 has a deep well, for example, the doping type of the deep well is P type (P well 201), and in addition, a shallow trench isolation structure (not shown in the figure) is formed in the substrate 200, and an active area (Active area, AA) is defined by the shallow trench isolation structure. The floating gate 210 and the select gate 220 are located on the active area AA, and N+ doping regions 203, 204, 205 are formed in the active area AA on both sides of the floating gate 210 and the select gate 220. The floating gate 210 and the select gate 220 share the N+ doping region 204 . For the convenience of subsequent description, the N+ doping region 203 is exemplarily defined as a source doping region, and the N+ doping region 205 is a drain doping region.

[0073] It should be noted that the substrate 200 includes a memory cell area and a peripheral circuit area. The floating gate 210 and the select gate 220 are located in the memory cell area, and are used to form a memory transistor and a high-voltage transistor for controlling the memory transistor. Structures such as capacitors are formed on the peripheral circuit area. Since the present invention mainly introduces the structural features of the multi-time programmable memory memory cell area, in order to make the diagram clearly express the core idea of ​​the present invention, the figure only shows the devices and structures of some multi-time programmable memory memory cell areas in the form of schematic diagrams, but this does not mean that the multi-time programmable memory cell structure involved in the present invention only includes these parts, and the known multi-time programmable memory cell structure may also be included therein. The structure and formation method in the peripheral circuit area are the same as the existing process, and will not be repeated here.

[0074] The interface where the floating gate 210 and the select gate 220 contact the substrate 200 is usually formed with a gate oxide layer 202, and the gate oxide layer 202 is, for example, silicon dioxide (SiO2). The material of the first spacer 211 and the second spacer 221 is silicon dioxide or silicon nitride, and the thickness is 3nm to 100nm. For example, the first spacer 211 and the second spacer 221 both have an ONO (Oxide-Nitride-Oxide, oxide-nitride-oxide) structure, that is, an isolation oxide layer, a spacer nitride layer and a spacer oxide layer are sequentially stacked on the sides of the floating gate 210 and the select gate 220, and the isolation oxide layer is, for example, silicon dioxide (SiO2), and the spacer nitride layer is, for example, silicon nitride (Si xN), the sidewall oxide layer is, for example, silicon oxynitride (SiO x N y ) or silicon dioxide (SiO2).

[0075] A self-aligned silicide area block (SAB) film 230 is located between the floating gate 210 and the control gate 240, and serves as an inter-gate dielectric layer between the floating gate 210 and the control gate 240. The SAB film 230 may be a single-layer structure composed of a single oxide or nitride, or a multi-layer structure composed of oxides or nitrides. For example, the SAB film 230 includes a three-layer structure of an oxide layer-nitride layer-oxide layer sequentially stacked on the surface of the floating gate 210, or the SAB film 230 includes a two-layer structure of an oxide layer-nitride layer sequentially stacked on the surface of the floating gate 210. The oxide layer in the SAB film 230 is made of silicon dioxide (SiO2), and the nitride layer is made of silicon nitride (Si x N). The SAB film 230 can be made of the same or similar materials and processes as the ONO three-layer structure in the first sidewall 211 and the second sidewall 221 (but not including the part formed by etching the sidewall). In this embodiment, the SAB film 230 is a two-layer structure, including an oxide layer 231 and a nitride layer 232 sequentially stacked on the surface of the floating gate 210.

[0076] like Figure 7B As shown, the SAB film 230 and the control gate 240 cover a portion of the first spacer 211 close to the floating gate 210, that is, when etching to form the SAB film 230 and the control gate 240, the etching stops at the side of the first spacer 211 close to the floating gate 210 (Landing on Spacer). Since the SAB film 230 and the first spacer 211 have similar structural compositions, the ONO structure of the first spacer 211 will be destroyed during the process of etching to form the SAB film 230 and the control gate 240. When the isolation oxide layer located on the inner side of the first spacer 211 is side-etched, the floating gate 210 may be in contact with the source / drain doping region, causing a short circuit. Therefore, when the SAB film 230 and the control gate 240 are etched to form, they cover the surface of the floating gate 210 and extend in a direction perpendicular to the thickness of the floating gate to cover a portion of the first sidewall 211, thereby reducing or avoiding damage to the first sidewall 211 when etching the SAB film 230, thereby avoiding the loss of the isolation oxide layer of the inner layer of the first sidewall 211 due to side etching, thereby improving the performance of the multi-time programmable memory.

[0077] like Fig. 7A and Figure 7BAs shown, the cell structure 20 of the multi-time programmable memory provided in this embodiment further includes a self-aligned metal silicide layer 206, and the self-aligned metal silicide layer 206 covers the selection gate 220, the control gate 240 and the N+ doped regions 203, 204, and 205. The self-aligned metal silicide layer 206 is, for example, a metal silicide with low resistance and good adhesion to silicon materials, such as cobalt silicide, titanium silicide, or nickel silicide. The self-aligned metal silicide layer 206 can be used as a contact structure (Contact) of a transistor to lead out the source, drain, and gate of the transistor.

[0078] The cell structure 20 of the multi-time programmable memory provided in this embodiment further includes: an interlayer dielectric layer 207 located on the salicide layer 206 and covering the substrate 200, a conductive plug 208 located in the interlayer dielectric layer 207 and connected to the salicide layer 206, and an electrode structure located on the interlayer dielectric layer 207 and connected to the conductive plug 208. The electrode structure includes a source electrode 213 (S / L), a drain electrode 215 (B / L), a selection signal electrode 214, and a programming signal electrode 216, wherein the source electrode 213 (S / L), the drain electrode 215 (B / L), the selection signal electrode 214, and the programming signal electrode 216 are respectively connected to the salicide layer 206 on the N+ doping region 203, the N+ doping region 205, the selection gate 220, and the control gate 240 through the conductive plug 208.

[0079] The memory cell area of ​​the multi-time programmable memory in this embodiment includes a plurality of the above-mentioned unit structures 20 (the dotted line frame portion in the figure), and the floating gate 210 and the control gate 240 in the unit structure 20 can be independently formed on an active area AA. Fig. 7A In other embodiments of the present invention, the control gates 240 of adjacent cell structures 20 in the storage cell area of ​​the multi-time programmable memory can be shared, that is, the floating gates 210 are segmented and located below the control gates 240, as shown in FIG. Figure 7C shown.

[0080] In the cell structure of the multi-time programmable memory provided in this embodiment, the floating gate 210 is used as an electron storage layer. Through programming, when the voltage difference between the control gate 240 and the substrate 200 is large enough, the electrons collected in the channel can enter the floating gate 210 through the tunneling effect. The gate dielectric layer (SAB film 230) between the control gate 240 and the floating gate 210 prevents the electrons from flowing through the control gate 240, thereby storing the electrons in the floating gate 210. For details, refer to Fig. 8A As shown, when performing a data write (PGM) operation, a high positive bias is applied to the control gate 240, so that electrons are injected from the N+ doped region 203 through the gate dielectric layer 202 into the floating gate 210; Figure 8B As shown, when a data erase (ERS) operation is performed, a high negative bias is applied to the control gate 240, and the control gate 240 controls the release of electrons in the floating gate 210 through coupling, so that the electrons stored in the floating gate 210 are removed from the floating gate 210 by using the Fowler-Nordheim (FN) tunneling effect, thereby completing the erasure of the data stored in the unit structure of the MTP device.

[0081] The cell structure 20 (the dotted line frame portion in the figure) of the multi-time programmable memory provided in this embodiment includes a selection gate 220, a floating gate 210, and the SAB film 230 and the control gate 240 located on the substrate 200. The control gate 240 controls the floating gate 210 by coupling to store and erase data, and no additional tunneling area is required, so that the size of the cell structure 20 (1 Bit-cell) of the multi-time programmable memory is reduced (about 1-10 μm). 2 ), meeting the small size requirements of the MTP device. Furthermore, the control gate 240 and the SAB film 230 extend to cover part of the first sidewall 211 in a direction perpendicular to the thickness of the floating gate, so as to reduce or avoid damage to the first sidewall 211 when etching the SAB film, thereby improving the performance of the multi-time programmable memory.

[0082] Accordingly, the present invention also provides a method for manufacturing a cell structure of a multi-time programmable memory. Figure 2 The flowchart of the method for manufacturing the unit structure of the multi-time programmable memory provided in this embodiment is as follows: Figure 2 As shown, the method for manufacturing the cell structure of the multi-time programmable memory provided in this embodiment includes the following steps:

[0083] S01: providing a substrate;

[0084] S02: forming a floating gate on the substrate, and forming a first spacer on the sidewall of the floating gate; and,

[0085] S03: forming a SAB film and a control gate in sequence on the floating gate, wherein the SAB film and the control gate extend in a direction perpendicular to the thickness of the floating gate to cover a portion of the first sidewall spacer.

[0086] Figures 3 to 7B The following is a schematic diagram of the structure corresponding to the corresponding steps of the method for manufacturing the unit structure of the multi-time programmable memory provided in this embodiment. Figure 2 and Figures 3 to 7B The method for manufacturing the cell structure of the multi-time programmable memory provided by this embodiment is described in detail.

[0087] First, if Figure 3 As shown, step S01 is performed to provide a substrate 200. The material of the substrate 200 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or silicon on insulator (SOI), germanium on insulator (GOI); or it may be other materials, such as III-V compounds such as gallium arsenide. The substrate 200 described in this embodiment is only taken as an example of a silicon substrate, which is only an example here, and the present invention is not limited to this. When executing step S01, it can be considered that the following process steps including but not limited to can also be completed on the substrate 200: an isolation channel (such as a shallow trench isolation structure, STI) is formed on the substrate 200, and well implantation (such as P well 201), other ion implantation and annealing steps are performed on the substrate 200.

[0088] Next, continue to refer to Figure 3 As shown, step S02 is performed to form a floating gate 210 on the substrate 200, and to form a first spacer 211 on the sidewall of the floating gate 210. Before forming the floating gate 210, a gate oxide layer 202 is formed on the substrate 200. The gate oxide layer 202 can be formed on the global surface of the substrate 200 by using a thermal oxidation (wet oxidation or dry oxidation) process, an in-situ steam generation process (ISSG), a chemical vapor deposition (CVD) process, or an atomic layer deposition process. The material of the gate oxide layer 202 can be silicon dioxide (SiO2), silicon oxynitride (SiO x N y ) or silicon nitride (Si x N), etc., and the thickness can be 2nm to 30nm.

[0089] It should be noted that the materials, thicknesses and formation methods of the layers mentioned above and below are merely examples of an embodiment of the present invention. Different materials, different thicknesses and different formation methods may be used in different situations, and these should not constitute limitations to the present invention.

[0090] After the gate oxide layer 202 is formed on the substrate 200, a floating gate 210 and a select gate 220 are formed on the gate oxide layer 202. Specifically, first, a gate material layer is formed on the substrate 200, and the material of the gate material layer may be polysilicon, a metal material, a metal material compound or other suitable materials. Then, a patterned photoresist layer is formed on the gate material layer, and then the gate material layer is etched using the patterned photoresist layer as a mask to form the floating gate 210 and the select gate 220. In this embodiment, the materials of the floating gate 210 and the select gate 220 are both polysilicon. For example, the floating gate 210 and the select gate 220 may be formed by dry etching. In other embodiments of the present invention, the materials of the floating gate 210 and the select gate 220 may also be different, and different methods may also be used to form the floating gate 210 and the select gate 220, respectively, which is not limited here.

[0091] After forming the floating gate 210 and the select gate 220 on the gate oxide layer 202, a first sidewall 211 and a second sidewall 221 are formed on the sidewalls of the floating gate 210 and the select gate 220, respectively. The materials of the first sidewall 211 and the second sidewall 221 are both silicon oxide or silicon nitride or a combination thereof, and the thickness is 3nm to 100nm. Exemplarily, the first sidewall 211 and the second sidewall 221 both have an ONO (Oxide-Nitride-Oxide) structure, that is, an isolation oxide layer, a sidewall nitride layer and a sidewall oxide layer (not shown in the figure) are formed by stacking the sides of the floating gate 210 and the select gate 220 in sequence, the isolation oxide layer is close to the floating gate 210 and the select gate 220, and is the inner layer of the first sidewall 211 and the second sidewall 221, the isolation oxide layer is, for example, silicon dioxide (SiO2), and the sidewall nitride layer is, for example, silicon nitride (Si x N), the sidewall oxide layer is, for example, silicon oxynitride (SiO x N y ) or silicon dioxide (SiO2). Exemplarily, the isolation oxide layer can be deposited by plasma enhanced chemical vapor deposition (PECVD) process, the sidewall nitride layer can be deposited by low pressure chemical vapor deposition (LPCVD) process or plasma enhanced chemical vapor deposition (PECVD) process, and the sidewall oxide layer can be deposited by atmospheric pressure chemical vapor deposition (APCVD) process, low pressure chemical vapor deposition (LPCVD) process or plasma enhanced chemical vapor deposition (PECVD) process. The formation of the first sidewall 211 and the second sidewall 221 also includes anisotropically etching the isolation oxide layer, the sidewall nitride layer and the sidewall oxide layer.

[0092] After forming the first sidewall 211 and the second sidewall 221, ion implantation is performed on the substrate 200 to form N+ doping regions 203, 204, and 205 on both sides of the floating gate 210 and the select gate 220. For example, an existing source-drain implantation process may be used to implant, for example, at least one of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions, and high-temperature annealing is performed after implantation. The floating gate 210 and the select gate 220 share the N+ doping region 204, and for the convenience of subsequent description, the N+ doping region 203 is exemplarily defined as a source doping region, and the N+ doping region 205 is a drain doping region.

[0093] Then, if Figures 4 to 6 As shown, step S03 is performed to sequentially form a SAB film 230 and a control gate 240 on the floating gate 210, wherein the SAB film 230 and the control gate 240 cover a portion of the first sidewall spacer 211 close to the floating gate 230. Specifically, first, as Figure 4 As shown, a SAB thin film material layer 230' and a control gate material layer 240' are sequentially formed on the substrate 200. In this embodiment, the SAB thin film material layer 230' is a double-layer structure consisting of an oxide layer 231' and a nitride layer 232'. For example, the oxide layer 231' is made of silicon dioxide (SiO2), and the nitride layer 232' is made of silicon nitride (Si x N), the oxide layer 231' can be formed by low pressure chemical vapor deposition (LPCVD), and then the nitride layer 232' is formed on the oxide layer 231' by low pressure chemical vapor deposition. In other embodiments of the present invention, the SAB thin film material layer 230' can also be a three-layer structure consisting of an oxide layer, a nitride layer and an oxide layer. Then, a control gate material layer 240' is formed on the SAB thin film material layer 230', and the material of the control gate material layer 240' can be polysilicon, a metal material, a metal material compound or other suitable materials. In this embodiment, the materials of the floating gate 210 and the control gate 240 are both polysilicon.

[0094] Then, if Figure 5As shown, a patterned photoresist layer 250 is formed on the surface of the control gate material layer 240′ using a SAB mask (SAB Photo), wherein the patterned photoresist layer 250 covers the control gate material layer 240′ on the floating gate 210 and extends to the first sidewalls 210 on both sides of the floating gate 210, so as to avoid damaging the ONO structure of the first sidewalls 211 during subsequent etching of the SAB film material layer, and especially to avoid damaging the isolation oxide layer located on the inner side of the first sidewall 211 by side etching. Next, using the patterned photoresist layer 250 as a mask, the control gate material layer 240′ and the SAB film material layer 230′ are sequentially etched to form the SAB film 230 and the control gate 240 on the floating gate 210, and the SAB film 230 and the control gate 240 extend in a direction perpendicular to the thickness of the floating gate 210 to cover a portion of the first sidewall 211, as shown in FIG. Figure 6 As shown. For example, dry etching can be used to remove the control gate material layer 240′ to form the control gate 240, and then wet etching can be used to sequentially remove the nitride layer 232′ and the oxide layer 231′ in the SAB film material layer 230′. For example, a phosphoric acid solution can be used to wet-etch the nitride layer 232′, and then a hydrofluoric acid solution can be used to wet-etch the oxide layer 231′. The wet etching stops at the first side wall 211, so that the SAB film 230 and the control gate 240 formed after etching cover part of the first side wall 211, protecting the isolation oxide layer in the first side wall 211 close to the floating gate 210. In this embodiment, the thickness of the nitride layer 232 in the SAB film layer 230 is 5nm-10nm, and the oxide layer 231 is a silicon oxide layer with a thickness of 5nm-10nm. As Figure 6 As shown, the thickness d of the SAB film 230 and the control gate 240 covering the first sidewall 210 is 20nm-30nm. According to the different structures of the first sidewall 211, the thickness d of the parts covered by the SAB film 230 and the control gate 240 is also different.

[0095] The method for manufacturing the cell structure of the multi-time programmable memory provided in this embodiment further includes: forming a self-aligned metal silicide layer 206, wherein the self-aligned silicide layer 206 is a metal silicide, such as cobalt silicide, titanium silicide and nickel silicide. Figure 7BAs shown, a self-aligned metal silicide process can be used to form a self-aligned metal silicide 206 on the select gate 220, the control gate 240 and the N+ doped regions 203, 204, 205, including the following process: firstly forming a metal layer (for example, including at least one metal selected from nickel Ni, cobalt Co, tungsten W, platinum Pt, manganese Mn, titanium Ti, tantalum Ta, etc.) on the substrate 200, the metal layer covering the surfaces of the select gate 220, the control gate 240 and the N+ doped regions 203, 204, 205; then performing a thermal annealing process to allow the metal particles (M) in the metal layer to react with the silicon (Si) on the surfaces of the select gate 220, the control gate 240 and the N+ doped regions 203, 204, 205 to generate a self-aligned metal silicide (MSi). x ) layer 206. The self-aligned metal silicide layer 206 can reduce the contact resistance between the select gate 220, the control gate 240 and the N+ doped regions 203, 204, 205 and the subsequently formed conductive plugs (Contact), thereby improving device performance. It should be noted that before forming the self-aligned metal silicide layer 206, the gate oxide layer 202 is patterned to expose the N+ doped regions 203, 204, 205.

[0096] After that, please continue to refer to Fig. 7A and Figure 7B As shown, the method for manufacturing the cell structure of the multi-time programmable memory provided in this embodiment also includes: forming an interlayer dielectric layer 207 on the substrate 200, and the interlayer dielectric layer 207 is, for example, a silicon dioxide layer; forming a contact hole in the interlayer dielectric layer 207, for example, the interlayer dielectric layer 207 can be etched by dry etching to form a contact hole exposing the N+ doped region 203, the N+ doped region 205, the selection gate 220 and the control gate 240; filling the inner wall of the contact hole with a conductive material to form a conductive plug 208, and the conductive material is, for example, metal tungsten; forming a metal layer on the interlayer dielectric layer 207, and patterning the metal layer to form an electrode structure. The electrode structure includes a source electrode 213 (S / L), a drain electrode 215 (B / L), a selection signal electrode 214 and a programming signal electrode 216, wherein the source electrode 213 (S / L), the drain electrode 215 (B / L), the selection signal electrode 214 and the programming signal electrode 216 are respectively connected to the N+ doped region 203, the N+ doped region 205, the selection gate 220 and the self-aligned metal silicide layer 206 on the control gate 240 through the conductive plug 208.

[0097] In the method for manufacturing the cell structure of the multi-time programmable memory provided by the present invention, a SAB film is used as the inter-gate dielectric layer between the control gate and the floating gate. When etching to form the control gate 240 and the SAB film 230, the pattern used to define the control gate 240 can be embedded in the SAB mask used to define the SAB film, and the control gate 240 and the SAB film 230 can be defined simultaneously with one SAB mask. Moreover, the SAB film and the control gate extend to cover part of the first sidewall in a direction perpendicular to the thickness of the floating gate, so as to reduce or avoid damage to the first sidewall when etching the SAB film, thereby improving the performance of the multi-time programmable memory.

[0098] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a cell structure of a multi-time programmable memory, characterized in that: include: providing a substrate; forming a floating gate on the substrate, and forming a first spacer on the sidewall of the floating gate; as well as, forming a SAB thin film material layer and a control gate material layer on the substrate in sequence; Using a SAB mask, forming a patterned photoresist layer on the control gate material layer, wherein the patterned photoresist layer covers the control gate material layer on the floating gate and extends to the first sidewalls on both sides of the floating gate; Using the patterned photoresist layer as a mask, the control gate material layer and the SAB film material layer are etched in sequence, and a control gate and a SAB film are formed in sequence on the floating gate, and the SAB film and the control gate extend in a direction perpendicular to the thickness of the floating gate to cover a portion of the first side wall, so as to reduce or avoid damage to the first side wall when etching the SAB film.

2. The method for manufacturing a cell structure of a multi-time programmable memory according to claim 1, characterized in that: Also includes: forming a select gate on the substrate while forming a floating gate on the substrate; While forming the first spacer on the sidewall of the floating gate, a second spacer is formed on the sidewall of the select gate.

3. The method for manufacturing a cell structure of a multi-time programmable memory according to claim 1, characterized in that: Before forming the floating gate on the substrate, the method further includes: forming a gate oxide layer on the substrate.

4. The method for manufacturing a cell structure of a multi-time programmable memory according to claim 2, characterized in that: After forming a first sidewall spacer on the sidewall of the floating gate and before sequentially forming a SAB film layer and a control gate layer on the substrate, the method further includes: performing ion implantation on the substrate to form a source doping region and a drain doping region.

5. The method for manufacturing a cell structure of a multi-time programmable memory according to claim 2, characterized in that: The SAB film includes an oxide layer and a nitride layer sequentially stacked on the surface of the floating gate, and the first sidewall spacer and the second sidewall spacer both have an ONO structure.

6. The method for manufacturing a cell structure of a multi-time programmable memory according to claim 4, characterized in that: After forming the SAB film and the control gate on the floating gate, the method further includes: Forming a self-aligned metal silicide layer on the substrate, wherein the self-aligned metal silicide layer covers the select gate, the control gate, the source doping region, and the drain doping region; forming an interlayer dielectric layer on the substrate; forming a contact hole in the interlayer dielectric layer to expose the select gate, the control gate, the source doped region, and the drain doped region; Filling the inner wall of the contact hole with a conductive material to form a conductive plug; A metal layer is formed on the interlayer dielectric layer, and the metal layer is patterned to form an electrode structure.

7. A cell structure of a multi-time programmable memory, characterized in that: The method for manufacturing a unit structure of a multi-time programmable memory according to any one of claims 1 to 6 is used, wherein the unit structure of the multi-time programmable memory comprises: Substrate, a floating gate located on the substrate, a first spacer located on the sidewall of the floating gate, a gate oxide layer formed between the floating gate and the substrate, the material of the gate oxide layer comprising silicon dioxide; and A SAB film and a control gate are sequentially located on the floating gate, and the SAB film and the control gate extend perpendicular to the thickness direction of the floating gate to cover a portion of the first sidewall, so as to reduce or avoid damage to the first sidewall when etching the SAB film.

8. The cell structure of the multi-time programmable memory according to claim 7, characterized in that: It also includes a selection gate located on the substrate, and a second spacer is formed on the sidewall of the selection gate.

9. The cell structure of the multi-time programmable memory according to claim 8, characterized in that: An active region is formed in the substrate, and an active doping region and a drain doping region are formed in the active region.

10. The cell structure of the multi-time programmable memory according to claim 9, characterized in that: The floating gate and the select gate are located between the source doping region and the drain doping region.

11. The cell structure of the multi-time programmable memory according to claim 9, characterized in that: It also includes a self-aligned metal silicide layer, which covers the selection gate, the control gate, the source doping region and the drain doping region.

12. The cell structure of the multi-time programmable memory according to claim 11, characterized in that: It also includes an interlayer dielectric layer located on the self-aligned metal silicide layer and covering the substrate, a conductive plug located in the interlayer dielectric layer and connected to the self-aligned metal silicide layer, and an electrode structure located on the interlayer dielectric layer and connected to the conductive plug.

13. The cell structure of the multi-time programmable memory according to claim 7, characterized in that: The SAB film includes an oxide layer and a nitride layer sequentially stacked on the surface of the floating gate.

14. The cell structure of the multi-time programmable memory according to claim 8, characterized in that: The first sidewall spacer and the second sidewall spacer both have an ONO structure.

Images