Semiconductor devices

Abstract

A semiconductor device is provided. The semiconductor device includes: a channel layer located on a substrate, the channel layer including a conductive oxide; a gate structure located on the channel layer, the gate structure including a gate electrode and a gate spacer located on both sidewalls of the gate electrode; and a source region and a drain region located on both sides of the gate structure in a recessed region having a first height from a top surface of the channel layer. The source region and the drain region are configured to apply a tensile stress to a portion of the channel layer located below the gate structure.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0003291 filed on January 10, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including an oxide channel layer. Background Art

[0003] As electronic products tend to be lightweight, thin, and miniaturized, the demand for highly integrated semiconductor devices has increased. As the size of semiconductor devices decreases, the size of components included in transistors is also decreasing. Therefore, leakage current occurs due to the short channel effect. Therefore, it is necessary to reduce the leakage current of transistors and improve the reliability of semiconductor devices. Summary of the invention

[0004] The inventive concept provides a semiconductor device having both low leakage current and increased on-current.

[0005] According to one aspect of the inventive concept, a semiconductor device is provided, the semiconductor device comprising: a channel layer located on a substrate, the channel layer comprising a conductive oxide; a gate structure located on the channel layer, the gate structure comprising a gate electrode and a gate spacer located on both sidewalls of the gate electrode; and a source region and a drain region located on both sides of the gate structure in a recessed region having a first height from a top surface of the channel layer. The source region and the drain region are configured to apply tensile stress to a portion of the channel layer located below the gate structure.

[0006] According to another aspect of the inventive concept, a semiconductor device is provided, the semiconductor device comprising: a channel layer located on a substrate, the channel layer comprising a conductive oxide; a gate structure located on the channel layer, the gate structure comprising a gate electrode and a gate spacer located on both sides of the gate electrode; and a source region and a drain region located on both sides of the gate structure in a recessed region having a first height from a top surface of the channel layer. The source region and the drain region partially overlap with the gate spacer relative to a top view (i.e., in a direction perpendicular to the top surface of the substrate).

[0007] According to another aspect of the inventive concept, a semiconductor device is provided, the semiconductor device comprising: a channel layer located on a substrate; a gate structure located on the channel layer, the gate structure comprising gate spacers located on both sidewalls of a gate electrode; and a source region and a drain region located on both sides of the gate structure in a recessed region having a first height from a top surface of the channel layer, the source region and the drain region being configured to apply tensile stress to a portion of the channel layer located below the gate structure. The channel layer comprises a RAO 3 (MO)m A material represented by, wherein R is at least one of scandium (Sc), ytterbium (Yb), lutetium (Lu) and indium (In), A is at least one of gallium (Ga), aluminum (Al), iron (Fe) and indium (In), M is at least one of zinc (Zn) and magnesium (Mg), and m is an integer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 shows a layout of a semiconductor device according to an example embodiment;

[0010] Figure 2 is along the lines of an exemplary embodiment Figure 1 A cross-sectional view taken along line II-II';

[0011] Figure 3 is a cross-sectional view of a semiconductor device according to an example embodiment;

[0012] Figure 4 is a cross-sectional view of a semiconductor device according to an example embodiment;

[0013] Figure 5 is a cross-sectional view of a semiconductor device according to an example embodiment;

[0014] Figure 6 is a cross-sectional view of a semiconductor device according to an example embodiment;

[0015] Figure 7 is a cross-sectional view of a semiconductor device according to an example embodiment;

[0016] Figure 8 is a cross-sectional view of a semiconductor device according to an example embodiment;

[0017] Fig. 9 is a cross-sectional view of a semiconductor device according to an example embodiment;

[0018] FIG. 10A to FIG. 10H is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments; and

[0019] FIG. 11A to FIG. 11E is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0020] Embodiments will now be described more fully with reference to the accompanying drawings, in which some embodiments are shown.

[0021] Figure 1 A layout of a semiconductor device 100 according to example embodiments is shown. Figure 2 is along the lines of an exemplary embodiment Figure 1 For simplicity, Figure 1 Only some components of the semiconductor device 100 are shown.

[0022] Reference Figure 1 and Figure 2 , the semiconductor device 100 may include a channel layer 114 , source and drain regions 120 , a gate structure 130 , a contact plug 150 , and a gate contact 160 , which may be located on a substrate 110 .

[0023] In example embodiments, the substrate 110 may include a Group IV semiconductor such as silicon (Si) or germanium (Ge), a Group IV-IV compound semiconductor such as silicon germanium (SiGe) or silicon carbide (SiC), or a Group III-V compound semiconductor such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The substrate 110 may include a conductive region, for example, a doped well or a doped structure.

[0024] The blocking insulating layer 112 may be located on the substrate 110. The blocking insulating layer 112 may include at least one of silicon oxide, silicon nitride, and aluminum oxide. For example, the blocking insulating layer 112 may be used as a buffer layer configured to reduce stress caused by the difference in lattice constant between the material used for the substrate 110 and the material used for the channel layer 114. Alternatively, the blocking insulating layer 112 may be used as a barrier layer configured to prevent impurities (e.g., hydrogen atoms) from diffusing from the substrate 110 into the channel layer 114 and to prevent current flowing in the channel layer 114 from leaking into the substrate 110.

[0025] The channel layer 114 may be located on the blocking insulating layer 112. The channel layer 114 may have a flat top surface, and a top level LV1 of the channel layer 114 may be higher than a top level LV0 of the substrate 110. Hereinafter, each of the plurality of levels LV0 to LV3 may be referred to as a vertical level with respect to the top surface of the substrate 110.

[0026] In example embodiments, the channel layer 114 may include a conductive oxide. For example, the channel layer 114 may include a homologous oxide. Here, the homologous oxide may represent a conductive oxide having a formula of RAO. 3 (MO) mdenoted by (here, R is at least one of scandium (Sc), ytterbium (Yb), lutetium (Lu), and indium (In); A is at least one of gallium (Ga), aluminum (Al), iron (Fe), and indium (In); M is at least one of zinc (Zn) and magnesium (Mg), and m is an integer). However, the elements R, A, and M that may be included in the homologous oxide are not limited to the elements listed above. In example embodiments, the channel layer 114 may include InGaZnO x 、InGaSiO x 、InSnZnO x (ITZO), InZnO x (IZO), SnO 2 、HfInZnO x (HIZO) or YbGaO 3 (ZnO) 5 (YGZO) or a combination thereof.

[0027] In example embodiments, the channel layer 114 may have an amorphous structure or a c-axis oriented crystal structure. For example, when the channel layer 114 includes InGaZnO having a c-axis oriented crystal structure, x When the channel layer 114 has a YbFe 2 O 4 The crystal structure of YbFe 2 O 4 In the crystal structure, InO with a hexagonal arrangement 2 The layers may be arranged in a layered structure along the c-axis direction, and the (Ga, Zn)O x Can be arranged between two adjacent InO 2 However, the crystal structure of the channel layer 114 is not limited thereto. Optionally, the channel layer 114 may be doped with impurities of at least one element of fluorine (F), hydrogen (H), nitrogen (N), magnesium (Mg), yttrium (Y), ruthenium (Ru), and arsenic (As). For example, in order to dope the channel layer 114 with impurities of at least one element, the impurities may be in-situ doped during the formation of the channel layer 114, or the impurity ions may be implanted after the channel layer 114 is formed.

[0028] The device isolation film 116 may be formed on the substrate 110 and define an active region AC in the channel layer 114. The channel layer 114 may include an active region AC that may constitute an NMOS transistor. In another case, the channel layer 114 may include an active region AC that may constitute a PMOS transistor. For example, an NMOS transistor or a PMOS transistor may be included as a component in a semiconductor device, such as a memory device (e.g., a dynamic random access memory (DRAM) device, a phase change random access memory (PRAM), a static random access memory (SRAM), a NAND flash memory, a NOR flash memory, an electrically erasable programmable read-only memory (EEPROM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM)), a complementary metal oxide semiconductor (CMOS) image sensor, and a logic device.

[0029] The device isolation film 116 may be located in the device isolation trench 116T, and the device isolation trench 116T may pass through the channel layer 114 and the blocking insulating layer 112 and extend into the substrate 110. The device isolation film 116 may include silicon oxide, flowable CVD (FCVD) oxide, tetraethyl orthosilicate (TEOS) oxide, and / or high density plasma (HDP) oxide, but the inventive concept is not limited thereto. The bottom surface of the device isolation film 116 may be located at a level lower than the top level LV0 of the substrate 110.

[0030] The gate structure 130 may be located on the channel layer 114 and may extend in a first direction (refer to Figure 2 The gate structure 130 may include a gate insulating layer 132, a gate electrode 134, a gate capping layer 136, and a gate spacer 138.

[0031] The gate insulating layer 132 may be located on the channel layer 114. The gate insulating layer 132 may include a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a dielectric constant higher than that of the silicon oxide film, or a combination thereof. The high-k dielectric film may include a metal oxide or a metal oxynitride. For example, the high-k dielectric film that may be used for the gate insulating layer 132 may include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina or a combination thereof, but are not limited thereto.

[0032] The gate electrode 134 may be located on the gate insulating layer 132. The gate electrode 134 may include doped polysilicon (poly-Si), metal, or a combination thereof.

[0033] The gate capping layer 136 may be located on the gate electrode 134. The gate capping layer 136 may cover the top surface of the gate electrode 134 and extend in a first direction (refer to Figure 2 For example, the gate capping layer 136 may include silicon nitride.

[0034] The gate spacer 138 may be located on both sidewalls of the gate insulating layer 132, the gate electrode 134, and the gate capping layer 136, and may extend in a first direction (refer to Figure 2 In example embodiments, the gate spacer 138 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Carbide Nitride (SiC x N y ), silicon oxynitride and carbon oxynitride (SiO x C y N z ) or a combination thereof. Each of the gate spacers 138 may be Figure 2 The first thickness t11 may be in a range of about 2 nm to about 20 nm, but the inventive concept is not limited thereto.

[0035] In example embodiments, the gate spacer 138 may include a plurality of layers including different materials, respectively. Figure 2 134, but in another case, the gate spacer 138 may include a first spacer layer (not shown), a second spacer layer (not shown), and a third spacer layer (not shown) that may be sequentially stacked on the sidewalls of the gate insulating layer 132, the gate electrode 134, and the gate capping layer 136. In an example embodiment, the first spacer layer and the third spacer layer may include silicon nitride, silicon oxide, or silicon oxynitride. The second spacer layer may include an insulating material having a dielectric constant lower than that of the first spacer layer. For example, the second spacer layer may include an air space.

[0036] A recessed region RS1 having a first height h11 from a top surface of the channel layer 114 may be formed in the channel layer 114 on both sides of the gate structure 130. The source and drain regions 120 may be located in the recessed region RS1. The channel layer 114 provided with the source and drain regions 120 may be located on the blocking insulating layer 112. For example, Figure 2As shown in , the bottom level LV2 of the recessed region RS1 may be higher than the top level LV0 of the substrate 110 and lower than the top level LV1 of the channel layer 114. The recessed region RS1 may have a maximum width w11 at the top surface of the recessed region RS1 in the Y direction, and have a cross-sectional shape in which the width of the recessed region RS1 decreases toward the bottom of the recessed region RS1. The boundary between the bottom and the sidewall of the recessed region RS1 may be rounded. However, the shape of the recessed region RS1 is not limited thereto.

[0037] In example embodiments, the source and drain regions 120 may include amorphous InO 3 -ZnO(IZO), InGaSiO x , silicon doped with phosphorus (P), silicon doped with arsenic (As), germanium doped with phosphorus, or germanium doped with arsenic, or a combination thereof. The formation of the source and drain regions 120 may include removing portions of the channel layer 114 on both sides of the gate structure 130 to form a recessed region RS1 and filling the recessed region RS1 with the above materials using a selective epitaxial growth (SEG) process. The source and drain regions 120 may be doped with impurities in situ during the selective epitaxial growth process, or impurity ions may be implanted after the source and drain regions 120 are formed.

[0038] In example embodiments, the source and drain regions 120 may include a compressive strain material. The source and drain regions 120 may serve as a stressor configured to apply tensile stress to a portion of the channel layer 114 located below the gate structure 130 (i.e., the channel region CH). In addition, the source and drain regions 120 may serve as a stressor configured to apply tensile stress to the channel layer 114. Because the source and drain regions 120 are configured to apply tensile stress to the portion of the channel layer 114, the mobility and density of states (DOS) of carriers (e.g., electrons) in the channel region CH may be improved. Meanwhile, for the sake of brevity, in Figure 2 The channel region CH is schematically shown in FIG. Figure 2 The shapes shown in are different.

[0039] In example embodiments, the source and drain regions 120 may include a material different from that of the channel layer 114. For example, the channel layer 114 may include InGaZnO x , and the source and drain regions 120 may include InGaSiO x In other embodiments, the source and drain regions 120 may include a material that may include the same element as the channel layer 114 at a different content than the channel layer 114. For example, the channel layer 114 may include In x Ga y Si z O w, and the source and drain regions 120 may include In x Ga y Si z O w In this case, the contents x, y, z, and w of the elements included in the channel layer 114 may be different from the contents x, y, z, and w of the elements included in the source and drain regions 120. In other embodiments, the source and drain regions 120 may include a material that may include the same elements as the elements of the channel layer 114 and have a crystal structure different from that of the channel layer 114. For example, the channel layer 114 may include crystalline InZnO x (IZO), the source and drain regions 120 may include amorphous InO 3 -ZnO (IZO) In other embodiments, the source and drain regions 120 may include a material having a lower lattice constant than that of the channel layer 114 .

[0040] For example, when the active region AC is an active region of an NMOS transistor, the source and drain regions 120 may be used as a stressor configured to apply tensile stress to the channel layer 114. However, the inventive concept is not limited thereto. When the active region AC is an active region of a PMOS transistor, the materials included in the channel layer 114 and the source and drain regions 120 may be appropriately selected so that the source and drain regions 120 may be used as a stressor configured to apply compressive stress to the channel layer 114. Because the source and drain regions 120 are configured to apply compressive stress to a portion of the channel layer 114, the mobility and DOS of carriers (e.g., holes) in the channel region CH may be improved.

[0041] like Figure 2 As shown in FIG. 1 , the source and drain regions 120 may be formed in the recessed region RS1, and a portion of the recessed region RS1 may be formed in a vertical direction (eg, Figure 2 The recessed region RS1 and the drain region 120 are formed to fill the recessed region RS1, so that the shortest distance between each of the source and drain regions 120 and the gate electrode 134 may be substantially equal to the shortest distance d11 between the sidewall of the recessed region RS1 and the gate electrode 134 and the gate electrode 134.

[0042] In a manufacturing method according to example embodiments, portions of the channel layer 114 on both sides of the gate structure 130 may be removed to form pre-recessed regions (see Fig. 10DBy extending the pre-recessed region RS1P in the lateral direction, the recessed region RS1 may partially overlap the gate spacer 138. In a manufacturing method according to another example embodiment, portions of the channel layer 114 on both sides of the gate structure 130 may be removed using an isotropic etching process. Therefore, the recessed region RS1 may partially overlap the gate spacer 138.

[0043] In a semiconductor device having a typical structure in which portions of the channel layer 114 on both sides of the gate structure 130 are doped with impurities to form source and drain regions, portions of the channel layer 114 directly below the gate spacer 138 (e.g., an underlap portion of the channel layer 114 vertically overlapping the gate spacer 138) may be doped with impurities at a relatively low concentration. As a result, this may deteriorate the performance of the semiconductor device. For example, the underlap portion of the channel layer 114 may have a high resistance, and the semiconductor device may have a relatively low on-current.

[0044] According to the above-described example embodiments, the source and drain regions 120 may be formed in the recessed region RS1 partially overlapping the gate spacer 138, and therefore, the lower overlapping portion may have a relatively small width. As a result, the semiconductor device 100 may have an increased on-current. In addition, since the source and drain regions 120 are formed to partially overlap the gate spacer 138, a relatively high tensile stress may be applied to the channel region CH located below the gate electrode 134. Therefore, the mobility and DOS of carriers in the channel region CH may be increased.

[0045] The interlayer insulating film 140 may be located on the channel layer 114, the device isolation film 116, and the source and drain regions 120 to cover the gate structure 130. The interlayer insulating film 140 may include silicon nitride, silicon oxide, silicon oxynitride, a TEOS film, or an ultra low k (ULK) film having an ultra low dielectric constant of about 2.2 to about 2.4.

[0046] The contact plug 150 may pass through the interlayer insulating film 140 and be electrically connected to the source and drain regions 120. Figure 1 As shown in , the gate contact 160 may pass through the interlayer insulating film 140 and the gate capping layer 136 and be electrically connected to the gate electrode 134 .

[0047] The contact plug 150 and the gate contact 160 may include doped polysilicon, metal, metal nitride, metal silicide, or a combination thereof. For example, the contact plug 150 and the gate contact 160 may have a double-layer structure including a metal filling layer (not shown) and a conductive barrier layer (not shown) configured to surround the side surface and bottom surface of the metal filling layer. For example, the metal filling layer may include at least one of cobalt (Co), tungsten (W), nickel (Ni), ruthenium (Ru), copper (Cu), aluminum (Al), silicides thereof, and alloys thereof, and the conductive barrier layer may include titanium (Ti), tantalum (Ta), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, but the inventive concept is not limited thereto. When the contact plug 150 includes a double-layer metal material, the contact plug 150 may be used as an additional stressor configured to apply tensile stress to the channel region CH and / or the source and drain regions 120.

[0048] Although Figure 1 An example is shown in which one contact plug 150 is located on each of both sides of the gate structure 130 , but at least two contact plugs 150 may be located on each of both sides of the gate structure 130 .

[0049] Generally, as the size of components included in a transistor decreases, a short channel effect occurs and leakage current increases. For example, homologous oxides (e.g., IGZO) have been proposed as materials for a channel layer of a thin film transistor (TFT). However, although homologous oxides have low leakage current, homologous oxides may not have sufficient carrier mobility for use in silicon-based semiconductor devices (such as memory devices, CMOS image sensors, and logic devices).

[0050] However, according to the above-described example embodiment, the channel layer 114 including the homologous oxide may have improved carrier mobility due to the source and drain regions 120 formed in the recessed region RS1 and configured to apply tensile stress to the channel layer 114. In addition, since the recessed region RS1 vertically overlaps the gate spacer 138, an increase in resistance caused by a lower overlapping portion of the channel layer 114 vertically overlapping the gate spacer 138 may be prevented. Therefore, the semiconductor device 100 may have both low leakage current characteristics and improved on-current characteristics.

[0051] Figure 3 is a cross-sectional view of a semiconductor device 100A according to example embodiments. Figure 3 is along Figure 1 The cross-sectional view corresponding to the cross-sectional view taken along the line II-II'. Figure 3 In the present invention, the same reference numerals are used to represent Figure 1 and Figure 2 The same elements as the elements in .

[0052] Reference Figure 3 , each of the source and drain regions 120A of the semiconductor device 100A may include a protrusion 120_P that may protrude outward. The boundary between the sidewall and the bottom of each of the source and drain regions 120A may have a rounded shape. The level LV3 of the protrusion 120_P may be lower than the top level LV1 of the channel layer 114 and higher than the bottom level LV2 of the recessed region RS1A. The level LV3 of the protrusion 120_P may also be lower than the top surface of the source and drain regions 120A.

[0053] like Figure 3 As shown in , in the second direction (Y direction), each of the source and drain regions 120A may have a maximum width w11a at the same level as the level LV3 of the protrusion 120_P. In addition, in the Y direction, the shortest distance d11 between the recessed region RS1A and the gate electrode 134 may be obtained at the same level as the level LV3 of the protrusion 120_P. The shortest distance d11 between the recessed region RS1A and the gate electrode 134 may be less than the first thickness t11 of each gate spacer 138 measured in the Y direction. For example, in the Y direction, the distance between the recessed region RS1A at the top level LV1 of the channel layer 114 and the gate electrode 134 may be greater than the shortest distance d11 between the recessed region RS1A and the gate electrode 134 at the level LV3.

[0054] In a manufacturing method according to example embodiments, portions of the channel layer 114 on both sides of the gate structure 130 may be removed to form pre-recessed regions (see Fig. 10D By extending the pre-recessed region RS1P in the lateral direction, a portion of the sidewall of the recessed region RS1A may have a shape corresponding to the protrusion 120_P. In a manufacturing method according to another example embodiment, portions of the channel layer 114 on both sides of the gate structure 130 may be removed using an isotropic etching process. Therefore, a portion of the sidewall of the recessed region RS1A may have a shape corresponding to the protrusion 120_P.

[0055] In a semiconductor device having a typical structure in which portions of the channel layer 114 on both sides of the gate structure 130 are doped with impurities to form source and drain regions, portions of the channel layer 114 directly below the gate spacer 138 (e.g., lower overlapping portions of the channel layer 114 vertically overlapping the gate spacer 138) may be doped with impurities at a relatively low concentration. As a result, the performance of the semiconductor device may be degraded. For example, the lower overlapping portion of the channel layer 114 may have a high resistance, and the semiconductor device may have a relatively low on-current.

[0056] According to the above-described example embodiments, the source and drain regions 120A including the protrusions 120_P may be formed in the recessed region RS1A, and therefore, the lower stacked portion may have a relatively small width. As a result, the semiconductor device 100A may have an increased on-current. In addition, since the source and drain regions 120A have a relatively large volume, a relatively large tensile stress may be applied to the channel region CH located below the gate electrode 134. Therefore, the mobility and DOS of the carriers in the channel region CH may be increased. Therefore, the semiconductor device 100A may have both low leakage current characteristics and improved on-current characteristics.

[0057] Figure 4 is a cross-sectional view of a semiconductor device 100B according to example embodiments. Figure 4 is along Figure 1 The cross-sectional view corresponding to the cross-sectional view taken along the line II-II'. Figure 4 In the present invention, the same reference numerals are used to represent Figures 1 to 3 The same elements as the elements in .

[0058] Reference Figure 4 , each recessed region RS1B of the semiconductor device 100B may have an inclined sidewall RS_S and a flat bottom surface RS_B. The source and drain regions 120B of the semiconductor device 100B may be located in the recessed regions RS1B, respectively. Each of the source and drain regions 120B may include a step unit 120_S at a boundary between the inclined sidewall RS_S and the flat bottom surface RS_B.

[0059] In a manufacturing method according to an example embodiment, portions of the channel layer 114 on both sides of the gate structure 130 may be removed using an anisotropic etching process to form a pre-recessed region (refer to Fig. 10D By extending the pre-recessed region RS1P in the lateral direction, an inclined sidewall RS_S of the recessed region RS1B may be formed at a position overlapping the gate spacer 138.

[0060] According to the above-described example embodiments, due to the source and drain regions 120B formed in the recessed region RS1B and configured to apply tensile stress to the channel layer 114 (e.g., the channel region CH), the channel layer 114 including the homologous oxide may have improved carrier mobility and DOS. In addition, since the recessed region RS1B is vertically overlapped with the gate spacer 138, an increase in resistance caused by a lower overlapping portion of the channel layer 114 vertically overlapped with the gate spacer 138 may be prevented. Therefore, the semiconductor device 100B may have low leakage current characteristics and improved on-current characteristics.

[0061] Figure 5 is a cross-sectional view of a semiconductor device 100C according to example embodiments. Figure 5 is along Figure 1 The cross-sectional view corresponding to the cross-sectional view taken along the line II-II'. Figure 5 In the present invention, the same reference numerals are used to represent Figures 1 to 4 The same elements as the elements in .

[0062] Reference Figure 5 , the recessed region RS1C of the semiconductor device 100C may include an upper expanded region RS_SE. The sidewall of the upper expanded region RS_SE may extend outward from the lower sidewall of the recessed region RS1C and vertically overlap the gate spacer 138. The level LV3 at the bottom surface of the upper expanded region RS_SE may be lower than the top level LV1 of the channel layer 114 and higher than the bottom level LV2 of the recessed region RS1C.

[0063] Each of the source and drain regions 120C may include an upper region 120C1 having a first width w21 and a lower region 120C2 having a second width w22 less than the first width w21. The upper region 120C1 may be located in the upper expansion region RS_SE. The lower region 120C2 may be located below the upper region 120C1 and formed continuously with the upper region 120C1. In an example embodiment, an isotropic etching process is performed to form the upper region 120C1, and an anisotropic etching process is performed to form the lower region 120C2. Because each of the source and drain regions 120C includes the upper region 120C1 and the lower region 120C2, the performance of the semiconductor device 100C may be optimized by appropriately selecting the magnitude of the tensile stress applied to the channel region CH by the source and drain regions 120C and the reduction in the length of the lower layer overlap portion due to the upper region 120C1. For example, by appropriately selecting the width and / or height of the upper region 120C1 and the lower region 120C2, the tensile stress applied to the channel region CH can be increased due to the increase in the total volume of the source and drain regions 120C, while the increase in the resistance of the channel region CH can be prevented due to the reduction in the length of the lower overlapping portion of the channel layer 114 vertically overlapping the gate spacer 138. Therefore, the semiconductor device 100C can have a low leakage current characteristic and an improved on-current characteristic.

[0064] Figure 6 is a cross-sectional view of a semiconductor device 100D according to example embodiments. Figure 6 is along Figure 1 The cross-sectional view corresponding to the cross-sectional view taken along the line II-II'. Figure 6 In the present invention, the same reference numerals are used to represent Figures 1 to 5 The same elements as the elements in .

[0065] Reference Figure 6, the recessed region RS1D of the semiconductor device 100D may pass through the channel layer 114 and the blocking insulating layer 112 and extend into the substrate 110. The recessed region RS1D may have a first height h11d that may be greater than the vertical thickness of the channel layer 114. The bottom level LV2 of the recessed region RS1D may be lower than the top level LV0 of the substrate 110. Each of the source and drain regions 120D may fill the recessed region RS1D, and a portion of a sidewall of each of the source and drain regions 120D may be surrounded by the blocking insulating layer 112. The bottom surface of each of the source and drain regions 120D may be in contact with the top surface of the substrate 110.

[0066] Figure 6 1 shows an example in which the bottom level LV2 of the recessed region RS1D is lower than the top level LV0 of the substrate 110. Figure 6 , the bottom level LV2 of the recessed region RS1D may be equal to the top level LV0 of the substrate 110. In this case, the bottom surface of each of the source and drain regions 120D may be located at the top level LV0 of the substrate 110 and in contact with the top surface of the substrate 110. In other embodiments, the bottom level LV2 of the recessed region RS1D may be higher than the top surface of the substrate 110 and lower than the top level of the blocking insulating layer 112. In this case, the bottom surface of each of the source and drain regions 120D may be surrounded by the blocking insulating layer 112. In other embodiments, the bottom level LV2 of the recessed region RS1D may be higher than the top level LV0 of the substrate 110 and equal to the top level of the blocking insulating layer 112. In this case, the bottom surface of each of the source and drain regions 120D may be in contact with the top surface of the blocking insulating layer 112.

[0067] According to example embodiments, since each of the source and drain regions 120D is located in the recessed region RS1D configured to pass through the channel layer 114, a relatively high tensile stress may be applied to the channel layer 114 through the source and drain regions 120D. Therefore, the semiconductor device 100D may have a low leakage current characteristic and an improved on-current characteristic.

[0068] Figure 7 is a cross-sectional view of a semiconductor device 100E according to example embodiments. Figure 7 is along Figure 1 The cross-sectional view corresponding to the cross-sectional view taken along the line II-II'. Figure 7 In the present invention, the same reference numerals are used to represent Figures 1 to 6 The same elements as the elements in .

[0069] Reference Figure 7The source and drain regions 120E of the semiconductor device 100E may include a first material layer 122 conformally formed on the inner wall of the recessed region RS1 and a second material layer 124 filling the recessed region RS1 on the first material layer 122. The first material layer 122 and the second material layer 124 may include amorphous InO 3 -ZnO(IZO), InGaSiO x , silicon doped with phosphorus (P), silicon doped with arsenic (As), germanium doped with phosphorus, germanium doped with arsenic, or a combination thereof.

[0070] In example embodiments, the first material layer 122 may include impurities of a first concentration, and the second material layer 124 may include impurities of a second concentration higher than the first concentration. In a manufacturing method according to example embodiments, impurities may be in-situ doped at a first concentration during a process of forming the first material layer 122 to a predetermined thickness in the recessed region RS1. Thereafter, impurities may be in-situ doped at a second concentration during a process of forming the second material layer 124 on the first material layer 122 in the recessed region RS1.

[0071] According to other embodiments, the first material layer 122 may include a material having a relatively small lattice constant difference (or lattice mismatch) with a material included in the channel layer 114. The second material layer 124 may include a material having a relatively large lattice constant difference with a material included in the channel layer 114. For example, the second material layer 124 has a lattice constant greater than that of the first material layer 122. In this case, a tensile stress (or compressive stress) applied to the channel region CH by the source and drain regions 120E may be increased, or occurrence of defects in the source and drain regions 120E may be suppressed.

[0072] Figure 7 An example is shown in which the source and drain regions 120E include two layers such as a first material layer 122 and a second material layer 124. In some examples, the source and drain regions 120E may have a multilayer structure of at least three layers including a first material layer 122, a second material layer 124, and at least one additional material layer (not shown), wherein the first material layer 122, the second material layer 124, and the at least one additional material layer may be sequentially formed in the recessed region RS1. For example, the first material layer 122 may include InGaSiO x , the second material layer 124 may include InGaZnO x , at least one additional material layer may include InGaSiO x .

[0073] According to example embodiments, since the source and drain regions 120E have a double-layer structure including impurities of different concentrations, the impurities may be prevented from diffusing from the source and drain regions 120E to the channel region CH. Alternatively, the resistance of the source and drain regions 120E may be reduced, and an increase in resistance due to a lower overlapping portion of the channel layer 114 vertically overlapping the gate spacer 138 may be prevented. Therefore, the semiconductor device 100E may have a low leakage current characteristic and an improved on-current characteristic.

[0074] Figure 8 is a cross-sectional view of a semiconductor device 100F according to example embodiments. Figure 8 is along Figure 1 The cross-sectional view corresponding to the cross-sectional view taken along the line II-II'. Figure 8 In the present invention, the same reference numerals are used to represent Figures 1 to 7 The same elements as the elements in .

[0075] Reference Figure 8 , the gate structure 130A of the semiconductor device 100F may include a gate insulating layer 132A, a gate electrode 134A, a gate capping layer 136A, and a gate spacer 138A. The gate insulating layer 132A may surround both the side surface and the bottom surface of the gate electrode 134A. The gate insulating layer 132A may be located between the gate electrode 134A and the channel layer 114 and between the gate electrode 134A and the gate spacer 138A.

[0076] The gate electrode 134A may include at least one of a metal, a metal nitride, and a metal carbide. For example, the gate electrode 134A may include aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium nitride carbide (TaCN), tantalum carbide (TaC), tantalum nitride (TaSiN), or a combination thereof, but the inventive concept is not limited thereto. In example embodiments, the gate electrode 134A may include a work function control metal inclusion layer and a gap-filling metal film. The work function control metal inclusion layer may include a metal selected from at least one of titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The interstitial metal film may include a tungsten (W) film or an aluminum (Al) film. In example embodiments, the gate electrode 134A may include a stack structure of TiAlC / TiN / W, a stack structure of TiN / TaN / TiAlC / TiN / W, or a stack structure of TiN / TaN / TiN / TiAlC / TiN / W, but the inventive concept is not limited thereto.

[0077] The interlayer insulating film 140 may have a top surface located at the same level as the top surface of the gate structure 130A. The interlayer insulating film 140 may surround the sidewalls of the gate spacer 138. An upper insulating layer 142 may be further located on the interlayer insulating film 140 and the gate structure 130A. The contact plug 150 may pass through the upper insulating layer 142 and the interlayer insulating film 140 and be connected to the top surface of the source and drain regions 120.

[0078] Since the gate electrode 134A includes at least one of a metal, a metal nitride, and a metal carbide, the gate electrode 134A may function as a stressor configured to apply a tensile stress to a portion of the channel layer 114 located below the gate electrode 134A (ie, the channel region CH). Therefore, the semiconductor device 100F may have a low leakage current characteristic and an improved on-current characteristic.

[0079] Fig. 9 is a cross-sectional view of a semiconductor device 100G according to example embodiments. Fig. 9 is along Figure 1 The cross-sectional view corresponding to the cross-sectional view taken along the line II-II'. Fig. 9 In the present invention, the same reference numerals are used to represent Figures 1 to 8 The same elements as the elements in .

[0080] Reference Fig. 9 The capping layer 128 of the semiconductor device 100G may be further located on the source and drain regions 120. The capping layer 128 may include a compressive strain material. In addition, the capping layer 128 may include a material that can help the source and drain regions 120 maintain compressive strain and have a low contact resistance with the metal included in the contact plug 150. For example, the capping layer 128 may include phosphorus-doped silicon, arsenic-doped silicon, phosphorus-doped germanium, arsenic-doped germanium, InZnO doped x and at least one of InAs.

[0081] In example embodiments, the capping layer 128 may cover the entire top surface of the source and drain regions 120, and the contact plug 150 may be located on the capping layer 128. Therefore, the source and drain regions 120 may not be in contact with the contact plug 150, and the capping layer 128 may be interposed between the source and drain regions 120 and the contact plug 150. In other embodiments, the contact plug 150 may extend further downward so that the bottom surface of the contact plug 150 may pass through the capping layer 128 and contact the top surface of the source and drain regions 120. In this case, the capping layer 128 may surround the sidewalls of the contact plug 150 and cover the entire top surface of the remaining region of the source and drain regions 120 that is not in contact with the contact plug 150.

[0082] FIG. 10A to FIG. 10His a cross-sectional view illustrating a method of manufacturing the semiconductor device 100 according to example embodiments.

[0083] exist FIG. 10A to FIG. 10H The process sequence is shown in Figure 1 The cross section corresponding to the cross section taken by the line II-II'. FIG. 10A to FIG. 10H In the present invention, the same reference numerals are used to represent Figures 1 to 9 The same elements as the elements in .

[0084] Reference Fig. 10A , a blocking insulating layer 112 may be formed on the substrate 110. For example, a top level LV0 of the substrate 110 may be at the same level as a level of a bottom surface of the blocking insulating layer 112. The blocking insulating layer 112 may be formed on the substrate 110 using silicon oxide, silicon nitride, and aluminum oxide. The blocking insulating layer 112 may be formed using a chemical vapor deposition (CVD) process, a thermal oxidation process, or an atomic layer deposition (ALD) process.

[0085] Subsequently, a channel layer 114 may be formed on the blocking insulating layer 112. InGaZnO x 、InGaSiO x 、ITZO、IZO、SnO 2 , HIZO, or YGZO to form the channel layer 114. The channel layer 114 may be formed using a physical vapor deposition (PVD) process, a pulsed laser deposition (PLD) process, a CVD process, or an ALD process.

[0086] The channel layer 114 may have an amorphous structure or a c-axis-aligned crystal structure. In example embodiments, a laser annealing process for crystallizing the channel layer 114 may be further performed.

[0087] In some examples, the channel layer 114 may be doped with impurities of at least one element of fluorine (F), hydrogen (H), nitrogen (N), magnesium (Mg), yttrium (Y), ruthenium (Ru), and arsenic (As). For example, in order to dope the channel layer 114 with impurities of at least one element, the impurities may be in-situ doped during the formation of the channel layer 114, or the impurity ions may be implanted after the channel layer 114 is formed.

[0088] Reference Fig. 10B, a mask pattern (not shown) may be formed on the channel layer 114, and the mask pattern may be used as an etching mask to remove portions of the channel layer 114, the blocking insulating layer 112, and the substrate 110, thereby forming a device isolation trench 116T. Thereafter, an insulating layer (not shown) may be formed on the channel layer 114 to fill the device isolation trench 116T, and an upper portion of the insulating layer may be removed until the channel layer 114 is exposed. Thus, a device isolation film 116 may be formed inside the device isolation trench 116T. An active region AC may be defined in the channel layer 114 by the device isolation film 116.

[0089] Subsequently, a pre-gate insulating layer (not shown), a pre-gate electrode layer (not shown), and a gate capping layer 136 may be sequentially formed on the channel layer 114 and the device isolation film 116. The pre-gate electrode layer and the pre-gate insulating layer may be patterned using the gate capping layer 136 as an etching mask, thereby forming the gate electrode 134 and the gate insulating layer 132.

[0090] Reference Fig. 10C , a spacer insulating layer (not shown) may be formed using an ALD process or a CVD process to cover the gate capping layer 136, the gate electrode 134, and the gate insulating layer 132. An anisotropic etching process may be performed on the spacer insulating layer so that gate spacers 138 may be formed on sidewalls of the gate capping layer 136, the gate electrode 134, and the gate insulating layer 132.

[0091] Here, the gate capping layer 136, the gate electrode 134, the gate insulating layer 132 and the gate spacers 138 will be referred to as the gate structure 130. Each gate spacer 138 has a bottom surface at which a second direction (refer to Figure 2 The substrate may have a first thickness t11 of about 2 nm to about 20 nm in the Y direction (in the Y direction), but the inventive concept is not limited thereto.

[0092] Reference Fig. 10D , portions of the channel layer 114 on both sides of the gate structure 130 may be etched to form the pre-recessed region RS1P. For example, the process of forming the pre-recessed region RS1P may be an isotropic etching process using a wet etchant or a dry etchant, but the inventive concept is not limited thereto.

[0093] The bottom level LV2P of the pre-recessed region RS1P may be lower than the top level LV1 of the channel layer 114 and higher than the top level LV0 of the substrate 110. Fig. 10DAs shown in , the sidewalls of the pre-recessed region RS1P may be substantially aligned with the sidewalls of the gate spacer 138. In this case, the shortest distance d11p between the pre-recessed region RS1P and the gate electrode 134 may be equal to or similar to the first thickness t11 of the gate spacer 138. In other embodiments, the pre-recessed region RS1P may be formed to have a thickness greater than t11. Fig. 10D The pre-recessed region RS1P may be positioned not to vertically overlap the gate spacer 138 .

[0094] Reference Fig. 10E , portions of the channel layer 114 exposed by the sidewalls and the bottom of the pre-recessed region RS1P may be further removed by a predetermined thickness to form the recessed region RS1. The removal process may be an isotropic etching process using a wet etchant or a dry etchant, but is not limited thereto.

[0095] exist Fig. 10E , for comparison, the shape of the pre-recessed region RS1P is shown by a dotted line. The pre-recessed region RS1P may expand laterally and downwardly, so that the recessed region RS1 may have a width w11 and / or a height h11 greater than the width and / or height of the pre-recessed region RS1P. Therefore, the shortest distance d11 between the recessed region RS1 and the gate electrode 134 may be smaller than the shortest distance d11p between the pre-recessed region RS1P and the gate electrode 134.

[0096] Reference Fig.10F , a source region and a drain region 120 may be formed to fill the recessed region RS1. The source region and the drain region 120 may be formed by an epitaxial process using the channel layer 114 exposed by the inner wall of the recessed region RS1 as a seed layer. The epitaxial process may be a vapor phase epitaxy (VPE) process, a CVD process (e.g., an ultra-high vacuum chemical vapor deposition (UHV-CVD) process), a molecular beam epitaxy (MBE) process, or a combination thereof. In the epitaxial process, a liquid or gaseous precursor may be used as a precursor for forming the source region and the drain region 120.

[0097] Amorphous InO can be used 3 -ZnO(IZO), InGaSiO x The source and drain regions 120 may be formed by using silicon doped with phosphorus (P), silicon doped with arsenic (As), germanium doped with phosphorus, or germanium doped with arsenic, or a combination thereof. The source and drain regions 120 may be in-situ doped with impurities during the SEG process, or impurity ions may be implanted after the source and drain regions 120 are formed.

[0098] Reference Figure 10G, a laser annealing process P210 may be performed on the source and drain regions 120. The source and drain regions 120 may be crystallized due to the laser annealing process P210. For example, during the formation of the source and drain regions 120, the source and drain regions 120 may be made of amorphous InGaSiO x formed, and crystallized into c-axis oriented crystalline InGaSiO due to the laser annealing process P210 x .

[0099] In some examples, the laser annealing process P210 may be omitted.

[0100] Reference Fig. 10H , an interlayer insulating film 140 may be formed on the channel layer 114, the source and drain regions 120, and the gate structure 130. Thereafter, a mask pattern (not shown) may be formed on the interlayer insulating film 140, and a contact hole 150H may be formed using the mask pattern as an etching mask. The contact hole 150H may pass through the interlayer insulating film 140 and expose the top surface of the source and drain regions 120.

[0101] A conductive layer (not shown) may be formed on the interlayer insulating film 140 to fill the contact holes 150H, and an upper portion of the conductive layer may be removed until the top surface of the interlayer insulating film 140 is exposed. Thus, contact plugs 150 may be formed inside the contact holes 150H. Each contact plug 150 may have a double-layer structure including a metal filling layer (not shown) and a conductive barrier layer (not shown), the conductive barrier layer being configured to surround the side surface and the bottom surface of the metal filling layer.

[0102] The above-described processes may be performed to complete the manufacture of the semiconductor device 100 .

[0103] According to the above-described example embodiments, due to the source and drain regions 120 formed in the recessed region RS1 and configured to apply tensile stress to the channel layer 114, the mobility and DOS of carriers in the channel layer 114 including the homologous oxide may be improved. In addition, due to the process of extending the pre-recessed region RS1P in the lateral direction, the recessed region RS1 may be vertically overlapped with the gate spacer 138. Therefore, an increase in resistance due to a lower overlapping portion of the channel layer 114 vertically overlapped with the gate spacer 138 may be prevented. Therefore, the semiconductor device 100 may have both low leakage current characteristics and improved on-current characteristics.

[0104] FIG. 11A to FIG. 11E is a cross-sectional view illustrating a method of manufacturing a semiconductor device 100F according to example embodiments.

[0105] exist FIG. 11A to FIG. 11E The process sequence is shown in Figure 1 The cross-sectional view corresponding to the cross-sectional view taken along the line II-II'. FIG. 11A to FIG. 11E In the present invention, the same reference numerals are used to represent Figures 1 to 9 and FIG. 10A to FIG. 10H The same elements as the elements in .

[0106] First, you can perform a reference FIG. 10A to FIG. 10G The process is described to form a structure including a sacrificial gate structure 130 and source and drain regions 120. The sacrificial gate structure 130 may include a sacrificial gate insulating layer 132, a sacrificial gate electrode 134, a sacrificial gate capping layer 136, and gate spacers 138A.

[0107] Reference Fig.11A An insulating layer (not shown) may be formed on the channel layer 114, the source and drain regions 120, the sacrificial gate capping layer 136, and the gate spacer 138A. The upper portion of the insulating layer may be planarized until the top surfaces of the sacrificial gate capping layer 136 and the gate spacer 138A are exposed, thereby forming an interlayer insulating film 140.

[0108] Reference Fig. 11B , the sacrificial gate capping layer can be removed (refer to Fig.11A 136), sacrificial gate electrode (refer to Fig.11A 134) and a sacrificial gate insulating layer (refer to Fig.11A 132 in the gate spacer 138A), so that a gate space GS can be defined between the sidewalls of the gate spacer 138A. In example embodiments, the process of removing the sacrificial gate capping layer 136, the sacrificial gate electrode 134, and the sacrificial gate insulating layer 132 may include a wet etching process. For example, a wet etching process including HNO 3 , dilute fluoric acid (DHF), NH 4 The wet etching process is performed by using an etchant selected from the group consisting of OH, tetramethylammonium hydroxide (TMAH), KOH, or a combination thereof.

[0109] Reference Fig. 11C , a pre-gate insulating layer 132AP may be formed on the inner wall of the gate space GS. Thereafter, a pre-gate electrode layer 134AP may be formed on the pre-gate insulating layer 132AP to fill the inside of the gate space GS.

[0110] Reference Fig.11D , the pre-gate electrode layer can be etched back (refer to Fig. 11C 134AP) and the pre-gate insulation layer (refer to Fig. 11C The upper portion of the gate space GS is exposed again due to the etch-back process.

[0111] Reference Fig.11E, an insulating layer (not shown) may be formed on the gate electrode 134A and the gate insulating layer 132A to fill the remaining portion of the gate space GS. Thereafter, the upper portion of the insulating layer may be removed until the top surface of the interlayer insulating film 140 or the top surface of the gate spacer 138A is exposed. Thus, a gate capping layer 136A may be formed to fill the gate space GS.

[0112] Thereafter, an upper insulating layer 142 may be formed on the gate capping layer 136A, the gate spacer 138A, and the interlayer insulating film 140. Subsequently, a contact hole 150H may be formed to pass through the upper insulating layer 142 and the interlayer insulating film 140, and a contact plug 150 may be formed to fill the contact hole 150H.

[0113] The above-described processes may be performed to complete the manufacture of the semiconductor device 100F.

[0114] In other embodiments, during the process of forming the recessed region RS1A, a portion of the sidewall of the channel layer 114 located at a level lower than the top level LV1 of the channel layer 114 may be more exposed to the etchant or more collided with the etchant than a portion of the channel layer 114 located at the top level LV1 of the channel layer 114. Therefore, the recessed region RS1A may be expanded to the maximum extent in the lateral direction at a level lower than the top level LV1 of the channel layer 114, and each of the source and drain regions 120A may include a protrusion 120_P. In this case, the reference 120 may be formed. Figure 3 A semiconductor device 100A is described.

[0115] In other embodiments, in order to form the recessed region RS1B, an anisotropic etching process may be performed, or an anisotropic etching process and a subsequent enlargement process may be performed. Thus, the recessed region RS1B including the step unit 120_S may be formed. In this case, the reference Figure 4 A semiconductor device 100B is described.

[0116] In other embodiments, in order to form the recessed region RS1C, two etching processes may be performed. For example, a first etching process may be used to first form an upper expanded region RS_SE having a first width w21. Thereafter, a second etching process may be used to form the bottom of the recessed region RS1C having a second width w22. In this case, the first etching process may be an isotropic etching process, and the second etching process may be an anisotropic etching process. In another case, a first etching process may be used to first form the bottom of the recessed region RS1C having a second width w22. Thereafter, a second etching process may be used to form the upper expanded region RS_SE having a first width w21. In this case, the first etching process may be an anisotropic etching process, the second etching process may be an isotropic etching process, and a reference may be formed. Figure 5 A semiconductor device 100C is described.

[0117] Typical example embodiments of the inventive concept are disclosed in the above description and accompanying drawings. Although specific terms are employed, they are used only in a general and descriptive sense and not for the purpose of limitation. It will be understood by those skilled in the art that various changes in form and details may be made to the disclosed embodiments without departing from the spirit and scope of the inventive concept as defined by the claims.

Claims

1. A semiconductor device, the semiconductor device include: substrate; a blocking insulating layer disposed on the substrate; A channel layer is located on the blocking insulating layer, the channel layer includes a conductive oxide, the conductive oxide is a homologous oxide, and the semiconductor device includes a PMOS transistor or an NMOS transistor; A gate structure, located on the channel layer, the gate structure comprising a gate electrode and gate spacers located on two sidewalls of the gate electrode; as well as a source region and a drain region located on both sides of the gate structure in a recessed area having a first height from a top surface of the channel layer, Wherein, when the semiconductor device comprises a PMOS transistor, the source region and the drain region comprise strained materials, and the source region and the drain region are configured to apply compressive stress to a portion of the channel layer located below the gate structure, Wherein, when the semiconductor device comprises an NMOS transistor, the source region and the drain region comprise a compressive strain material, and the source region and the drain region are configured to apply a tensile stress to a portion of the channel layer located below the gate structure, and Among them, conductive oxides include InGaZnO x 、InGaSiO x 、InSnZnO x 、InZnO x SnO 2 and HfInZnO x At least one of Conductive oxides include RAO 3 (MO) m The material represented by is, and R is at least one of scandium, ytterbium, lutetium and indium, A is at least one of gallium, aluminum, iron and indium, M is at least one of zinc and magnesium, and m is an integer.

2. The semiconductor device according to claim 1, in, Each of the source region and the drain region includes amorphous InO 3 -ZnO, InGaSiO x , at least one of phosphorus-doped silicon, arsenic-doped silicon, phosphorus-doped germanium and arsenic-doped germanium.

3. The semiconductor device according to claim 1, in, The gate structure extends in a first direction parallel to the top surface of the substrate, wherein each of the gate spacers has a first thickness in a second direction perpendicular to the first direction and parallel to the top surface of the substrate, and Wherein, a distance between each of the source region and the drain region and the gate electrode in the second direction is smaller than the first thickness.

4. The semiconductor device according to claim 1, in, The gate spacer vertically partially overlaps the source region and the drain region.

5. The semiconductor device according to claim 1, in, A boundary between a side wall and a bottom of each recessed region has a rounded shape.

6. The semiconductor device according to claim 1, in, Each of the source region and the drain region includes: A first material layer conformally disposed on an inner wall of the recessed region, the first material layer comprising impurities of a first concentration; and A second material layer is provided on the first material layer to fill the recessed region, and the second material layer includes impurities of a second concentration different from the first concentration.

7. The semiconductor device according to claim 1, in, In a first direction parallel to the top surface of the substrate, a maximum width of each of the source region and the drain region is at the same level as a top surface of the source region and the drain region.

8. The semiconductor device according to claim 1, in, Each of the source region and the drain region includes a protrusion protruding outward in a first direction parallel to a top surface of the substrate, and The maximum width of each of the source region and the drain region in the first direction is at a level lower than top surfaces of the source region and the drain region and higher than bottom surfaces of the source region and the drain region.

9. The semiconductor device according to claim 1, in, Each of the source region and the drain region includes: an upper region having a first width in a first direction parallel to the top surface of the substrate; and The lower region is located below the upper region, and the lower region has a second width in the first direction that is smaller than the first width.

10. The semiconductor device according to claim 1, in, The gate structure further includes a gate insulating layer between the gate electrode and the channel layer and between the gate electrode and the gate spacer. wherein the gate electrode comprises at least one of a metal, a metal nitride and a metal carbide, and The gate electrode is configured to apply tensile stress to a portion of the channel layer located below the gate structure.

11. The semiconductor device according to claim 1, further comprising: include: a capping layer, located on the source region and the drain region; as well as A contact plug, located on the cover layer, The covering layer includes at least one of phosphorus-doped silicon, arsenic-doped silicon, phosphorus-doped germanium, arsenic-doped germanium, doped indium zinc oxide and indium arsenide.

12. The semiconductor device according to claim 1, in, The channel layer has a first lattice constant, and each of the source region and the drain region includes a material layer having a second lattice constant lower than the first lattice constant.

13. The semiconductor device according to claim 1, further comprising: include: The insulating layer is located between the substrate and the channel layer. The insulating layer includes at least one of silicon oxide, silicon nitride and aluminum oxide.

14. A semiconductor device, the semiconductor device include: substrate; a blocking insulating layer disposed on the substrate; A channel layer is located on the blocking insulating layer, the channel layer includes a conductive oxide, and the semiconductor device includes a PMOS transistor or an NMOS transistor; A gate structure, located on the channel layer, the gate structure comprising a gate electrode and gate spacers located on both sides of the gate electrode; as well as a source region and a drain region located on both sides of the gate structure in a recessed area having a first height from a top surface of the channel layer, wherein the source region and the drain region partially overlap with the gate spacer in a direction perpendicular to the top surface of the substrate, and Among them, conductive oxides include InGaZnO x 、InGaSiO x 、InSnZnO x 、InZnO x SnO 2 and HfInZnO x At least one of Conductive oxides include RAO 3 (MO) m The material represented by is, and R is at least one of scandium, ytterbium, lutetium and indium, A is at least one of gallium, aluminum, iron and indium, M is at least one of zinc and magnesium, and m is an integer.

15. The semiconductor device according to claim 14, in, The gate structure extends in a first direction parallel to the top surface of the substrate, wherein each of the gate spacers has a first thickness in a second direction perpendicular to the first direction and parallel to the top surface of the substrate, and Wherein, a distance between each of the source region and the drain region and the gate electrode in the second direction is smaller than the first thickness.

16. The semiconductor device according to claim 14, in, Conductive oxides are homologous oxides. Wherein, when the semiconductor device comprises a PMOS transistor, the source region and the drain region comprise strained materials, and the source region and the drain region are configured to apply compressive stress to a portion of the channel layer located below the gate structure, and Wherein, when the semiconductor device includes an NMOS transistor, the source region and the drain region include a compressive strain material, and the source region and the drain region are configured to apply a tensile stress to a portion of the channel layer located below the gate structure.

17. A semiconductor device, the semiconductor device include: substrate; a blocking insulating layer disposed on the substrate; A channel layer is located on the blocking insulating layer, and the semiconductor device includes a PMOS transistor or an NMOS transistor; A gate structure is located on the channel layer, the gate structure comprising gate spacers located on two sidewalls of the gate electrode; as well as a source region and a drain region located on both sides of the gate structure in a recessed area having a first height from a top surface of the channel layer, Wherein, when the semiconductor device comprises a PMOS transistor, the source region and the drain region comprise strained materials, and the source region and the drain region are configured to apply compressive stress to a portion of the channel layer located below the gate structure, Wherein, when the semiconductor device comprises an NMOS transistor, the source region and the drain region comprise a compressive strain material, and the source region and the drain region are configured to apply a tensile stress to a portion of the channel layer located below the gate structure, The channel layer includes RAO 3 (MO) m The material indicated, Wherein, R is at least one of scandium, ytterbium, lutetium and indium, A is at least one of gallium, aluminum, iron and indium, M is at least one of zinc and magnesium, and m is an integer.

18. The semiconductor device according to claim 17, further comprising: include: a capping layer, located on the source region and the drain region; as well as A contact plug, located on the cover layer, wherein the cover layer comprises a compressively strained material, and The covering layer includes at least one of phosphorus-doped silicon, arsenic-doped silicon, phosphorus-doped germanium, arsenic-doped germanium, doped indium zinc oxide and indium arsenide.

19. The semiconductor device according to claim 17, in, The recessed region extends from the same level as a top surface of the channel layer to a level lower than a bottom surface of the channel layer, and The bottom surfaces of the source region and the drain region are in contact with the top surface of the substrate.

20. The semiconductor device according to claim 17, in, Each of the source region and the drain region includes: A first material layer conformally disposed on an inner wall of the recessed region, the first material layer having a first lattice constant; and The second material layer fills the recessed area on the first material layer, and the second material layer has a second lattice constant different from the first lattice constant.

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