A wireless charging parallel chip device, wireless charging method and device
Through the parallel resonant cavity structure and transistor control, the problem of heat waste caused by parasitic resistance under high power in wireless charging is solved, and a more efficient charging effect is achieved.
Patent Information
- Application Number
- CN202010462120.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-05-27
- Publication Date
- 2025-09-23
- Estimated Expiration
- 2040-05-27
Smart Images

Figure CN111463908B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of wireless charging, and in particular relates to a wireless charging parallel chip device, a wireless charging method and a device. Background Art
[0002] Wireless charging technology originates from wireless power transmission and can be categorized into low-power and high-power wireless charging. Low-power wireless charging often utilizes electromagnetic induction, such as the Qi method used to charge mobile phones. This involves a power supply (charger) transmitting energy to a device that uses the energy to charge its battery and power itself. Because energy is transferred between the charger and the device via a magnetic field, eliminating the need for wires, neither the charger nor the device has exposed conductive contacts.
[0003] In high-power charging state, the chip's inherent parasitic resistance will generate heat, resulting in a waste of transmission power. Summary of the Invention
[0004] To address the deficiencies in the prior art, the present invention proposes a wireless charging parallel chip device, a wireless charging method, and a device, which solve the problem that when the current increases, the inductor coil wastes a lot of power and generates heat.
[0005] A wireless charging parallel chip device includes a resonance unit and a bridge rectifier chip. The resonance unit is connected to the bridge rectifier chip, and the bridge rectifier chip is connected in parallel with another rectifier chip.
[0006] The resonance unit includes at least two resonance cavities.
[0007] There are two resonant cavities, including a first resonant cavity and a second resonant cavity connected in parallel with each other, the first resonant cavity includes a first inductor Ls1 and a first capacitor Cs1 connected in series with each other, and the second resonant cavity includes a second inductor Ls2 and a second capacitor Cs2 connected in series with each other, and both ends of the first resonant cavity and the second resonant cavity are connected to the input end of the bridge rectifier chip;
[0008] A first switch M5e is provided in series between the second capacitor and the bridge rectifier chip, and a second switch is provided in series between the second inductor and the bridge rectifier chip;
[0009] Wires are connected between the first inductor Ls1 and the first capacitor Cs1 , and between the second inductor L2 and the second capacitor Cs2 .
[0010] The first capacitor Cs1 and the second capacitor Cs2 have the same capacitance value.
[0011] The first inductor Ls1 and the second inductor Ls2 have the same inductance value.
[0012] The second switch includes two field effect transistors, a first transistor M6e and a second transistor M7e;
[0013] The gate of the first transistor M6e is connected to the gate of the second transistor M7e, and is also connected to the first driving terminal DRV_M6e of the bridge rectifier chip. The source of the first transistor M6e is connected to the source of the second transistor M7e. The drain of the first transistor M6e is connected to one end of the second inductor Ls2. The drain of the second transistor M7e is connected to one end of the first inductor Ls1.
[0014] A filter capacitor is connected in parallel with the first resonant cavity and the second resonant cavity.
[0015] The rectifier chip includes a rectifier unit and a logic control unit. The rectifier unit is connected to the bridge rectifier chip via the logic control unit.
[0016] The resonance unit includes a resonance cavity.
[0017] A wireless charging method is implemented using the wireless charging parallel resonant cavity;
[0018] In the first working state, when the first switch and the second switch are both turned off, the first resonant cavity is connected;
[0019] In the second working state, when the first switch and the second switch are both turned on, the first resonant cavity and the second resonant cavity are connected.
[0020] A wireless charging device comprises the wireless charging parallel chip device.
[0021] Beneficial effects achieved by this application:
[0022] The present invention provides a wireless charging parallel chip device and a wireless charging device. When in a high-power charging state, the rectifier unit reduces parasitic resistance due to the effect of parallel connection, thereby reducing power loss and heat generation. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 : Schematic diagram of a wireless charging parallel chip device with two resonant cavities according to an embodiment of the present invention;
[0024] Figure 2 : Schematic diagram of a wireless charging parallel chip device with a resonant cavity according to an embodiment of the present invention. DETAILED DESCRIPTION
[0025] The present application will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present application.
[0026] A wireless charging parallel chip device includes a resonance unit and a bridge rectifier chip. The resonance unit is connected to the bridge rectifier chip, and the bridge rectifier chip is connected in parallel with another rectifier chip.
[0027] The resonance unit includes at least two resonance cavities.
[0028] There are two resonant cavities, including a first resonant cavity and a second resonant cavity connected in parallel with each other, the first resonant cavity includes a first inductor Ls1 and a first capacitor Cs1 connected in series with each other, and the second resonant cavity includes a second inductor Ls2 and a second capacitor Cs2 connected in series with each other, and both ends of the first resonant cavity and the second resonant cavity are connected to the input end of the bridge rectifier chip;
[0029] A first switch M5e is provided in series between the second capacitor and the bridge rectifier chip, and a second switch is provided in series between the second inductor and the bridge rectifier chip;
[0030] Wires are connected between the first inductor Ls1 and the first capacitor Cs1 , and between the second inductor L2 and the second capacitor Cs2 .
[0031] The purpose of the wires: When two resonant cavities are connected in parallel, the inductance of L decreases and the value of C increases, ensuring stable resonant frequencies. In a preferred embodiment, the inductances of Ls1 and Ls2 are equal, and the capacitances of Cs1 and Cs2 are equal. This results in the inductance of the new resonant cavity being half the original value and the capacitance being doubled. The overall resonant frequency remains unchanged, ensuring that after the change, it matches the resonant cavity at the transmitter, ensuring maximum transmission efficiency.
[0032] The first capacitor Cs1 and the second capacitor Cs2 have the same capacitance value.
[0033] The first inductor Ls1 and the second inductor Ls2 have the same inductance value.
[0034] A wireless charging method is implemented using the wireless charging parallel resonant cavity;
[0035] In the first working state, when the first switch and the second switch are both turned off, the first resonant cavity is connected;
[0036] In the second working state, when the first switch and the second switch are both turned on, the first resonant cavity and the second resonant cavity are connected.
[0037] When the first switch and the second switch are both turned off, that is, the first switch M5e, the first transistor M6e and the second transistor M7e are all in the off state and connected to the first resonant cavity;
[0038] At this time, the device is in a low-power state and is connected to a resonant cavity. Since the current is small, it will not generate high heat.
[0039] In order to make the receiving coil easily driven by the wireless transmitting coil, Ls1 and Cs1 are 8μH and 300nH;
[0040] At low power, the first resonant cavity Ls1, Cs1 works, and the resonant frequency is:
[0041]
[0042] Among them, f T1 is the resonant frequency in the first working state, Ls1 is the inductance value of the first inductor Ls1, and Cs1 is the capacitance value of the first capacitor Cs1;
[0043] In the second working state, when the first switch and the second switch are both turned on, that is, the first switch M5e, the first transistor M6e and the second transistor M7e are all in the on state, connecting the first resonant cavity and the second resonant cavity;
[0044] In low-power operation, due to the low current, the heat generated by the resonant cavity is low, the temperature rise is not significant, and the impact on the operation of the semiconductor device is not significant.
[0045] In high-power operation, the current increases compared to low-power operation. In the aforementioned low-power state, if the resonant cavity does not change, the heat generated by the cavity increases, causing the temperature to rise, affecting the normal operation of the semiconductor device. Since the total power transmitted from the transmitter to the receiver is constant, the increase in the heat generated by the cavity reduces the actual power used for charging. To this end, in high-power operation, another resonant cavity is incorporated by changing the connection relationship, reducing the parasitic resistance of the entire resonant unit, thereby reducing the heat generated and improving the actual charging efficiency.
[0046] When the charging current increases, Rx sends a predetermined instruction to Tx, causing Tx to increase the voltage of the transmitting coil; at the same time:
[0047] DRV_M5e=BSTP;
[0048] DRV_M6e=BSTN;
[0049] Among them, DRV_M5e is the voltage of the drive signal terminal DRV_M5e of the bridge rectifier chip IC, DRV_M6e is the voltage of the drive signal terminal DRV_M6e of the bridge rectifier chip IC, BSTP is the voltage of the bridge rectifier chip connection point BSTP, and BSTN is the voltage of the bridge rectifier chip connection point BSTN.
[0050] External MOSFETs: M5e, M6e, and M7e are turned on simultaneously, with an on-resistance of 10mOhms. By properly designing Ls2 = Ls1 and Cs2 = Cs1, the inductance and capacitance of the resonant cavity are:
[0051]
[0052] Cs Total =2·Cs1
[0053] Therefore, the resonant frequency of the resonant cavity remains unchanged:
[0054]
[0055] Among them, Ls Total is the total inductance of the resonant cavity, Cs Total is the total capacitance of the resonant cavity.
[0056] However, the parallel connection of Ls1 and Ls2 reduces the series parasitic resistance of the coil to 1 / 2 of the original resistance, thus saving power consumption and reducing heat generation.
[0057] The second switch includes two field effect transistors, a first transistor M6e and a second transistor M7e;
[0058] The gate of the first transistor M6e is connected to the gate of the second transistor M7e, and is also connected to the first driving terminal DRV_M6e of the bridge rectifier chip. The source of the first transistor M6e is connected to the source of the second transistor M7e. The drain of the first transistor M6e is connected to one end of the second inductor Ls2. The drain of the second transistor M7e is connected to one end of the first inductor Ls1.
[0059] A filter capacitor is connected in parallel with the first resonant cavity and the second resonant cavity.
[0060] The rectifier chip includes a rectifier unit and a logic control unit, and the rectifier unit is connected to the bridge rectifier chip through the logic control unit. Figure 1 The detailed connection method is described as follows:
[0061] Specifically including: a first switch M5e, a first transistor M6e, a second transistor M7e, a first inductor Ls1, a second inductor Ls2, a first capacitor Cs1, and a second capacitor Cs2;
[0062] The first inductor Ls1 and the first capacitor Cs1 are connected in series to form a first resonant cavity, and the second inductor Ls2 and the second capacitor Cs2 are connected in series to form a second resonant cavity. The first resonant cavity and the second resonant cavity are connected in parallel and are both connected to a bridge rectifier chip.
[0063] The first switch M5e is located on the second capacitor Cs2 side of the second resonant cavity, and is respectively connected to the second capacitor Cs2 and the bridge rectifier chip. The first transistor M6e and the second transistor M7e are connected in series and are placed on the second inductor Ls2 side of the second resonant cavity, and are respectively connected to the second inductor Ls2 and the bridge rectifier chip. The connection point between the first inductor Ls1 and the first capacitor Cs1 is connected to the connection point between the second inductor Ls2 and the second capacitor Cs2.
[0064] In the first resonant cavity, one end of the first capacitor Cs1 is connected to the connection point ACP of the bridge rectifier chip, and the other end is respectively connected to one end of the first inductor Ls1 and the connection point between the second inductor Ls2 and the second capacitor Cs2; the other end of the first inductor Ls1 is connected to the connection point ACN of the bridge rectifier chip; the connection point ACN of the bridge rectifier chip is connected to the drain of the second transistor M7e, the source of the second transistor M7e is connected to the source of the first transistor M6e, and the gate of the second transistor M7e is respectively connected to the drain of the second transistor M7e and the source of the second transistor M6e. The first transistor M6e is connected to the gate of the first transistor M6e and the drive signal terminal DRV_M6e of the bridge rectifier chip. The drain of the first transistor M6e is connected to one end of the second inductor Ls2. The other end of the second inductor Ls2 is connected to one end of the second capacitor Cs2. The other end of the second capacitor Cs2 is connected to the drain of the first switch M5e. The source of the first switch M5e is connected to the connection point ACP of the bridge rectifier chip. The gate of the first switch M5e is connected to the drive signal terminal DRV_M5e of the bridge rectifier chip.
[0065] The first rectifier unit includes: M1, M2, M3, and M4.
[0066] The second rectifier unit includes: M1e, M2e, M3e, and M4e.
[0067] The resonant unit includes a resonant cavity, such as Figure 2 shown.
[0068] The resonant cavity includes: a first inductor Ls1 and a first capacitor Cs1;
[0069] One end of the first inductor Ls1 is connected to one end of the first capacitor Cs1, and the other end of the first capacitor Cs1 is respectively connected to the connection point ACP and one end of the filter capacitor C3, and the other end of the first inductor Ls1 is respectively connected to the other end of C3 and the connection point ACN.
[0070] The applicant of the present invention has made a detailed explanation and description of the implementation examples of the present invention in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation plans of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, and is not a limitation on the scope of protection of the present invention. On the contrary, any improvements or modifications based on the inventive spirit of the present invention should fall within the scope of protection of the present invention.
Claims
1. A wireless charging parallel chip device, comprising a resonance unit and a bridge rectifier chip, wherein the resonance unit is connected to the bridge rectifier chip, characterized in that: The bridge rectifier chip is connected in parallel with another rectifier chip; The resonant unit includes a first resonant cavity and a second resonant cavity connected in parallel to each other, the first resonant cavity includes a first inductor (Ls1) and a first capacitor (Cs1) connected in series, and the second resonant cavity includes a second inductor (Ls2) and a second capacitor (Cs2) connected in series, and both ends of the first resonant cavity and the second resonant cavity are connected to the input end of the bridge rectifier chip; A first switch is provided in series between the second capacitor and the bridge rectifier chip, and a second switch is provided in series between the second inductor and the bridge rectifier chip; A wire is connected between the first inductor (Ls1) and the first capacitor (Cs1), and between the second inductor (Ls2) and the second capacitor (Cs2); The first capacitor (Cs1) and the second capacitor (Cs2) have the same capacitance value; The first inductor (Ls1) and the second inductor (Ls2) have equal inductance values; The second switch includes two field effect transistors, a first transistor (M6e) and a second transistor (M7e); The gate of the first transistor (M6e) is connected to the gate of the second transistor (M7e) and is also connected to the first driving end (DRV_M6e) of the bridge rectifier chip. The source of the first transistor (M6e) is connected to the source of the second transistor (M7e). The drain of the first transistor (M6e) is connected to one end of the second inductor (Ls2). The other end of the second inductor (Ls2) is connected to one end of the second capacitor (Cs2). The other end of the second capacitor (Cs2) is connected to one end of the first switch. The other end of the first switch is connected to the input end of the bridge rectifier chip. The drain of the second transistor (M7e) is connected to one end of the first inductor (Ls1) and the input end of the bridge rectifier chip. The other end of the first inductor (Ls1) is connected to one end of the first capacitor (Cs1). The other end of the first capacitor (Cs1) is connected to the input end of the bridge rectifier chip. A filter capacitor is connected in parallel with the first resonant cavity and the second resonant cavity; The rectifier chip includes a rectifier unit and a logic control unit, and the rectifier unit is connected to the bridge rectifier chip through the logic control unit; In the first working state, when the first switch and the second switch are both turned off, the first resonant cavity is connected; In the second working state, when the first switch and the second switch are both turned on, the first resonant cavity and the second resonant cavity are connected.
2. A wireless charging device, characterized in that: The invention comprises the wireless charging parallel chip device described in claim 1.
Citation Information
Patent Citations
Non-contact power transmission device
CN107276247A
Wireless charging parallel chip device and wireless charging device
CN212114904U