Power converter, synchronous rectifier controller for switch mode power supply and method thereof

Abstract

The present invention relates to a power converter, a synchronous rectifier controller for a switch mode power supply and a method thereof. In one form, the power converter includes a transformer, a first primary side transistor coupled to a primary winding, a primary side controller providing a gate signal to the gate of the first primary side transistor, a first synchronous rectifier SR transistor, and an SR controller. The first SR transistor has a drain coupled to the secondary winding of the transformer, a gate for receiving a first SR gate signal, and a source coupled to a first output terminal of the power converter. The SR controller is coupled to the gate and drain of the first SR transistor and is used to activate the first SR gate signal when the voltage on the drain drops below a turn-on threshold and deactivate the first SR gate signal when the voltage on the drain rises above a variable turn-off threshold, wherein the variable turn-off threshold increases within the expected turn-on time of the first SR gate signal.

Description

Technical Field

[0001] The present disclosure relates generally to power conversion circuits, and more particularly to synchronous rectifiers for use in switch mode power supplies and the like. Background Art

[0002] A switch mode power supply can be used to generate a DC voltage from a direct current (DC) or alternating current (AC) input voltage by switching current through an energy storage component such as a transformer. The duty cycle of the switch is controlled to regulate the output voltage to the desired level. The secondary side of the transformer is used to deliver power to the load at a regulated voltage. Typically, a switch mode power supply delivers power to the output capacitor and load through a rectifier, which prevents reverse current flow when the power supply conducts current through the primary winding of the transformer.

[0003] Rectifiers can take two forms. A passive rectifier, such as a diode, can be placed in series with the secondary winding to prevent reverse current flow. However, if the output supply voltage exceeds the breakdown voltage of the diode, the diode cannot properly prevent reverse current flow. In addition, the diode causes a forward voltage drop when it is turned on, thereby reducing the efficiency of the converter. To address these problems, another form of rectifier called a synchronous rectifier is often used. A synchronous rectifier includes an active switch (usually an N-channel metal oxide semiconductor field effect transistor (MOSFET)) connected in series with the secondary winding, and a controller that turns on the transistor at the appropriate time. Since the transistor can be fully biased to turn on, a synchronous rectifier is generally more efficient than a passive rectifier.

[0004] The synchronous rectifier compares the drain voltage with various thresholds to determine when to turn on and off the synchronous rectifier transistor. In order to reduce the dead time and achieve high efficiency, a higher turn-off threshold voltage is required. If the stray inductance caused by the MOSFET package and the printed circuit board (PCB) pattern is large, the positive turn-off threshold shows much higher system efficiency and smaller dead time. However, the positive turn-off threshold can cause delayed turn-off during transient conditions and cause reverse current and drain spikes. In order to prevent delayed turn-off during transient conditions, the turn-off time threshold can be set to about zero volts or even negative values. However, a zero or negative turn-off threshold reduces the system efficiency of itself. Therefore, it is difficult to achieve a smaller dead time while avoiding reverse current and drain spikes during the synchronous rectifier turn-off. Summary of the invention

[0005] In one aspect, a power converter includes a transformer, a first primary side transistor, a primary side controller, a first synchronous rectifier (SR) transistor, and a synchronous rectifier controller. The transformer has a primary winding and a secondary winding. The first primary side transistor is coupled to the primary winding and has a gate for receiving a first primary gate signal, wherein the first primary side transistor causes the primary winding to selectively conduct current in response to the first primary gate signal. The primary side controller has an input for receiving a voltage feedback signal and an output for providing the first primary gate signal. The first synchronous rectifier (SR) transistor has a drain coupled to the secondary winding, a gate for receiving a first SR gate signal, and a source coupled to a first output terminal of the power converter. The synchronous rectifier controller is coupled to the gate and the drain of the first SR transistor and is used to activate the first SR gate signal when the voltage on the drain drops below a turn-on threshold, and to deactivate the first SR gate signal when the voltage on the drain rises above a variable turn-off threshold, wherein the variable turn-off threshold increases within the expected turn-on time of the first SR gate signal.

[0006] In another aspect, a controller for use with a synchronous rectifier (SR) transistor having a drain, a gate, and a source includes a first comparator, a second comparator, a third comparator, and a fourth comparator, a logic circuit, a latch, and a gate driver. The first comparator has a negative input adapted to be coupled to the drain of the SR transistor, a positive input, and an output. The second comparator has a positive input adapted to be coupled to the drain of the SR transistor, a negative input for receiving a first value, and an output. The third comparator has a positive input adapted to be coupled to the drain of the SR transistor, a negative input for receiving a second value, and an output. The fourth comparator has a positive input adapted to be coupled to the drain of the SR transistor, a negative input for receiving a third value, and an output. The logic circuit is coupled to the outputs of the second comparator, the third comparator, and the fourth comparator and has an output, wherein if the output of any of the second comparator, the third comparator, and the fourth comparator is active during the respective first, second, and third portions of the expected on-time, the logic circuit activates the output thereof. A latch has a set input coupled to the output of the first comparator, a reset input coupled to the output of the logic circuit, and an output. A gate driver has an input coupled to the output of the latch, and an output adapted to be coupled to a gate of an SR transistor.

[0007] In another aspect, a method for power conversion using a synchronous rectifier (SR) transistor includes sensing a drain voltage on a drain of the SR transistor; activating a gate signal to turn on the SR transistor in response to the drain voltage dropping below a turn-on threshold; and deactivating the gate signal when the drain voltage rises above a variable turn-off threshold, wherein the variable turn-off threshold increases within an expected turn-on time of the gate signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referring to the accompanying drawings, in which:

[0009] Figure 1 The electrical model of the synchronous rectifier transistor is shown in schematic form;

[0010] Figure 2 shows a diagram useful for understanding its operation Figure 1 The timing diagram of the signal of the electrical model;

[0011] Figure 3 shows a timing diagram showing the positive turn-off threshold when Figure 1 The operation of synchronous rectifier under light load conditions;

[0012] Figure 4 shows a timing diagram showing the zero turn-off threshold Figure 1 The operation of synchronous rectifier under light load conditions;

[0013] Figure 5 shows in schematic form a switched mode power supply according to various embodiments;

[0014] Figure 6 shows a timing diagram that shows Figure 5 The operation of the synchronous rectifier transistors of a switch mode power supply.

[0015] Figure 7 shows a timing diagram that shows Figure 5 The operation of the synchronous rectifier transistor under varying load conditions;

[0016] Figure 8 A block diagram is shown that can be used to implement Figure 5 A synchronous rectifier controller of a synchronous rectifier controller;

[0017] Fig. 9 The block diagram shows the Figure 8 A timing generator of an embodiment of a timing generator;

[0018] Fig.10A block diagram is shown that can be used to implement Figure 8 Another embodiment of the timing generator of the timing generator;

[0019] Fig.11 shows a timing diagram that shows Figure 8 The operation of another embodiment of a synchronous rectifier; and

[0020] Fig.12 A partial block diagram and a partial schematic diagram are provided to illustrate a method for implementing Fig.11 The timing diagram of the operation of the sequential circuit.

[0021] The same reference symbols are used in different drawings to indicate the same or similar components. Unless otherwise specified, the word "couple" and its associated verb forms include both direct connection and indirect electrical connection by means known in the art; and unless otherwise specified, any description of direct connection also implies an alternative embodiment using a suitable form of indirect electrical connection. DETAILED DESCRIPTION

[0022] Figure 1 An electrical model 100 of a synchronous rectifier transistor is shown in schematic form. The electrical model 100 includes an N-channel MOSFET 110, a body diode 120, a parasitic inductor 130, and a parasitic capacitor 140. The N-channel MOSFET 110 has a first source / drain terminal, a gate, a resistor labeled “I SR ”, and a body terminal connected to the second source / drain terminal. Body diode 120 is a PN junction diode having an anode connected to the second source / drain terminal of N-channel MOSFET 110 and a cathode connected to the first source / drain terminal of N-channel MOSFET 110. Parasitic inductor 130 has a capacitor for receiving a current labeled “V DRAIN ”, a first terminal connected to the first source / drain terminal of the N-channel MOSFET 110 and the cathode of the body diode 120, and having a STRAY ” The voltage drop across inductor 130 is labeled “V LS The parasitic capacitor 140 has a first terminal connected to a first source / drain terminal of the N-channel MOSFET 110 and a cathode of the body diode 120 , and a second terminal connected to a second source / drain terminal of the N-channel MOSFET 110 .

[0023] Figure 2 shows a diagram useful for understanding its operation Figure 1The timing diagram 200 of the signals of the electrical model 100 is shown. In the timing diagram 200, the horizontal axis represents the time in microseconds (μs), and the vertical axis represents the magnitude of certain signals in corresponding units. The timing diagram 200 includes the current I in amperes (amps). SR The waveform 210, the drain voltage V in volts DRAIN The waveform 220, marked as "V GATE The waveform of the gate voltage and the inductor voltage V in volts LS The timing diagram 200 also shows four points in time of interest, including the time period marked as “t 1 ”, “t 2 ”, “t 3 ” and “t 4 ” time.

[0024] In t 1 Before, the synchronous rectifier is turned off. V GATE The N-channel MOSFET 110 is at a low voltage, thereby keeping the N-channel MOSFET 110 non-conducting (off state). No current flows through the N-channel MOSFET 110 and the body diode 120 is reverse biased. In a transformer-based system, as current is conducted through the primary winding, the flux in the transformer induces a high voltage on the secondary winding, i.e., signal V DRAIN However, when the primary side transistor is made non-conductive, V DRAIN decreases until at time t 1 It reaches zero volts.

[0025] At time t 1 Afterwards, the body diode 120 is forward biased, causing V LS drops below zero volts and causes V DRAIN drops below zero volts. When V DRAIN down to the value marked as "V TH_ON ”, the synchronous rectifier controller activates V at a high voltage GATE , so that the N-channel MOSFET 110 is 2 The N-channel MOSFET 110 is turned on at a low on-resistance, and since most of the current flows through the N-channel MOSFET 110, the voltage on the second terminal of the parasitic inductor 130 jumps by an amount equal to the product of the ISR magnitude and the on-resistance. DRAIN Follow V LS Subtract I SR The value of the resistive (IR) drop is determined by the 1 With t 4 Between, the current I SRIt rises initially, then falls as the current flowing to the load reduces the flux in the transformer.

[0026] At time t 3 When V DRAIN Reach the value marked as "V TH_OFF ” is the shutdown threshold. When V DRAIN Reach V TH_OFF When the synchronous rectifier controller deactivates the V to N-channel MOSFET 110, GATE Since the current path from N-channel MOSFET 110 to body diode 120 changes, V DRAIN The voltage on the 3 With t 4 Between DRAIN It rises slightly because the current flowing through the parasitic inductor 130 decreases.

[0027] At time t 4 When t 3 With t 4 The time between 1 and 2 defines the dead time, during which the N-channel MOSFET 110 is not turned on. Figure 2 It can be seen that when the shutdown threshold V TH_OFF When it decreases, it is marked as "t DEAD ” The dead time increases, thus reducing the system efficiency.

[0028] Figure 3 A timing diagram 300 is shown, which shows that when a positive turn-off threshold is used Figure 1 The operation of the synchronous rectifier under light load conditions. In the timing diagram 300, the horizontal axis represents time in μs, and the vertical axis represents the magnitude of certain signals in corresponding units. The timing diagram 300 shows a current I in amperes. SR The waveform 310 shows the drain voltage V in volts. DRAIN The waveform 320 shows the gate voltage V in volts. GATE The timing diagram 300 also shows three points in time of interest, t 1 ,t 2 and t 3 .

[0029] Timing diagram 300 shows the timing of the TH_OFF >0), the current I SRdrops below zero, thereby generating a relatively large reverse current that flows through the parasitic inductor 130 and the N-channel MOSFET 110 and reduces the efficiency of the converter. The primary-side controller causes the primary-side transistor to switch on at t 1 Before and until t 2 The synchronous rectifier controller is turned on at t 1 With t 3 The N-channel MOSFET 110 is activated between t 2 With t 3 A large undesirable current is generated between them.

[0030] Figure 4 A timing diagram 400 is shown, which shows that when a zero turn-off threshold is used Figure 1 The operation of the synchronous rectifier under light load conditions. In the timing diagram 400, the horizontal axis represents time in μs, and the vertical axis represents the magnitude of various signals in corresponding units. The timing diagram 400 shows a current I in amperes. SR Waveform 410 shows the drain voltage V in volts. DRAIN The waveform 420 shows the gate voltage V in volts. GATE The timing diagram 400 shows two points in time of interest, t 1 and t 2 .

[0031] Timing diagram 400 shows the timing of the TH_OFF ≈0), I SR The current transient on the primary side usually disappears. The primary side controller makes the primary side transistor 1 Before and until t 2 The synchronous rectifier controller is turned on at t 1 With t 2 N-channel MOSFET 110 is activated between t and t. When zero volt switching is used, there is essentially no dead time, and at approximately the same time, t 2 When V GATE becomes inactive and the primary side switch becomes inactive. There is no significant reverse current, but V TH_OFF Setting it to zero results in a larger dead time as the load gets heavier and this has lower efficiency at high loads.

[0032] According to the disclosed embodiments, a synchronous rectifier controller provides high efficiency with little to no reverse current transients for both light and heavy loads. As will be described in more detail below, this is accomplished by providing a multi-step turn-off threshold that increases with the size of the load and the length of the switching cycle.

[0033] Figure 5 A power converter 500 according to various embodiments is shown in schematic form. The power converter 500 generally includes an input section 510, a primary switching section 520, a resonant tank 530, a transformer 540, a first synchronous rectifier circuit 550, a second output section 560, a synchronous rectifier controller 570, an output section 580, and a feedback section 590.

[0034] Input section 510 includes an electromagnetic interference (EMI) filter 512, a diode bridge 514, a power factor correction (PFC) stage 516, and an input capacitor 518. EMI filter 512 has a circuit for receiving a voltage labeled “V AC ”, and an output port. The diode bridge 514 has an input port connected to the output port of the EMI filter 512, and an output port. The PFC stage 516 has an input port connected to the output port of the diode bridge 514, and an output port having a first terminal and a second terminal connected to the primary ground. The capacitor 518 has a first terminal connected to the first terminal of the output port of the PFC stage 516, and a second terminal connected to the secondary ground.

[0035] The primary switching portion 520 includes a high-side transistor 522, a low-side transistor 524, and an LLC controller 526. The high-side transistor 522 is an N-channel MOSFET having a drain connected to a first terminal of the output port of the PFC stage 516, a gate, a source, and a body terminal connected to its source, and is shown with a body diode and a capacitor, each coupled between the source and the drain. The low-side transistor 524 is an N-channel MOSFET having a drain connected to the source of the high-side transistor 522, a gate, a source connected to the primary ground, and a body terminal connected to its source, each coupled between the source and the drain. The LLC controller 526 has a first input for receiving a feedback signal, a second input connected to the primary ground, a first output connected to the gate of the high-side transistor 522, and a second output connected to the gate of the low-side transistor 524.

[0036] The resonant tank 530 includes a capacitor 532, an inductor 534, and an inductor 536. The capacitor 532 has a first terminal connected to the source of the high-side transistor 522, and a second terminal. The inductor 534 has a first terminal connected to the second terminal of the capacitor 532, a second terminal. The inductor 536 has a first terminal connected to the second terminal of the inductor 534, a second terminal connected to the primary ground, and may represent the magnetizing inductance at the primary winding of the transformer 540.

[0037] Transformer 540 has a primary winding 542 and a secondary winding 544, the secondary winding having a first section 546 and a second section 548. Primary winding 532 has a first end connected to the second terminal of inductor 534 and to the first terminal of inductor 536, and a second end connected to primary ground. First section 546 has a first end and a second end for providing a voltage labeled “V O ” The second end of the output voltage. The second segment 548 has a first end connected to the second terminal of the first segment 546, and a second end.

[0038] The first synchronous rectifier circuit 550 includes a synchronous rectifier transistor 551, a resistor 552, and a capacitor 553. The synchronous rectifier 551 has a drain connected to the second end of the second segment 548, a gate, and a source connected to the secondary ground, and is shown with a body diode and a capacitor, each coupled between the source and the drain. The resistor 552 has a first terminal for receiving a resistor labeled “R OFFSET1 ” signal, and a second terminal connected to the second end of the second segment 548. The capacitor 553 has a first terminal connected to the first terminal of the resistor 552, and a second terminal connected to the secondary ground.

[0039] The second output portion 560 includes a synchronous rectifier transistor 561, a resistor 562, and a capacitor 563. The synchronous rectifier 561 has a drain connected to the first end of the first segment 546, a gate, and a source connected to the secondary ground, and is shown with a body diode and a capacitor, each coupled between the source and the drain. The resistor 562 has a first terminal connected to the first end of the first segment 546 and to the drain of the synchronous rectifier transistor 561, a resistor 562 for receiving a resistor labeled “R OFFSET2 " and a control terminal of the signal, and a second terminal. Capacitor 563 has a first terminal connected to resistor 562, a first terminal connected to the first end of the first segment 546 and to the drain of the synchronous rectifier transistor 561, and a second terminal connected to the secondary ground.

[0040] The synchronous rectifier controller 570 in the integrated circuit controller has eight terminals, including a terminal marked as "G1" connected to the gate of the synchronous rectifier transistor 551, a terminal marked as "GND" connected to the secondary ground, a terminal marked as "VS1" connected to the secondary ground, a terminal marked as "VD1" connected to the resistor 552 and the first terminal of the capacitor 553, a terminal marked as "VS2" connected to the secondary ground, a terminal marked as "VD2" connected to the first terminal of the resistor 562 and the capacitor 563, a terminal marked as "VDD" connected to the center tap of the secondary winding of the transformer 540 (and optionally connected to an external power supply), and a terminal marked as "G2" connected to the gate of the synchronous rectifier 561.

[0041] Output section 580 includes capacitor 582 and resistor 584. Capacitor 582 is an output capacitor having a first terminal connected to the center tap of the secondary winding and a second terminal connected to the secondary ground. Resistor 584 has a first terminal connected to the center tap of the secondary winding and a second terminal connected to the secondary ground, and represents the resistance of the load.

[0042] Feedback portion 590 includes resistors 591, 592, 593, 594, and 595, capacitor 596, shunt regulator 597, optocoupler 598, and resistor 599. Resistor 591 has a first terminal connected to the center tap of the secondary winding of transformer 540, and a second terminal. Resistor 592 has a first terminal connected to the second terminal of resistor 591, and a second terminal connected to the secondary ground. Resistor 593 has a first terminal connected to the center tap of the secondary winding of transformer 540, and a second terminal. Resistor 594 has a first terminal connected to the center tap of the secondary winding of transformer 540, and a second terminal. Resistor 595 has a first terminal connected to the second terminal of resistor 594, and a second terminal. Capacitor 596 has a first terminal connected to the second terminal of resistor 595, and a second terminal connected to the second terminal of resistor 591. Shunt regulator 597 has a first terminal connected to the second terminal of resistor 591, a second terminal, and a third terminal connected to the secondary ground. Optocoupler 598 has a first input side terminal connected to the second terminal of resistor 593, a second input side terminal connected to the second terminal of resistor 594, a first output side terminal connected to the first input of LLC controller 526, and a second output side terminal connected to the primary ground. Resistor 599 has a first terminal connected to the first input of LLC controller 526, and a second terminal connected to the primary ground.

[0043] In operation, the power converter 500 is an offline inductor-inductor-capacitor (LLC) controller having two synchronous rectifier transistors 551 and 561, the operation of which is controlled by a synchronous rectifier controller 570 according to the techniques discussed herein. The input section 510 receives an offline AC mains voltage V AC and converted into a smooth half-haversine waveform by a diode bridge 514 and an input capacitor 518. The EMI filter 512 filters high frequency components that may interfere with other electronic devices close to the power converter 500. The primary switching section 520 controls the delivery of energy to the primary winding of the transformer 540, and the LLC controller 526 controls the operating frequency at a 50% duty cycle of the current flowing to the primary winding of the transformer 540 based on the output voltage feedback signal received from the optocoupler 598. The resonant tank 530 is an impedance circuit that stores energy when switching current through the primary winding 542 and delivers energy when current is switched at other times, thereby helping to maintain zero voltage switching and high efficiency. The transformer 540 has a center-tapped secondary winding to provide an output voltage V using two output sections. O Synchronous rectifier circuits 550 and 560 deliver power to output portion 580 using respective synchronous rectifier transistors 551 and 561. Feedback portion 590 forms a feedback signal that crosses the isolation barrier using optocoupler 598.

[0044] It should be apparent that although the synchronous rectifier control techniques disclosed herein can be used with Figure 6 , but they can also be used with other switch-mode power supply architectures.

[0045] Figure 6 shows a timing diagram that shows Figure 5 The operation of the synchronous rectifier transistor 551 of the power converter 500. In the timing diagram 600, the horizontal axis represents the time in μs, and the vertical axis represents the magnitude of certain signals in corresponding units. The timing diagram 600 shows the current I in amperes. SR Waveform 610 shows the drain voltage V in volts. DRAIN The timing diagram 600 shows five points in time of interest, t 1 ,t 2 ,t 3 ,t 4 and t 5 .

[0046] SR_COND is the time when the gate voltage G1 becomes high (t 1 ) and drain voltage VDRAIN The value that has exceeded the value marked as "V TH_HGH "The high threshold time (t 5 ) is a signal at a high voltage between the gate voltage and the gate voltage. The synchronous rectifier controller 570 uses a variable turn-off threshold that increases during the expected on-time of the gate voltage. In the embodiment shown in the timing diagram 600, the variable turn-off threshold starts at a first value during the first portion of the expected on-time. The first value is labeled “V TH_OFF1 " and equal to 0 volts, and the first part is from t 1 to 2 The first portion establishes a minimum on-time, which may be, for example, 0 to 50% of the time that SR_COND was active during the previous cycle labeled “SR_COND(n-1)”.

[0047] The variable turn-off threshold is at a second value higher than the first value during the second portion of the expected on-time. The second value is labeled “V TH_OFF2 ” and may be, for example, labeled “V TH_OFF3 The second portion of the expected on-time is after the first portion of the on-time and in this example is from t 2 to 3 The second portion may be, for example, 50% to 70% of SR_COND(n-1).

[0048] The variable turn-off threshold is at a third value, V, higher than the second value, during a third portion of the expected on-time. TH_OFF3 The third portion of the on-time is expected to follow the second portion of the on-time and in this example is from t 3 to 4 The third part may be, for example, 70% to 100% of SR_COND(n–1). 4 With t 5 In between, the synchronous rectifier controller 570 provides a dead time.

[0049] To prevent the N-channel MOSFET transistor from being unexpectedly turned off (ie, false triggering) due to noise, the synchronous rectifier controller 570 adds a debounce time to the first portion. The debounce time is not added to the second and third portions.

[0050] By providing a variable threshold that increases within the cycle, the synchronous rectifier controller 570 achieves both high efficiency and good transient response over all expected load ranges. The synchronous rectifier controller 570 is also robust enough to handle rapid changes in load (and thus natural changes in switching frequency).

[0051] Figure 7 A timing diagram 700 is shown, which shows Figure 5 The operation of the synchronous rectifier transistor 551 under varying load conditions. In the timing diagram 700, the horizontal axis represents time in μs, and the vertical axis represents the magnitude of various signals in corresponding units. The timing diagram 700 shows a current I in amperes. SR Waveform 710 shows the drain voltage V in volts. DRAIN The timing diagram 700 shows five points of interest associated with the first (n-1)th cycle corresponding to the first load condition. 1 ,t 2 ,t 3 ,t 4 and t 5 , and the second (n)th cycle associated with the second load condition is labeled “t 6 ”, “t 7 ”, “t 8 ”, “t 9 ” and “t 10 "A set of five time points. Waveforms 710, 720, and 730 are substantially the same as during the first cycle. Figure 6 The corresponding waveforms shown are the same, where SR_COND indicates the time when G1 goes high and V DRAIN The ones that have exceeded the previous (n–1) cycle are marked as V TH_HGH The time between the high threshold times.

[0052] However, at t 5 After that, the load is reduced and the natural switching frequency f S Increase. Therefore I SR Waveform 710 has a smaller peak and shorter period. However, SR_COND reflects the time when G1 goes high and V DRAIN The ones that have exceeded the previous (n–1) cycle are marked as V TH_HGH The time of the high threshold. Figure 7 As shown, the primary-side controller makes the primary-side transistor 6 Shortly before, the synchronous rectifier controller 570 is not conducting at time t 6 The N-channel MOSFET is activated when the dead time is t 8 With t 9 , and the proportion of this cycle remains approximately the same as that of the (n–1)th cycle. However, unlike the nth cycle, V DRAIN The waveform reaches this threshold during the second step, when V TH Yes V TH_OFFTherefore when the load decreases, the variable threshold ensures that the synchronous rectifier transistor turns off earlier in the cycle to maintain high efficiency without large transient currents.

[0053] Circuitry that can be used to implement the various features will now be described.

[0054] Figure 8 A block diagram is shown that can be used to implement Figure 5 The synchronous rectifier controller 800 of the synchronous rectifier controller 570 of the present invention includes a drain input terminal 801 labeled “VD1 / VD2”, a gate output terminal 802 labeled “G1 / G2”, comparators 810, 820, 830 and 840, a timing circuit 850, a latch 860, and a gate driver 870. The comparator 810 has a gate input terminal 801 for receiving a gate output terminal 802 labeled “VD1 / VD2”, and a gate output terminal 802 for receiving a gate output terminal 802 labeled “G1 / G2”. TH_ON The comparator 820 has a positive input connected to the drain input terminal 801, a negative input terminal connected to the drain input terminal 801, and an output terminal for providing a signal labeled "SR ON". The comparator 820 has a positive input connected to the drain input terminal 801, a negative input terminal connected to the drain input terminal 801, and an output terminal for providing a signal labeled "SR ON". TH_OFF1 The comparator 830 has a positive input connected to the drain input terminal 801, a negative input terminal for receiving V TH_OFF2 The comparator 840 has a positive input connected to the drain input terminal 801, a negative input terminal for receiving V TH_OFF3 The negative input terminal and the output terminal.

[0055] Timing circuit 850 includes AND gates 851, 852, and 853, a debounce time circuit 854, an OR gate 855, and a timing generator 856. AND gate 851 has a first input connected to the output of comparator 820, a second input for receiving a signal labeled "T1STEP", and an output. AND gate 852 has a first input connected to the output of comparator 830, a second input for receiving a signal labeled "T2STEP", and an output. AND gate 853 has a first input connected to the output of comparator 840, a second input for receiving a signal labeled "T3STEP", and an output. Debounce time circuit 854 has an input connected to the output of AND gate 851, and an output. OR gate 855 has a first input connected to the output of debounce time circuit 854, a second input connected to the output of AND gate 852, a third input connected to the output of AND gate 853, and an output for providing a signal labeled "SR OFF". Timing generator 856 has a first input connected to terminal 801, a second input, a first output connected to the second input terminal of AND gate 851 for providing a T1STEP signal, a second output connected to the second input terminal of AND gate 852 for providing a T2STEP signal, and a third output connected to the second input terminal of AND gate 853 for providing a T3STEP signal.

[0056] Latch 860 has a set input labeled “S” connected to the output of comparator 810, a reset input labeled “R” connected to the output of OR gate 855, and an output labeled “Q” connected to a second input of timing generator 856 for providing a signal labeled “VG1 / VG2”. Gate driver 870 has an input connected to the output of latch 860, and an output connected to gate terminal 802. Synchronous rectifier controller 570 includes two circuits having the same construction, one of which is a circuit for synchronous rectifier transistor 551 connected to terminals VD1 and G1, and the other is a circuit for synchronous rectifier transistor 561 connected to terminals VD2 and G2. The circuits in synchronous rectifier controller 800 are also connected to VDD and GND terminals, but these connections are not in Figure 8 Clearly shown in.

[0057] In operation, comparator 810 determines the activation time of the synchronous rectifier transistor as the time when the drain voltage drops below V TH_ON When the drain voltage drops below V TH_ON When , comparator 810 activates the SR turn-on signal, which sets latch 860 and causes gate driver 870 to drive the signal G1 or G2 on gate terminal 802 to a voltage that turns on the synchronous rectifier transistor.

[0058] The synchronous rectifier controller 800 turns off the synchronous rectifier transistor as follows. Each of the comparators 820, 830, and 840 is at V DRAIN When V rises above the corresponding threshold, it activates its corresponding output. The timing generator 856 determines the time when the corresponding threshold is used. During the first part of the cycle (e.g., 0-50% of the previous cycle), the timing generator 856 activates T1STEP so that if V DRAIN rises above V TH_OFF1 , then OR gate 855 activates the SR shutdown signal, thereby resetting latch 860 and causing driver 870 to deactivate the gate signal to make the synchronous rectifier transistor non-conductive. During the second portion of the cycle (e.g., 50-70% of the previous cycle), timing generator 856 activates T2STEP so that if V DRAIN rises above V TH_OFF2 , then OR gate 855 activates the SR shutdown signal, thereby resetting latch 860 and causing driver 870 to deactivate the gate signal to make the synchronous rectifier transistor non-conductive. During the third portion of the cycle (e.g., 70-100% of the previous cycle), timing generator 856 activates T3STEP so that if V DRAIN rises above V TH_OFF3 , then OR gate 855 activates the SR shutdown signal, thereby resetting latch 860 and causing driver 870 to deactivate the gate signal to make the synchronous rectifier transistor non-conductive.

[0059] Fig. 9 The block diagram shows the Figure 8 The timing generator 900 is an embodiment of the timing generator 856 of the present invention. The timing generator 900 includes a terminal 901 for receiving a VG1 signal, a terminal 902 for receiving a VD1 signal, a terminal 903 for providing a T1STEP signal, a terminal 904 for providing a T2STEP signal, a terminal 905 for providing a T3STEP signal, a comparator 910, a latch 920, a sample-and-hold circuit 930 labeled “S / H”, and dividers 940, 950, and 960. The comparator 910 has a positive input connected to the terminal 902, a positive input connected to the terminal 903, a positive input connected to the terminal 904, a positive input connected to the terminal 905, and a negative input connected to the terminal 906. TH_HGHThe latch 920 has an S input connected to the terminal 901, an R input connected to the output of the comparator 910, and an output for providing the SR_COND signal. The sample and hold circuit 930 has an input connected to the Q output of the latch 920, and an output for providing the SR_COND(n–1) signal. The divider 940 has an input connected to the output of the sample and hold circuit 930, a first output connected to the terminal 903, and a second output connected to the terminal 903. The divider 950 has a first input connected to the output of the sample and hold circuit 930, a second input connected to the second output of the divider 940, a first output connected to the terminal 904, and a second output. The divider 960 has a first input connected to the output of the sample and hold circuit 930, a second input connected to the second output of the divider 950, and an output connected to the terminal 905.

[0060] In operation, the SR_COND signal is at the time when VG1 goes high and VD1 will have exceeded “V TH_HGH ”. The activation of signal VG1 sets latch 920 and establishes the beginning of SR_COND, and the point at which VD1 exceeds VTH_HGH resets latch 920 and establishes the end of SR_COND. Sample-and-hold circuit 930 stores a value indicating the length of time SR_COND is active, and provides a SR_COND(n–1) signal to reflect the SR_COND waveform of the previous cycle. Dividers 940, 950, and 960 divide the time period of SR_COND(n–1) into three portions, which in the example discussed above correspond to 0-50% of SR_COND(n–1), 50-70% of SR_COND(n–1), and 70-100% of SR_COND(n–1).

[0061] The implementation of the sample-and-hold circuit 930 and the dividers 940, 950, and 960 may take a variety of forms. For example, the sample-and-hold circuit 930 may integrate a fixed current source to store charge in a capacitor, where the voltage of the capacitor is proportional to the duration of SR_COND(n–1). Each of the dividers 940, 950, and 960 may then use the sampled voltage to form a corresponding TSTEP waveform with appropriate start timing and duration. For example, the divider 940 may synchronize the start of the T1STEP waveform with the activation of VG1, and bisect the voltage at the output of the sample-and-hold circuit 930 and provide a T1STEP with a duration of half SR_COND(n–1). The divider 950 may provide a T2STEP with a duration of 20% of SR_COND(n–1) starting from the deactivation of T1STEP indicated by the second output of the divider 940. Likewise, divider 960 may provide T3STEP, which lasts 30% of SR_COND(n-1) from the deactivation of T2STEP indicated by the second output of divider 950. It should be apparent that this example is merely an implementation of Figure 8 The timing generator 856 functions in one particular manner.

[0062] Fig.10 The block diagram shows the Figure 8 Another embodiment of a timing generator 1000 of another embodiment of the timing generator 856 of the present invention is provided. The timing generator 1000 includes a terminal 1001 for receiving a VG1 signal, a terminal 1002 for providing a T1STEP signal, a terminal 1003 for providing a T2STEP signal, a terminal 1004 for providing a T3STEP signal, a sample-and-hold circuit 1010, a divider 1020, a divider 1030, and a divider 1040. In this embodiment, the VG1 signal serves as a proxy for the SR_COND signal, and the sample-and-hold circuit 1010 has an input connected to the terminal 1001, and an output for providing the SR_COND(n–1) signal. The divider 1020 has an input connected to the output of the sample-and-hold circuit 1010, a first output connected to the terminal 1002, and a second output. Divider 1030 has a first input connected to the output of sample and hold circuit 1010, a second input connected to the second output of divider 1020, a first output connected to terminal 1003, and a second output. Divider 1040 has a first input connected to the output of sample and hold circuit 1010, a second input connected to the second output of divider 1030, and an output connected to terminal 1004.

[0063] Timing generator 1000 is similar to timing generator 900, except that it uses only the VG1 signal from the time of G1 high to G1 low to form SR_COND. Since the dead time remains substantially constant between consecutive cycles and only occupies a small portion of the cycle time, using only the gate voltage to form SR_COND approximates operation using both gate and drain voltages. Timing generator 1000 thus achieves similar results as timing generator 900, but with a simplified circuit design.

[0064] Fig.11 A timing diagram 1100 is shown, which shows Figure 8 The timing diagram 1100 is similar to the timing diagram 600, except that in this embodiment, V TH_OFF2 Not V TH_OFF1 With V TH_OFF3 fixed value between V TH_OFF1 With V TH_OFF3 Changes linearly between.

[0065] Fig.12 A partial block diagram and a partial schematic diagram are provided to illustrate a method for implementing Fig.11 The timing diagram of the operation of the timing circuit 1200. The timing circuit 1200 includes a circuit for receiving V TH_OFF1 Terminal 1201, used to receive V TH_OFF3 Terminal 1202 for providing signal T2STEP, terminal 1203 for providing V TH_OFF2 1201, a subtractor 1210, a divider 1220, a current source 1230, a capacitor 1240, an inverter 1250, and a switch 1260. The subtractor has a first input connected to terminal 1201, a second input connected to terminal 1202, and a V TH_OFF3 With V TH_OFF1 The divider 1220 has a first input connected to the output of the subtractor 1210, a second input for receiving the T2STEP signal, and a second input for providing a signal equal to (V TH_OFF3 -V TH_OFF1) / T2STEP. Current source 1230 has a first terminal for receiving a voltage labeled "V1", a second terminal connected to terminal 1204, and a control terminal connected to the output terminal of divider 1220. Capacitor 1240 has a first terminal connected to the second terminal of current source 1230, and a second terminal connected to ground. Inverter 1250 has a first terminal connected to terminal 1203, and an output. Switch 1260 has a first terminal connected to the first terminal of capacitor 1240, a second terminal connected to ground, and a control terminal connected to the output terminal of inverter 1250.

[0066] In operation, when T2STEP is low, capacitor 1240 is grounded, i.e., it is at V TH_OFF1 = 0 volts when V TH_OFF1 When T2STEP is high, capacitor 1240 integrates the current provided by current source 1230. Subtractor 1210 forms V received at terminal 1202. TH_OFF3 and V received at terminal 1201 TH_OFF1 The divider 1220 forms a voltage equal to (V TH_OFF3 -V TH_OFF1 ) / T2STEP. This voltage controls the current of variable current source 1230, which operates as an integrator and charges capacitor 1240. Therefore, the voltage on the first terminal of capacitor 1240 (i.e., V TH_OFF2 ) from V within the time period defined by T2STEP TH_OFF1 Rise linearly to V TH_OFF2 .

[0067] In V TH_OFF3 In another embodiment not equal to 0 volts, the second terminal of capacitor 1240 will instead receive V TH_OFF1 When V TH_OFF3 When φ is equal to 0V, the subtractor 1210 can be omitted.

[0068] Thus, various embodiments of a switch mode power converter have been described. In one form, the power converter includes a synchronous rectifier controller that controls a synchronous rectifier transistor by increasing a turn-off threshold, wherein the turn-off threshold increases during an expected on-time of a gate signal. In one example, the threshold may have a first value during a first portion of the expected on-time, a second value higher than the first value during a second portion of the expected on-time after the first portion of the expected on-time, and a third value higher than the second value during a third portion of the expected on-time after the second portion of the expected on-time. In another example, the variable turn-off threshold has a first value during the first portion of the expected on-time, a third value higher than the first value during the third portion of the expected on-time, and a second value that varies between the first value and the third value during the second portion of the expected on-time after the first portion and before the third portion.

[0069] The subject matter disclosed above should be considered as exemplary rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true scope of the claims. For example, the synchronous rectifier control method can be used for a variety of switch mode power supplies, including LLC, voltage mode flyback, synchronous rectifier (SR) flyback, etc. In addition, although the examples shown above have used N-channel MOSFET transistors as synchronous rectification components, other transistor types can be used in other embodiments. In addition, other ways of increasing the turn-off threshold can be used, including more or fewer discrete steps, variable steps, etc.

[0070] In one form, a power converter includes a transformer, a first primary side transistor, a primary side controller, a first synchronous rectifier (SR) transistor, and a synchronous rectifier controller. The transformer has a primary winding and a secondary winding. The first primary side transistor is coupled to the primary winding and has a gate for receiving a first primary gate signal, wherein the first primary side transistor causes the primary winding to selectively conduct current in response to the first primary gate signal. The primary side controller has an input for receiving a voltage feedback signal and an output for providing the first primary gate signal. The first synchronous rectifier (SR) transistor has a drain coupled to the secondary winding, a gate for receiving a first SR gate signal, and a source coupled to a first output terminal of the power converter. The synchronous rectifier controller is coupled to the gate and the drain of the first SR transistor and is used to activate the first SR gate signal when the voltage on the drain drops below a turn-on threshold and deactivate the first SR gate signal when the voltage on the drain rises above a variable turn-off threshold, wherein the variable turn-off threshold increases within the expected turn-on time of the first SR gate signal.

[0071] According to one aspect, the variable turn-off threshold has a first value during a first portion of the expected on-time, a second value higher than the first value during a second portion of the expected on-time after the first portion of the expected on-time, and a third value higher than the second value during a third portion of the expected on-time after the second portion of the expected on-time. In this case, the first value may be approximately zero volts and the first portion of the expected on-time is approximately zero to fifty percent of the expected on-time, the second value may be approximately sixty percent of a final value and the second portion of the expected on-time is approximately fifty to seventy percent of the expected on-time, and the third value may be approximately the final value and the third portion of the expected on-time is approximately seventy to one hundred percent of the expected on-time. The SR controller may also have a first comparator having a negative input coupled to the drain of the first SR transistor, a positive input, and an output; a latch having a set input coupled to the output of the first comparator and an output; a gate driver having an input coupled to the output of the latch and an output for providing the first SR gate signal; a second comparator having a positive input coupled to the drain of the first SR transistor, a negative input for receiving the first value, and an output; a third comparator having a positive input coupled to the drain of the first SR transistor, a set input for receiving the first value, and an output; a fourth comparator having a positive input coupled to the drain of the first SR transistor, a negative input for receiving the third value, and an output; and a logic circuit coupled to the outputs of the second, third and fourth comparators and having an output, wherein the logic circuit activates its output if any one of the outputs of the second, third and fourth comparators is active during the respective first, second and third portions of the expected on-time, wherein the latch also has a reset input coupled to the output of the logic circuit.

[0072] The logic circuit may include a first AND gate having a first input, a second input, and an output coupled to the output of the second comparator; a second AND gate having a first input, a second input, and an output coupled to the output of the third comparator; a third AND gate having a first input, a second input, and an output coupled to the output of the fourth comparator; and an OR gate having a first input, a second input, and a third input coupled to the outputs of the first, second, and third AND gates, respectively, and an output coupled to the reset input of the latch. In this case, the logic circuit may further include a debounce timer coupled between the output of the first AND gate and the first input of the OR gate. The logic circuit may also include a timing generator having a first input coupled to the drain of the first SR transistor, a second input coupled to the output of the latch, and a first output, a second output, and a third output respectively coupled to the second input of the first AND gate, the second AND gate, and the third AND gate.

[0073] According to another aspect, the power converter may further include a second SR transistor having a drain coupled to the secondary winding, a gate receiving a second SR gate signal, and a source coupled to the first output terminal of the power converter, wherein the SR controller is coupled to the gate and the drain of the second SR transistor for activating the second SR gate signal when a voltage on the drain of the second SR transistor drops below the turn-on threshold, and deactivating the second SR gate signal when a voltage on the drain of the second SR transistor rises above the variable turn-off threshold, wherein the variable turn-off threshold increases within the expected turn-on time of the second SR gate signal. In this case, the secondary winding may include a first end, a second end, and a center tap, wherein the first end is coupled to the drain of the first SR transistor, the second end is coupled to the drain of the second SR transistor, and the center tap forms the second output terminal of the power converter.

[0074] In another form, a controller for use with a synchronous rectifier (SR) transistor having a drain, a gate, and a source includes a first comparator, a second comparator, a third comparator, and a fourth comparator, a logic circuit, a latch, and a gate driver. The first comparator has a negative input adapted to be coupled to the drain of the SR transistor, a positive input, and an output. The second comparator has a positive input adapted to be coupled to the drain of the SR transistor, a negative input for receiving a first value, and an output. The third comparator has a positive input adapted to be coupled to the drain of the SR transistor, a negative input for receiving a second value, and an output. The fourth comparator has a positive input adapted to be coupled to the drain of the SR transistor, a negative input for receiving a third value, and an output. The logic circuit is coupled to the outputs of the second comparator, the third comparator, and the fourth comparator and has an output, wherein if the output of any of the second comparator, the third comparator, and the fourth comparator is active during the respective first, second, and third portions of the expected on-time, the logic circuit activates the output thereof. A latch has a set input coupled to the output of the first comparator, a reset input coupled to the output of the logic circuit, and an output. A gate driver has an input coupled to the output of the latch, and an output adapted to be coupled to a gate of an SR transistor.

[0075] According to one aspect, a timing generator has an input coupled to the output of the latch and determines the first, second, and third portions of the expected on-time based on a time from when the output of the latch is active to when the output of the latch is inactive.

[0076] According to another aspect, the timing generator also includes a ramp circuit having an input for receiving the first value, an input for receiving the second value, a third input for receiving the second timing signal, and an output for providing the second value, wherein the ramp circuit changes the second value between the first value and the third value when the second timing signal is active.

[0077] According to yet another aspect, the first portion of the expected on-time is approximately zero to fifty percent of the expected on-time, the second portion of the expected on-time is approximately fifty to seventy percent of the expected on-time, and the third portion of the expected on-time is approximately seventy to one hundred percent of the expected on-time.

[0078] In yet another form, a method for power conversion using a synchronous rectifier (SR) transistor includes sensing a drain voltage at a drain of the SR transistor; activating a gate signal to turn on the SR transistor in response to the drain voltage dropping below a turn-on threshold; and deactivating the gate signal when the drain voltage rises above a variable turn-off threshold, wherein the variable turn-off threshold increases within an expected turn-on time of the gate signal.

[0079] According to one aspect, the method further includes coupling an SR transistor to a secondary winding of a transformer and driving a primary winding of the transformer based on a difference between an output voltage from the secondary winding and a desired voltage. According to this other aspect, driving the primary winding of the transformer may include driving the primary winding through a resonant tank.

[0080] According to another aspect, the deactivation includes generating the variable turn-off threshold at a first value during a first portion of the expected on-time, generating the variable turn-off threshold at a second value during a second portion of the expected on-time after the first portion of the expected on-time, and generating the variable turn-off threshold at a third value higher than the second value during a third portion of the expected on-time after the second portion of the expected on-time.

[0081] According to another aspect, the deactivation also includes generating the variable turn-off threshold at approximately zero volts during approximately zero to fifty percent of the expected on-time, generating the variable turn-off threshold at approximately sixty percent of the final value during approximately fifty to seventy percent of the expected on-time, and generating the variable turn-off threshold at approximately the final value during approximately seventy to one hundred percent of the expected on-time.

[0082] According to another aspect, the deactivation includes generating the variable turn-off threshold at a first value during a first portion of the expected on-time, generating the variable turn-off threshold at a third value higher than the first value during a third portion of the expected on-time, and generating the variable turn-off threshold at a second value varying between the first value and the third value during a second portion of the expected on-time after the first portion and before the third portion.

[0083] Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. A power converter, comprising: a transformer having a primary winding and a secondary winding; a first primary-side transistor coupled to the primary winding and having a gate for receiving a first primary gate signal, wherein the first primary-side transistor causes the primary winding to selectively conduct current in response to the first primary gate signal; a primary side controller having an input for receiving a voltage feedback signal and an output for providing the first primary gate signal; a first synchronous rectifier (SR) transistor having a drain coupled to the secondary winding, a gate for receiving a first SR gate signal, and a source coupled to a first output terminal of the power converter; and a synchronous rectifier controller coupled to the gate and the drain of the first SR transistor for activating the first SR gate signal when the voltage on the drain drops below a turn-on threshold and deactivating the first SR gate signal when the voltage on the drain rises above a variable turn-off threshold, wherein the variable turn-off threshold increases within an expected turn-on time of the first SR gate signal, wherein the expected turn-on time begins with activation of the first SR gate signal and continues for a period of time based on the turn-on time of the first SR gate signal in a previous cycle.

2. The power converter according to claim 1, wherein the variable turn-off threshold: has a first value during a first portion of the expected on-time; has a second value greater than the first value during a second portion of the expected on-time after the first portion of the expected on-time; and has a third value higher than the second value during a third portion of the expected on-time after the second portion of the expected on-time.

3. The power converter according to claim 2, wherein the SR controller comprises: a first comparator having a negative input coupled to the drain of the first SR transistor, a positive input for receiving the conduction threshold, and an output; a latch having a set input coupled to the output of the first comparator, and an output; and A gate driver has an input coupled to the output of the latch and an output for providing the first SR gate signal.

4. The power converter according to claim 3, wherein the SR controller further comprises: a second comparator having a positive input coupled to the drain of the first SR transistor, a negative input for receiving the first value, and an output; a third comparator having a positive input coupled to the drain of the first SR transistor, a negative input for receiving the second value, and an output; a fourth comparator having a positive input coupled to the drain of the first SR transistor, a negative input for receiving the third value, and an output; and a logic circuit coupled to the outputs of the second, third and fourth comparators and having an output, wherein the logic circuit activates the output if any of the outputs of the second, third and fourth comparators is active during the respective first, second and third portions of the expected on-time, The latch also has a reset input coupled to the output of the logic circuit.

5. The power converter of claim 1 , wherein the variable turn-off threshold: has a first value during a first portion of the expected on-time; has a third value greater than the first value during a third portion of the expected on-time; and A second value that varies between the first value and the third value is present during a second portion of the expected on-time that is subsequent to the first portion and prior to the third portion.

6. A controller for use with a synchronous rectifier (SR) transistor having a drain, a gate and a source, comprising: a first comparator having a negative input adapted to be coupled to the drain of the SR transistor, a positive input for receiving a conduction threshold, and an output; a second comparator having a positive input adapted to be coupled to the drain of the SR transistor, a negative input for receiving a first value of a variable turn-off threshold, and an output; a third comparator having a positive input adapted to be coupled to the drain of the SR transistor, a negative input for receiving a second value of the variable turn-off threshold, and an output; a fourth comparator having a positive input adapted to be coupled to the drain of the SR transistor, a negative input for receiving a third value of the variable turn-off threshold, and an output; and a logic circuit coupled to the outputs of the second comparator, the third comparator, and the fourth comparator and having an output, wherein the logic circuit activates the output thereof if the output of any one of the second comparator, the third comparator, and the fourth comparator is active during a respective first portion, a second portion, and a third portion of an expected on-time, wherein during the first portion, the second portion, and the third portion of the expected on-time, the variable off-threshold has the first value, the second value, and the third value of the variable off-threshold, respectively, wherein the second value of the variable off-threshold is higher than the first value of the variable off-threshold, and the third value of the variable off-threshold is higher than the second value of the variable off-threshold; a latch having a set input coupled to the output of the first comparator, a reset input coupled to the output of the logic circuit, and an output; and A gate driver has an input coupled to the output of the latch and an output adapted to be coupled to the gate of the SR transistor.

7. The controller according to claim 6, further comprising: A timing generator is coupled to the logic circuit and has an output for providing a first timing signal, a second timing signal, and a third timing signal corresponding to the first portion, the second portion, and the third portion of the expected on-time, respectively.

8. The controller according to claim 7, wherein: The timing generator also has a first input coupled to the drain of the SR transistor and a second input coupled to the output of the latch, and determines the first portion, the second portion, and the third portion of the expected on-time based on a time between when the output of the latch is active and when a voltage on the drain of the SR transistor is above a high threshold.

9. A method for power conversion using a synchronous rectifier (SR) transistor, comprising: sensing a drain voltage on a drain of the SR transistor; activating a gate signal to turn on the SR transistor in response to the drain voltage falling below a turn-on threshold; as well as The gate signal is deactivated when the drain voltage rises above a variable turn-off threshold, wherein the variable turn-off threshold increases within an expected on-time of the gate signal, wherein the expected on-time begins at activation of the gate signal and continues for a period of time based on the on-time of a previous cycle.

10. The method of claim 9, wherein the deactivation comprises: generating the variable turn-off threshold at a first value during a first portion of the expected on-time; generating the variable turn-off threshold at a second value during a second portion of the expected on-time after the first portion of the expected on-time; as well as The variable turn-off threshold is generated at a third value higher than the second value during a third portion of the expected on-time after the second portion of the expected on-time.

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