Burst transimpedance amplifier circuit for XGSPON

Abstract

The present technology discloses a burst transimpedance amplifier circuit applied to XGSPON, which includes a burst buffer circuit. The burst buffer circuit includes a first emitter follower, a second emitter follower, an RC filter network, and a base current cancellation circuit. The first emitter follower includes a constant current source I1 and a triode Q1. The second emitter follower includes a constant current source I2 and a triode Q2. The RC filter network includes a resistor R1, a resistor R2, a controlled switch TG1, and a capacitor C1. The resistor R1 is connected to the resistor R2 and the controlled switch TG1 at the same time. The resistor R2 and the controlled switch TG1 are connected to one end of the capacitor C1, the base of the triode Q2, and the base current cancellation circuit at the same time. With the DC operating point establishment network controlled by the reset signal and the base current cancellation circuit of the emitter follower, the present technology can ensure the rapid establishment of the link operating point and the sensitivity index when the XGPSON system signal bursts.

Description

Technical Field

[0001] The present technology belongs to the field of microelectronics technology, and specifically relates to a burst transimpedance amplifier circuit applied to XGSPON. Background Art

[0002] With the rapid development of the broadband access market worldwide, domestic 100M broadband has gradually become the standard. The existing PON (passive optical network) technical standards are facing new upgrade requirements in terms of bandwidth requirements, business support capabilities, and performance improvement of access node equipment and supporting equipment. PON adopts TDM broadcast mode for downstream and time division multiple access mode for upstream. This working mode determines that the transceiver circuits in the downstream direction of PON (including the transmitter at the OLT end and the receiver at the ONU end) work in continuous mode; while the transceiver circuits in the upstream direction (including the transmitter at the ONU end and the receiver at the OLT end) work in burst mode. Compared with the continuous mode, the burst optical transceiver chip at the XGSPON OLT end, especially the transimpedance amplifier (TIA), has a higher technical threshold, a shorter protection time between burst signal data packets, and a shorter preamble sequence used for level recovery and clock recovery, which makes it more demanding on the performance requirements of the XGSPON burst transceiver chip. Summary of the invention

[0003] The technical problem to be solved by the present technology is to provide a burst transimpedance amplifier circuit applied to XGSPON in view of the deficiencies of the above-mentioned prior art. The burst transimpedance amplifier circuit applied to XGSPON establishes a network and a base current compensation circuit of the emitter follower by means of a DC operating point controlled by a reset signal. It can ensure the rapid establishment of the link operating point and the sensitivity index when the signal of the XGPSON system bursts, which will significantly improve the security of the chip and the signal transmission quality.

[0004] In order to achieve the above technical objectives, the technical solution adopted by this technology is:

[0005] A burst transimpedance amplifier circuit applied to XGSPON includes a burst buffer circuit, wherein the burst buffer circuit includes a first emitter follower, a second emitter follower, an RC filter network and a base current compensation circuit;

[0006] The first emitter follower comprises a constant current source I1 and a transistor Q1;

[0007] The second emitter follower comprises a constant current source I2 and a transistor Q2;

[0008] The RC filter network includes a resistor R1, a resistor R2, a controlled switch TG1 and a capacitor C1;

[0009] The constant current source I1 is connected to the emitter of the transistor Q1, the collector of the transistor Q1 is connected to the ground wire, one end of the resistor R1 is connected to the resistor R2 and the controlled switch TG1 at the same time, the resistor R2 and the controlled switch TG1 are connected to one end of the capacitor C1, the base of the transistor Q2 and the base current offset circuit at the same time, the other end of the capacitor C1 is connected to the ground wire, the constant current source I2 is connected to the emitter of the transistor Q2, and the collector of the transistor Q2 is connected to the ground wire;

[0010] The other end of the resistor R1 is interconnected with the base of the transistor Q1, and the base of the transistor Q1 serves as the input end of the burst buffer circuit, the emitter of the transistor Q1 serves as the first output end of the burst buffer circuit, the emitter of the transistor Q2 serves as the second output end of the burst buffer circuit, and one end of the controlled switch TG1 is used to connect a reset signal.

[0011] As a further improved solution of the present technology, the base current compensation circuit includes a constant current source I3, a constant current source I DOC , resistor R3, resistor R4, transistor Q3, transistor Q4 and transistor Q5; the collector of the transistor Q4 is connected to the base of the transistor Q2, the emitter of the transistor Q4 is connected to the ground wire through the resistor R3, the base of the transistor Q4 is simultaneously connected to the base of the transistor Q5 and the base of the transistor Q3, the emitter of the transistor Q5 is connected to the ground wire through the resistor R4, the collector of the transistor Q5 is connected to the base of the transistor Q3, the constant current source I3 is simultaneously connected to the emitter of the transistor Q3 and the constant current source I DOC One end of the constant current source I DOC The other end of is connected to the ground wire, and the collector of the transistor Q3 is connected to the ground wire.

[0012] As a further improvement of the present technology, the resistance value of the resistor R2 is greater than the resistance value of the resistor R1.

[0013] As a further improvement of the present technology, the device parameters of the transistor Q1, the transistor Q2 and the transistor Q3 are consistent, and all are PNP transistors.

[0014] As a further improvement of the present technology, the transistor Q4 and the transistor Q5 have the same device parameters and are both NPN transistors.

[0015] As a further improvement of the present technology, the resistance values ​​of the resistor R3 and the resistor R4 are consistent.

[0016] As a further improvement of the present technology, the constant current source I3 is subtracted from the constant current source I DOC The current of the constant current source I1, the current of the constant current source I2 are equal.

[0017] The beneficial effects of this technology are: the burst transimpedance amplifier applied to XGSPON can quickly establish the link DC operating point in the burst mode; at the same time, the base current compensation circuit of the emitter follower helps to improve the sensitivity after the burst reset ends. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the circuit block diagram of the burst transimpedance amplifier used in XGSPON.

[0019] Figure 2 Schematic diagram of the burst buffer circuit in the burst transimpedance amplifier circuit used in XGSPON.

[0020] Figure 3 Schematic diagram of the signal of the burst mode of the burst transimpedance amplifier circuit applied to XGSPON.

[0021] Figure 4 This is the working state diagram of the burst mode of the burst transimpedance amplifier circuit applied to XGSPON.

[0022] Figure 5 This is the eye diagram of the burst mode reset signal of the burst transimpedance amplifier circuit applied to XGSPON after the end of the burst mode reset signal. DETAILED DESCRIPTION

[0023] The following is based on the attached Figure 1-5 The specific implementation methods of this technology are further described as follows:

[0024] This embodiment provides a burst transimpedance amplifier circuit applied to XGSPON, and the block diagram is as follows: Figure 1 As shown in the figure, the main link of the transimpedance amplifier consists of a core amplifier Amp, a burst buffer, a single-ended to differential amplifier (S2D), an output buffer (buffer), an automatic gain control (AGC), and a differential mode offset cancellation (DOC). The current signal is input from the IN end, converted into a single-ended voltage signal by the core transimpedance amplifier (i.e., the core amplifier Amp), and transmitted to the burst buffer. After being processed, one end of the output is a signal after the DC voltage is boosted, and the other end is the average value of the signal voltage and serves as the input common mode level of the single-ended to differential module. The S2D module completes the work of converting the single-ended signal voltage into a differential voltage, and the output buffer transmits the differential signal to the next-level chip and ensures impedance matching during the transmission process. Figure 1 The replica circuit (Dummy) of the core amplifier in the circuit is used to generate the voltage reference point required by the automatic gain control (AGC). The output of the differential offset cancellation (DOC) is used to connect to the output buffer stage.

[0025] The burst buffer circuit is as follows Figure 2As shown, it includes a first emitter follower, a second emitter follower, an RC filter network and a base current compensation circuit. The first emitter follower includes a constant current source I1 and a transistor Q1. The second emitter follower includes a constant current source I2 and a transistor Q2. The RC filter network includes a resistor R1, a resistor R2, a controlled switch TG1 and a capacitor C1. The constant current source I1 is connected to the emitter of the transistor Q1, the collector of the transistor Q1 is connected to the ground wire, one end of the resistor R1 is connected to the resistor R2 and the controlled switch TG1 at the same time, the resistor R2 and the controlled switch TG1 are simultaneously connected to one end of the capacitor C1, the base of the transistor Q2 and the base current compensation circuit, the other end of the capacitor C1 is connected to the ground wire, the constant current source I2 is connected to the emitter of the transistor Q2, and the collector of the transistor Q2 is connected to the ground wire; the other end of the resistor R1 is connected to the base of the transistor Q1, and the base of the transistor Q1 serves as the input end of the burst buffer circuit, the emitter of the transistor Q1 serves as the first output end of the burst buffer circuit, the emitter of the transistor Q2 serves as the second output end of the burst buffer circuit, and one end of the controlled switch TG1 is used to connect the reset signal.

[0026] The base current compensation circuit includes constant current source I3, constant current source I DOC , resistor R3, resistor R4, transistor Q3, transistor Q4 and transistor Q5; the collector of the transistor Q4 is connected to the base of the transistor Q2, the emitter of the transistor Q4 is connected to the ground wire through the resistor R3, the base of the transistor Q4 is simultaneously connected to the base of the transistor Q5 and the base of the transistor Q3, the emitter of the transistor Q5 is connected to the ground wire through the resistor R4, the collector of the transistor Q5 is connected to the base of the transistor Q3, the constant current source I3 is simultaneously connected to the emitter of the transistor Q3 and the constant current source I DOC One end of the constant current source I DOC The other end of is connected to the ground wire, and the collector of the transistor Q3 is connected to the ground wire.

[0027] The burst buffer circuit of this embodiment uses transistors Q1 and Q2 as followers to increase the bandwidth of the link at low power consumption. The signal voltage is divided into two paths at the base of Q1. One path passes through the first emitter follower composed of Q1 and the constant current source I1 to increase the DC voltage by one V. BE1 , get Vout; the other path passes through an RC filter network to extract the average value of the signal, and then passes through the second emitter follower composed of transistor Q2 and constant current source I2 to increase the DC voltage by V BE2, and the voltage Vcm is obtained. The RC filter network composed of resistor R1, resistor R2, controlled switch TG1 and capacitor C1 realizes the rapid establishment of the burst mode transimpedance amplifier link under the control of the external reset signal RESET, where the resistance of R2 is greater than R1. Devices Q3, Q4, Q5, R3, R4 and I3, I DOC To achieve the base current cancellation function of Q2, the parameters of devices Q1, Q2, and Q3 are kept consistent, the resistance values ​​of R3 and R4 are kept consistent, and I1 and I2 and (I3-I DOC ) currents are equal, so that the base current of Q2 does not pass through resistors R1 and R2, in order to prevent the sudden switching process from introducing common-mode offset and deteriorating the sensitivity performance of the transimpedance amplifier. DOC The purpose is to reduce the problem of inequality between the base current of transistor Q2 and the collector current of Q4 caused by device imbalance.

[0028] The working mode of this burst transimpedance amplifier circuit is as follows Figure 3 As shown in the figure, there is only a short protection time between two signal packets with different powers. During normal operation, TG1 is turned off, the RC constant of the filter network is large, and the low-frequency cutoff frequency of the transimpedance amplifier link is low to ensure the CID performance of the link. During the burst reset, TG1 is turned on, the RC constant of the filter network is reduced, and the common-mode voltage Vcm is quickly established. pp-s Refers to the peak-to-peak voltage of high-power signal, V pp-w Refers to the peak-to-peak value of the low-power signal voltage; e -t / τ is the response function of a single-pole system to a step signal.

[0029] Figure 4 This is a simulation diagram of the burst transimpedance amplifier (where the horizontal axis represents time and the vertical axis represents voltage). The two curves in the first row, the one with signal is the input Vin of the burst buffer, and the flat one is the Vave after filtering; the two curves in the second row, the one with signal is the output Vout of the burst buffer, and the flat one is the common-mode voltage Vcm after filtering. The third row of curves is the reset RESET signal (from outside the chip). During the burst change of the signal amplitude, the RESET signal controls TG1 to turn on, Vcm is quickly established, and no large offset jitter is introduced after the reset is completed. Figure 5 The simulated eye diagram of the small signal after the reset is completed is shown (where the horizontal axis represents time and the vertical axis represents voltage). The cross point and eye diagram have good quality.

[0030] This embodiment relies on the DC operating point establishment network and emitter follower base current compensation circuit controlled by the reset signal to ensure the rapid establishment of the link operating point and sensitivity index when the XGPSON system signal bursts, which will significantly improve the chip security and signal transmission quality.

[0031] The protection scope of the present technology includes but is not limited to the above embodiments. The protection scope of the present technology shall be based on the claims. Any replacement, deformation, and improvement of the present technology that can be easily thought of by technicians in this field shall fall within the protection scope of the present technology.

Claims

1. A burst transimpedance amplifier circuit for XGSPON, including a burst buffer circuit, characterized in that: The burst buffer circuit includes a first emitter follower, a second emitter follower, an RC filter network and a base current compensation circuit; The first emitter follower comprises a constant current source I1 and a transistor Q1; The second emitter follower comprises a constant current source I2 and a transistor Q2; The RC filter network includes a resistor R1, a resistor R2, a controlled switch TG1 and a capacitor C1; The constant current source I1 is connected to the emitter of the transistor Q1, the collector of the transistor Q1 is connected to the ground wire, one end of the resistor R1 is connected to the resistor R2 and the controlled switch TG1 at the same time, the resistor R2 and the controlled switch TG1 are connected to one end of the capacitor C1, the base of the transistor Q2 and the base current offset circuit at the same time, the other end of the capacitor C1 is connected to the ground wire, the constant current source I2 is connected to the emitter of the transistor Q2, and the collector of the transistor Q2 is connected to the ground wire; The other end of the resistor R1 is connected to the base of the transistor Q1, and the base of the transistor Q1 is used as the input end of the burst buffer circuit, the emitter of the transistor Q1 is used as the first output end of the burst buffer circuit, the emitter of the transistor Q2 is used as the second output end of the burst buffer circuit, and one end of the controlled switch TG1 is used to connect the reset signal; the base current compensation circuit includes a constant current source I3, a constant current source I DOC , resistor R3, resistor R4, transistor Q3, transistor Q4 and transistor Q5; The collector of the transistor Q4 is connected to the base of the transistor Q2, the emitter of the transistor Q4 is connected to the ground wire through the resistor R3, the base of the transistor Q4 is simultaneously connected to the base of the transistor Q5 and the base of the transistor Q3, the emitter of the transistor Q5 is connected to the ground wire through the resistor R4, the collector of the transistor Q5 is connected to the base of the transistor Q3, and the constant current source I3 is simultaneously connected to the emitter of the transistor Q3 and the constant current source I DOC One end of the constant current source I DOC The other end of is connected to the ground wire, and the collector of the transistor Q3 is connected to the ground wire.

2. The burst transimpedance amplifier circuit applied to XGSPON according to claim 1, characterized in that: The resistance value of the resistor R2 is greater than the resistance value of the resistor R1.

3. The burst transimpedance amplifier circuit applied to XGSPON according to claim 2, characterized in that: The device parameters of the transistor Q1 , the transistor Q2 and the transistor Q3 are consistent, and they are all PNP transistors.

4. The burst transimpedance amplifier circuit applied to XGSPON according to claim 3, characterized in that: The transistor Q4 and the transistor Q5 have the same device parameters and are both NPN transistors.

5. The burst transimpedance amplifier circuit applied to XGSPON according to claim 4, characterized in that: The resistance values ​​of the resistor R3 and the resistor R4 are consistent.

6. The burst transimpedance amplifier circuit applied to XGSPON according to claim 5, characterized in that: The constant current source I3 is subtracted from the constant current source I DOC The current of the constant current source I1, the current of the constant current source I2 are equal.

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