A three-dimensional interconnect fan-out packaging method and structure

Abstract

The present invention discloses a three-dimensional interconnected fan-out packaging method and structure, which belongs to the technical field of integrated circuit wafer-level packaging. A resin-based wafer is provided, and n layers of rewiring are made on its surface and cut into resin vertical interconnection channel units, wherein n≥1; the resin vertical interconnection channel unit and the chip are mounted on the first glass carrier through a first temporary bonding glue, and wafer-level plastic sealing is performed; the first glass carrier on the front is removed and the first temporary bonding glue is cleaned to form a resin plastic sealing body, and after making n layers of rewiring, the second glass carrier is bonded through a second temporary bonding glue; the back of the resin plastic sealing body is thinned to expose the resin vertical interconnection channel unit, and n layers of rewiring are made. The present invention uses resin as a matrix to plastic-seal the resin vertical interconnection channel unit in a resin-based wafer, while reducing the problem of high warping of the wafer caused by CTE mismatch, and is simple to manufacture and low-cost.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit wafer-level packaging, and in particular to a three-dimensional interconnected fan-out packaging method and structure. Background Art

[0002] Vertical interconnection structure is the basis of wafer-level 3D packaging. Commonly used vertical interconnection structures include TSV (Through Silicon Via), TMV (Through Molding Via) and TGV (Through Glass Via). These three technologies are usually implemented using dry etching technology and laser drilling technology. With the development of miniaturized, intelligent and highly integrated system-level 3D fan-out, the demand for higher aspect ratio and vertical interconnection density is increasing. However, high aspect ratio and high vertical interconnection density are a very big challenge for traditional TSV, TMV and TGV. In addition, with the development of high aspect ratio and vertical interconnection density, the cost and difficulty of making TSV, TMV and TGV are rapidly increasing. Summary of the invention

[0003] The purpose of the present invention is to provide a three-dimensional interconnect fan-out packaging method and structure to solve the problem of high difficulty and high cost in manufacturing high aspect ratio and high density vertical interconnect structures in current three-dimensional packaging.

[0004] In order to solve the above technical problems, the present invention provides a three-dimensional interconnect fan-out packaging method, comprising:

[0005] Providing a resin-based wafer, making n layers of rewiring on its surface and cutting into resin vertical interconnection channel units, where n≥1;

[0006] The resin vertical interconnection channel unit and the chip are mounted on the first glass carrier through a first temporary bonding adhesive sheet, and wafer-level encapsulation is performed;

[0007] The first glass carrier on the front side is removed and the first temporary bonding adhesive is cleaned to form a resin plastic package, and after making n layers of wiring, the second glass carrier is bonded by the second temporary bonding adhesive;

[0008] The back side of the resin encapsulation body is thinned until the resin vertical interconnection channel unit is exposed to produce n-layer rewiring.

[0009] Optionally, after thinning the back side of the resin encapsulation body until the resin vertical interconnection channel unit is exposed and n layers of rewiring are fabricated, the three-dimensional interconnection fan-out packaging method further comprises:

[0010] Welding a number of heterogeneous or heterogeneous chips on the back of the resin plastic package through micro-bumps and filling the bottom with underfill;

[0011] The second glass carrier is removed and the second temporary bonding adhesive is cleaned, bumps are grown on the front side of the resin package body, and the body is cut and separated to form a single three-dimensional system-level packaging unit.

[0012] Optionally, after thinning the back side of the resin encapsulation body until the resin vertical interconnection channel unit is exposed and n layers of rewiring are fabricated, the three-dimensional interconnection fan-out packaging method further comprises:

[0013] Remove the second glass carrier and clean the second temporary bonding glue;

[0014] Use wafer-level 3D stacking technology or C2W stacking technology to perform 3D stacking through micro-bumps, with at least 2 stacking layers;

[0015] Fill the gap between each layer with bottom filler, remove the top n-layer for rewiring and grow bumps on the bottom layer, and cut and separate to form a single three-dimensional system-level packaging unit.

[0016] Optionally, the n-layer rewiring includes a passivation layer and a metal circuit layer; the passivation layer is an inorganic material or polyimide or resin, and the metal circuit layer is one or more metal materials;

[0017] The inorganic materials include SiO2, SiN and SiC; the metal materials include Ti, W, Cu, Ni and Au.

[0018] Optionally, the resin-based wafer is 8 inches or 12 inches and has a thickness of not less than 1 μm.

[0019] Optionally, the material used for wafer-level encapsulation is the same as the material of the resin-based wafer, that is, resin material.

[0020] The present invention also provides a three-dimensional fan-out packaging structure, comprising:

[0021] A resin-molded body, wherein the front and back sides of the resin-molded body are both provided with n layers of rewiring;

[0022] Bumps, grown on the front side of the resin-molded body;

[0023] A plurality of heterogeneous or heterogeneous chips are flip-chip welded on the back of the resin plastic package body through micro-bumps, and the bottom of the heterogeneous or heterogeneous chips is filled with bottom filler.

[0024] Optionally, the resin molding body is formed by wafer-level molding of the chip and the resin vertical interconnection channel unit using molding material; the resin molding body is thinned to expose the resin vertical interconnection channel unit; wherein the resin vertical interconnection channel unit includes a resin-based wafer, and n layers of rewiring are made on one side of the resin-based wafer.

[0025] The present invention also provides a three-dimensional fan-out stacked packaging structure, comprising:

[0026] Optionally, a plurality of resin plastic encapsulation bodies are three-dimensionally stacked by micro-bumps, and bottom fillers are filled between each layer;

[0027] There are bumps growing on the front of the resin-encapsulated body at the bottom;

[0028] The front and back sides of the resin package body are both made with n layers of rewiring.

[0029] Optionally, the resin molding body is formed by wafer-level molding of the chip and the resin vertical interconnection channel unit using molding material; the resin molding body is thinned to expose the resin vertical interconnection channel unit; wherein the resin vertical interconnection channel unit includes a resin-based wafer, and n layers of rewiring are made on one side of the resin-based wafer.

[0030] The present invention provides a three-dimensional interconnect fan-out packaging method and structure, providing a resin-based wafer, making n layers of rewiring on its surface and cutting it into resin vertical interconnection channel units, where n≥1; mounting the resin vertical interconnection channel unit and the chip on the first glass carrier through a first temporary bonding glue, and performing wafer-level plastic sealing; removing the first glass carrier on the front side and cleaning the first temporary bonding glue to form a resin plastic sealing body, making n layers of rewiring, and bonding the second glass carrier through a second temporary bonding glue; thinning the back of the resin plastic sealing body to expose the resin vertical interconnection channel unit, and making n layers of rewiring. The present invention uses resin as a matrix to plastic-seal the resin vertical interconnection channel unit in a resin-based wafer, while reducing the problem of high wafer warpage caused by CTE mismatch, and is simple to manufacture and low-cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the process flow of the three-dimensional interconnect fan-out packaging method provided by the present invention;

[0032] Figure 2 It is a schematic diagram of using resin material to encapsulate a resin-based disc;

[0033] Figure 3 It is a schematic diagram of making n-layer rewiring on a resin-based wafer;

[0034] Figure 4 It is a top view of the resin-based wafer after making n layers of rewiring;

[0035] Figure 5 is a schematic diagram of a vertically interconnected channel unit of a resin;

[0036] Figure 6 is a schematic diagram of vertically interconnecting the resin channel unit and mounting the chip on the first glass carrier;

[0037] Figure 7 It is a schematic diagram of forming a resin plastic package;

[0038] Figure 8 It is a schematic diagram of making n-layer rewiring on the front side of the resin plastic package;

[0039] Fig. 9 It is a schematic diagram of bonding the second glass carrier plate to the front side of the resin plastic packaging body;

[0040] Fig.10 It is a schematic diagram of thinning the back of the resin plastic package and making n-layer rewiring;

[0041] Fig.11 It is a schematic diagram of making a three-dimensional interconnected fan-out packaging structure;

[0042] Fig.12 It is a schematic diagram of making a three-dimensional fan-out stacked packaging structure. DETAILED DESCRIPTION

[0043] The following is a further detailed description of a three-dimensional interconnected fan-out packaging method and structure proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0044] Embodiment 1

[0045] The present invention provides a three-dimensional interconnect fan-out packaging method, the process of which is as follows: Figure 1 As shown, the following steps are included:

[0046] Step S11, providing a resin-based wafer, making n layers of rewiring on its surface and cutting it into resin vertical interconnection channel units, where n≥1;

[0047] Step S12, placing the resin vertical interconnection channel unit and the chip on the first glass carrier through a first temporary bonding adhesive sheet, and performing wafer-level encapsulation;

[0048] Step S13, removing the first glass carrier on the front side and cleaning the first temporary bonding adhesive to form a resin plastic package, making n layers of wiring and then bonding the second glass carrier with the second temporary bonding adhesive;

[0049] Step S14, thinning the back side of the resin encapsulation body until the resin vertical interconnection channel unit is exposed, and making n-layer rewiring.

[0050] like Figure 2 As shown, an 8-inch or 12-inch resin-based wafer 101a is encapsulated with a resin material, and the thickness of the resin-based wafer 101a is not less than 1 μm;

[0051] like Figure 3As shown, an n-layer rewiring is fabricated on the resin-based wafer 101a by physical vapor deposition, electroplating and photolithography processes, wherein the n-layer rewiring consists of a passivation layer 102a and a metal wiring layer 102b, wherein the passivation layer 102a is an inorganic material such as SiO2, SiN, SiC or an organic material such as polyimide and resin, and the metal wiring layer 102b is a metal material, including one or more of Ti, W, Cu, Ni and Au;

[0052] like Figure 4 As shown, it is a top view after making n-layer rewiring; after the n-layer rewiring is prepared, it is separated into single independent resin vertical interconnection channel units by laser and mechanical cutting. The separated resin vertical interconnection channel units need to be rotated 90° before use. The specific resin vertical interconnection channel units are as follows Figure 5 As shown;

[0053] Provide a first glass carrier plate 301, Figure 5 The resin vertical interconnection channel unit and the chip 201 are mounted on the first glass carrier 301 with high precision and fixed in the middle by a temporary bonding adhesive 302; the pad 202 of the chip 201 faces inwards, as shown in FIG. Figure 6 As shown;

[0054] Wafer-level encapsulation is performed using wafer encapsulation technology and the first glass carrier 301 on the front is removed, and the first temporary bonding adhesive 302 is cleaned to form a resin encapsulation body, such as Figure 7 As shown; the plastic encapsulation material 101b is made of the same material as the resin-based wafer 101a, both of which are resin materials;

[0055] like Figure 8 As shown, n-layer rewiring (including passivation layer 102a and metal wiring layer 102b) is made on the front side;

[0056] like Fig. 9 As shown, the front side of the resin encapsulated body is bonded to the second glass carrier 304 via a second temporary bonding adhesive 303;

[0057] The back of the resin encapsulated body is thinned to expose the metal circuit of the resin vertical interconnection channel unit, and n-layer rewiring (including the passivation layer 102a and the metal circuit layer 102b) is manufactured. Fig.10 As shown;

[0058] When used as a 3D fan-out package,

[0059] like Fig.11As shown, a heterogeneous chip 203, a heterogeneous chip 204 and a heterogeneous chip 205 are welded on the back of the resin plastic package by using micro bumps 206 and flip-chip welding technology, the number of the heterogeneous chips is greater than or equal to 1, and the bottom filler 207 is filled at the same time; at the same time, the second glass carrier 304 on the front of the resin plastic package is removed and the second temporary bonding glue 303 is cleaned, and bumps 104 are grown, and finally a single three-dimensional system-level packaging unit is formed after cutting and separation;

[0060] When used as a three-dimensional fan-out stacked package,

[0061] like Fig.12 As shown, the second glass carrier 304 is removed and the second temporary bonding glue 303 is cleaned; wafer-level three-dimensional stacking technology or C2W stacking technology is used to perform three-dimensional stacking through micro-bumps 206, and the number of stacking layers is at least 2; bottom filler 207 is filled between each layer, the top n layers are removed and re-wired, and bumps 104 are grown on the bottom layer, which are cut and separated to form a single three-dimensional system-level packaging unit.

[0062] Embodiment 2

[0063] When used as a three-dimensional fan-out package, this second embodiment provides a three-dimensional fan-out package structure, such as Fig.11 As shown, it includes a resin plastic package, a bump 104 and a plurality of heterogeneous or heterogeneous chips (including a heterogeneous or heterogeneous chip 203, a heterogeneous or heterogeneous chip 204, and a heterogeneous or heterogeneous chip 205); the front and back sides of the resin plastic package are both made with n layers of rewiring; the bump 104 grows on the front side of the resin plastic package; the plurality of heterogeneous or heterogeneous chips are flip-chip welded on the back side of the resin plastic package through micro bumps 206, and the bottom of the heterogeneous or heterogeneous chips is filled with bottom filler 207.

[0064] like Figure 7 As shown, the resin encapsulation body is formed by encapsulating the chip 201 and the resin vertical interconnection channel unit through the encapsulation material 101b at the wafer level, and the resin encapsulation body is thinned from the back of the chip 201 to expose the resin vertical interconnection channel unit; wherein the resin vertical interconnection channel unit is as shown Figure 5 As shown, it includes a resin-based wafer 101a, and one side of the resin-based wafer 101a is made with n layers of rewiring (including a passivation layer 102a and a metal wiring layer 102b).

[0065] When used as a three-dimensional fan-out stacked package, this embodiment also provides a three-dimensional fan-out stacked package structure, such as Fig.12As shown, it includes several resin plastic packaging bodies stacked three-dimensionally through micro-bumps 206, and bottom fillers 207 are filled between each layer; the front side of the bottom resin plastic packaging body has bumps 104 grown on it; the front and back sides of the resin plastic packaging body are both made with n layers of rewiring and the top n layers of rewiring are removed.

[0066] like Figure 7 As shown, the resin encapsulation body is formed by encapsulating the chip 201 and the resin vertical interconnection channel unit through the encapsulation material 101b at the wafer level, and the resin encapsulation body is thinned from the back of the chip 201 to expose the resin vertical interconnection channel unit; wherein the resin vertical interconnection channel unit is as shown Figure 5 As shown, it includes a resin-based wafer 101a, and one side of the resin-based wafer 101a is made with n layers of rewiring (including a passivation layer 102a and a metal wiring layer 102b).

[0067] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A three-dimensional interconnect fan-out packaging method, characterized in that: include: Providing a resin-based wafer, making n layers of rewiring on its surface and cutting into resin vertical interconnection channel units, where n≥1; The resin vertical interconnection channel unit and the chip are mounted on the first glass carrier through a first temporary bonding glue, and wafer-level sealing is performed; specifically, the cut resin vertical interconnection channel unit needs to be rotated 90° before use, a first glass carrier is provided, the resin vertical interconnection channel unit and the chip are mounted on the first glass carrier through high-precision, and fixed in the middle through a temporary bonding glue; the chip's pad faces inward, and wafer-level sealing is performed using wafer-level sealing technology; The first glass carrier on the front side is removed and the first temporary bonding adhesive is cleaned to form a resin plastic package, and after making n layers of wiring, the second glass carrier is bonded by the second temporary bonding adhesive; The back side of the resin encapsulation body is thinned until the resin vertical interconnection channel unit is exposed to produce n-layer rewiring.

2. The three-dimensional interconnect fan-out packaging method according to claim 1, characterized in that: After thinning the back of the resin encapsulation body until the resin vertical interconnection channel unit is exposed and n layers of rewiring are made, the three-dimensional interconnection fan-out packaging method further includes: Welding a number of heterogeneous or heterogeneous chips on the back of the resin plastic package through micro-bumps and filling the bottom with underfill; The second glass carrier is removed and the second temporary bonding adhesive is cleaned, bumps are grown on the front side of the resin package body, and the body is cut and separated to form a single three-dimensional system-level packaging unit.

3. The three-dimensional interconnect fan-out packaging method according to claim 1, characterized in that: After thinning the back of the resin encapsulation body until the resin vertical interconnection channel unit is exposed and n layers of rewiring are made, the three-dimensional interconnection fan-out packaging method further includes: Remove the second glass carrier and clean the second temporary bonding glue; Use wafer-level 3D stacking technology or C2W stacking technology to perform 3D stacking through micro-bumps, with at least 2 layers of stacking; Fill the gap between each layer with bottom filler, remove the top n-layer for rewiring and grow bumps on the bottom layer, and cut and separate to form a single three-dimensional system-level packaging unit.

4. The three-dimensional interconnect fan-out packaging method according to any one of claims 1 to 3, characterized in that: The n-layer rewiring includes a passivation layer and a metal circuit layer; the passivation layer is an inorganic material or polyimide or resin, and the metal circuit layer is one or more metal materials; The inorganic materials include SiO2, SiN and SiC; the metal materials include Ti, W, Cu, Ni and Au.

5. The three-dimensional interconnect fan-out packaging method according to any one of claims 1 to 3, characterized in that: The resin-based wafer is 8 inches or 12 inches and has a thickness of not less than 1 μm.

6. The three-dimensional interconnect fan-out packaging method according to claim 2, characterized in that: The material used for wafer-level encapsulation is the same as the material of the resin-based wafer, which is resin material.

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